KR102648421B1 - Pixel Sensing Device And Electroluminescence Display Device Including The Same - Google Patents

Abstract

A pixel sensing device according to an embodiment of the present invention stores the pixel current flowing from the pixel as a sampling voltage during a vertical blank period when writing of image data to the pixel in one frame is stopped, and stores the pixel current flowing from the pixel as a sampling voltage, and transmits the image to the pixel in the one frame. a current radiation unit that generates a radiation current according to the sampling voltage in a vertical active period in which data is written; In the vertical blank period, the pixel current is bypassed to the current radiation unit through the first node, and in the vertical active period, an integrator output voltage that changes from the integrator reference voltage according to the radiation current is generated and output to the first node. a current integrator; and a switching circuit unit connected between the current radiation unit and the current integrator to make the first current path of the pixel current and the second current path of the radiation current different from each other.

Description

Pixel sensing device and electroluminescence display device including the same {Pixel Sensing Device And Electroluminescence Display Device Including The Same}

The present invention relates to an electroluminescent display device.

An active matrix type electroluminescent display device arranges pixels, each including a light-emitting element and a driving element, in a matrix form and adjusts the luminance of the image implemented in the pixels according to the gradation of the image data. The driving element controls the pixel current flowing to the light emitting element according to the voltage applied between its gate electrode and source electrode (hereinafter referred to as “gate-source voltage”). The amount of light emitted from the light emitting device and the brightness of the screen are determined by the pixel current.

The threshold voltage and electron mobility of the driving element, the operating point voltage (or turn-on voltage) of the light-emitting element, etc. determine the driving characteristics of the pixel and must be the same for all pixels. However, driving characteristics may vary between pixels due to various reasons such as process characteristics and time-varying characteristics. This difference in driving characteristics causes luminance deviation, which limits the ability to create a desired image. In order to compensate for luminance differences between pixels, a current mirror sensing method is known that senses the driving characteristics of pixels and corrects data of an input image based on the sensing results. However, the current mirror sensing method has the following problems.

Since the current mirror sensing method uses two large amplifiers, the mounting area of the sensing circuit is large and the manufacturing cost of the drive integrated circuit increases. Additionally, the current mirror sensing method causes sensing errors due to process deviation between the two transistors that perform mirroring. The sensing current is different from the pixel current that actually flows through the driving TFT of the pixel, and this difference becomes larger due to current amplification due to current mirroring. In addition, the current mirror sensing method, which senses pixel current using a vertical blank period, has insufficient sensing time, making it impossible to sense low current for high-resolution, high-speed display devices.

Accordingly, the present invention provides a pixel sensing device that can reduce the size and sensing error of a sensing circuit and secure sufficient sensing time, and an electroluminescent display device including the same.

A pixel sensing device according to an embodiment of the present invention stores the pixel current flowing from the pixel as a sampling voltage during a vertical blank period when writing of image data to the pixel in one frame is stopped, and stores the pixel current flowing from the pixel as a sampling voltage, and transmits the image to the pixel in the one frame. a current radiation unit that generates a radiation current according to the sampling voltage in a vertical active period in which data is written; In the vertical blank period, the pixel current is bypassed to the current radiation unit through the first node, and in the vertical active period, an integrator output voltage that changes from the integrator reference voltage according to the radiation current is generated and output to the first node. a current integrator; and a switching circuit unit connected between the current radiation unit and the current integrator to make the first current path of the pixel current and the second current path of the radiation current different from each other.

The present invention can significantly reduce the size and manufacturing cost of the driver integrated circuit on which the sensing unit is mounted by implementing the number of amplifiers included in the sensing unit to one.

Since the present invention generates a radiation current using the gate-source voltage applied to the same transistor, the error between the pixel current and the radiation current can be prevented in advance, thereby eliminating the sensing error.

The present invention quickly stores the pixel current in the form of voltage in the vertical blank period and senses the same radiation current as the pixel current using a current integration method in the vertical active period with relatively ample time, so that sufficient sensing time is secured for sensing. accuracy can be dramatically increased.

The effects according to the present invention are not limited to the contents exemplified above, and further various effects are included in the present specification.

1 is a diagram showing an electroluminescence display device according to an embodiment of the present invention.
FIG. 2 is a diagram showing an example of a pixel array provided in the display panel of FIG. 1.
FIG. 3 is a diagram showing a configuration of a data driver connected to the pixel array of FIG. 2.
FIG. 4 is an equivalent circuit diagram of the pixel shown in FIG. 3.
FIG. 5 is a diagram showing another configuration of a data driver connected to the pixel array of FIG. 2.
FIG. 6 is an equivalent circuit diagram of the pixel shown in FIG. 5.
Figure 7 is a diagram showing a pixel sensing device according to an embodiment of the present invention.
FIG. 8 is a driving waveform diagram of the pixel sensing device of FIG. 7.
FIGS. 9A and 9B are diagrams showing the operation of the pixel sensing device of FIG. 7.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present specification is complete, and that common knowledge in the technical field to which this specification pertains is provided. It is provided to fully inform those who have the scope of the invention, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

First, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical idea of the present specification.

In this specification, the pixel circuit formed on the substrate of the display panel may be implemented as a TFT with an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure or a TFT with a p-type MOSFET structure. TFT is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the TFT, carriers begin to flow from the source. The drain is the electrode through which carriers go out of the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of n-type TFT (NMOS), because the carriers are electrons, the source voltage has a lower voltage than the drain voltage to allow electrons to flow from the source to the drain. Since electrons flow from the source to the drain in an n-type TFT, the direction of current flows from the drain to the source. On the other hand, in the case of p-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage.

Meanwhile, in this specification, the semiconductor layer of the TFT may be implemented as at least one of an oxide device, an amorphous silicon device, and a polysilicon device.

Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings. In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted.

1 is a diagram showing an electroluminescence display device according to an embodiment of the present invention. And, FIG. 2 is a diagram showing an example of a pixel array provided in the display panel of FIG. 1.

1 and 2, the electroluminescent display device according to an embodiment of the present invention includes a display panel 10, a driver IC (D-IC) 20, a compensation IC 30, and a host system 40. , and may include a storage memory 50. The panel driver of the present invention includes a gate driver 15 provided in the display panel 10 and a data driver 25 embedded in a driver IC (D-IC) 20.

The display panel 10 is provided with a plurality of pixel lines (PNL1 to PNL4), and each pixel line is provided with a plurality of pixels (PXL) and a plurality of signal lines. The “pixel line” described in the present invention does not mean a physical signal line, but rather a collection of pixels (PXL) and signal lines that are adjacent to each other along the extension direction of the gate line. The signal lines are data lines 140 for supplying a display data voltage (VDIS) and a sensing data voltage (VSEN) to the pixels (PXL), and a reference voltage (VREF) for supplying the pixels (PXL). Reference voltage lines 150, gate lines 160 for supplying gate signals to pixels PXL, and high potential power lines PWL for supplying high potential pixel voltages to pixels PXL. It can be included.

The pixels (PXL) of the display panel 10 are arranged in a matrix form to form a pixel array. Each pixel (PXL) included in the pixel array of FIG. 2 is connected to one of the data lines 140, one of the reference voltage lines 150, and one of the high potential power lines (PWL), And it may be connected to any one of the gate lines 160. Each pixel (PXL) included in the pixel array of FIG. 2 may be connected to a plurality of gate lines 160. Additionally, each pixel (PXL) included in the pixel array of FIG. 2 may further receive a low-potential pixel voltage from the power generator. The power generator may supply a low-potential pixel voltage to the pixel (PXL) through a low-potential power line or pad portion.

A gate driver 15 may be built into the display panel 10.

The gate driver 15 may include a plurality of stages connected to the gate lines 160 of the pixel array of FIG. 2 . The stages may generate gate signals to control switch elements of the pixels PXL and supply them to the gate lines 160.

The driver IC (D-IC) 20 includes a timing control unit 21 and a data driver 25. The data driver 25 may include a sensing unit 22 and a driving voltage generator 23, but is not limited thereto.

The timing control unit 21 refers to timing signals input from the host system 40, such as the vertical synchronization signal (Vsync), horizontal synchronization signal (Hsync), dot clock signal (DCLK), and data enable signal (DE). A gate timing control signal (GDC) for controlling the operation timing of the gate driver 15 and a data timing control signal (DDC) for controlling the operation timing of the data driver 25 can be generated.

The data timing control signal (DDC) may include, but is not limited to, a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the driving voltage generator 23. The source sampling clock is a clock signal that controls the sampling timing of data based on the rising or falling edge. The source output enable signal controls the output timing of the driving voltage generator 23.

The gate timing control signal (GDC) may include, but is not limited to, a gate start pulse and a gate shift clock. The gate start pulse is applied to the stage that generates the first gate output and activates the operation of that stage. The gate shift clock is commonly input to the stages and is a clock signal for shifting the gate start pulse.

The timing control unit 21 can sense the driving characteristics of the pixels PXL not only in the vertical blank period of each frame but also in the vertical active period of each frame by controlling the operation timing of the panel driver. Here, the vertical active period is a period in which image data is written to the display panel 10 for screen playback, and the vertical blank period is located between adjacent vertical active periods and is a period in which writing of image data is stopped. The vertical active period is very long compared to the vertical blank period. The driving characteristics of the pixels PXL include the threshold voltage and electron mobility of the driving elements included in the pixels PXL, and the operating point voltage of the light-emitting elements.

The timing control unit 21 can implement display driving and sensing driving by controlling the sensing driving timing and display driving timing for the pixel lines (PNL1 to PNL4) of the display panel 10 according to a predetermined sequence.

The timing control unit 21 may generate timing control signals (GDC, DDC) for display driving and timing control signals (GDC, DDC) for sensing driving differently. Sensing driving writes the sensing data voltage (VSEN) to the pixels (PXL) included in the sensing target pixel line to sense the driving characteristics of the pixels (PXL), and based on the sensing result data (SDATA), the corresponding pixel This means updating the compensation value to compensate for changes in driving characteristics of PXL. And, display driving corrects the digital image data to be input to the corresponding pixels (PXL) based on the updated compensation value, and applies the display data voltage (VDIS) corresponding to the corrected image data (CDATA) to the corresponding pixel. This means displaying the input image by applying it to the PXL.

The driving voltage generator 23 is implemented as a digital to analog converter (hereinafter referred to as DAC) that converts a digital signal into an analog signal. The driving voltage generator 23 generates a sensing data voltage (VSEN) required for sensing driving and a display data voltage (VDIS) required for display driving and supplies them to the data lines 140. The driving voltage generator 23 generates a reference voltage (VREF) necessary for sensing driving and display driving and supplies it to the reference voltage lines 150.

The display data voltage (VDIS) is the result of digital-to-analog conversion of the digital image data (CDATA) corrected in the compensation IC 30, and its size may vary in pixel units depending on the gray level value and compensation value. The sensing data voltage (VSEN) can be set differently for each R (red), G (green), B (blue), and W (white) pixel, considering that the driving characteristics of the driving elements are different for each color.

For sensing driving, the sensing unit 22 may sense the driving characteristics of the pixels PXL, for example, the threshold voltage and electron mobility of the driving device, and the operating point voltage of the light-emitting device through sensing lines. Sensing lines may be implemented as data lines 140 or reference voltage lines 150. However, if the data lines 140 are used as sensing lines, the data output channel and the sensing channel can be unified, which is advantageous in reducing the number of pads of the driver IC (D-IC) 20. The sensing unit 22 may be implemented as a current sensing type that senses the pixel current flowing through each pixel (PXL). For this purpose, the sensing unit 22 includes a current radiation unit that copies the pixel current, a current integrator that senses the radiation current, and a switching circuit unit that makes the first current path of the pixel current and the second current path of the radiation current different from each other. It may include, which will be described in detail through FIGS. 7 to 9B.

The sensing unit 22 may simultaneously process a plurality of analog sensing values in parallel using a plurality of analog-digital converters (ADCs), or sequentially process a plurality of analog sensing values in serial using one ADC. . There is a trade-off relationship between the sampling rate of the ADC and the accuracy of sensing. A parallel processing ADC can slow down the sampling rate compared to a serial processing ADC, which is advantageous in improving sensing accuracy. The ADC can be implemented as a flash type ADC, an ADC using a tracking technique, or a successive approximation register type ADC. The ADC converts analog sensing values into digital sensing result data (SDATA) according to a predetermined sensing range and supplies it to the storage memory 50 and the sensing output control unit 27.

The storage memory 50 stores digital sensing result data (SDATA) input from the sensing unit 22 during sensing operation. The storage memory 50 may be implemented as a flash memory, but is not limited thereto.

The compensation IC 30 may include a compensation unit 31 and a compensation memory 32. The compensation memory 32 transmits the digital sensing result data (SDATA) read from the storage memory 50 to the compensation unit 31. The compensation memory 32 may be RAM (Random Access Memory), for example, DDR SDRAM (Double Date Rate Synchronous Dynamic RAM), but is not limited thereto. The compensation unit 31 calculates the compensation offset and compensation gain for each pixel based on the digital sensing result data (SDATA) read from the storage memory 50, and calculates the compensation offset and compensation gain based on the calculated compensation offset and compensation gain. Accordingly, the image data input from the host system 40 is corrected, and the corrected image data (CDATA) is supplied to the driver IC 20.

FIG. 3 is a diagram showing a configuration of the data driver 25 connected to the pixel array of FIG. 2. The data driver 25 of FIG. 3 is used to sense the driving characteristics of the pixels PXL through the reference voltage lines 150.

Referring to FIG. 3, the data driver 25 is connected to the first node of the pixel (PXL) (connected to the gate electrode of the driving element) through the data line 140, and the pixel (connected to the gate electrode of the driving element) through the reference voltage line 150. PXL) may be connected to the second node (connected to the source electrode of the driving element). Since the pixel current IPIX flows through the second node of the pixel PXL, the reference voltage line 150 connected to the second node through the second switch element can be used as a sensing line.

The reference voltage line 150 is selectively connected to the driving voltage generator 23 and the sensing unit 22 through connection switches SX1 and SX2. The driving voltage generator 23 includes a first driving voltage generator (DAC1) that generates a data voltage (VSEN) for sensing and a data voltage (VDIS) for display, and a second drive voltage generator that generates a reference voltage (VREF). (DAC2) may be included. A first connection switch (SX1) is connected between the reference voltage line 150 and the second driving voltage generator (DAC2), and a second connection switch (SX2) is connected between the reference voltage line 150 and the sensing unit 22. is connected. The first connection switch (SX1) and the second connection switch (SX2) are selectively turned on. Only the first connection switch (SX1) is turned on in synchronization with the timing at which the reference voltage (VREF) is written to the pixel (PXL), and the second connection switch is turned on in synchronization with the timing of sensing the pixel current (IPIX) flowing through the pixel (PXL). Only the switch (SX2) is turned on. Accordingly, the reference voltage line 150 is selectively connected to the second driving voltage generator DAC2 and the sensing unit 22 through the first and second connection switches SX1 and SX2.

FIG. 4 is an equivalent circuit diagram of the pixel shown in FIG. 3.

Referring to FIG. 4, one pixel (PXL) using the reference voltage line 150 as a sensing line includes a light emitting element (EL), a driving TFT (DT), switch TFTs (ST1, ST2), and a storage capacitor (Cst). ) includes. The driving TFT (DT) and the switch TFTs (ST1 and ST2) may be implemented as NMOS, but are not limited to this.

The light emitting element (EL) is a light emitting element that emits light with an intensity corresponding to the pixel current drawn from the driving TFT (DT). The light emitting device (EL) may be implemented as an organic light emitting diode including an organic light emitting layer, or may be implemented as an inorganic light emitting diode including an inorganic light emitting layer. The anode electrode of the light emitting element EL is connected to the second node N2, and the cathode electrode is connected to the input terminal of the low potential pixel voltage EVSS.

The driving TFT (DT) is a driving element that generates pixel current in response to the gate-source voltage. The gate electrode of the driving TFT (DT) is connected to the first node (N1), the first electrode is connected to the input terminal of the high-potential pixel voltage (EVDD) through the high-potential power line (PWL), and the second electrode is connected to the first node (N1). 2 Connected to node (N2).

The switch TFTs (ST1 and ST2) are switch elements that set the gate-source voltage of the driving TFT (DT) and connect the second electrode of the driving TFT (DT) to the reference voltage line 150.

The first switch TFT (ST1) is connected between the data line 140 and the first node (N1) and is turned on according to the gate signal (SCAN) from the gate line 160. The first switch TFT (ST1) is turned on during programming for display driving or sensing driving. When the first switch TFT (ST1) is turned on, the sensing data voltage (VSEN) or the display data voltage (VDIS) is applied to the first node (N1). The gate electrode of the first switch TFT (ST1) is connected to the gate line 160, the first electrode is connected to the data line 140, and the second electrode is connected to the first node (N1).

The second switch TFT (ST2) is connected between the reference voltage line 150 and the second node (N2) and is turned on according to the gate signal (SCAN) from the gate line 160. The second switch TFT (ST2) is turned on during programming for display driving or sensing driving, and applies the reference voltage (VREF) to the second node (N2). Additionally, the second switch TFT (ST2) is turned on even during the sensing period during the sensing drive to apply the pixel current generated in the driving TFT (DT) to the reference voltage line 150. The gate electrode of the second switch TFT (ST2) is connected to the gate line 160, the first electrode is connected to the reference voltage line 150, and the second electrode is connected to the second node (N2).

The storage capacitor Cst is connected between the first node N1 and the second node N2 to maintain the gate-source voltage of the driving TFT DT for a certain period of time.

FIG. 5 is a diagram showing another configuration of the data driver 25 connected to the pixel array of FIG. 2. The data driver 25 of FIG. 5 is used to sense the driving characteristics of the pixels PXL through the data line 140.

Referring to FIG. 5, the data driver 25 is connected to the first node (connected to the gate electrode of the driving element) of the pixel PXL through the reference voltage line 150, and the pixel (connected to the gate electrode of the driving element) through the data line 140. PXL) may be connected to the second node (connected to the source electrode of the driving element). Since the pixel current IPIX flows through the second node of the pixel PXL, the data line 140 connected to the second node through the second switch element can be used as a sensing line.

The data line 140 is selectively connected to the driving voltage generator 23 and the sensing unit 22 through connection switches SX1 and SX2. The driving voltage generator 23 includes a first driving voltage generator (DAC1) that generates a data voltage (VSEN) for sensing and a data voltage (VDIS) for display, and a second drive voltage generator that generates a reference voltage (VREF). (DAC2) may be included. A first connection switch (SX1) is connected between the data line 140 and the first driving voltage generator (DAC1), and a second connection switch (SX2) is connected between the data line 140 and the sensing unit 22. do. The first connection switch (SX1) and the second connection switch (SX2) are selectively turned on. Only the first connection switch (SX1) is turned on in synchronization with the timing at which the sensing data voltage (VSEN) and the display data voltage (VDIS) are written to the pixel (PXL), and the pixel current (IPIX) flowing in the pixel (PXL) Only the second connection switch (SX2) is turned on in synchronization with the sensing timing. Accordingly, the data line 140 is selectively connected to the first driving voltage generator DAC1 and the sensing unit 22 through the first and second connection switches SX1 and SX2.

FIG. 6 is an equivalent circuit diagram of the pixel shown in FIG. 5.

Referring to FIG. 6, one pixel (PXL) using the data line 140 as a sensing line includes a light emitting element (EL), a driving TFT (DT), switch TFTs (ST1, ST2), and a storage capacitor (Cst). Includes. The driving TFT (DT) and the switch TFTs (ST1, ST2) may be implemented as NMOS, but are not limited to this.

The light emitting element (EL) is a light emitting element that emits light with an intensity corresponding to the pixel current drawn from the driving TFT (DT). The light emitting device (EL) may be implemented as an organic light emitting diode including an organic light emitting layer, or may be implemented as an inorganic light emitting diode including an inorganic light emitting layer. The anode electrode of the light emitting element EL is connected to the second node N2, and the cathode electrode is connected to the input terminal of the low potential pixel voltage EVSS.

The driving TFT (DT) is a driving element that generates pixel current in response to the gate-source voltage. The gate electrode of the driving TFT (DT) is connected to the first node (N1), the first electrode is connected to the input terminal of the high-potential pixel voltage (EVDD) through the high-potential power line (PWL), and the second electrode is connected to the first node (N1). 2 Connected to node (N2).

The switch TFTs (ST1 and ST2) are switch elements that set the voltage between the gate and source of the driving TFT (DT) and connect the second electrode of the driving TFT (DT) and the data line 140.

The first switch TFT (ST1) is connected between the reference voltage line 150 and the first node (N1) and is turned on according to the gate signal (SCAN) from the gate line 160. The first switch TFT (ST1) is turned on during programming for display driving or sensing driving. When the first switch TFT (ST1) is turned on, the reference voltage (VREF) is applied to the first node (N1). The gate electrode of the first switch TFT (ST1) is connected to the gate line 160, the first electrode is connected to the reference voltage line 150, and the second electrode is connected to the first node (N1).

The second switch TFT (ST2) is connected between the data line 140 and the second node (N2) and is turned on according to the gate signal (SCAN) from the gate line 160. The second switch TFT (ST2) is turned on during programming for display driving or sensing driving, and applies the sensing data voltage (VSEN) or the display data voltage (VDIS) to the second node (N2). Additionally, the second switch TFT (ST2) is turned on even during the sensing period during the sensing drive to apply the pixel current generated in the driving TFT (DT) to the data line 140. The gate electrode of the second switch TFT (ST2) is connected to the gate line 160, the first electrode is connected to the data line 140, and the second electrode is connected to the second node (N2).

The storage capacitor Cst is connected between the first node N1 and the second node N2 to maintain the gate-source voltage of the driving TFT DT for a certain period of time.

Figure 7 is a diagram showing a pixel sensing device according to an embodiment of the present invention. The pixel sensing device of FIG. 7 includes the sensing unit 22 of FIG. 1 . FIG. 8 is a driving waveform diagram of the pixel sensing device of FIG. 7.

Referring to FIGS. 7 and 8 , the sensing unit 22 may include a current radiating unit (ICP), a current integrator (CI), a switching circuit unit (PSW), and an analog-digital converter (ADC). Although not shown, the sensing unit 22 may further include a sample and hold circuit between the current integrator (CI) and the ADC.

The current integrator (CI) is connected to one pixel (PXL) through the sensing line (SL) of the display panel 10. The current integrator (CI) bypasses the pixel current (IPIX) flowing in the pixel (PXL) in the vertical blank period (VB) to the current radiator (ICP) through the first node (Na), and An integrator output voltage (CI-OUT) that varies from the integrator reference voltage (Vref) to the radiation current (Icpy in FIG. 9B) at (VA) is generated and output to the first node (Na).

This current integrator (CI) includes an integrator amplifier (AMP), a reset switch (RST), and an integrator capacitor (CFB). The integrator amplifier (AMP) has a first input terminal (-) through which the pixel current (IPIX) flows in in the vertical blank period (VB) and the radiation current flows in in the vertical active period (VA), and the integrator reference voltage (Vref) is input. It has a second input terminal (+) and an output terminal. The reset switch (RST) is connected between the first input terminal (-) and the first node (Na). Additionally, the integrator capacitor (CFB) is also connected in parallel with the reset switch (RST) between the first input terminal (-) and the first node (Na).

The integrator amplifier (AMP) may also be implemented as a negative type. As shown in FIG. 7, the negative type amplifier has a first input terminal (-) that becomes the inverting input terminal of the integrator amplifier (AMP), and the second input terminal (+) that becomes a non-inverting input terminal of the integrator amplifier (AMP). do. In this negative type amplifier (AMP), as current flows into the integrator capacitor (CFB), the integrator output voltage (CI-OUT) decreases from the integrator reference voltage (Vref), and conversely, as the current flows out of the integrator capacitor (CFB) Accordingly, the integrator output voltage (CI-OUT) increases from the integrator reference voltage (Vref) (see Figure 8). The slope of change (i.e., falling slope or rising slope) of the integrator output voltage (CI-OUT) is proportional to the magnitude of the current.

Meanwhile, the first input terminal of the positive type amplifier becomes the non-inverting input terminal (+) of the integrator amplifier (AMP), and the second input terminal becomes the inverting input terminal (-) of the integrator amplifier (AMP). In this positive type amplifier, the direction of change of the integrator output voltage is opposite to that of the negative type amplifier. In other words, in a positive type amplifier, as current flows into the integrator capacitor (CFB), the integrator output voltage (CI-OUT) increases from the integrator reference voltage (Vref), and conversely, as current flows out of the integrator capacitor (CFB), the integrator output voltage (CI-OUT) increases from the integrator reference voltage (Vref). The voltage (CI-OUT) is lowered from the integrator reference voltage (Vref). The slope of change (i.e., falling slope or rising slope) of the integrator output voltage (CI-OUT) is proportional to the magnitude of the current.

The technical idea of the present invention can be applied to a negative amplifier (AMP) and a positive amplifier (AMP). For convenience, the embodiment of the present invention will be described focusing on the negative amplifier (AMP).

The current radiation unit (ICP) stores the pixel current (IPIX) flowing from the pixel (PXL) as a sampling voltage in the vertical blank period (VB) and generates a radiation current according to the sampling voltage in the vertical active period (VA).

This current radiation unit (ICP) may include a first transistor (TR1), a sampling switch (SWx), and a sampling capacitor (Cx). The first transistor TR1 has a first electrode connected to the second node Nb, a second electrode connected to the base voltage source VSS, and a gate electrode connected to the third node Nc. Here, the second node (Nb) is connected to the first node (Na) in the vertical blank period (VB) and to the first input terminal (-) in the vertical active period (VA). Additionally, the sampling switch (SWx) remains on in the vertical blank period (VB) and remains off in the vertical active period (VA). When the pixel current IPIX flows through the first transistor TR1 in the vertical blank period VB, the gate-source voltage Vgs of the first transistor TR1 is stored as a sampling voltage in the sampling capacitor Cx. . The gate-source voltage (Vgs) of the first transistor (TR1) is set according to the pixel current (IPIX) in the vertical blank period (VB) and maintained at the set value in the vertical active period (VA) by the sampling capacitor (Cx). do. Additionally, the radiation current is a current flowing in the first transistor TR1 according to the gate-source voltage (Vgs) of the first transistor TR1 in the vertical active period (VA). Therefore, the radiation current is substantially equal to the pixel current (IPIX).

The switching circuit unit (PSW) is connected between the current radiation unit (ICP) and the current integrator (CI) to make the first current path of the pixel current (IPIX) and the second current path of the radiation current (Icpy) different from each other.

This switching circuit unit (PSW) may include a first switch (SW1), a second switch (SW2), and a third switch (SW3). Each of the first to third switches SW1, SW2, and SW3 may be a three-terminal switch element. The first switch (SW1) selectively connects the sensing line (SL) connected to the pixel (PXL) and the first input terminal (-) in the vertical blank period (VB), and the second node (-) in the vertical active period (VA) It serves to selectively connect Nb) and the first input terminal (-). The second switch (SW2) disconnects the output terminal of the integrator amplifier (AMP) and the first node (Na) in the vertical blank period (VB), and disconnects the output terminal of the integrator amplifier (AMP) and the first node (Na) in the vertical blank period (VA). It serves to selectively connect the first node (Na). The third switch (SW3) selectively connects the first node (Na) and the second node (Nb) in the vertical blank period (VB), and connects the second node (Nb) to the first input in the vertical active period (VA). It serves to selectively connect the terminal (-).

Meanwhile, the switching circuit unit (PSW) may further include a second transistor (TR2) to ensure operational stability. The second transistor (TR2) has a gate electrode connected to the output terminal of the integrator amplifier (AMP) through the second switch (SW2) in the vertical blank period (VB) and floating in the vertical active period (VA), and a first node ( a first electrode connected to Na) and a second electrode connected to the second node (Nb) through the third switch (SW3) in the vertical blank period (VB) and floating in the vertical active period (VA). have

The sample and hold circuit samples and holds the integrator output voltage (CI-OUT) and then outputs it to the ADC. Then, the ADC converts the analog signal (i.e., integrator output voltage) into a digital signal (i.e., digital sensing result data) according to a predetermined sensing range.

FIGS. 9A and 9B are diagrams showing the operation of the pixel sensing device of FIG. 7. The operation of the pixel sensing device is further described in conjunction with FIG. 8 as follows.

8 and 9A show the operation of the pixel sensing device during the vertical blank period (VB).

Referring to FIGS. 8 and 9A, during the vertical blank period (VB), the first and second input terminals (-, +) and the first node (Na) of the integrator amplifier (AMP) are connected to the integrator reference voltage (Vref). It is initialized. Therefore, the integrator output voltage (CI-OUT) maintains the integrator reference voltage (Vref) during the vertical blank period (VB).

Referring to FIGS. 8 and 9A , in the vertical blank period VB, the pixel current IPIX is applied to the current radiating unit ICP along the first current path. That is, in the vertical blank period (VB), the pixel current (IPIX) is transmitted through the first switch (SW1), the reset switch (RST), the second transistor (TR2), and the third switch (SW3) through the current radiation unit (ICP). ) is approved. Then, the pixel current IPIX flows through the first transistor TR1 of the current radiation unit ICP.

Referring to FIGS. 8 and 9A, when the pixel current (IPIX) flows through the first transistor (TR1) in the vertical blank period (VB), the sampling switch (SWx) is turned on to connect the first transistor (TR1) to the diode. Therefore, the gate-source voltage (Vgs) of the first transistor (TR1) is stored in the sampling capacitor (Cx). The gate-source voltage (Vgs) of the first transistor (TR1) is a value determined according to the size of the pixel current (IPIX).

Considering the power consumption of the electroluminescent display device, the pixel current (IPIX) is low current. Therefore, the current mirror sensing method that senses the pixel current using the vertical blank period may have insufficient sensing time. Moreover, because the vertical blank period is becoming shorter due to the current technology trend of higher resolution and higher speed operation, it is practically impossible for the current mirror sensing method to sense low current in the vertical blank period.

On the other hand, in the vertical blank period (VB), the present invention does not directly sense the pixel current (IPIX) through a current integration method using an integrator capacitor (CFB), but detects the gate-source voltage (Vgs) of the first transistor (TR1). ) is set. In the vertical blank period (VB), the first transistor (TR1) is diode-connected, so the gate-source voltage (Vgs) can be quickly set. Therefore, in the present invention, there is no problem even if the vertical blank period (VB) is shortened.

8 and 9B show the operation of the pixel sensing device during the vertical active period (VA).

Referring to FIGS. 8 and 9B, during the vertical active period VA, the reset switch RST and the second transistor TR2 are turned off, so that the first current path of the pixel current IPIX is released. In contrast, a second current path is formed by the radiation current (Icpy) flowing through the first transistor (TR1). The radiation current Icpy is a current determined by the gate-source voltage Vgs of the first transistor TR1 stored in the sampling capacitor Cx, and is substantially the same as the pixel current IPIX.

The conventional current mirror method copies current by setting the same gate-source voltage to the two transistors forming the mirror, so if there is a process deviation between the two transistors, an error occurs between the pixel current and the radiation current. . In contrast, the present invention copies the current by setting the gate-source voltage to one transistor (i.e., the first transistor TR1). Therefore, the present invention can sense the same current without transistor processing errors.

The second current path of the radiation current Icpy is a current that sinks from the integrator capacitor CFB to the first transistor TR1 via the first switch SW1 and the third switch SW3. In other words, the radiated current (Icpy) is the current flowing out of the integrator capacitor (CFB) in the vertical active period (VA). Accordingly, the integrator output voltage (CI-OUT) increases from the integrator reference voltage (Vref) by the radiation current (Icpy) sinking into the first transistor (TR1) in the vertical active period (VA).

Referring to FIGS. 8 and 9B, during the vertical active period (VA), the current integrator (CI) senses the magnitude of the radiation current (Icpy) and outputs it as the integrator output voltage (CI-OUT). Since the radiation current (Icpy) and the pixel current (IPIX) have the same size, the pixel current (IPIX) and size can be sensed through the sensing result of the radiation current (Icpy). Since the current integrator (CI) is disconnected from the sensing line (SL) during this vertical active period (VA), the pixel sensing device of the present invention senses independently of the image display operation of the display panel during the vertical active period (VA). The action can be performed. The vertical active period (VA) is a very long time compared to the vertical blank period (VB). Therefore, since the present invention can sense the radiated current (Icpy) through the vertical active period (VA), that is, a current integration method using an integrator capacitor (CFB) for a sufficient period of time, more accurate sensing is possible.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

10: display panel 15: gate driver
20: Driver IC 21: Timing control unit
22: Sensing unit

Claims (10)

A first transistor having a first electrode connected to a second node, a second electrode connected to a base voltage source, and a gate electrode connected to a third node, a sampling switch connected between the second node and the third node, and the first transistor. 3 nodes and a sampling capacitor connected to the base voltage source, storing the pixel current flowing from the pixel as a sampling voltage during a vertical blank period when writing of image data to the pixel in one frame is stopped, and storing the pixel current as a sampling voltage in the pixel in one frame. a current radiation unit that generates a radiation current according to the sampling voltage in a vertical active period in which the image data is written;
An integrator amplifier having a first input terminal through which the pixel current flows in the vertical blank period and the radiation current flows into the vertical active period, and a second input terminal through which an integrator reference voltage is input, A current integrator that bypasses the pixel current to the current radiation unit through a first node, generates an integrator output voltage that changes from the integrator reference voltage according to the radiation current in the vertical active period, and outputs it to the first node. ; and
A switching circuit unit connected between the current radiation unit and the current integrator to make a first current path of the pixel current and a second current path of the radiation current different from each other,
The switching circuit unit,
a first switch selectively connecting a sensing line connected to the pixel and the first input terminal in the vertical blank period and selectively connecting the second node and the first input terminal in the vertical active period;
a second switch that disconnects the output terminal of the amplifier and the first node in the vertical blank period and selectively connects the output terminal of the amplifier and the first node in the vertical active period; and
A pixel sensing device including a third switch selectively connecting the first node and the second node in the vertical blank period and selectively connecting the second node and the first input terminal in the vertical active period. According to claim 1,
The current integrator is,
Further comprising an integrator capacitor and a reset switch connected in parallel to the first input terminal and the first node,
The reset switch maintains an on state in the vertical blank period and an off state in the vertical active period. According to claim 1,
the second node is connected to the first node in the vertical blank period and to the first input terminal in the vertical active period,
The sampling switch remains on in the vertical blank period and remains off in the vertical active period. According to claim 1,
When the pixel current flows through the first transistor in the vertical blank period, the voltage between the gate and source of the first transistor is stored in the sampling capacitor as the sampling voltage. According to claim 4,
The radiation current is a current flowing in the first transistor according to the gate-source voltage of the first transistor in the vertical active period. According to claim 5,
A pixel sensing device wherein the radiation current is equal to the pixel current. delete According to claim 1,
The switching circuit further includes a second transistor,
The second transistor is,
a gate electrode connected to an output terminal of the amplifier through the second switch in the vertical blank period and floating in the vertical active period;
A first electrode connected to the first node,
A pixel sensing device having a second electrode connected to the second node through the third switch in the vertical blank period and floating in the vertical active period. According to claim 1,
The first input terminal is an inverting terminal, and the second input terminal is a non-inverting terminal,
A pixel sensing device in which the integrator output voltage rises from the integrator reference voltage according to the radiation current. A display panel including at least one pixel and a sensing line connected to the pixel; and
An electroluminescent display device including the pixel sensing device of any one of claims 1 to 6, 8, and 9, which is connected to the pixel through the sensing line and senses driving characteristics of the pixel.