KR20210065078A - Array substrate and organic light emitting display device including the same - Google Patents

Abstract

An array substrate and an organic light emitting diode display device including the same are provided. The array substrate according to one embodiment of the present invention includes: a substrate; a barrier layer disposed on the substrate; a buffer layer disposed on the barrier layer; a first insulating film disposed on the buffer layer; a second insulating film disposed on the first insulating layer; a plurality of wiring patterns interposed between the first insulating film and the second insulating film or disposed on the second insulating film, spaced apart from each other, and extending toward one side of the substrate; a recess pattern recessed by a predetermined depth from the upper surface of the second insulating film to at least partially expose the upper surface of the substrate; and an organic insulating film disposed on the second insulating layer and at least partially exposing a top surface of the substrate exposed by the recess pattern.

Description

Array substrate and organic light emitting display device including same {ARRAY SUBSTRATE AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to an array substrate and a display device including the same, and more particularly, to an array substrate including a display area and a non-display area, and a display device including the same.

A display device such as a liquid crystal display (LCD) or an organic light emitting display (OLED) may include an array substrate including a display area and a non-display area disposed outside the display area. The display device as described above is a basic component for displaying an image, and includes a plurality of pixels in a display area, and each pixel includes a switching element for independent driving.

Meanwhile, the array substrate is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic light emitting display device, or the like. A gate line transmitting a scan signal, a data line transmitting an image signal, a thin film transistor, and various organic or inorganic insulating films are disposed on the array substrate. Among them, the thin film transistor is a semiconductor forming a channel with a gate electrode, which is a part of the gate wiring. It consists of a layer, a source electrode and a drain electrode that are part of the data wiring, and serves as a switching element.

A plurality of wirings connected to gate lines or data lines of the display area are disposed in the non-display area disposed outside the display area. The plurality of wirings may extend in various forms, and one end thereof may be connected to pads disposed in a pad portion of the lower array substrate.

Such an array substrate may be exposed to various impacts from the manufacturing process thereof. Specifically, a certain impact may be applied to the array substrate when transporting the array substrate or performing various inspection tasks, and cracks may be formed in the array substrate by such impact. Such cracks have a tendency to grow or propagate through the inorganic insulating film layer disposed on the substrate. That is, for example, when a crack is generated in a portion of the non-display area, the crack may propagate to the display area through the inorganic insulating layer, which may result in poor reliability of the display area. In order to solve these problems, various technical attempts are being made on the structure of the array substrate resistant to impact and the structure of the array substrate capable of suppressing the propagation of cracks generated in the non-display area.

An object of the present invention is to provide an array substrate having a structure that prevents the occurrence of cracks.

Another object to be solved by the present invention is to provide an array substrate having a structure that suppresses propagation of generated cracks.

Another object of the present invention is to provide an organic light emitting diode display having a structure that prevents cracks from occurring.

Another object of the present invention is to provide an organic light emitting diode display having a structure for suppressing propagation of generated cracks.

The problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

An array substrate according to an embodiment of the present invention for solving the above problems is provided with a substrate, a barrier layer disposed on the substrate, a buffer layer disposed on the barrier layer, a first insulating layer disposed on the buffer layer, and a first insulating layer disposed on the first insulating layer a plurality of wiring patterns interposed between the first insulating film and the second insulating film, or disposed on the second insulating film, spaced apart from each other and extending toward one side of the substrate, a predetermined depth recessed from the upper surface of the second insulating film and a recess pattern at least partially exposing the top surface of the substrate and an organic insulating layer disposed on the second insulating layer and at least partially exposing the top surface of the substrate exposed by the recess pattern.

An array substrate according to an embodiment of the present invention for solving the above problems includes a display area and a non-display area disposed outside the display area, wherein the non-display area includes a substrate, a barrier layer disposed on the substrate, and a barrier layer a buffer layer disposed on the buffer layer, a first insulating layer disposed on the buffer layer, a second insulating layer disposed on the first insulating layer, interposed between the first insulating layer and the second insulating layer, or disposed on the second insulating layer, the substrate being spaced apart from each other a plurality of wiring patterns extending toward one side of the plurality of wiring patterns, a recess pattern recessed by a predetermined depth from the upper surface of the second insulating film to at least partially expose the upper surface of the substrate, and disposed on the second insulating film, by the recess pattern and an organic insulating layer at least partially exposing the exposed upper surface of the substrate.

An organic light emitting diode display according to an exemplary embodiment is an array substrate having a display area and a non-display area disposed outside the display area, wherein the non-display area is disposed on a substrate, a barrier layer disposed on the substrate, and the barrier layer a buffer layer, a first insulating film disposed on the buffer layer, a second insulating film disposed on the first insulating film, interposed between the first insulating film and the second insulating film, or disposed on the second insulating film, spaced apart from each other to form one side of the substrate a plurality of wiring patterns extending toward the upper surface, a recess pattern recessed by a predetermined depth from the upper surface of the second insulating film to at least partially expose the upper surface of the substrate; and a plurality of wiring patterns disposed on the second insulating film and exposed by the recess pattern An array substrate including an organic insulating layer at least partially exposing an upper surface of the substrate, and an encapsulation member disposed on the array substrate.

The details of other embodiments are included in the detailed description and drawings.

According to the embodiments of the present invention, there are at least the following effects.

That is, it is possible to prevent cracks from occurring in the array substrate due to an external impact.

In addition, it is possible to suppress the growth or propagation of cracks generated by external impact.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a plan view of an array substrate according to an embodiment of the present invention;
Figure 2 is a partial enlarged view of part 'A' of Figure 1,
FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 2 .
4 is a partial enlarged view of part 'B' of FIG. 1,
5 is a cross-sectional view taken along line II-II' of FIG. 4;
6 is a cross-sectional view taken along line III-III' of FIG. 4;
7 is a cross-sectional view taken along line IV-IV' of FIG. 4 .
8 is a partially enlarged view of an array substrate according to a modification of FIG. 4 .
9 is a partially enlarged view of an array substrate according to a modified example of FIG. 8 .
FIG. 10 is a partially enlarged view of an array substrate according to a modified example of FIG. 4 .
11 is a cross-sectional view taken along line V-V' of FIG. 10 .
12 is a cross-sectional view taken along line VI-VI' of FIG. 10 .
13 is a cross-sectional view of an array substrate according to a modified example of FIG. 11 .
14 is a cross-sectional view of an array substrate according to a modified example of FIG. 12 .
15 is a partially enlarged view of an array substrate according to a modified example of FIG. 10 .
16 is a cross-sectional view taken along line VII-VII' of FIG. 15 .
17 is a cross-sectional view of an array substrate according to a modification of FIG. 6 .
18 is a cross-sectional view of an array substrate according to a modification of FIG. 7 .
19 is a partially enlarged view of an array substrate according to another embodiment of the present invention.
20 is a cross-sectional view taken along line VIII-VIII' of FIG. 19 .
21 is a partially enlarged view of an array substrate according to another embodiment of the present invention.
22 is a plan view of an array substrate according to another embodiment of the present invention.
23 is a partially enlarged view of part 'C' of FIG. 22 .
24 is a cross-sectional view taken along line IX-IX' of FIG. 23 .
FIG. 25 is a partially enlarged view of part 'D' of FIG. 22 .
26 is a cross-sectional view taken along line X-X of FIG. 25 .
27 is a cross-sectional view of an organic light emitting diode display according to an exemplary embodiment.
28 is a cross-sectional view of an organic light emitting diode display according to another exemplary embodiment.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

Reference to an element or layer “on” another element or layer includes any intervening layer or other element directly on or in the middle of the other element or layer. Like reference numerals refer to like elements throughout.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first component mentioned below may be the second component within the spirit of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a plan view of an array substrate according to an embodiment of the present invention, FIG. 2 is an enlarged partial view of part 'A' of FIG. 1, and FIG. 3 is a view taken along line Ⅰ-I' of FIG. It is a cross section.

1 to 3 , the array substrate 100 according to an exemplary embodiment may include a display area DA and a non-display area NDA disposed outside the display area DA. .

The display area DA may include a plurality of gate lines 50 extending in one direction and a plurality of data lines 60 extending in a direction crossing the gate lines 50 . Also, a pixel area surrounded by the plurality of gate lines 50 and data lines 60 may be defined. A thin film transistor connected to the gate line 50 and the data line 60 may be formed in each pixel area defined by the plurality of gate lines 50 and data lines 60 .

2 and 3 are referenced for a detailed description of the display area DA.

The substrate 10 is a member having a plate shape, and may serve to support other components to be described later. The substrate 10 is an insulating substrate and may be formed of a polymer material including glass or plastic. In an exemplary embodiment, the substrate 10 may be formed of poly imide (PI), but this is exemplary and the material of the substrate 10 is not limited thereto.

The substrate 10 may be a rigid substrate 10 , but is not limited thereto, and may be a flexible or flexible substrate 10 . That is, in this specification, the term "substrate" may be understood as a concept including a flexible substrate capable of bending, folding, or rolling.

As shown in FIG. 2 , the substrate 10 may have a single-layer structure, but is not limited thereto. That is, in another exemplary embodiment, the substrate 10 may have a stacked structure in which two or more layers are stacked. In other words, the substrate 10 may include a base layer and a protective layer disposed on the base layer.

The base layer may be formed of an insulating material. In an exemplary embodiment, the base layer may be formed of poly imide (PI), but the material of the base layer is not limited thereto. A protective layer may be disposed on the base layer. The protective layer may be made of an organic material or an inorganic material. For example, the protective layer may include any one or more selected from polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), but this is exemplary and the material of the protective layer is not limited thereto. .

A barrier layer 11 may be disposed on the substrate 10 . The barrier layer 11 may serve to prevent penetration of impurity elements from the substrate 10 . In an exemplary embodiment, the barrier layer 11 may include at least one selected from the group consisting of silicon oxide (SiOx) and silicon nitride (SiNx), but the material of the barrier layer 11 is not limited thereto. The barrier layer 11 may have a single layer structure or a stacked structure in which two or more layers are stacked. In an exemplary embodiment in which the barrier layer 11 has two layers, the two layers are formed of different materials. can be For example, the first layer may be made of silicon oxide and the second layer may be made of silicon nitride. However, this is exemplary and the structure of the barrier layer 11 is not limited thereto.

Also, in another exemplary embodiment, the barrier layer 11 may be omitted depending on the material of the substrate 10 or process conditions.

A buffer layer 12 covering the barrier layer 11 may be disposed on the barrier layer 11 . The buffer layer 12 may be an inorganic layer formed of an inorganic material. In an exemplary embodiment, the buffer layer 12 may be formed including at least one selected from the group consisting of silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), and silicon oxynitride (SiON), but the buffer layer ( 12) is not limited thereto. In addition, the buffer layer 12 may have a single layer structure or a stacked structure in which two or more layers are stacked. In an exemplary embodiment in which the buffer layer 12 has two layers, the two layers are formed of different materials. can be For example, the first layer may be made of silicon oxide and the second layer may be made of silicon nitride. However, this is exemplary and the structure of the buffer layer 12 is not limited thereto.

The semiconductor layer 40 may include amorphous silicon or polycrystalline silicon. In an exemplary embodiment, the semiconductor layer 40 may be formed by applying and patterning amorphous silicon and then crystallizing it, but the method of forming the semiconductor layer 40 is not limited thereto. In addition, it may be understood that what is referred to as a “semiconductor layer” in this specification includes an oxide semiconductor.

A gate insulating layer 20 may be formed on the semiconductor layer 40 . The gate insulating layer 20 may include silicon nitride (SiNx) or silicon oxide (SiOx), but the material of the gate insulating layer 20 is not limited thereto. The gate insulating layer 20 may have a single layer structure, but is not limited thereto, and may have a multilayer structure including at least two insulating layers having different physical properties.

A gate wiring including a gate line 50 , a gate electrode 51 , and a gate pad 55 may be disposed on the gate insulating layer 20 . Gate wiring consists of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, and molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys. , chromium (Cr), tantalum (Ta) and titanium (Ti) may be formed including any one or more materials selected from the group consisting of, but the material of the gate wiring is not limited thereto, and as a conductive material, transparent or A translucent material may be used to form the gate wiring.

As described above, a plurality of gate lines 50 may extend in one direction to be parallel to each other.

An interlayer insulating layer 30 covering the gate wiring may be disposed on the gate wiring. The interlayer insulating layer 30 may be an inorganic layer formed of an inorganic material. In an exemplary embodiment, the interlayer insulating layer 30 may include silicon nitride (SiNx) or silicon oxide (SiOx), but the material of the interlayer insulating layer 30 is not limited thereto. The interlayer insulating layer 30 may have a single layer structure, but is not limited thereto, and may have a multilayer structure including at least two insulating layers having different physical properties. The interlayer insulating film 30 having a multilayer structure will be described later.

A data line including a source electrode 61 , a drain electrode 62 , and a data line 60 may be disposed on the interlayer insulating layer 30 . The data wiring may be formed of a refractory metal such as molybdenum, chromium, tantalum and titanium or an alloy thereof, but the material of the data wiring is not limited thereto, and a transparent or translucent material as a conductive material is used to form the data wiring. can be used

The data line 60 transmits a data signal and may be disposed to cross the gate line 50 . That is, in the exemplary embodiment, the gate line 50 may extend in a horizontal direction, and the data line 60 may extend in a vertical direction to intersect the same.

2 illustrates a case in which the data line 60 and the gate line 50 have a straight line shape, but in an exemplary embodiment, the data line 60 and the gate line 50 may include bent portions. However, this is obvious to those skilled in the art, and detailed description thereof will be omitted to avoid obscuring the scope of the present invention.

The source electrode 61 is a part of the data line 60 and may be disposed on the same line as the data line 60 . The drain electrode 62 may be formed to extend parallel to the source electrode 61 . In this case, the drain electrode 62 may be parallel to a portion of the data line 60 .

The gate electrode 51 , the source electrode 61 , and the drain electrode 62 form one thin film transistor (TFT) together with the semiconductor layer 40 , and a channel of the thin film transistor is a source electrode It may be formed in the semiconductor layer 40 between the 61 and the drain electrode 62 .

A planarization layer 70 covering the data line and the interlayer insulating layer 30 may be disposed on the data line. The thickness of the planarization layer 70 may be relatively thicker than that of the interlayer insulating layer 30 . Due to the thickness difference, the upper surface of the planarization film 70 may be relatively flat compared to the lower surface in contact with the interlayer insulating film 30 and the source/drain electrodes 62 . The planarization layer 70 may include, for example, at least one material selected from the group consisting of acryl, benzocyclic butene (BCB), and polyimide in order to alleviate the step difference on the substrate 10 , but is not limited thereto. In addition, the planarization layer 70 may be made of a photosensitive material.

A first contact hole 71 exposing at least partially exposing the drain electrode 62 may be formed in the planarization layer 70 . Specifically, the first contact hole 71 may pass through the planarization layer 70 and partially expose the top surface of the drain electrode 62 .

A first electrode 80 may be disposed on the planarization layer 70 and the exposed drain electrode 62 . That is, the first electrode 80 may be disposed to cover the planarization layer 70 , the sidewall of the first contact hole, and the upper surface of the drain electrode 62 , whereby the first electrode 80 and the drain electrode 62 . This can be electrically connected. In an exemplary embodiment, the first electrode 80 may be an anode electrode, but is not limited thereto. The first electrode 80 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO), but the material of the first electrode 80 is not limited thereto. A pixel defining layer, an organic layer, and a second electrode may be disposed on the first electrode 80 . A detailed description thereof will be provided later.

Hereinafter, the non-display area NDA of the array substrate according to an embodiment of the present invention will be described.

Referring back to FIG. 1 , the non-display area NDA disposed outside the display area DA includes a scan driver 200 , an emission driver 300 , and a scan driver 200 and an emission driver 300 . Alternatively, a plurality of wiring patterns connected to the display area DA may be disposed. The wiring pattern is disposed at one end of the scan driver 200 , the emission driver 300 or the wiring line unit 401 extending from the display area DA and the wiring line unit 401 , and the other end of the wiring line unit ( The wiring pad part 402 having a width wider than that of the 401 may be included. A detailed description of the structure of the wiring pattern will be described later.

For a more detailed description of the non-display area NDA, reference is made to FIGS. 4 to 7 .

4 is a partially enlarged view of part 'B' of FIG. 1 , FIG. 5 is a cross-sectional view taken along line II-II' of FIG. 4 , and FIG. 6 is a cross-sectional view cut along line Ⅲ-III' of FIG. 4 . It is a cross-sectional view, and FIG. 7 is a cross-sectional view taken along line IV-IV' of FIG. 4 .

4 to 7 , the non-display area NDA of the array substrate according to an embodiment of the present invention includes a substrate 10 , a barrier layer 11 disposed on the substrate 10 , and a barrier layer 11 . The buffer layer 12 disposed thereon, the first insulating layer 25 disposed on the buffer layer 12 , the second insulating layer 35 disposed on the first insulating layer 25 , the first insulating layer 25 and the second A plurality of wiring patterns interposed between the insulating layers 35 or disposed on the second insulating layer 35, spaced apart from each other and extending toward one side of the substrate 10, a predetermined depth from the upper surface of the second insulating layer 35 A recess pattern that is recessed to at least partially expose the upper surface of the substrate 10 and an organic insulating film 75 disposed on the second insulating film and at least partially exposing the upper surface of the substrate exposed by the recess pattern includes

Since the substrate 10 , the barrier layer 11 , and the buffer layer 12 may be substantially the same as those described with reference to FIGS. 1 to 3 , a description thereof will be omitted.

A first insulating layer 25 may be disposed on the buffer layer 12 . The first insulating layer 25 may be an inorganic insulating layer formed of an inorganic material. The first insulating layer 25 may include, for example, silicon nitride (SiNx) or silicon oxide (SiOx), but this is an example and the material of the first insulating layer 25 is not limited thereto.

In an exemplary embodiment, the first insulating layer 25 may be formed of substantially the same material as the gate insulating layer 20 of the display area DA. In other words, the first insulating layer 25 of the non-display area NDA may be formed substantially simultaneously with the gate insulating layer 20 of the display area DA. However, this is not limited thereto, and the first insulating layer 25 of the non-display area NDA and the gate insulating layer 20 of the display area DA may be independently formed as separate components.

A second insulating layer 35 may be disposed on the first insulating layer 25 . Like the first insulating layer 25 , the second insulating layer 35 may be an inorganic insulating layer formed of an inorganic material. Like the first insulating layer 25 , the second insulating layer 35 may also include silicon nitride (SiNx) or silicon oxide (SiOx). The first insulating layer 25 and the second insulating layer 35 may be formed of different materials, but the present invention is not limited thereto, and the first insulating layer 25 and the second insulating layer 35 may be formed of the same material. have. In an exemplary embodiment, the second insulating layer may be made of substantially the same material as the interlayer insulating layer of the display area. That is, the second insulating layer may be formed substantially simultaneously with the interlayer insulating layer of the display area. However, this is not limited thereto, and the interlayer insulating layer of the display area and the second insulating layer of the non-display area are independent and separate components, and may be formed independently.

A wiring pattern may be disposed on the first insulating layer 25 or the second insulating layer 35 . In other words, the wiring pattern may be disposed on the first insulating layer 25 , interposed between the first insulating layer 25 and the second insulating layer 35 , or disposed on the second insulating layer 35 . Also, in an exemplary embodiment, a portion of the wiring pattern may be formed on the first insulating layer 25 , and the remainder may be formed on the second insulating layer 35 .

The wiring pattern may be connected to the display area DA, the scan driver 200 or the emission driver 300 to transmit or receive a signal. For this purpose, the wiring pattern consists of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, and molybdenum such as molybdenum (Mo) or a molybdenum alloy It may be formed of at least one material selected from the group consisting of a series metal, chromium (Cr), tantalum (Ta), and titanium (Ti), but the material of the wiring pattern is not limited thereto, and a conductive conductor having conductivity can be used to form a wiring pattern.

In an exemplary embodiment, the wiring pattern may include a wiring line part 401 , a wiring pad part 402 , and a wiring connection part 403 .

* The wiring line unit 401 is electrically connected to the display area DA, the scan driver 200 or the emission driver 300 , and the display area DA, the scan driver 200 or the emission driver 300 . It may be formed extending toward one side of the substrate 10 from the. A plurality of wiring line units 401 may be disposed to be spaced apart from each other by a predetermined interval, and each wiring line unit 401 may extend in a straight line or may have at least one bent portion and extend toward one side of the substrate 10 .

In an exemplary embodiment, the wiring line unit 401 may be disposed on the first insulating layer 25 . That is, the wiring line part 401 may be interposed between the first insulating layer 25 and the second insulating layer 35 . The wiring line unit 401 may be formed of the same material as the gate wiring of the display area DA. In other words, the wiring line unit 401 may be formed substantially simultaneously with the gate wiring of the display area DA. However, the present invention is not limited thereto, and the wiring line unit 401 of the non-display area NDA and the gate wiring of the display area DA may be formed independently.

One end of the wiring line unit 401 may partially overlap the other end of the wiring pad unit 402 to be described later.

The wiring pad unit 402 is electrically connected to one end of the wiring line unit 401 , and may be formed to extend from one end of the wiring line unit 401 toward one side of the substrate 10 . A plurality of wire pad parts 402 may be disposed, and each wire pad part 402 may be arranged along one side of the substrate 10 . In an exemplary embodiment, one end of the extended wiring pad part 402 may contact one side of the substrate 10 , but is not limited thereto. The width of the other end of the wiring pad part 402 may be relatively larger than the width of the wiring line part 401 . An external circuit module such as a flexible printed circuit board (FPC) connected to a test device for performance test of the board 10 or the printed circuit board 10 may be connected to the wiring pad part 402. , when the wiring pad part 402 has a wider width than the wiring line part 401, electrical contact with the circuit module can be made more easily.

In an exemplary embodiment, the wiring pad part 402 may be disposed on the second insulating layer 35 . That is, the wiring pad unit 402 may be disposed to have a different level from that of the wiring line unit 401 . In other words, the wiring pad unit 402 and the wiring line unit 401 may be disposed on different layers.

The wiring line unit 401 and the wiring pad unit 402 may be electrically connected to each other. Specifically, one end of the wiring line unit 401 and the other end of the wiring pad unit 402 may be electrically connected. In the exemplary embodiment in which the wiring line part 401 is disposed on the first insulating film 25 and the wiring pad part 402 is disposed on the second insulating film 35 , the wiring pad part 402 and the wiring line The part 401 may be electrically connected through a wiring connection part 403 . For a detailed description of the wiring connection portion 403 , reference is made to FIG. 5 .

Referring to FIG. 5 , a second insulating layer 35 is disposed on the wiring line unit 401 , and the second insulating layer 35 may at least partially expose the wiring line unit 401 . That is, since the wiring pad part 402 is disposed on the wiring line part 401 exposed by the second insulating layer 35 , the wiring pad part 402 and the wiring line part 401 may be electrically connected.

At least one recess pattern 500 may be disposed to be adjacent to the plurality of wiring patterns. The recess pattern 500 may be formed by being recessed at a predetermined interval from the upper surface of the second insulating layer 35 . The recess pattern 500 formed by being recessed at a predetermined distance from the top surface of the second insulating layer 35 may at least partially expose the top surface of the substrate 10 . In other words, the bottom surface of the recess pattern 500 may at least partially include the top surface of the substrate 10 .

In other words, the recess pattern 500 penetrates the barrier layer 11 , the buffer layer 12 , the first insulating layer 25 , and the second insulating layer 35 , and at least partially exposes the upper surface of the substrate 10 . can do it That is, in the exemplary embodiment, the bottom surface of the recess pattern 500 is formed as the top surface of the substrate 10 , and the sidewalls of the recess pattern 500 are the barrier layer 11 , the buffer layer 12 , and the first The insulating layer 25 and the inner surface of the second insulating layer 35 may be formed. However, the present invention is not limited thereto, and when an intermediate layer is interposed between the second insulating layer 35 and the substrate 10 or another layer is disposed on the second insulating layer 35 , the sidewall of the recess pattern 500 . The silver layer may include an inner surface of the intermediate layer and an inner surface of another layer disposed on the second insulating layer 35 . A detailed description thereof will be provided later.

In an exemplary embodiment, the at least one recess pattern 500 may be disposed adjacent to the wiring line unit 401 or between one wiring line unit and another wiring line unit.

4 and 6 illustrate that the recess pattern 500 is adjacent to the wiring line unit 401 but spaced apart from the wiring line unit 401 by a predetermined interval, but is not limited thereto, and the recess pattern 500 is not limited thereto. ) may be formed to be at least partially in contact with the wiring line unit 401 .

As described above, when the recess pattern 500 penetrating the at least one inorganic insulating film is formed on the substrate 10 , the propagation of cracks generated by the impact applied in the manufacturing process of the array substrate, the inspection process, and the transport process, etc. can be suppressed. That is, cracks generated by various impacts have a tendency to grow or propagate through the inorganic insulating film of the substrate 10. As described above, when the recess pattern 500 from which the inorganic insulating film is removed is disposed, the recess pattern ( 500) by blocking the path along which the crack proceeds, it is possible to suppress the propagation of the crack. That is, cracks generated in the non-display area NDA may be prevented from growing to reach the display area DA. In other words, the recess pattern 500 may serve as a crack stopper.

An organic insulating layer 75 may be disposed on the second insulating layer 35 . The organic insulating layer 75 may be made of an organic material. For example, the organic insulating layer 75 may include at least one material selected from the group consisting of acryl, benzocyclic butene (BCB), and polyimide, but is not limited thereto. In addition, the organic insulating layer 75 may be made of a photosensitive material. .

The organic insulating layer 75 disposed on the second insulating layer 35 in the region where the wiring line part 401 is formed may at least partially expose the recess pattern 500 . (See FIG. 6 ) That is, the organic insulating layer 75 may at least partially expose the upper surface of the substrate 10 exposed by the recess pattern 500 . In other words, the organic insulating layer 75 may expose all or part of the upper surface of the substrate 10 exposed by the recess pattern 500 .

In the region where the wiring pad unit 402 is disposed, the organic insulating layer 75 may cover the second insulating layer 35 and a portion of the wiring pad unit 402 disposed on the second insulating layer 35 . (See FIG. 7 ) That is, the organic insulating layer 75 may expose a portion of the wiring pad part 402 . In other words, the organic insulating layer 75 may include a contact part 72 penetrating through the organic insulating layer 75 and at least partially exposing the upper surface of the wiring pad part 402 . As described above, to the wiring pad part 402, various test devices for inspecting the performance of the board 10 or a flexible printed circuit board 10 (Flexible Printed Circuit, FPC) connected to the printed circuit board 10 may be connected. can That is, by exposing the wiring pad unit 402 , the contact unit may induce the device and the like to be connected to the wiring pad unit 402 .

In an exemplary embodiment, the organic insulating layer 75 may be formed of substantially the same material as the planarization layer 70 of the display area DA. In other words, the organic insulating layer 75 may be formed simultaneously with the formation of the planarization layer 70 in the display area DA. However, this is by way of example and is not limited thereto, and the planarization layer 70 of the display area DA and the organic insulating layer 75 of the non-display area NDA are separate, and may be independently formed. have.

Hereinafter, other embodiments of the present invention will be described. In the following embodiments, the same components as those already described are referred to by the same reference numerals, and duplicate descriptions will be omitted or simplified.

8 is a partially enlarged view of an array substrate according to a modification of FIG. 4 . Referring to FIG. 8 , the array substrate according to the modified example of the present invention is different from the embodiment of FIG. 4 in that a plurality of recess patterns 507 are formed between one wiring line unit and another adjacent wiring line unit. to be.

At least one recess pattern 507 may be disposed between one wiring line unit and another adjacent wiring line unit. 8 illustrates that three recess patterns 507 are arranged in a line between one wiring line unit and another adjacent wiring line unit, but the number and arrangement of the recess patterns 507 are limited thereto. doesn't happen That is, there may be a plurality of recess patterns 507 , and the plurality of recess patterns 507 may be arranged in a line or in a matrix shape having a plurality of columns and rows. This will be described later.

9 is a partially enlarged view of an array substrate according to a modified example of FIG. 8 . Referring to FIG. 9 , in an array substrate according to a modified example of the present invention, a plurality of recess patterns 508 are disposed between one wiring line part and another adjacent wiring line part, and the plurality of recess patterns 508 are disposed. It is different from the modified example of FIG. 8 in that it is arranged in a matrix having columns and rows.

As described above, a plurality of recess patterns 508 may be disposed between one wiring line unit and another adjacent wiring line unit. The plurality of recess patterns 508 may be arranged in a line or may be arranged in a matrix shape having a plurality of columns and rows. 9 illustrates that the plurality of recess patterns 508 are in the form of 3 rows by 2 columns, but this is exemplary and the arrangement shape of the recess patterns 508 is not limited thereto. That is, the number of rows and the number of columns may be greater than or equal to two. In addition, although FIG. 9 illustrates that the plurality of recess patterns 508 are regularly arranged, the present invention is not limited thereto, and the plurality of recess patterns 508 may be arranged irregularly and scattered.

10 is a partially enlarged view of the array substrate according to the modified example of FIG. 4 , FIG. 11 is a cross-sectional view taken along line V-V' of FIG. 10, and FIG. 12 is a cross-sectional view taken along line VI-VI' of FIG. 10 . It is one cross section.

10 to 12 , in the array substrate according to the modified example of FIG. 4 , a recess pattern 501 disposed between the wiring line parts 401 is formed by extending between the wiring pad parts 402 . It is different from the 4th embodiment.

The recess pattern 501 disposed between one wiring line unit 401 and another wiring line unit 401 may extend between a wiring pad unit connected to one wiring line unit and a wiring pad unit connected to another wiring line unit. have. That is, the recess pattern 501 disposed between the interconnection line portions 401 adjacent to each other may extend toward one side of the substrate 10 . As described above, the width of the wiring pad part 402 may be relatively larger than the width of the wiring line part 401 . Accordingly, the width d2 of the recess pattern 501 disposed between the wiring pad parts 402 is relatively higher than the width d1 of the recess pattern 501 disposed between the wiring line parts 401 . can be small However, the present invention is not limited thereto, and the width of the recess pattern 501 disposed between the wiring line part 401 and the recess pattern 501 disposed between the wiring pad part 402 may be substantially the same. .

13 is a cross-sectional view of the array substrate according to the modified example of FIG. 11 , and FIG. 14 is a cross-sectional view of the array substrate according to the modified example of FIG. 12 .

13 and 14 , the organic insulating layer 75 disposed on the second insulating layer 35 covers the substrate 10 exposed by the recess pattern 501 in the embodiment of FIGS. 11 and 12 . is different from

As described above, the organic insulating layer 75 may be disposed on the second insulating layer 35 . In an exemplary embodiment, the organic insulating layer 75 may completely cover the upper surface of the substrate 10 exposed by the recess pattern 501 . That is, the organic insulating layer 75 includes the second insulating layer 35 , A sidewall of the recess pattern 500 and a bottom surface of the recess pattern 500 may be covered. 11 and 12 illustrate that the organic insulating film 75 completely covers the upper surface of the substrate 10 exposed by the recess pattern 501, but is not limited thereto, and the organic insulating film 75 is All or part of the upper surface of the substrate 10 exposed by the recess pattern 501 may be exposed. The contact portion 72 exposing the wiring pad portion 402 at least partially may be formed in the organic insulating layer 75 is substantially the same as that described above with reference to FIG. 7 , and thus a detailed description thereof will be omitted. .

15 is a partially enlarged view of an array substrate according to a modified example of FIG. 10 . 16 is a cross-sectional view taken along line VII-VII' of FIG. 15 .

15 and 16 , the array substrate according to the modified example of FIG. 10 is disposed inside the wiring pad unit 402 and passes through the wiring pad unit 402 to expose the upper surface of the substrate 10 . It is different from FIG. 8 in that it further includes a set groove 502 .

A recess groove 502 may be disposed inside the wiring pad part 402 . Specifically, the recess groove 502 may be disposed inside the outer periphery of the wiring pad part 402 .

The recess groove 502 sequentially penetrates the wiring pad part 402 , the second insulating layer 35 , the first insulating layer 25 , the buffer layer 12 , and the barrier layer 11 to form the upper surface of the substrate 10 . can be exposed. That is, the bottom surface of the recess groove 502 includes the top surface of the substrate 10 , and sidewalls of the recess groove 502 include the wiring pad part 402 , the second insulating layer 35 , and the first insulating layer 25 . ), the inner surface of the buffer layer 12 and the barrier layer 11 may be included.

As described above, the organic insulating layer 75 may be disposed on the second insulating layer 35 and the wiring pad part 402 . 16 exemplifies that the organic insulating film 75 exposes all of the upper surface of the substrate 10 exposed by the second insulating film 35 , the wiring pad portion 402 and the recess groove 502 . However, the present invention is not limited thereto, and the organic insulating layer 75 may at least partially cover the upper surface of the substrate 10 exposed by the recess groove 502 . When the recess groove 502 penetrating through the wiring pad unit 402 and exposing the upper surface of the substrate 10 is disposed in the wiring pad unit 402 , the wiring pad unit 402 includes a substrate 10 inspection device or When the FPC or the like is connected or disconnected, a crack generated by an impact applied to the wiring pad unit 402 is formed through the wiring pad unit 402 or an inorganic insulating film disposed under the wiring pad unit 402 to the display area DA. can be prevented from spreading.

17 is a cross-sectional view of an array substrate according to a modification of FIG. 6 . 18 is a cross-sectional view of an array substrate according to a modification of FIG. 7 .

Referring to FIGS. 17 and 18 , in the array substrate according to the modified example of FIGS. 6 and 7 , the second insulating layer 35 includes the first sub insulating layer 31 and the second sub insulating layer 32 in FIG. 6 . and different from the embodiment of FIG. 7 .

As described above, the second insulating layer 35 may have a single layer structure, but is not limited thereto, and may have a multilayer structure including at least two insulating layers. For convenience of description, the insulating layer covering the first insulating layer 25 will be referred to as the first sub insulating layer 31 and the insulating layer covering the first sub insulating layer 31 will be referred to as the second sub insulating layer 32 .

The first sub insulating layer 31 and the second sub insulating layer 32 may be inorganic insulating layers made of an inorganic material. For example, the first sub insulating layer 31 and the second sub insulating layer 32 may include at least one selected from silicon oxide and silicon nitride, but the materials of the first sub insulating layer 31 and the second sub insulating layer 32 are different. It is not limited thereto. The first sub insulating layer 31 and the second sub insulating layer 32 may be made of different materials.

The fact that the second insulating layer 35 has a multilayer structure may be due to the structure of the display area DA. Specifically, although not shown in the drawings, a storage capacitor may be disposed adjacent to the thin film transistor in the display area DA. In an exemplary embodiment, the storage capacitor includes a first gate metal disposed on the gate insulating layer 20 , a first sub insulating layer 31 disposed on the first gate metal, and a first sub insulating layer 31 disposed on the first sub insulating layer 31 . It may include the second sub insulating layer 32 and the second gate metal disposed on the second sub insulating layer 32 . Also, in response to the storage capacitor, the source/drain electrodes 62 of the thin film transistor may be disposed on the second sub insulating layer 32 . However, this is an example, and the specific structure of the display area DA is not limited thereto.

19 is a partially enlarged view of an array substrate according to another embodiment of the present invention. 20 is a cross-sectional view taken along line VIII-VIII' of FIG. 19 .

19 and 20 , in the array substrate according to another embodiment of the present invention, the wiring line part 411 extends toward one side of the substrate 10, and has a zigzag shape compared to the embodiment of FIG. 4 . It's different.

The wiring line part 411 may have at least one bent part. In an exemplary embodiment, the wiring line part 411 has a zigzag shape and may extend toward one side of the substrate 10 . For convenience of description, a direction toward one side of the substrate 10 will be defined as a first direction. Also, a direction perpendicular to the first direction will be referred to as a second direction, and a direction opposite to the second direction will be referred to as a third direction.

As shown in FIG. 19 , the wiring line portions 411 extending in the first direction extend at a predetermined interval in the second direction, extend again in the first direction at a predetermined interval, and then extend at a predetermined interval in the third direction, It may extend in the first direction again. That is, it may sequentially extend in the order of the first direction, the second direction, the first direction, the third direction, and the first direction.

In an exemplary embodiment, the distance extending in the second direction and the distance extending in the third direction may be substantially the same, but is not limited thereto.

In other words, the wiring line unit 411 sequentially extends in the order of the first direction, the second direction, the first direction, the third direction, and the first direction, and may be extended by repeating this order at least once or more. have.

As described above, when the wiring line part 411 sequentially extends in the first direction, the second direction, the first direction, the third direction, and the first direction, the second direction, the first direction and the third direction or A predetermined space may be defined inside the wiring line part 411 extending in the third direction, the first direction, and the second direction. In an exemplary embodiment, the recess pattern 503 is formed in a space defined by the wiring line portion 411 extending in the second direction, the first direction, and the third direction, or in the third direction, the first direction, and the second direction. can be placed. In other words, the wiring line part 411 may be disposed adjacent to the outer periphery of each recess pattern 503 , and may be disposed along a portion of the outer periphery of each recess pattern 503 . In other words, the recess pattern 503 may be disposed between the respective wiring line portions 411 extending in a zigzag shape. That is, at least one recess pattern 503 may be disposed between each wiring line unit 411 .

Referring back to the recess pattern 503 , a plurality of recess patterns 503 are arranged in a matrix shape having columns and rows, and between the recess patterns 503 having a matrix shape having a plurality of columns and rows. A wiring line portion 411 extending in a zigzag shape may be disposed. 19 illustrates a case in which the plurality of recess patterns 503 are aligned in a straight line in the row direction and alternately aligned in the column direction, but the arrangement shape of the recess patterns 503 is not limited thereto. The recess patterns 503 may be aligned in a straight line in the row and column directions, staggered in the row direction, aligned in a straight line in the column direction, staggered in the column direction, and aligned along a straight line in the row direction. have.

Also, the wiring line unit 411 may be disposed between the recess patterns 503 arranged in a matrix shape, and at least one or more ridges are disposed between one wiring line unit 411 and the other wiring line unit 411 . A set pattern 503 may be disposed.

21 is a partially enlarged view of an array substrate according to another embodiment of the present invention. Referring to FIG. 21 , the array substrate according to another embodiment of the present invention is different from the embodiment of FIG. 4 in that the wiring line parts 421 extend in a curved shape having a pitch.

In the array substrate according to another embodiment of the present invention, the wiring line part 421 may extend in a curved shape having a pitch. In other words, the wiring line portion 421 may have a corrugated shape. In other words, the wiring line portion 421 may extend in a meandering manner while drawing a gentle curve.

When the wiring line unit 421 extends in a curved shape having a pitch, valleys and ridges may be formed on both sides of the wiring line unit 421 . That is, the valleys and the ridges may be repeated at least once on one side of each wiring line unit 421 , and the valleys and the valleys may be repeated at least once on the other side of each wiring line unit 421 to correspond thereto.

The recess pattern 504 may be disposed to be adjacent to the valley portion of the wiring line portion 421 . At least one recess pattern 504 may be disposed adjacent to valleys formed on one side and the other side of each wiring line unit 421 . 19 illustrates a case in which the wiring line part 421 is adjacent to the valley, but is not limited thereto, and the recess pattern 504 may partially contact the valley of the wiring line part 421 .

Referring back to the recess pattern 504 , a plurality of recess patterns 504 are arranged in a matrix shape having columns and rows, and between the recess patterns 504 having a matrix shape having a plurality of columns and rows. A wiring line portion 421 that has a curved shape with a pitch and is extended may be disposed.

19 illustrates a case in which the plurality of recess patterns 504 are aligned along a straight line in the row direction and alternately aligned in the column direction, but the arrangement shape of the recess patterns 504 is not limited thereto. The recess patterns 504 may be aligned in a straight line in the row and column directions, staggered in the row direction, aligned in a straight line in the column direction, staggered in the column direction, and aligned along a straight line in the row direction. have.

In addition, the wiring line part 421 may be disposed between the recess patterns 504 arranged in a matrix shape, and at least one or more recesses are disposed between one wiring line part 421 and the other wiring line part 421 . A set pattern 504 may be disposed.

222 is a plan view of an array substrate according to another embodiment of the present invention. 23 is a partially enlarged view of part 'C' of FIG. 22 . 24 is a cross-sectional view taken along line IX-IX' of FIG. 23 . FIG. 25 is a partially enlarged view of part 'D' of FIG. 22 . 26 is a cross-sectional view taken along line X-X of FIG. 25 .

22 to 25 , in the array substrate according to another embodiment of the present invention, the cell ID pattern 45 and/or the cutting line 700 are formed in the non-display area NDA, which is different from the embodiment of FIG. 1 . It's different.

The array substrate according to another embodiment of the present invention may include the cell ID pattern 45 and/or the cutting line 700 in the non-display area NDA.

The cell ID pattern 45 may be disposed in the non-display area NDA. In an exemplary embodiment, the cell ID pattern 45 may be disposed outside the wiring line unit 401 disposed at the outermost of the plurality of wiring line units 401 . That is, it may be disposed to be adjacent to the wiring line part 401 disposed at the outermost part. A unique number for identifying the array substrate or various figures and identification codes may be patterned on the cell ID pattern 45 . That is, information on the array substrate may be acquired through unique numbers, various figures, and identification codes patterned on the cell ID pattern 45 .

For a detailed description of the cell ID pattern, reference is made to FIGS. 23 to 24 .

23 and 24 illustrate that the cell ID pattern 45 has a rectangular shape. However, the shape of the cell ID pattern 45 is not limited thereto, and the shape of the cell ID pattern 45 may be a circular shape or a shape at least partially including a curve.

As described above, a unique number, various figures, or identification codes may be patterned on the cell ID pattern 45 . 23 illustrates a case in which a cross-shaped figure 46 is patterned on the cell ID pattern 45, but this is an example, and the shapes of various figures formed on the cell ID pattern 45 are limited thereto. it is not

In an exemplary embodiment, the cell ID pattern 45 may be disposed on the buffer layer 12 . However, this is exemplary and the position of the cell ID pattern 45 is not limited thereto. When the cell ID pattern 45 is disposed on the buffer layer 12 , the cell ID pattern 45 may be made of substantially the same material as the semiconductor layer 40 of the display area DA. That is, the cell ID pattern 45 of the non-display area NDA may be formed simultaneously with the semiconductor layer 40 of the display area DA. However, this is not limited thereto, and the cell ID pattern may be formed independently of the semiconductor layer 40 of the display area DA.

A recess pattern 505 may be disposed along the outer periphery of the cell ID pattern 45 . The recess pattern 505 may be in contact with or adjacent to the outer periphery of the cell ID pattern 45 . In an exemplary embodiment in which the cell ID pattern 45 has a rectangular shape, the recess pattern 505 may have a hollow rectangular shape, but as described above, the shape of the cell ID pattern 45 is not limited, and the shape of the cell ID pattern 45 is not limited. The set pattern 505 may have a shape corresponding to the shape of the outer periphery of the cell ID pattern 45 . When the recess pattern 505 is disposed along the outer periphery of the cell ID pattern 45 , cracks generated during the manufacturing process or transport process of the array substrate propagate to the cell ID pattern 45 and damage the cell ID pattern 45 . can be prevented from being applied.

A cutting line 700 may be formed in the non-display area NDA of the array substrate according to another embodiment of the present invention. Depending on the type of product, a corner portion of the non-display area NDA of the array substrate may be cut. That is, a corner portion of the array substrate may be chamfered.

To this end, a cutting line 700 may be formed on the array substrate. In an exemplary embodiment, the cutting line 700 may be formed to extend in an oblique direction on both sides of the non-display area NDA of the array substrate. That is, the cutting line 700 may at least partially cross the array substrate.

An angle between the cutting line 700 and one side of the array substrate is not limited. That is, an angle between the cutting line 700 and one side of the array substrate may vary depending on an applied product.

In order to prevent cracks that may occur during the cutting process, the cutting line 700 may be recessed at a predetermined distance from the upper surface of the second insulating layer 35 . That is, as shown in the cross-sectional view of FIG. 26 , the cutting line 700 may be recessed from the top surface of the second insulating layer 35 to expose the top surface of the substrate 10 . In other words, the bottom surface of the cutting line 700 includes the top surface of the substrate 10 , and the sidewalls of the cutting line 700 are the barrier layer 11 , the buffer layer 12 , the first insulating film 25 and the second An inner surface of the insulating layer 35 may be included.

A recess pattern 506 may be disposed adjacent to the cut line 700 . Specifically, the recess pattern 506 may be disposed adjacent to the other side of the cutting line 700 . In other words, when the array substrate is cut along the cutting line 700 by the cutting process, one side of the cutting line 700 may be removed and the other side of the cutting line 700 may be maintained as it is. The recess pattern 506 may be disposed adjacent to the other side of the cutting line 700 , and at least one or more recess patterns 506 may be disposed to be spread out. The recess patterns 506 may be arranged in column and row directions, but are not limited thereto, and may be arranged regularly or irregularly.

When one side of the cutting line 700 is removed by the cutting process, the other side of the cutting line 700 may be vulnerable to impact. In this case, when an impact is applied to the other side of the cutting line 700 , a crack may be generated due to the impact, and the generated crack may grow and propagate to the display area DA. When at least one or more recess patterns 506 are disposed adjacent to the other side of the cutting line 700 , the recess patterns 506 may serve as a crack stopper. That is, the propagation of the generated crack may be blocked by the recess pattern 506 .

27 is a cross-sectional view of an organic light emitting diode display according to an exemplary embodiment.

Referring to FIG. 27 , an organic light emitting diode display according to an exemplary embodiment is an array substrate having a display area DA and a non-display area NDA disposed outside the display area DA, and the non-display area ( NDA) is a substrate 10 , a barrier layer 11 disposed on the substrate 10 , a buffer layer 12 disposed on the barrier layer 11 , and a first insulating layer 25 disposed on the buffer layer 12 . , a second insulating layer 35 disposed on the first insulating layer 25 , interposed between the first insulating layer 25 and the second insulating layer 35 , or disposed on the second insulating layer 35 , spaced apart from each other A plurality of wiring patterns extending toward one side of the substrate 10 are recessed by a predetermined depth from the upper surface of the second insulating film 35 to at least partially expose the upper surface of the substrate 10 and on the second insulating film an array substrate including an organic insulating layer 75 at least partially exposing an upper surface of the substrate exposed by the recess pattern; and an encapsulation member disposed on the array substrate.

27 illustrates one unit pixel area by limiting it for convenience of description, and it goes without saying that the organic light emitting diode display according to the exemplary embodiment is not limited thereto. That is, the organic light emitting diode display according to an embodiment of the present invention may include a plurality of unit pixel areas as described above with respect to the array substrate according to some embodiments of the present invention.

First, the display area DA of the array substrate in the organic light emitting diode display according to an embodiment of the present invention will be described.

The substrate 10 is a member having a plate shape, and may serve to support other components to be described later. The substrate 10 is an insulating substrate 10 and may be formed of a polymer material including glass or plastic. In an exemplary embodiment, the substrate 10 may be formed of poly imide (PI), but this is exemplary and the material of the substrate 10 is not limited thereto.

The substrate 10 may be a rigid substrate 10 , but is not limited thereto, and may be a flexible or flexible substrate 10 . That is, in this specification, the term "substrate 10" may be understood as a concept including a flexible substrate 10 capable of bending, folding, or rolling.

27 , the substrate 10 may have a single-layer structure, but is not limited thereto. That is, in another exemplary embodiment, the substrate 10 may have a stacked structure in which two or more layers are stacked. In other words, the substrate 10 may include a base layer and a protective layer disposed on the base layer.

The base layer may be formed of an insulating material. In an exemplary embodiment, the base layer may be formed of poly imide (PI), but the material of the base layer is not limited thereto. A protective layer may be disposed on the base layer. The protective layer may be made of an organic material. For example, the protective layer may include any one or more selected from polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), but this is exemplary and the material of the protective layer is not limited thereto. .

A barrier layer 11 may be disposed on the substrate 10 . The barrier layer 11 may serve to prevent penetration of impurity elements and planarize the surface. In an exemplary embodiment, the barrier layer 11 may include silicon oxide (SiOx) or silicon nitride (SiNx), but the material of the barrier layer 11 is not limited thereto. Also, in another exemplary embodiment, the barrier layer 11 may be omitted depending on the material of the substrate 10 or process conditions.

A buffer layer 12 covering the barrier layer 11 may be disposed on the barrier layer 11 . The buffer layer 12 may be an inorganic layer formed of an inorganic material. In an exemplary embodiment, the buffer layer 12 may be formed including at least one selected from the group consisting of silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), and silicon oxynitride (SiON), but the buffer layer ( 12) is not limited thereto. In addition, the buffer layer 12 may have a single layer structure or a stacked structure in which two or more layers are stacked. In an exemplary embodiment in which the buffer layer 12 has two layers, the two layers are formed of different materials. can be For example, the first layer may be made of silicon oxide and the second layer may be made of silicon nitride. However, this is exemplary and the structure of the buffer layer 12 is not limited thereto.

The semiconductor layer 40 may include amorphous silicon or polycrystalline silicon. In an exemplary embodiment, the semiconductor layer 40 may be formed by applying and patterning amorphous silicon and then crystallizing it, but the method of forming the semiconductor layer 40 is not limited thereto. As used herein, the term “semiconductor layer 40” may be understood to include an oxide semiconductor, but is not limited thereto.

A gate insulating layer 20 may be formed on the semiconductor layer 40 . The gate insulating layer 20 may include silicon nitride (SiNx) or silicon oxide (SiOx), but the material of the gate insulating layer 20 is not limited thereto. The gate insulating layers 20 and 20 may have a single layer structure, but are not limited thereto, and may have a multilayer structure including at least two insulating layers having different physical properties.

A gate line including a gate line 50 , a gate electrode 51 , and a gate pad may be disposed on the gate insulating layer 20 . Gate wiring consists of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, and molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys. , chromium (Cr), tantalum (Ta) and titanium (Ti) may be formed including any one or more materials selected from the group consisting of, but the material of the gate wiring is not limited thereto, and as a conductive material, transparent or A translucent material may be used to form the gate wiring.

As described above, a plurality of gate lines 50 may extend in one direction to be parallel to each other.

An interlayer insulating layer 30 covering the gate wiring may be disposed on the gate wiring. The interlayer insulating layer 30 may be an inorganic layer formed of an inorganic material. In an exemplary embodiment, the interlayer insulating layer 30 may include silicon nitride (SiNx) or silicon oxide (SiOx), but the material of the interlayer insulating layer 30 and 20 is not limited thereto. The interlayer insulating layers 30 and 20 may have a single layer structure, but is not limited thereto, and may have a multilayer structure including at least two insulating layers having different physical properties. The interlayer insulating film 30 having a multilayer structure will be described later.

A data line including a source electrode 61 , a drain electrode 62 , and a data line 60 may be disposed on the interlayer insulating layer 30 . The data wiring may be formed of a refractory metal such as molybdenum, chromium, tantalum and titanium or an alloy thereof, but the material of the data wiring is not limited thereto, and a transparent or translucent material as a conductive material is used to form the data wiring. can be used

The data line 60 transmits a data signal and may be disposed to cross the gate line 50 . That is, in the exemplary embodiment, the gate line 50 may extend in a horizontal direction, and the data line 60 may extend in a vertical direction to intersect the same.

In an exemplary embodiment, the data line 60 and the gate line 50 may include bent portions. However, this is obvious to those skilled in the art, and detailed description thereof will be omitted to avoid obscuring the scope of the present invention.

The source electrode 61 is a part of the data line 60 and may be disposed on the same line as the data line 60 . The drain electrode 62 may be formed to extend parallel to the source electrode 61 . In this case, the drain electrode 62 may be parallel to a portion of the data line 60 .

The gate electrode 51 , the source electrode 61 , and the drain electrode 62 form one thin film transistor (TFT) together with the semiconductor layer 40 , and the channel of the thin film transistor is the source electrode ( 61 ) and the semiconductor layer 40 between the drain electrode 62 .

A planarization layer 70 covering the data line and the interlayer insulating layer 30 may be disposed on the data line. The thickness of the planarization layer 70 may be relatively thicker than that of the interlayer insulating layer 30 . Due to the thickness difference, the upper surface of the planarization film 70 may be relatively flat compared to the lower surface in contact with the interlayer insulating film 30 and the source/drain electrodes 62 .

A first contact hole for at least partially exposing the drain electrode 62 may be formed in the planarization layer 70 . Specifically, the first contact hole may pass through the planarization layer 70 and partially expose the top surface of the drain electrode 62 .

A first electrode 80 may be disposed on the planarization layer 70 and the exposed drain electrode 62 . That is, the first electrode 80 may be disposed to cover the planarization layer 70 , the sidewall of the first contact hole, and the upper surface of the drain electrode 62 , whereby the first electrode 80 and the drain electrode 62 . This can be electrically connected. In an exemplary embodiment, the first electrode 80 may be an anode electrode, but is not limited thereto. The first electrode 80 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO), but the material of the first electrodes 80 and 70 is not limited thereto. does not

A pixel defining layer may be disposed on the first electrode 80 . The pixel defining layer may at least partially expose the first electrode 80 . The pixel defining layer 40 includes at least one organic material selected from benzocyclobutene (BCB), polyimide (PI), polyamide (PA), acrylic resin, and phenolic resin. It may be made of, or may be made of, including an inorganic material such as silicon nitride. The pixel defining layer 40 may also be made of a photosensitive material including a black pigment. In this case, the pixel defining layer 40 may serve as a light blocking member.

An organic layer may be disposed on the first electrode 80 exposed by the pixel defining layer. The organic layer 91 is an organic material layer included in the organic light emitting display device 100 , that is, an organic light emitting layer (EML), a hole injection layer (HIL), a hole transport layer, HTL), an electron injection layer (EIL), an electron transport layer (ETL), and the like. The organic layer 91 may have a single-layer structure including one selected from the organic material layers or a multi-layer structure including two or more organic material layers.

A second electrode 92 may be formed on the organic layer 91 . The second electrode 92 may cover the pixel defining layer 90 and the organic layer 91 . In an exemplary embodiment, the second electrode 92 may be a front electrode covering the pixel defining layer 90 and the organic layer 91 , but is not limited thereto. Also, in an exemplary embodiment, the second electrode 92 may be a cathode electrode.

The second electrode 92 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO), but the material of the second electrode 92 is not limited thereto.

The non-display area NDA of the array substrate may be substantially the same as that described above for the array substrate according to some embodiments of the present invention, and thus a detailed description thereof will be omitted.

* An encapsulation member may be disposed on the array substrate. In this specification, the encapsulation member may be the encapsulation film 803 or the encapsulation substrate 800 . 27 illustrates a case in which the encapsulation member is the encapsulation substrate 800 , but the encapsulation member is not limited thereto. A case in which the encapsulation member is the encapsulation film 803 will be described with reference to FIG. 28 . In an exemplary embodiment, the encapsulation substrates 800 and 10 may be sealed by being adhered to the array substrate by an encapsulant (not shown).

In order to allow the encapsulation substrate 800 to be adhered to the array substrate, the encapsulant may be at least any one selected from an adhesive epoxy adhesive, an ultraviolet curing adhesive, a frit, and the like, but this is exemplary. The material of the encapsulant is not limited thereto.

The encapsulation substrate 10 may be bonded and bonded to the array substrate by the above-described encapsulant. In an exemplary embodiment, the encapsulation substrate 800 may be formed of any one selected from transparent glass, transparent plastic, transparent polymer, and the like, but the material of the encapsulation substrate 800 is not limited thereto.

A conductive layer 801 may be formed on one surface of the encapsulation substrate 800 facing the array substrate. The conductive layer 801 may serve to ground static electricity generated outside the organic light emitting diode display and flowing through the encapsulation substrate 10 . However, this is obvious to those skilled in the art, and detailed description thereof will be omitted so as not to obscure the scope of the present invention.

28 is a cross-sectional view of an organic light emitting diode display according to another exemplary embodiment.

Referring to FIG. 28 , the organic light emitting diode display according to another exemplary embodiment is different from the exemplary embodiment of FIG. 28 in that an encapsulation member is an encapsulation film.

As described above, in the exemplary embodiment, the encapsulation member may be the encapsulation film 803 . The encapsulation layer 803 may cover the display area DA and the non-display area NDA. In an exemplary embodiment, the encapsulation layer 803 may at least partially expose the wiring line unit 401 and/or the wiring pad unit 402 , but is not limited thereto.

The encapsulation layer 803 may be formed of an organic material and/or an inorganic material.

The organic material for forming the encapsulation film 803 may be, for example, epoxy, acrylate, and urethane acrylate, but is not limited thereto. The inorganic material for forming the encapsulation layer 803 may be, for example, aluminum oxide or silicon oxide, but is not limited thereto.

28 illustrates that the encapsulation film 803 has a single-layer structure, the structure of the encapsulation film 803 is not limited thereto, and the encapsulation film 803 may have a stacked structure in which one or more layers are stacked. In an exemplary embodiment, the encapsulation layer 803 may have a structure in which an organic layer and an inorganic layer are alternately stacked at least once, but this is exemplary and the structure of the encapsulation layer 803 is not limited thereto.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: array substrate
50: gate line
60: data line
402: wiring line part
401: wiring pad part
403: wiring connection part
500, 501, 503, 504, 505, 506, 507, 508: recess pattern
502: recess home
200: scan driver
300: emission driver
10: substrate
11: barrier layer
12: buffer layer
20: gate insulating film
30: interlayer insulating film
70: planarization film
80: first electrode
90: pixel defining layer
91: organic layer
92: second electrode
51: gate electrode
61: source electrode
62: drain electrode
72: contact part
75: organic insulating film
35: second insulating film
25: first insulating film
45: cell ID pattern
700: cutting line
800: encapsulation substrate
803: encapsulation film

Claims (17)

a substrate including a display area and a non-display area;
a thin film transistor positioned on the substrate, positioned in the display area, and including a semiconductor layer;
a first insulating layer positioned on the substrate and positioned in the display area and the non-display area;
a wiring pattern located on the first insulating layer, located in the non-display area, and electrically connected to the thin film transistor;
a recess pattern positioned in the non-display area and disposed adjacent to the wiring pattern and penetrating the first insulating layer; and
an organic insulating layer disposed on the wiring pattern and in contact with an upper surface of the substrate exposed by the recess pattern;
The wiring pattern is in direct contact with the first insulating film,
The semiconductor layer is an array substrate positioned between the substrate and the first insulating layer. The method of claim 1,
A bottom surface of the recess pattern includes a top surface of the substrate, and a sidewall of the recess pattern includes an inner surface of the first insulating layer. The method of claim 1,
The wiring pattern is plural,
The plurality of recess patterns is plural, and the plurality of recess patterns are disposed between the plurality of wiring patterns. 4. The method of claim 3,
Each of the wiring patterns may include a wiring line portion extending toward one side of the substrate;
a wiring pad unit having a second end at least partially overlapping the wiring line unit and having one end wider than the wiring line unit; and
and a wiring connection part electrically connected to the wiring line part and the wiring pad part in contact with each other. 5. The method of claim 4,
The recess pattern is disposed between adjacent interconnection line portions and extends to between adjacent interconnection pad portions. 6. The method of claim 5,
A width of the recess pattern disposed between the wiring line parts is greater than a width of the recess pattern disposed between the wiring pad parts. 5. The method of claim 4,
The wiring line portion extends in a zigzag shape, and the recess pattern is at least one disposed between the adjacent wiring line portions. 8. The method of claim 7,
The recess pattern is disposed between a plurality of wiring line portions, and is arranged in a matrix form having a plurality of columns and a plurality of rows. 5. The method of claim 4,
and a recess groove disposed inside the wiring pad unit and penetrating through the wiring pad unit, the first insulating layer, and the buffer layer to expose a top surface of the substrate. 5. The method of claim 4,
The recess pattern is disposed outside the wiring line portion disposed at the outermost of the plurality of wiring line portion. 11. The method of claim 10,
The array substrate further includes a cell ID pattern disposed outside the outermost wiring line portion among the plurality of wiring line portions, wherein the recess pattern is disposed along an outer periphery of the cell ID pattern. The method of claim 1,
At least one cut line is defined on the substrate at least partially crossing the substrate, and the recess pattern is disposed adjacent to the cut line. The method of claim 1,
The first insulating layer is an array substrate comprising silicon oxide or silicon nitride. The method of claim 1,
The substrate is an array substrate which is a flexible substrate. a substrate including a display area and a non-display area;
a first insulating layer positioned on the substrate and positioned in the display area and the non-display area;
a thin film transistor positioned on the first insulating layer, positioned in the display area, and including a semiconductor layer;
a wiring pattern located on the first insulating layer, located in the non-display area, and electrically connected to the thin film transistor;
a recess pattern positioned in the non-display area and disposed adjacent to the wiring pattern and penetrating the first insulating layer; and
an organic insulating layer disposed on the wiring pattern and in contact with an upper surface of the substrate exposed by the recess pattern;
The organic insulating layer is in direct contact with a side surface of the first insulating layer defining the recess pattern. 16. The method of claim 15,
Further comprising a second insulating film positioned between the first insulating film and the wiring pattern,
The semiconductor layer of the thin film transistor is disposed between the first insulating layer and the second insulating layer. 17. The method of claim 16,
The recess pattern is further defined by a side surface of the second insulating layer,
The organic insulating layer is in direct contact with a side surface of the second insulating layer defining the recess pattern.

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