KR20140146510A - Array substrate and organic light emitting display device including the same - Google Patents

Abstract

The present invention relates to an array substrate and an organic light emitting display device including the same. The array substrate according to an embodiment of the present invention includes: a substrate; a barrier layer arranged on the substrate; a buffer layer arranged on the barrier layer; a first insulating film arranged on the buffer layer; a second insulating film arranged on the insulating film; multiple wire patterns which are arranged between the first and second insulating films or on the second insulating films and are spaced apart from each other while extending to a side of the substrate; a recess pattern which is recessed from the upper surface of the second insulating film by a predetermined depth to partially expose the upper surface of the substrate; and an organic insulating film which is arranged on the second insulating film and partially exposes the upper surface of the substrate exposed by the recess pattern.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting diode (OLED)

The present invention relates to an array substrate and a display device including the array substrate, and more particularly, to an array substrate including a display region and a non-display region, and a labeling apparatus including the same.

A display device such as a liquid crystal display (LCD) or an organic light emitting display (OLED) may include an array substrate including a display area and a non-display area disposed outside the display area. Such a display device is a basic component for displaying an image, and includes a plurality of pixels in a display area, and each pixel includes a switching element for independent driving.

On the other hand, the array substrate is used as a circuit substrate for independently driving each pixel in a liquid crystal display device, an organic light emitting display device or the like. On the array substrate, a gate wiring for transferring a scanning signal and a data wiring for transferring an image signal, a thin film transistor, and various organic or inorganic insulating films are arranged. The thin film transistor includes a gate electrode, which is a part of the gate wiring, A source electrode and a drain electrode which are a part of the data wiring, and serve as a switching element.

A plurality of wirings connected to a gate line or a data line of the display region are disposed in a non-display region disposed outside the display region. The plurality of wirings may extend in various forms, and one end thereof may be connected to the pads disposed on the pad portion under the array substrate.

Such an array substrate can be exposed to various impacts from the manufacturing process. Specifically, a certain impact may be applied to the array substrate when carrying the array substrate or conducting various inspection operations. Cracks may be formed on the array substrate by the shock. These cracks tend to grow or propagate through the inorganic insulating film layer disposed on the substrate. That is, if a crack is generated in a part of the non-display area by way of example, such a crack can propagate to the display area in an inorganic insulating film, which may lead to poor reliability of the display area. In order to solve these problems, various technical attempts have been made on the structure of the array substrate having a strong impact and the structure of the array substrate capable of suppressing the propagation of cracks generated in the non-display region.

An object of the present invention is to provide an array substrate having a structure for preventing occurrence of cracks.

Another object to be solved by the present invention is to provide an array substrate having a structure for suppressing propagation of generated cracks.

Another problem to be solved by the invention is to provide an organic light emitting display having a structure for preventing occurrence of cracks.

Another problem to be solved by the present invention is to provide an organic light emitting display having a structure for suppressing the propagation of cracks generated.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing the same.

According to an aspect of the present invention, there is provided an array substrate including a substrate, a barrier layer disposed on the substrate, a buffer layer disposed on the barrier layer, a first insulating layer disposed on the buffer layer, A plurality of wiring patterns interposed between the first insulating film and the second insulating film or disposed on the second insulating film so as to be spaced apart from each other and extending toward one side of the substrate; And an organic insulating film disposed on the second insulating film, the organic insulating film at least partially exposing the top surface of the substrate exposed by the recess pattern.

According to an aspect of the present invention, there is provided an array substrate including a display region and a non-display region disposed outside the display region, wherein the non-display region includes a substrate, a barrier layer disposed on the substrate, A first insulating film disposed on the buffer layer, a second insulating film disposed on the first insulating film, a second insulating film interposed between the first insulating film and the second insulating film, or disposed on the second insulating film, A recess pattern recessed by a predetermined depth from an upper surface of the second insulating film to expose an upper surface of the substrate at least partially, and a plurality of wiring patterns formed on the second insulating film, And an organic insulating film at least partially exposing an upper surface of the exposed substrate.

An organic light emitting display according to an embodiment of the present invention is an array substrate having a display region and a non-display region disposed outside the display region, wherein the non-display region includes a substrate, a barrier layer disposed on the substrate, A first insulating film disposed on the buffer layer, a second insulating film disposed on the first insulating film, a second insulating film interposed between the first insulating film and the second insulating film, or disposed on the second insulating film, A recess pattern recessed at a predetermined depth from an upper surface of the second insulating film to at least partially expose an upper surface of the substrate, and a recess pattern formed on the second insulating film, the recess pattern being exposed by the recess pattern, An array substrate including an organic insulating film at least partially exposing an upper surface of the substrate, and a sealing member disposed on the array substrate .

The details of other embodiments are included in the detailed description and drawings.

The embodiments of the present invention have at least the following effects.

That is, cracks can be prevented from being generated in the array substrate due to an external impact.

Further, it is possible to suppress the growth or propagation of cracks caused by external shocks.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a plan view of an array substrate according to an embodiment of the present invention,
FIG. 2 is an enlarged partial enlarged view of the portion 'A' of FIG. 1,
3 is a cross-sectional view taken along the line I-I 'in Fig.
4 is an enlarged partial enlarged view of the 'B' portion of FIG. 1,
5 is a cross-sectional view taken along line II-II 'of FIG. 4,
6 is a cross-sectional view taken along line III-III 'of FIG. 4,
7 is a cross-sectional view taken along line IV-IV 'of FIG.
FIG. 8 is a partially enlarged view of an array substrate according to a modification of FIG. 4; FIG.
9 is a partially enlarged view of an array substrate according to a modification of Fig.
10 is a partially enlarged view of an array substrate according to a modification of FIG.
11 is a cross-sectional view taken along the line V-V 'of FIG.
12 is a cross-sectional view taken along the line VI-VI 'of FIG.
13 is a cross-sectional view of an array substrate according to a modification of Fig.
14 is a cross-sectional view of an array substrate according to a modification of Fig.
15 is a partially enlarged view of an array substrate according to a modification of Fig.
16 is a cross-sectional view taken along line VII-VII 'of FIG.
17 is a cross-sectional view of an array substrate according to a modification of Fig.
FIG. 18 is a cross-sectional view of an array substrate according to a modification of FIG. 7;
19 is a partially enlarged view of an array substrate according to another embodiment of the present invention.
20 is a cross-sectional view taken along the line VIII-VIII 'of FIG. 19;
21 is a partially enlarged view of an array substrate according to another embodiment of the present invention.
22 is a plan view of an array substrate according to another embodiment of the present invention.
FIG. 23 is an enlarged partial view of a portion 'C' in FIG. 22; FIG.
24 is a cross-sectional view taken along line IX-IX 'of Fig.
FIG. 25 is an enlarged view of a portion 'D' of FIG. 22 enlarged.
26 is a cross-sectional view taken along the line X-X of Fig.
27 is a cross-sectional view of an OLED display according to an embodiment of the present invention.
28 is a cross-sectional view of an OLED display according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

It will be understood that when an element or layer is referred to as being "on" of another element or layer, it encompasses the case where it is directly on or intervening another element or intervening layers or other elements. Like reference numerals refer to like elements throughout the specification.

Although the first, second, etc. are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may be the second component within the technical scope of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a plan view of an array substrate according to an embodiment of the present invention. FIG. 2 is a partially enlarged view of the portion 'A' of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line I- Sectional view.

1 to 3, the array substrate 100 according to an exemplary embodiment of the present invention may include a display area DA and a non-display area NDA disposed outside the display area DA .

The display region DA may include a plurality of gate lines 50 extending in one direction and a plurality of data lines 60 extending in a direction intersecting the gate lines 50. In addition, a pixel region surrounded by the plurality of gate lines 50 and data lines 60 can be defined. A thin film transistor connected to the gate line 50 and the data line 60 may be formed in each pixel region defined by the plurality of gate lines 50 and the data lines 60.

2 and 3 are referred to for a detailed description of the display area DA.

The substrate 10 is a member having a plate shape and can play a role of supporting other structures to be described later. The substrate 10 may be an insulating substrate, and may be formed of a polymer material including glass or plastic. In an exemplary embodiment, the substrate 10 may be formed of polyimide (PI), but this is illustrative only and the material of the substrate 10 is not limited thereto.

The substrate 10 may be a rigid substrate 10, but is not limited thereto, and may be a substrate 10 having flexibility or flexibility. That is, in this specification, the term "substrate" can be understood as a concept including a flexible substrate capable of bending, folding, and rolling.

As shown in FIG. 2, the substrate 10 may have a single layer structure, but is not limited thereto. That is, in other exemplary embodiments, the substrate 10 may have a laminated structure in which two or more layers are laminated. In other words, the substrate 10 may include a base layer and a protective layer disposed on the base layer.

The base layer may be formed of an insulating material. In an exemplary embodiment, the base layer may be formed of polyimide (PI), but the material of the base layer is not limited thereto. A protective layer may be disposed on the base layer. The protective layer may be composed of an organic material or an inorganic material. For example, the protective layer may include at least one selected from the group consisting of polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), but the protective layer is not limited thereto. .

A barrier layer 11 may be disposed on the substrate 10. The barrier layer 11 may serve to prevent penetration of impurity elements from the substrate 10. In the exemplary embodiment, the barrier layer 11 may include at least one selected from the group consisting of silicon oxide (SiOx) and silicon nitride (SiNx), but the material of the barrier layer 11 is not limited thereto. The barrier layer 11 may have a single film structure or a laminated structure in which two or more layers are laminated. In an exemplary embodiment in which the barrier layer 11 has two layers, the two layers are formed of materials different from each other . For example, the first layer may be made of silicon oxide and the second layer may be made of silicon nitride. However, this is illustrative and the structure of the barrier layer 11 is not limited thereto.

Further, in other exemplary embodiments, the barrier layer 11 may be omitted depending on the material of the substrate 10 or the processing conditions.

On the barrier layer 11, a buffer layer 12 covering the barrier layer 11 may be disposed. The buffer layer 12 may be an inorganic film formed of an inorganic material. In the exemplary embodiment, the buffer layer 12 may be formed to include at least one selected from the group consisting of silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx) and silicon oxynitride (SiON) 12 are not limited thereto. In addition, the buffer layer 12 may have a single-layer structure or a laminate structure in which two or more layers are stacked. In an exemplary embodiment in which the buffer layer 12 has two layers, the two layers are formed of materials different from each other . For example, the first layer may be made of silicon oxide and the second layer may be made of silicon nitride. However, this is illustrative and the structure of the buffer layer 12 is not limited thereto.

The semiconductor layer 40 may include amorphous silicon or polycrystalline silicon. In the exemplary embodiment, the semiconductor layer 40 may be formed by applying and patterning amorphous silicon and then crystallizing the amorphous silicon. However, the method of forming the semiconductor layer 40 is not limited thereto. Also, what is referred to herein as a "semiconductor layer" can be understood to include oxide semiconductors.

A gate insulating layer 20 may be formed on the semiconductor layer 40. The gate insulating film 20 may include silicon nitride (SiNx) or silicon oxide (SiOx), but the material of the gate insulating film 20 is not limited thereto. The gate insulating film 20 may have a single film structure, but is not limited thereto and may have a multi-layer structure including at least two insulating layers having different physical properties.

A gate line including a gate line 50, a gate electrode 51, and a gate pad 55 may be disposed on the gate insulating film 20. Examples of the gate wiring include aluminum-based metals such as aluminum (Al) and aluminum alloys; series metals such as silver (Ag) and silver alloys; copper-based metals such as copper (Cu) and copper alloys; molybdenum-based metals such as molybdenum , Chromium (Cr), tantalum (Ta), and titanium (Ti), but the material of the gate wiring is not limited thereto. Semitransparent materials can be used to form gate wirings.

The plurality of gate lines 50 are arranged as described above, and may extend in one direction so as to be parallel to each other.

An interlayer insulating film 30 covering the gate wiring may be disposed on the gate wiring. The interlayer insulating film 30 may be an inorganic film formed of an inorganic material. In the exemplary embodiment, the interlayer insulating film 30 may include silicon nitride (SiNx) or silicon oxide (SiOx), but the material of the interlayer insulating film 30 is not limited thereto. The interlayer insulating film 30 may have a single-layer structure, but is not limited thereto and may have a multi-layer structure including at least two insulating layers having different physical properties. The interlayer insulating film 30 having a multilayer structure will be described later.

A data line including the source electrode 61, the drain electrode 62, and the data line 60 may be disposed on the interlayer insulating film 30. [ The data line may be formed of a refractory metal such as molybdenum, chromium, tantalum and titanium, or an alloy thereof. However, the material of the data line is not limited thereto, and a transparent or translucent material may be used as a material for forming a data line Can be used.

The data line 60 carries a data signal and may be arranged to intersect the gate line 50. That is, in the exemplary embodiment, the gate line 50 extends in the lateral direction, and the data line 60 may extend in the longitudinal direction so as to intersect with the gate line 50.

Although the data line 60 and the gate line 50 are illustrated as being straight in FIG. 2, the data line 60 and the gate line 50 may include a bend in the exemplary embodiment. It will be apparent to those skilled in the art that a detailed description thereof will not be given to avoid obscuring the scope of the present invention.

The source electrode 61 may be disposed on the same line as the data line 60 as a part of the data line 60. [ The drain electrode 62 may be formed to extend in parallel with the source electrode 61, in which case the drain electrode 62 may be parallel to a portion of the data line 60.

The gate electrode 51, the source electrode 61 and the drain electrode 62 form a single thin film transistor (TFT) together with the semiconductor layer 40, And the semiconductor layer 40 between the source electrode 61 and the drain electrode 62.

A planarizing film 70 covering the data wiring and the interlayer insulating film 30 may be disposed on the data wiring. The thickness of the planarizing film 70 may be relatively thicker than that of the interlayer insulating film 30. [ Due to such a difference in thickness, the upper surface of the planarization film 70 may be relatively flat as compared with the lower surface in contact with the interlayer insulating film 30 and the source / drain electrodes 62. The planarizing film 70 may include, but is not limited to, one or more materials selected from the group consisting of acrylic, BCB (benzocyclic butylenes), and polyimide to alleviate the level difference on the substrate 10. [ In addition, the planarization layer 70 may be made of a photosensitive material.

The planarization layer 70 may be formed with a first contact hole 71 at least partially exposing the drain electrode 62. Specifically, the first contact hole 71 penetrates the planarizing film 70, and can partially expose the upper surface of the drain electrode 62. [

A first electrode 80 may be disposed on the planarization layer 70 and the exposed drain electrode 62. That is, the first electrode 80 may be disposed to cover the top surface of the planarization layer 70, the sidewalls of the first contact holes, and the drain electrode 62, thereby forming the first electrode 80 and the drain electrode 62, Can be electrically connected. In an exemplary embodiment, the first electrode 80 may be, but is not limited to, an anode electrode. The first electrode 80 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO), but the material of the first electrode 80 is not limited thereto. On the first electrode 80, a pixel defining layer, an organic layer, and a second electrode may be disposed. A detailed description thereof will be described later.

Hereinafter, the non-display area NDA of the array substrate according to the embodiment of the present invention will be described.

1, the scan driver 200, the emission driver 300, the scan driver 200, and the emission driver 300 are provided in a non-display area NDA disposed outside the display area DA, Or a plurality of wiring patterns connected to the display area DA can be disposed. The wiring pattern is disposed at one end of the wiring line portion 401 and the wiring line portion 401 extending from the scan driver 200, the emission driver 300 or the display area DA, The wiring pad portion 402 having a larger width than the wiring pad portion 401 shown in FIG. A detailed description of the structure of the wiring pattern will be given later.

For a more detailed description of the non-display area (NDA), reference is made to Figs. 4-7.

4 is a cross-sectional view taken along the line II-II 'in FIG. 4, and FIG. 6 is a cross-sectional view taken along the line III-III' And FIG. 7 is a cross-sectional view taken along line IV-IV 'of FIG.

4 to 7, the non-display area NDA of the array substrate according to the embodiment of the present invention includes a substrate 10, a barrier layer 11 disposed on the substrate 10, a barrier layer 11, A first insulating film 25 disposed on the buffer layer 12, a second insulating film 35 disposed on the first insulating film 25, a first insulating film 25 and a second insulating film 25 disposed on the buffer layer 12, A plurality of wiring patterns interposed between the insulating films 35 or disposed on the second insulating film 35 so as to extend toward one side of the substrate 10 so as to extend from the upper surface of the second insulating film 35, (75) at least partially exposing the top surface of the substrate exposed by the recess pattern, the recessed pattern being formed on the second insulating film and at least partially exposing the top surface of the substrate (10) .

The substrate 10, the barrier layer 11, and the buffer layer 12 may be substantially the same as those described above with reference to FIGS. 1 to 3, and a description thereof will be omitted.

The first insulating film 25 may be disposed on the buffer layer 12. The first insulating film 25 may be an inorganic insulating film formed of an inorganic material. The first insulating film 25 may be formed of silicon nitride (SiNx) or silicon oxide (SiOx), for example. However, the material of the first insulating film 25 is not limited thereto.

In the exemplary embodiment, the first insulating film 25 may be formed of a material substantially the same as the gate insulating film 20 of the display area DA. In other words, the first insulating film 25 of the non-display area NDA can be formed substantially simultaneously with the gate insulating film 20 of the display area DA. However, the present invention is not limited thereto, and the first insulating film 25 of the non-display area NDA and the gate insulating film 20 of the display area DA may be independently formed as separate structures.

A second insulating film 35 may be disposed on the first insulating film 25. The second insulating film 35 may be an inorganic insulating film formed of an inorganic material in the same manner as the first insulating film 25. The second insulating film 35 may be formed to include silicon nitride (SiNx) or silicon oxide (SiOx) like the first insulating film 25. The first insulating layer 25 and the second insulating layer 35 may be formed of the same material as the first insulating layer 25 and the second insulating layer 35. However, have. In an exemplary embodiment, the second insulating film may be made of substantially the same material as the interlayer insulating film in the display region. That is, the second insulating film can be formed substantially simultaneously with the interlayer insulating film in the display region. However, the present invention is not limited to this example, and the interlayer insulating film in the display region and the second insulating film in the non-display region may be formed independently of each other as independent structures.

A wiring pattern may be disposed on the first insulating film 25 or the second insulating film 35. In other words, the wiring pattern may be disposed on the first insulating film 25, interposed between the first insulating film 25 and the second insulating film 35, or disposed on the second insulating film 35. In the exemplary embodiment, a part of the wiring pattern may be formed on the first insulating film 25, and the remaining part may be formed on the second insulating film 35. [

The wiring pattern may be connected to the display area DA, the scan driver 200, or the emission driver 300 to transmit or receive a signal. For this purpose, the wiring pattern may be formed of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a series metal such as silver or silver alloy, a copper-based metal such as copper or a copper alloy, a molybdenum The conductive pattern may be formed of any one or more materials selected from the group consisting of copper, chromium (Cr), tantalum (Ta), and titanium (Ti), but the material of the wiring pattern is not limited thereto, May be used to form the wiring pattern.

In an exemplary embodiment, the wiring pattern may include a wiring line portion 401, a wiring pad portion 402, and a wiring connection portion 403. [

The wiring line unit 401 is electrically connected to the display area DA, the scan driver 200 or the emission driver 300 and is connected to the display area DA, the scan driver 200, or the emission driver 300 And may extend toward one side of the substrate 10. The wiring line portions 401 may extend in a straight line or may extend toward one side of the substrate 10 with at least one bent portion.

In an exemplary embodiment, the wiring line portion 401 may be disposed on the first insulating film 25. [ That is, the wiring line portion 401 may be interposed between the first insulating film 25 and the second insulating film 35. The wiring line portion 401 may be formed of the same material as the gate wiring of the display area DA. In other words, the wiring line portion 401 can be formed substantially simultaneously with the gate wiring of the display area DA. However, the present invention is not limited thereto, and the gate line of the wiring line portion 401 of the non-display region NDA and the gate line of the display region DA may be formed independently of each other.

One end of the wiring line portion 401 can be partially overlapped with the other end of the wiring pad portion 402 described later.

The wiring pad portion 402 is electrically connected to one end of the wiring line portion 401 and may extend from one end of the wiring line portion 401 toward one side of the substrate 10. A plurality of wiring pads 402 may be arranged, and the wiring pads 402 may be arranged along one side of the substrate 10. In the exemplary embodiment, one end of the extended wiring pad portion 402 may contact with one side of the substrate 10, but is not limited thereto. The width of the other end of the wiring pad portion 402 may be relatively larger than the width of the wiring line portion 401. An external circuit module such as a flexible printed circuit (FPC) connected to the inspection apparatus or the printed circuit board 10 may be connected to the wiring pad unit 402 And the wiring pad portion 402 has a width larger than that of the wiring line portion 401, the electrical contact with the circuit module can be made easier.

In the exemplary embodiment, the wiring pad portion 402 may be disposed on the second insulating film 35. [ That is, the wiring pad portion 402 can be arranged so as to have a level different from that of the wiring line portion 401. In other words, the wiring pad portion 402 and the wiring line portion 401 can be arranged in different layers.

The wiring line portion 401 and the wiring pad portion 402 can be electrically connected. Concretely, one end of the wiring line portion 401 and the other end of the wiring pad portion 402 can be electrically connected. In the exemplary embodiment in which the wiring line portion 401 is disposed on the first insulating film 25 and the wiring pad portion 402 is disposed on the second insulating film 35, The portion 401 may be electrically connected through the wiring connection portion 403. [ Refer to Fig. 5 for a detailed description of the wiring connecting portion 403. Fig.

Referring to FIG. 5, a second insulating film 35 is disposed on the wiring line portion 401, and the second insulating film 35 can expose the wiring line portion 401 at least partially. That is, the wiring pad portion 402 is disposed on the wiring line portion 401 exposed by the second insulating film 35, so that the wiring pad portion 402 and the wiring line portion 401 can be electrically connected.

At least one recess pattern 500 may be disposed adjacent to the plurality of wiring patterns. The recess pattern 500 may be formed by being spaced apart from the upper surface of the second insulating film 35 at a predetermined interval. The recess pattern 500 formed by being spaced apart from the upper surface of the second insulating film 35 at a predetermined interval may at least partially expose the upper surface of the substrate 10. [ In other words, the bottom surface of the recess pattern 500 may at least partially include the top surface of the substrate 10. [

In other words, the recess pattern 500 penetrates the barrier layer 11, the buffer layer 12, the first insulating film 25, and the second insulating film 35 to expose the upper surface of the substrate 10 at least partially . That is, in the exemplary embodiment, the bottom surface of the recess pattern 500 is formed on the upper surface of the substrate 10, and the side walls of the recess pattern 500 include the barrier layer 11, the buffer layer 12, The insulating film 25, and the inner surface of the second insulating film 35. When the intermediate layer is interposed between the second insulating layer 35 and the substrate 10 or another layer is disposed on the second insulating layer 35, May include an inner surface of the intermediate layer and an inner surface of another layer disposed on the second insulating film 35. A detailed description thereof will be described later.

In an exemplary embodiment, at least one recess pattern 500 may be disposed adjacent to the wiring line portion 401 or between one wiring line portion and another wiring line portion.

4 and 6 illustrate that the recess pattern 500 is adjacent to the wiring line portion 401 and is spaced apart from the wiring line portion 401 by a predetermined distance. However, the present invention is not limited thereto, and the recess pattern 500 May be formed at least partially in contact with the wiring line portion 401.

As described above, when the recess pattern 500 penetrating the at least one inorganic insulating film is formed on the substrate 10, the propagation of the crack caused by the impact applied in the manufacturing process, inspection process, Can be suppressed. That is, a crack generated by various impacts has a tendency to grow or propagate through the inorganic insulating film of the substrate 10. When the recessed pattern 500 from which the inorganic insulating film is removed as described above is arranged, 500 cuts off the path along which cracks propagate, and crack propagation can be suppressed. That is, cracks generated in the non-display area NDA grow and can be prevented from reaching the display area DA. In other words, the recess pattern 500 can serve as a crack stopper.

An organic insulating film 75 may be disposed on the second insulating film 35. The organic insulating layer 75 may be formed of an organic material. Illustratively, the organic insulating layer 75 may include, but is not limited to, any one or more materials selected from the group consisting of acrylic, BCB (benzocyclic butene), and polyimide. In addition, the organic insulating layer 75 may be made of a photosensitive material. .

The organic insulating film 75 disposed on the second insulating film 35 in the region where the wiring line portion 401 is formed can at least partially expose the recess pattern 500. [ 6). That is, the organic insulating film 75 can at least partially expose the upper surface of the substrate 10 exposed by the recess pattern 500. [0064] FIG. In other words, the organic insulating film 75 may expose all or a part of the upper surface of the substrate 10 exposed by the recess pattern 500.

The organic insulating film 75 may cover a part of the wiring pad portion 402 disposed on the second insulating film 35 and the second insulating film 35 in the region where the wiring pad portion 402 is disposed. (See FIG. 7). That is, the organic insulating film 75 can expose a part of the wiring pad portion 402. In other words, the organic insulating film 75 may include a contact portion 72 which penetrates the organic insulating film 75 and at least partially exposes the upper surface of the wiring pad portion 402. As described above, various inspection apparatuses for checking the performance of the substrate 10 or a flexible printed circuit (FPC) connected to the printed circuit board 10 are connected to the wiring pad unit 402 . That is, by exposing the wiring pad portion 402, the contact portion can induce the above-described apparatus and the like to be connected to the wiring pad portion 402.

In the exemplary embodiment, the organic insulating film 75 may be formed of substantially the same material as the planarizing film 70 of the display area DA. In other words, the organic insulating film 75 can be formed while forming the planarization film 70 in the display area DA. The planarizing film 70 of the display area DA and the organic insulating film 75 of the non-display area NDA may be formed independently of each other, have.

Hereinafter, other embodiments of the present invention will be described. In the following embodiments, the same components as those already described are referred to as the same reference numerals, and redundant description will be omitted or simplified.

FIG. 8 is a partially enlarged view of an array substrate according to a modification of FIG. 4; FIG. 8, an array substrate according to a modification of the present invention is different from the embodiment of FIG. 4 in that a plurality of recess patterns 507 are formed between one wiring line portion and another adjacent wiring line portion to be.

At least one recess pattern 507 may be disposed between one wiring line portion and another adjacent wiring line portion. 8 illustrates that three recess patterns 507 are arranged in a line between one wiring line portion and another adjacent wiring line portion, the number and arrangement of the recess patterns 507 are limited to this It does not. That is, the recess pattern 507 may be a plurality of recess patterns 507, and the plurality of recess patterns 507 may be arranged in a line or arranged in a matrix shape having a plurality of rows and columns. This will be described later.

9 is a partially enlarged view of an array substrate according to a modification of Fig. 9, a plurality of recess patterns 508 are disposed between one wiring line portion and another adjacent wiring line portion, and a plurality of recess patterns 508 are formed in the array substrate according to the modified example of the present invention. This embodiment is different from the modification of Fig. 8 in that the matrix is arranged in a matrix having the rows and columns.

As described above, a plurality of recess patterns 508 can be disposed between one wiring line portion and another adjacent wiring line portion. The plurality of recess patterns 508 may be arranged in a line or arranged in a matrix shape having a plurality of rows and columns. FIG. 9 illustrates that the plurality of recess patterns 508 are in the form of three rows by two columns, but this is illustrative only, and the arrangement of the recess patterns 508 is not limited thereto. That is, the number of rows and the number of columns may be greater than or equal to two. 9 illustrates that a plurality of recess patterns 508 are regularly arranged, but the present invention is not limited thereto, and a plurality of recess patterns 508 may be irregularly laid out.

FIG. 10 is a partial enlarged view of the array substrate according to the modification of FIG. 4, FIG. 11 is a sectional view taken along the line V-V 'of FIG. 10, Fig.

Referring to FIGS. 10 to 12, the array substrate according to the modification of FIG. 4 is characterized in that a recess pattern 501 disposed between the wiring line portions 401 is formed to extend between the wiring pad portions 402 4 is different from the embodiment of FIG.

The recess pattern 501 disposed between one wiring line portion 401 and the other wiring line portion 401 can be extended between the wiring pad portion connected to one wiring line portion and the wiring pad portion connected to another wiring line portion have. That is, the recess pattern 501 disposed between the wiring line portions 401 adjacent to each other can extend toward one side of the substrate 10. As described above, the width of the wiring pad portion 402 may be relatively large in comparison with the width of the wiring line portion 401. [ The width d2 of the recess pattern 501 disposed between the wiring pad portions 402 is smaller than the width d1 of the recess pattern 501 disposed between the wiring line portions 401, Can be small. The width of the recess pattern 501 disposed between the wiring line portions 401 and the wiring pad portion 402 may be substantially the same as the width of the recess pattern 501 disposed between the wiring line portions 401 .

FIG. 13 is a sectional view of an array substrate according to a modification of FIG. 11, and FIG. 14 is a sectional view of an array substrate according to a modification of FIG.

13 and 14, the point that the organic insulating film 75 disposed on the second insulating film 35 covers the substrate 10 exposed by the recess pattern 501 is the same as the embodiment of FIGS. 11 and 12 .

As described above, the organic insulating film 75 may be disposed on the second insulating film 35. The organic insulating film 75 may completely cover the upper surface of the substrate 10 exposed by the recess pattern 501. That is, the organic insulating film 75 may be formed on the second insulating film 35, The side wall of the recessed pattern 500 and the bottom surface of the recessed pattern 500 can be covered. 11 and 12 illustrate that the organic insulating film 75 completely covers the upper surface of the substrate 10 exposed by the recess pattern 501. However, the present invention is not limited to this, All or a part of the upper surface of the substrate 10 exposed by the seth pattern 501 can be exposed. The contact portion 72 that at least partially exposes the wiring pad portion 402 may be formed in the organic insulating film 75 is substantially the same as that described above with reference to FIG. 7, and a detailed description thereof will be omitted .

15 is a partially enlarged view of an array substrate according to a modification of Fig. 16 is a cross-sectional view taken along line VII-VII 'of FIG.

15 and 16, the array substrate according to the modification of FIG. 10 is disposed on the inner side of the wiring pad portion 402 and extends through the wiring pad portion 402 to expose the upper surface of the substrate 10 And differs from that of FIG. 8 in that it further includes a seth groove 502.

The recessed groove 502 may be disposed inside the wiring pad portion 402. More specifically, the recessed groove 502 can be disposed inside the outer periphery of the wiring pad portion 402. [

The recessed groove 502 sequentially penetrates the wiring pad portion 402, the second insulating film 35, the first insulating film 25, the buffer layer 12 and the barrier layer 11 to form the upper surface of the substrate 10 Can be exposed. That is, the bottom surface of the recessed groove 502 includes the upper surface of the substrate 10, and the sidewall of the recessed trench 502 includes the wiring pad portion 402, the second insulating film 35, the first insulating film 25 ), The buffer layer 12, and the inner surface of the barrier layer 11.

As described above, the organic insulating layer 75 may be disposed on the second insulating layer 35 and the wiring pad portion 402. 16 illustrates that the organic insulating film 75 exposes the entire upper surface of the substrate 10 exposed by the second insulating film 35, the wiring pad portion 402 and the recessed trenches 502. However, The organic insulating film 75 may at least partially cover the upper surface of the substrate 10 exposed by the recessed groove 502. [ When the recessed groove 502 for exposing the upper surface of the substrate 10 through the wiring pad portion 402 is disposed in the wiring pad portion 402, A crack generated by an impact applied to the wiring pad portion 402 at the time of disconnection is connected to the display region DA through an inorganic insulating film disposed under the wiring pad portion 402 or the wiring pad portion 402. [ As shown in Fig.

 17 is a cross-sectional view of an array substrate according to a modification of Fig. FIG. 18 is a cross-sectional view of an array substrate according to a modification of FIG. 7;

Referring to FIGS. 17 and 18, the array substrate according to the modification of FIGS. 6 and 7 has a structure in which the second insulating film 35 includes the first sub-insulating film 31 and the second sub- And the embodiment of FIG.

As described above, the second insulating film 35 may be a single film structure, but is not limited thereto, and may have a multi-layer structure including at least two insulating layers. The insulating film covering the first insulating film 25 is referred to as a first sub-insulating film 31 and the insulating film covering the first sub-insulating film 31 is referred to as a second sub-insulating film 32. [

The first sub-insulating film 31 and the second sub-insulating film 32 may be inorganic insulating films made of an inorganic material. For example, the first sub-insulating film 31 and the second sub-insulating film 32 may include at least one selected from silicon oxide and silicon nitride, but the material of the first sub-insulating film 31 and the second sub- But is not limited thereto. The first sub-insulating film 31 and the second sub-insulating film 32 may be made of materials different from each other.

The structure in which the second insulating film 35 has a multilayer structure can be attributed to the structure of the display area DA. Specifically, although not shown in the drawing, a storage capacitor may be disposed adjacent to the thin film transistor in the display area DA. In the exemplary embodiment, the storage capacitor includes a first gate metal disposed on the gate insulating film 20, a first sub-insulating film 31 disposed on the first gate metal, 2 sub-insulating film 32 and a second gate metal disposed on the second sub-insulating film 32. Further, corresponding to such a storage capacitor, the source / drain electrode 62 of the thin film transistor can be disposed on the second sub-insulating film 32. [ However, it should be understood that the structure of the display area DA is not limited thereto.

19 is a partially enlarged view of an array substrate according to another embodiment of the present invention. 20 is a cross-sectional view taken along the line VIII-VIII 'of FIG. 19;

19 and 20, an array substrate according to another embodiment of the present invention includes a wiring line portion 411 extending toward one side of the substrate 10, It is different.

The wiring line portion 411 may have at least one bent portion. In the exemplary embodiment, the wiring line portion 411 has a jig jig shape and can extend toward one side of the substrate 10. [ For convenience of description, a direction toward one side of the substrate 10 is defined as a first direction. The direction perpendicular to the first direction will be referred to as a second direction, and the direction opposite to the second direction will be referred to as a third direction.

As shown in FIG. 19, the wiring line portions 411 extending in the first direction extend at regular intervals in the second direction, extend at regular intervals in the first direction, then extend at regular intervals in the third direction, And again extend in the first direction. That is, it may be sequentially extended in the order of the first direction, the second direction, the first direction, the third direction, and the first direction.

In an exemplary embodiment, the distance extending in the second direction and the distance extending in the third direction may be substantially the same, but are not limited thereto.

In other words, the wiring line portion 411 is formed by sequentially extending in the order of the first direction, the second direction, the first direction, the third direction and the first direction, and repeating this sequence at least once have.

When the wiring line portion 411 is sequentially extended in the order of the first direction, the second direction, the first direction, the third direction and the first direction as described above, the second direction, the first direction and the third direction A certain space may be defined inside the wiring line portion 411 extending in the third direction, the first direction and the second direction. In an exemplary embodiment, the recess pattern 503 is formed in a space defined by the wiring line portion 411 extending in the second direction, the first direction and the third direction, or the third direction, the first direction and the second direction . In other words, the wiring line portion 411 is disposed adjacent to the outer periphery of each recess pattern 503, and can be disposed along a part of the outer periphery of each recess pattern 503. [ In other words, the recess pattern 503 can be disposed between the wiring line portions 411 extending in a jig jig shape. That is, at least one or more recess patterns 503 may be disposed between the wiring line portions 411.

To describe again with reference to the recess pattern 503, a plurality of recess patterns 503 are arranged in a matrix shape having columns and rows, and a plurality of recess patterns 503 having a matrix shape having a plurality of columns and rows A wiring line portion 411 extending in a jiggag shape can be disposed. FIG. 19 illustrates a case where a plurality of recess patterns 503 are aligned along a straight line in the row direction and are staggered in the column direction. However, the arrangement pattern of the recess pattern 503 is not limited thereto, The recess patterns 503 may be aligned along a straight line in the row and column direction, staggered in the row direction, aligned in the column direction, staggered in the column direction, and aligned along the straight line in the row direction have.

The wiring line portions 411 may be disposed between the recessed patterns 503 arranged in a matrix form and may be disposed between one wiring line portion 411 and another wiring line portion 411, A seth pattern 503 can be disposed.

21 is a partially enlarged view of an array substrate according to another embodiment of the present invention. Referring to FIG. 21, the array substrate according to another embodiment of the present invention is different from the embodiment of FIG. 4 in that the wiring line portion 421 extends in a curve shape having a pitch.

In the array substrate according to another embodiment of the present invention, the wiring line portion 421 may be extended in a curve shape having a pitch. In other words, the wiring line portion 421 may have a corrugated shape. In other words, the wiring line portion 421 can be extended in a meandering manner with a gentle curve.

When the wiring line portion 421 extends in a curved line shape having a pitch, a valley portion and a floor portion may be formed on both sides of the wiring line portion 421. That is, at the one side of each wiring line portion 421, the valley portion and the floor portion are repeated at least once, and at the other side of each wiring line portion 421, the floor portion and the valley portion can be repeated at least once.

The recess pattern 504 may be disposed adjacent to the valley of the wiring line portion 421. [ At least one recess pattern 504 may be disposed adjacent to the valleys formed on one side and the other side of each wiring line portion 421. 19 illustrates the case where the wiring line portion 421 is adjacent to the valley portion, but the present invention is not limited thereto, and the recess pattern 504 may be in partial contact with the valley portion of the wiring line portion 421. [

Referring again to the recess pattern 504, a plurality of recess patterns 504 are arranged in a matrix shape having rows and columns, and a plurality of recess patterns 504 having a matrix shape having a plurality of columns and rows An extended wiring line portion 421 having a curved shape with a pitch can be disposed.

19 illustrates a case where a plurality of recess patterns 504 are aligned along a straight line in the row direction and are staggered in the column direction, but the arrangement pattern of the recess pattern 504 is not limited thereto, The recessed patterns 504 may be aligned along a straight line in the row and column directions, staggered in the row direction, aligned in the column direction, staggered in the column direction and aligned along the straight line in the row direction have.

The wiring line portion 421 may be disposed between the recessed patterns 504 arranged in a matrix form and may be disposed between one wiring line portion 421 and the other wiring line portion 421, A seth pattern 504 may be disposed.

Figure 222 is a plan view of an array substrate according to another embodiment of the present invention. FIG. 23 is an enlarged partial view of a portion 'C' in FIG. 22; FIG. 24 is a cross-sectional view taken along line IX-IX 'of Fig. FIG. 25 is an enlarged view of a portion 'D' of FIG. 22 enlarged. 26 is a cross-sectional view taken along the line X-X of Fig.

22 to 25, an array substrate according to another embodiment of the present invention includes the cell ID pattern 45 and / or the cutting line 700 in the non-display area NDA, It is different.

The array substrate according to another embodiment of the present invention may include a cell ID pattern 45 and / or a cutting line 700 in the non-display area NDA.

The cell ID pattern 45 may be disposed in the non-display area NDA. In the exemplary embodiment, the cell ID pattern 45 may be disposed outside the wiring line portion 401 disposed at the outermost of the plurality of wiring line portions 401. That is, adjacent to the wiring line portion 401 disposed at the outermost portion. On the cell ID pattern 45, a unique number for identifying the array substrate, various graphics, an identification code, and the like may be patterned. That is, information on the array substrate can be acquired through the patterned unique number on the cell ID pattern 45, various graphics, identification codes, and the like.

For a detailed description of the cell ID pattern, reference is made to Figures 23-24.

23 and 24 illustrate that the cell ID pattern 45 has a rectangular shape. However, the shape of the cell ID pattern 45 is not limited thereto, and the shape of the cell ID pattern 45 may be circular, or at least partially including a curve.

As described above, a unique number, various graphics or identification codes can be patterned on the cell ID pattern 45. 23 illustrates a case where a cross-shaped figure 46 is patterned on the cell ID pattern 45, but this is an example, and the shape of various figures or the like formed on the cell ID pattern 45 is limited thereto It is not.

In an exemplary embodiment, the cell ID pattern 45 may be disposed on the buffer layer 12. However, this is merely exemplary and the position of the cell ID pattern 45 is not limited thereto. When the cell ID pattern 45 is disposed on the buffer layer 12, the cell ID pattern 45 may be made of substantially the same material as the semiconductor layer 40 of the display area DA. That is, the cell ID pattern 45 of the non-display area NDA can be formed simultaneously with the semiconductor layer 40 of the display area DA. However, the present invention is not limited thereto, and the cell ID pattern may be formed separately from the semiconductor layer 40 of the display area DA.

 The recess pattern 505 may be disposed along the periphery of the cell ID pattern 45. [ The recess pattern 505 may be disposed adjacent to the outer periphery of the cell ID pattern 45 or adjacent to the outer periphery thereof. In the exemplary embodiment in which the cell ID pattern 45 has a rectangular shape, the recess pattern 505 may be a rectangular shape having a hollow shape, but the shape of the cell ID pattern 45 is not limited as described above, The seth pattern 505 may have a shape corresponding to the shape of the outer periphery of the cell ID pattern 45. When the recess pattern 505 is disposed along the outer periphery of the cell ID pattern 45, cracks generated during the manufacturing process or transportation process of the array substrate are propagated to the cell ID pattern 45, Can be prevented.

The cutting line 700 may be formed in the non-display area NDA of the array substrate according to another embodiment of the present invention. Depending on the type of product, the corner portion of the array substrate non-display area NDA can be cut. That is, the corner portions of the array substrate can be chamfered.

To this end, a cutting line 700 may be formed on the array substrate. In an exemplary embodiment, the cutting lines 700 may be formed extending in oblique directions on both sides of the array substrate non-display area NDA. That is, the cutting line 700 may at least partially traverse the array substrate.

The angle formed by the cutting line 700 and one side of the array substrate is not limited. That is, the angle formed by the cutting line 700 and one side of the array substrate may be different depending on the applied product.

In order to prevent a crack that may occur in the cutting process, the cutting line 700 may be recessed a predetermined distance from the upper surface of the second insulating film 35. 26, the cutting line 700 may be recessed from the upper surface of the second insulating film 35 to expose the upper surface of the substrate 10. [ In other words, the bottom surface of the cutting line 700 includes the top surface of the substrate 10, and the side walls of the cutting line 700 include the barrier layer 11, the buffer layer 12, the first insulating film 25, And an inner surface of the insulating film 35.

The recess pattern 506 may be disposed adjacent the cutting line 700. Specifically, the recess pattern 506 may be disposed adjacent to the other side of the cutting line 700. In other words, when the array substrate is cut along the cutting line 700 by the cutting process, one side of the cutting line 700 can be removed and the other side of the cutting line 700 can be maintained as it is. The recess pattern 506 is disposed adjacent to the other side of the cutting line 700 and at least one recess pattern 506 may be deployed. The recess patterns 506 may be disposed in alignment in the column and row directions, but are not limited thereto, and may be regularly or irregularly arranged.

If one side of the cutting line 700 is removed by the cutting process, the other side of the cutting line 700 may be vulnerable to impact. In this case, when an impact is applied to the other side of the cutting line 700, cracks are generated due to the impact, the generated cracks can be propagated to the display area DA. When at least one recess pattern 506 is disposed adjacent to the other side of the cutting line 700, the recess pattern 506 may serve as a crack stopper. That is, the propagation of the generated crack can be blocked by the recess pattern 506.

27 is a cross-sectional view of an OLED display according to an embodiment of the present invention.

27, an OLED display device according to an embodiment of the present invention is an array substrate having a display area DA and a non-display area NDA disposed outside the display area DA, NDA includes a substrate 10, a barrier layer 11 disposed on the substrate 10, a buffer layer 12 disposed on the barrier layer 11, a first insulating film 25 disposed on the buffer layer 12, A second insulating film 35 disposed on the first insulating film 25 and a second insulating film 35 interposed between the first insulating film 25 and the second insulating film 35 or disposed on the second insulating film 35, A recess pattern recessed by a predetermined depth from an upper surface of a plurality of wiring pattern second insulating films 35 extending toward one side of the substrate 10 to at least partially expose an upper surface of the substrate 10, An organic insulating film (7) disposed at least partially to expose an upper surface of the substrate exposed by the recess pattern 5) and an encapsulating member disposed on the array substrate.

27 is a view illustrating a unit pixel region for convenience of description, and it is needless to say that the organic light emitting display according to an embodiment of the present invention is not limited thereto. That is, the organic light emitting diode display according to an exemplary embodiment of the present invention may include a plurality of unit pixel regions as described in the array substrate according to some embodiments of the present invention.

First, the display area DA of the array substrate in the organic light emitting diode display according to the embodiment of the present invention will be described.

The substrate 10 is a member having a plate shape and can play a role of supporting other structures to be described later. The substrate 10 may be formed of a polymer material including glass or plastic as the insulating substrate 10. In an exemplary embodiment, the substrate 10 may be formed of polyimide (PI), but this is illustrative only and the material of the substrate 10 is not limited thereto.

The substrate 10 may be a rigid substrate 10, but is not limited thereto, and may be a substrate 10 having flexibility or flexibility. That is, in this specification, the term "substrate 10" can be understood as a concept including a flexible substrate 10 capable of bending, folding, and rolling.

As shown in Fig. 27, the substrate 10 may have a single layer structure, but is not limited thereto. That is, in other exemplary embodiments, the substrate 10 may have a laminated structure in which two or more layers are laminated. In other words, the substrate 10 may include a base layer and a protective layer disposed on the base layer.

The base layer may be formed of an insulating material. In an exemplary embodiment, the base layer may be formed of polyimide (PI), but the material of the base layer is not limited thereto. A protective layer may be disposed on the base layer. The protective layer may be made of an organic material. For example, the protective layer may include at least one selected from the group consisting of polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), but the protective layer is not limited thereto. .

A barrier layer 11 may be disposed on the substrate 10. The barrier layer 11 prevents penetration of impurity elements and can serve to planarize the surface. In an exemplary embodiment, the barrier layer 11 may be formed of silicon oxide (SiOx) or silicon nitride (SiNx), but the material of the barrier layer 11 is not limited thereto. Further, in other exemplary embodiments, the barrier layer 11 may be omitted depending on the material of the substrate 10 or the processing conditions.

On the barrier layer 11, a buffer layer 12 covering the barrier layer 11 may be disposed. The buffer layer 12 may be an inorganic film formed of an inorganic material. In the exemplary embodiment, the buffer layer 12 may be formed to include at least one selected from the group consisting of silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx) and silicon oxynitride (SiON) 12 are not limited thereto. In addition, the buffer layer 12 may have a single-layer structure or a laminate structure in which two or more layers are stacked. In an exemplary embodiment in which the buffer layer 12 has two layers, the two layers are formed of materials different from each other . For example, the first layer may be made of silicon oxide and the second layer may be made of silicon nitride. However, this is illustrative and the structure of the buffer layer 12 is not limited thereto.

The semiconductor layer 40 may include amorphous silicon or polycrystalline silicon. In the exemplary embodiment, the semiconductor layer 40 may be formed by applying and patterning amorphous silicon and then crystallizing the amorphous silicon. However, the method of forming the semiconductor layer 40 is not limited thereto. In this specification, what is referred to as "semiconductor layer 40" may be understood to include oxide semiconductors, but is not limited thereto.

A gate insulating layer 20 may be formed on the semiconductor layer 40. The gate insulating film 20 may include silicon nitride (SiNx) or silicon oxide (SiOx), but the material of the gate insulating film 20 is not limited thereto. The gate insulating films 20 and 20 may have a single-layer structure, but not limited thereto, and may have a multi-layer structure including at least two insulating layers having different physical properties.

A gate line including a gate line 50, a gate electrode 51, and a gate pad may be disposed on the gate insulating film 20. Examples of the gate wiring include aluminum-based metals such as aluminum (Al) and aluminum alloys; series metals such as silver (Ag) and silver alloys; copper-based metals such as copper (Cu) and copper alloys; molybdenum-based metals such as molybdenum , Chromium (Cr), tantalum (Ta), and titanium (Ti), but the material of the gate wiring is not limited thereto. Semitransparent materials can be used to form gate wirings.

The plurality of gate lines 50 are arranged as described above, and may extend in one direction so as to be parallel to each other.

An interlayer insulating film 30 covering the gate wiring may be disposed on the gate wiring. The interlayer insulating film 30 may be an inorganic film formed of an inorganic material. In the exemplary embodiment, the interlayer insulating film 30 may include silicon nitride (SiNx) or silicon oxide (SiOx), but the material of the interlayer insulating films 30 and 20 is not limited thereto. The interlayer insulating films 30 and 20 may have a single film structure, but the present invention is not limited thereto and may have a multi-layer structure including at least two insulating layers having different physical properties. The interlayer insulating film 30 having a multilayer structure will be described later.

A data line including the source electrode 61, the drain electrode 62, and the data line 60 may be disposed on the interlayer insulating film 30. [ The data line may be formed of a refractory metal such as molybdenum, chromium, tantalum and titanium, or an alloy thereof. However, the material of the data line is not limited thereto, and a transparent or translucent material may be used as a material for forming a data line Can be used.

The data line 60 carries a data signal and may be arranged to intersect the gate line 50. That is, in the exemplary embodiment, the gate line 50 extends in the lateral direction, and the data line 60 may extend in the longitudinal direction so as to intersect with the gate line 50.

In an exemplary embodiment, the data line 60 and gate line 50 may include a bend. It will be apparent to those skilled in the art that a detailed description thereof will not be given to avoid obscuring the scope of the present invention.

The source electrode 61 may be disposed on the same line as the data line 60 as a part of the data line 60. [ The drain electrode 62 may be formed to extend in parallel with the source electrode 61, in which case the drain electrode 62 may be parallel to a portion of the data line 60.

The gate electrode 51, the source electrode 61 and the drain electrode 62 together with the semiconductor layer 40 constitute one thin film transistor (TFT), and the channel of the thin film transistor is connected to the source electrode 61) and the drain electrode (62).

A planarizing film 70 covering the data wiring and the interlayer insulating film 30 may be disposed on the data wiring. The thickness of the planarizing film 70 may be relatively thicker than that of the interlayer insulating film 30. [ Due to such a difference in thickness, the upper surface of the planarization film 70 may be relatively flat as compared with the lower surface in contact with the interlayer insulating film 30 and the source / drain electrodes 62.

The planarization layer 70 may be formed with a first contact hole at least partially exposing the drain electrode 62. Specifically, the first contact hole penetrates the planarizing film 70, and can partially expose the upper surface of the drain electrode 62. [

A first electrode 80 may be disposed on the planarization layer 70 and the exposed drain electrode 62. That is, the first electrode 80 may be disposed to cover the top surface of the planarization layer 70, the sidewalls of the first contact holes, and the drain electrode 62, thereby forming the first electrode 80 and the drain electrode 62, Can be electrically connected. In an exemplary embodiment, the first electrode 80 may be, but is not limited to, an anode electrode. The first electrode 80 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO), but the material of the first electrode 80 and the electrode 70 is not limited thereto. Do not.

A pixel defining layer may be disposed on the first electrode 80. The pixel defining layer may at least partially expose the first electrode 80. The pixel defining layer 40 may include at least one organic material selected from the group consisting of benzocyclobutene (BCB), polyimide (PI), polyamide (PA), acrylic resin, Or an inorganic material such as silicon nitride or the like. The pixel defining layer 40 may also be formed of a photosensitive agent including a black pigment. In this case, the pixel defining layer 40 may serve as a light shielding member.

An organic layer may be disposed on the first electrode 80 exposed by the pixel defining layer. The organic layer 91 may include organic material layers included in the organic light emitting diode display 100, that is, an organic light emitting layer (EML), a hole injection layer (HIL), a hole transport layer (HTL), an electron injection layer (EIL), an electron transport layer (ETL), and the like. The organic layer 91 may have a single-layer structure including one selected from the organic material layers, or may have a multi-layer structure including two or more layers.

A second electrode 92 may be formed on the organic layer 91. The second electrode 92 may cover the pixel defining layer 90 and the organic layer 91. In the exemplary embodiment, the second electrode 92 may be a front electrode covering the pixel defining layer 90 and the organic layer 91, but is not limited thereto. Also, in the exemplary embodiment, the second electrode 92 may be a cathode electrode.

The second electrode 92 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO), but the material of the second electrode 92 is not limited thereto.

The non-display area NDA of the array substrate may be substantially the same as that described above in the array substrate for some embodiments of the present invention, and therefore, a detailed description thereof will be omitted.

An encapsulation member may be disposed on the array substrate. In this specification, the sealing member may be the sealing film 803 or the sealing substrate 800. 27 illustrates a case where the sealing member is the sealing substrate 800, but the sealing member is not limited thereto. The case where the sealing member is the sealing film 803 will be described with reference to FIG. In an exemplary embodiment, the encapsulation substrates 800 and 10 may be adhered and sealed to the array substrate by an encapsulant (not shown).

In order to allow the encapsulation substrate 800 to be bonded to the array substrate, the encapsulation material may be at least one selected from an adhesive epoxy adhesive, an ultraviolet curable adhesive, a frit, and the like, The material of the sealing material is not limited thereto.

The encapsulation substrate 10 can be adhered and bonded to the array substrate by the encapsulation material described above. In an exemplary embodiment, the encapsulation substrate 800 may be formed of any one selected from transparent glass, transparent plastic, transparent polymer, and the like, but the material of the encapsulation substrate 800 is not limited thereto.

A conductive film 801 may be formed on one surface of the encapsulation substrate 800 facing the array substrate. The conductive film 801 may serve to ground the static electricity generated from the outside of the OLED through the sealing substrate 10. It will be apparent to those skilled in the art that various changes and modifications will be apparent to those skilled in the art in order to avoid obscuring the scope of the present invention.

28 is a cross-sectional view of an OLED display according to another embodiment of the present invention.

Referring to FIG. 28, the organic light emitting display according to another embodiment of the present invention is different from the embodiment of FIG. 28 in that the sealing member is a sealing film.

As described above, in the exemplary embodiment, the sealing member may be the sealing film 803. The sealing film 803 may cover the display area DA and the non-display area NDA. In an exemplary embodiment, the sealing film 803 may expose the wiring line portion 401 and / or the wiring pad portion 402 at least partially, but is not limited thereto.

The sealing film 803 may be made of an organic material and / or an inorganic material.

The organic material for forming the sealing film 803 may be, for example, epoxy, acrylate and urethane acrylate, but is not limited thereto. The inorganic material for forming the sealing film 803 may be, for example, aluminum oxide or silicon oxide, but is not limited thereto.

28 illustrates that the sealing film 803 has a single layer structure, but the sealing film 803 is not limited thereto, and the sealing film 803 may have a laminated structure in which one or more layers are laminated. In the exemplary embodiment, the sealing film 803 may have a structure in which the organic film and the inorganic film are laminated at least once, but this is merely an example, and the structure of the sealing film 803 is not limited thereto.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: array substrate
50: gate line
60: Data line
402: wiring line part
401: wiring pad portion
403:
500, 501, 503, 504, 505, 506, 507, 508: recess pattern
502: recess recess
200: scan driver
300: Emission driver
10: substrate
11: barrier layer
12: buffer layer
20: Gate insulating film
30: Interlayer insulating film
70: planarization film
80: first electrode
90: pixel defining film
91: Organic layer
92: second electrode
51: gate electrode
61: source electrode
62: drain electrode
72:
75: organic insulating film
35: second insulating film
25: First insulating film
45: Cell ID pattern
700: Cutting line
800: sealing substrate
803: sealing film

Claims (38)

Board;
A barrier layer disposed on the substrate;
A buffer layer disposed on the barrier layer;
A first insulating layer disposed on the buffer layer;
A second insulating layer disposed on the first insulating layer;
A plurality of wiring patterns interposed between the first insulating film and the second insulating film or disposed on the second insulating film and extending from the first insulating film to one side of the substrate;
A recess pattern disposed adjacent to the wiring pattern and recessed by a predetermined depth from an upper surface of the second insulating film to at least partially expose an upper surface of the substrate; And
And an organic insulating film disposed on the second insulating film and at least partially exposing an upper surface of the substrate exposed by the recess pattern. The method according to claim 1,
Wherein a bottom surface of the recess pattern includes an upper surface of the substrate and a side wall of the recess pattern includes an inner surface of the first insulating layer, the second insulating layer, the buffer layer, and the barrier layer. The method according to claim 1,
Wherein a plurality of the recess patterns are provided, and the plurality of recess patterns are disposed between the plurality of wiring patterns. The method of claim 3,
Each wiring pattern being interposed between the first insulating film and the second insulating film and extending toward one side of the substrate;
A wiring pad portion formed on the second insulating film and having an end at least partially overlapped with the wiring line portion and having one end wider than the wiring line portion; And
And a wiring connecting portion electrically connected to the wiring line portion and the wiring pad portion in contact with each other. 5. The method of claim 4,
Wherein the recess pattern is disposed between wiring line portions adjacent to each other and extends to a portion between adjacent wiring pad portions. 6. The method of claim 5,
And the width of the recessed pattern disposed between the wiring line portions is larger than the width of the recessed pattern disposed between the wiring pad portions. 5. The method of claim 4,
Wherein the wiring line portion extends in a jig jig shape, and at least one recessed pattern is disposed between adjacent wiring line portions. 8. The method of claim 7,
Wherein the recess pattern is arranged between a plurality of wiring line portions and arranged in a matrix form having a plurality of rows and a plurality of rows. 5. The method of claim 4,
Further comprising a recessed groove disposed on the inner side of the wiring pad portion and extending through the wiring pad portion, the second insulating film, the first insulating film, the buffer layer, and the barrier layer to expose an upper surface of the substrate. 5. The method of claim 4,
And the recessed pattern is disposed outside the wiring line portion disposed at the outermost one of the plurality of wiring line portions. 11. The method of claim 10,
Further comprising: a cell ID pattern disposed outside a wiring line portion disposed at an outermost one of the plurality of wiring line portions, wherein the recess pattern is disposed along an outer periphery of the cell ID pattern. The method according to claim 1,
At least one or more cutting lines at least partially crossing the substrate are defined on the substrate, and the recess pattern is disposed adjacent to the cutting line. The method according to claim 1,
Wherein the buffer layer comprises at least one selected from the group consisting of silicon oxide, nitrogen oxide, aluminum oxide, and silicon oxynitride. The method according to claim 1,
Wherein the substrate is a flexible substrate. The method according to claim 1,
Wherein the substrate includes a base layer and a protective layer disposed on the base layer, and the buffer layer is disposed on the protective layer. 16. The method of claim 15,
Wherein the base layer is made of polyimide (PI), and the protective layer is made of polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). The method according to claim 1,
Wherein the organic insulating film covers an upper surface of the substrate exposed by the recess pattern. An array substrate having a display region and a non-display region disposed outside the display region, the non-display region comprising: a substrate;
A barrier layer disposed on the substrate;
A buffer layer disposed on the barrier layer;
A first insulating layer disposed on the buffer layer;
A second insulating layer disposed on the first insulating layer;
A plurality of wiring patterns sandwiched between the first insulating film and the second insulating film or disposed on the second insulating film so as to be spaced apart from each other and extending toward one side of the substrate;
A recess pattern disposed adjacent to the wiring pattern and recessed from the upper surface of the second insulating film by a predetermined depth to at least partially expose an upper surface of the substrate; and a second insulating film disposed on the second insulating film, And an organic insulating film at least partially exposing an upper surface of the substrate. 19. The method of claim 18,
Wherein a bottom surface of the recess pattern includes an upper surface of the substrate and a side wall of the recess pattern includes an inner surface of the first insulating layer, the second insulating layer, the buffer layer, and the barrier layer. 19. The method of claim 18,
Wherein a plurality of the recess patterns are provided, and the plurality of recess patterns are disposed between the plurality of wiring patterns. 21. The method of claim 20,
Each wiring pattern being interposed between the first insulating film and the second insulating film and extending toward one side of the substrate;
A wiring pad portion formed on the second insulating film and having an end at least partially overlapped with the wiring line portion and having one end wider than the wiring line portion; And
And a wiring connecting portion electrically connected to the wiring line portion and the wiring pad portion in contact with each other. 22. The method of claim 21,
Wherein the recess pattern is disposed between wiring line portions adjacent to each other and extends to a portion between adjacent wiring pad portions. 23. The method of claim 22,
And the width of the recess pattern disposed between the wiring line portions is larger than the width of the recess pattern disposed between the wiring pad portions. 22. The method of claim 21,
Wherein the wiring line portion extends in a jig jig shape, and at least one recessed pattern is disposed between adjacent wiring line portions. 25. The method of claim 24,
Wherein the recess pattern is arranged between a plurality of wiring line portions and arranged in a matrix form having a plurality of rows and a plurality of rows. 22. The method of claim 21,
Further comprising a recessed groove disposed on the inner side of the wiring pad portion and extending through the wiring pad portion, the second insulating film, the first insulating film, the buffer layer, and the barrier layer to expose an upper surface of the substrate. 22. The method of claim 21,
And the recessed pattern is disposed outside the wiring line portion disposed at the outermost one of the plurality of wiring line portions. 22. The method of claim 21,
Further comprising: a cell ID pattern disposed outside a wiring line portion disposed at an outermost one of the plurality of wiring line portions, wherein the recess pattern is disposed along an outer periphery of the cell ID pattern. 19. The method of claim 18,
At least one or more cutting lines at least partially crossing the substrate are defined on the substrate, and the recess pattern is disposed adjacent to the cutting line. 19. The method of claim 18,
Wherein the buffer layer comprises at least one selected from the group consisting of silicon oxide, nitrogen oxide, aluminum oxide, and silicon oxynitride. 19. The method of claim 18,
Wherein the wiring pattern is a gate wiring or a data wiring. 19. The method of claim 18,
Wherein the substrate is a flexible substrate. 19. The method of claim 18,
Wherein the substrate includes a base layer and a protective layer disposed on the base layer, and the buffer layer is disposed on the protective layer. 34. The method of claim 33,
Wherein the base layer is made of polyimide (PI), and the protective layer is made of polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). 19. The method of claim 18,
Wherein the organic insulating film covers an upper surface of the substrate exposed by the recess pattern. 19. The method of claim 18,
Wherein the display region is provided with a gate wiring, a data wiring including a data pad, a source / drain electrode and a data line including a gate pad, a gate electrode and a gate line, and the wiring pattern is the same as the gate wiring or the data wiring ≪ / RTI > An array substrate having a display region and a non-display region disposed outside the display region, the non-display region comprising: a substrate;
A barrier layer disposed on the substrate;
A buffer layer disposed on the barrier layer;
A first insulating layer disposed on the buffer layer;
A second insulating layer disposed on the first insulating layer;
A plurality of wiring patterns sandwiched between the first insulating film and the second insulating film or disposed on the second insulating film so as to be spaced apart from each other and extending toward one side of the substrate;
A recess pattern disposed adjacent to the wiring pattern and recessed by a predetermined depth from an upper surface of the second insulating film to at least partially expose an upper surface of the substrate; And an organic insulating film disposed on the second insulating film and at least partially exposing an upper surface of the substrate exposed by the recess pattern; And
And an encapsulation member disposed on the array substrate. 39. The method of claim 37,
Wherein the sealing member is an encapsulating substrate or a sealing film.

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