KR102463349B1 - Display device - Google Patents

Abstract

SUMMARY OF THE INVENTION An embodiment of the present invention provides a display device capable of preventing loss of lead lines provided for testing whether a data line is defective and preventing a line defect. A display device according to an exemplary embodiment includes panel pads, data lines connected to one side of the panel pads, and first and second lead lines connected to the other side of the panel pads. The first and second lead lines are alternately disposed, and the first lead lines are disposed on a different layer from the second lead lines.

Description

display device {DISPLAY DEVICE}

An embodiment of the present invention relates to a display device including lead lines.

As the era develops into an information society, the importance of flat panel display devices (FPDs) having excellent characteristics such as thinness, light weight, and low power consumption is increasing. Flat panel displays include a liquid crystal display device (LCD), a plasma display panel device (PDP), an organic light emitting display device (OLED), and the like, and recently electrophoresis. An electrophoretic display device (EPD) is also widely used.

Among them, liquid crystal display devices and organic light emitting display devices including thin film transistors have excellent resolution, color display, and image quality, and are widely commercialized as display devices for televisions, notebook computers, tablet computers, or desktop computers.

A display panel constituting a conventional display device includes a display area in which an image is displayed and a non-display area in which an image is not displayed. In the display area, pixels are formed in each area where the gate line and the data line intersect. The non-display area is disposed on at least one side of the display area. The non-display area includes a pad area. Panel pads are provided in the pad area. In order to inspect whether the display panel is defective, an inspection area may be provided at an outer side of the display panel. In the inspection area, inspection pads for inspecting whether the data lines are defective, and lead lines connecting the inspection pads to the panel pads are provided. These panel pads may be gate pads or data pads.

In a conventional display device, a passivation layer and a planarization layer are provided so that the panel pads are exposed using a separate mask. However, in this case, there is a problem in that the process cost increases. To solve this problem, in a conventional display device, a method of exposing panel pads by forming a passivation layer on the entire surface of the base substrate and then removing a part of the passivation layer provided in the pad area using a laser has been devised.

However, since a separate passivation layer is not provided on the lead lines, some of the lead lines may be lost together with a portion of the passivation layer by the laser in a process of removing a portion of the passivation layer. If some of the lead lines are lost, the connection between the test pads and the panel pads is cut off, so it is difficult to inspect the display device for defects. Also, since a separate protective layer is not provided on some of the lead lines, line defects may occur in the display panel due to foreign substances.

SUMMARY OF THE INVENTION An embodiment of the present invention provides a display device capable of preventing loss of lead lines provided for testing whether a data line is defective and preventing a line defect.

A display device according to an exemplary embodiment includes panel pads, data lines connected to one side of the panel pads, and first and second lead lines connected to the other side of the panel pads. The first and second lead lines are alternately disposed, and the first lead lines are disposed on a different layer from the second lead lines.

In an embodiment of the present invention, the first and second lead lines are alternately arranged with each other. In addition, the first lead line is provided on the same layer as the light blocking layer, and the second lead line is provided on the same layer as the gate line. Accordingly, a passivation layer and a planarization layer protecting the first and second lead lines may be provided on the first and second lead lines. As a result, in the embodiment of the present invention, loss of the first and second lead lines by the laser can be prevented in the process of irradiating the passivation layer and the planarization layer with the laser to expose the panel pads.

In addition, in the embodiment of the present invention, since the passivation layer and the planarization layer protect the first and second lead lines, line defects caused by foreign substances generated in the process of cutting each of the display panels provided on the array mother substrate can be prevented. can

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below or will be clearly understood by those skilled in the art from such description and description.

1 is an exemplary view showing an array mother substrate including a plurality of display panels;
FIG. 2 is an exemplary view illustrating in detail display panels adjacent to each other of FIG. 1;
FIG. 3 is a cross-sectional view illustrating a cross-section of one side of the display area of FIG. 2 ;
FIG. 4 is a plan view showing a detailed area A of FIG. 2 ;
5 is a cross-sectional view taken along line I-I' of FIG. 4;
6 is a cross-sectional view taken along line II-II' of FIG. 4;
7 is a cross-sectional view taken along line III-III' of FIG. 4;
8 is a plan view schematically illustrating a display device according to an embodiment of the present invention;

The meaning of the terms described herein should be understood as follows.

The singular expression is to be understood as including the plural expression unless the context clearly defines otherwise, and the terms "first", "second", etc. are used to distinguish one element from another, The scope of rights should not be limited by these terms. It should be understood that terms such as “comprise” or “have” do not preclude the possibility of addition or existence of one or more other features or numbers, steps, operations, components, parts, or combinations thereof. The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It means a combination of all items that can be presented from more than one. The term “on” is meant to include not only cases in which a certain component is formed directly on top of another component, but also a case in which a third component is interposed between these components.

Hereinafter, a preferred example of a display device according to the present invention will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

1 is an exemplary view illustrating an array mother substrate including a plurality of display panels. Referring to FIG. 1 , in order to reduce the manufacturing cost of the display device, a plurality of display panels 100 may be formed on the array mother substrate 10 .

As the number of the plurality of display panels 100 formed on the array mother substrate 10 increases, the manufacturing cost of the display device may be further reduced. In order to increase the number of display panels 100 formed on the array mother substrate 10 , each of the display panels 100 is disposed on the display panels 100 adjacent thereto in the first direction (y-axis direction) as shown in FIG. 1 . It may be formed to abut. That is, upper and lower sides of one display panel 100 may contact other display panels 100 . Specifically, an upper side of one display panel 100 abuts with a lower side of another display panel 100 adjacent in the first direction (y-axis direction), and the lower side of the display panel 100 is in the first direction (y-axis direction). direction) and may come in contact with the upper side of another display panel 100 adjacent to each other.

Each of the display panels 100 may be formed to be spaced apart from the adjacent display panels 100 by a predetermined distance s in the second direction (x-axis direction) as shown in FIG. 1 . The second direction (x-axis direction) may be a direction crossing the first direction (y-axis direction). That is, the left and right sides of one display panel 100 may be formed to be spaced apart from other display panels 100 by a predetermined distance s. In this case, inspection pads for inspecting defects of thin film transistors and pixels provided in each of the display panels 100 may be provided at a predetermined interval s.

Meanwhile, when each of the plurality of display panels 100 is formed to contact the display panels 100 adjacent thereto in the first direction as shown in FIG. 1 , the display panel 100 includes panel pads connected to the inspection pads. can be provided. The test pads and the panel pads may be connected to each other through lead lines and test lines. The panel pads, lead lines, and inspection lines of the display panel 100 will be described in detail with reference to the following drawings.

FIG. 2 is an exemplary view illustrating in detail display panels adjacent to each other of FIG. 1 . FIG. 3 is a cross-sectional view illustrating a cross-section of one side of the display area of FIG. 2 . In FIG. 2 , only three display panels 100a , 100b , and 100c adjacent in the first direction (y-axis direction) are illustrated for convenience of explanation. Specifically, in FIG. 2, the display panel in contact with the upper side of the first display panel 100a is exemplified as the second display panel 100b, and the display panel in contact with the lower side of the first display panel 100a is the third display panel ( 100c).

2 and 3 , each of the display panels 100a , 100b , and 100c includes a display area DA and a non-display area NDA. Gate lines GL and data lines DL may be formed in the display area DA, and pixels P may be formed at intersections of the gate lines GL and data lines DL. In FIG. 2 , one pixel P provided in an area where one gate line GL and a data line DL intersects is illustrated, but in the display area DA, a plurality of gate lines GL and a plurality of Data lines DL are formed. In addition, a plurality of pixels P may be provided in cross regions of the plurality of gate lines GL and the plurality of data lines DL. In this case, each of the pixels P may include an organic light emitting device for outputting light and a thin film transistor for driving the organic light emitting device.

Specifically, specifically, the display panel 100 includes a base substrate 110 , a buffer layer 130 , a light blocking layer 125 , a thin film transistor T, a passivation layer PAS, a planarization layer PAC, and an organic light emitting device. (OLED), an encapsulation layer 180 , and an upper substrate 190 .

The base substrate 110 may be a glass substrate or a flexible plastic film. For example, the base substrate 110 is a cellulose resin such as triacetyl cellulose (TAC) or diacetyl cellulose (DAC), a cyclo olefin polymer (COP) such as norbornene derivatives, a cyclo olefin copolymer (COC), Acrylic resin such as PMMA(poly(methylmethacrylate), PC(polycarbonate), PE(polyethylene) or PP(polypropylene), polyolefin(polyolefin), PVA(polyvinyl alcohol), PES(poly ether sulfone), PEEK(polyetheretherketone), Polyetherimide (PEI), polyethylenenaphthalate (PEN), or polyester such as polyethyleneterephthalate (PET), polyimide (PI), polysulfone (PSF), or fluoride resin may be a sheet or film containing, However, the present invention is not limited thereto.

The buffer layer 130 is provided on the base substrate 110 . The buffer layer 130 includes a first buffer layer 131 and a second buffer layer 133 . The first buffer layer 131 is provided on the entire surface of the base substrate 110 . The first buffer layer 131 functions to prevent moisture from penetrating into the display panel 100 from the base substrate 110 which is vulnerable to moisture permeation. For example, the first buffer layer 131 may be silicon dioxide (SiO2) or silicon oxynitride (SiON), but is not limited thereto.

The second buffer layer 133 is provided on the first buffer layer 131 . The second buffer layer 133 prevents impurities such as metal ions from diffusing from the base substrate 110 and penetrating into the active layer ACT. In addition, the second buffer layer 133 prevents moisture from penetrating into the display panel 100 from degrading the characteristics of the thin film transistors T. For example, silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), or a multilayer thereof may be used, but is not necessarily limited thereto.

The light blocking layer 125 is provided between the first buffer layer 131 and the second buffer layer 133 . The light blocking layer 125 is provided under the active layer ACT. The light blocking layer 125 protects the active layer ACT from a laser beam or light introduced to the outside. The light blocking layer 125 may be simultaneously provided using the same process as the first lead line 141 among the lead lines 141 and 142 shown in FIG. 2 . The light blocking layer 125 and the first lead line 141 may be provided on the same layer. The light blocking layer 125 and the first lead line 141 may be formed of the same material. For example, the light blocking layer 125 may be made of a transparent conductive material such as ITO, but is not limited thereto, and may be made of a conductive metal material.

The thin film transistor T is provided on the base substrate 110 . The thin film transistor T includes an active layer ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer ILD, a source electrode SE, and a drain electrode DE.

The active layer ACT is provided on the second buffer layer 133 . The active layer ACT has one end region A1 positioned on the source electrode SE side, the other end region A2 positioned on the drain electrode DE side, and a center positioned between the one end region A1 and the other end region A2. It may include an area A3. The central region A3 may be made of a semiconductor material undoped with a dopant, and the one end region A1 and the other end region A2 may be made of a semiconductor material doped with a dopant.

The gate insulating layer GI is provided on the active layer ACT. The gate insulating layer GI functions to insulate the active layer ACT from the gate electrode GE. The gate insulating layer GI covers the active layer ACT and is formed on the entire surface of the display area DA. The gate insulating layer GI may be formed of an inorganic layer, for example, silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), or a multilayer thereof, but is not limited thereto.

The gate electrode GE is provided on the gate insulating layer GI. The gate electrode GE overlaps the central region A3 of the active layer ACT with the gate insulating layer GI interposed therebetween. The gate electrode GE is connected to the gate line GL. The gate electrode GE and the gate line GL may be simultaneously prepared using the same process. The gate electrode GE and the gate line GL may be disposed on the same layer. The gate electrode GE and the gate line GL may be formed of the same material. In this case, the gate electrode GE and the gate line GL may be simultaneously prepared using the same process as the second lead line 142 among the lead lines 141 and 142 illustrated in FIG. 2 . The gate electrode GE, the gate line GL, and the second lead line 142 may be disposed on the same layer. The gate electrode GE, the gate line GL, and the second lead line 142 may be formed of the same material. The gate electrode GE may include, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a single layer or multiple layers made of any one or an alloy thereof, but is not limited thereto.

The interlayer insulating layer ILD is provided on the gate electrode GE. The interlayer insulating layer ILD covers the gate electrode GE and may be provided on the entire surface of the base film 110 . The interlayer insulating layer ILD may be formed of the same inorganic layer as the gate insulating layer GI, for example, silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), or a multilayer thereof, but is not limited thereto. does not

The source electrode SE and the drain electrode DE are disposed to be spaced apart from each other on the interlayer insulating layer ILD. A portion of the first contact hole CNT1 exposing a portion of the region A1 at one end of the active layer ACT and a portion of the region A2 at the other end of the active layer ACT are formed in the gate insulating layer GI and the interlayer insulating layer ILD. A second contact hole CNT2 to be exposed is provided. The source electrode SE is connected to one end area A1 of the active layer ACT through the first contact hole CNT1 , and the drain electrode DE is connected to the active layer ACT through the second contact hole CNT2 . is connected to the other end area A2 of the

The source electrode SE and the drain electrode DE are connected to the data line DL. The source electrode SE, the drain electrode DE, and the data line DL may be simultaneously formed using the same process. The source electrode SE, the drain electrode DE, and the data line DL may be disposed on the same layer. The source electrode SE, the drain electrode DE, and the data line DL may be formed of the same material. The source electrode SE and the drain electrode DE may include, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), or neodymium (Nd). and copper (Cu), or may be a single layer or a multilayer made of an alloy thereof, but is not limited thereto. The configuration of the thin film transistor T is not limited to the example described above, and can be variously modified into a known configuration that can be easily implemented by those skilled in the art.

The passivation layer PAS is provided on the entire upper surface of the base substrate 110 . The passivation layer PAS is provided on the thin film transistor T. The passivation layer PAS serves to protect the thin film transistor T. In this case, the passivation layer PAS may also be provided on the lead lines 141 and 142 of the non-display area NDA. The passivation layer PAS may be formed of an inorganic layer, for example, silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), or a multilayer thereof, but is not limited thereto.

The planarization layer PAC is provided on the entire upper surface of the base substrate 110 . The planarization layer PAC is provided on the passivation layer PAS. The planarization layer PAC serves to planarize the upper portion of the base substrate 110 on which the thin film transistor T is provided. In this case, the passivation layer PAS may also be provided on the lead lines 141 and 142 of the non-display area NDA. The planarization layer (PAC) is made of, for example, acryl resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, etc. may be made, but is not limited thereto. A third contact hole CNT3 exposing the drain electrode DE of the thin film transistor T is provided in the passivation layer PAS and the planarization layer PAC located in the display area DA. The drain electrode DE and the anode electrode AND are connected through the third contact hole CNT3 .

The organic light emitting diode (OLED) is provided on the thin film transistor (T). The organic light emitting diode OLED includes an anode electrode AND, an organic layer EL, and a cathode electrode CAT. The anode electrode AND is connected to the drain electrode DE of the thin film transistor T through the third contact hole CNT3 provided in the passivation layer PAS and the planarization layer PAC. A bank B is provided between the anode electrodes AND adjacent to each other, so that the anode electrodes AND adjacent to each other may be electrically insulated. The bank B may be formed of, for example, an organic layer such as polyimides resin, acryl resin, benzocyclobutene (BCB), and the like, but is not limited thereto.

The organic layer EL is provided on the anode electrode AND. The organic layer EL may include a hole transporting layer, an organic light emitting layer, and an electron transporting layer. Furthermore, the organic layer EL may further include at least one functional layer for improving luminous efficiency and/or lifespan of the light emitting layer.

The cathode electrode CAT is provided on the organic layer EL and the bank B. When a voltage is applied to the anode electrode AND and the cathode electrode CAT, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic light emitting layer to emit light.

3 illustrates that the display panel 100 is implemented in a top emission method, but is not limited thereto, and may be implemented in a bottom emission method. In the top emission method, it is preferable that the anode electrode AND is formed of a metal material having high reflectance such as aluminum, a laminate structure of aluminum and ITO, and the cathode electrode CAT is formed of a transparent metal material such as ITO and IZO.

The encapsulation layer 180 is provided on the thin film transistor T and the organic light emitting diode OLED. The encapsulation layer 180 functions to protect the thin film transistor T and the organic light emitting diode OLED from external impact, and to prevent moisture from penetrating into the display panel 100 .

The upper substrate 190 is provided on the encapsulation layer 180 . The upper substrate 190 may be a protection film when the display panel 100 is implemented in a bottom emission method, and polyimide and polyimide when the display panel 100 is implemented in a top emission method. The same may be a flexible plastic film. However, the present invention is not limited thereto, and the upper substrate 190 may be a metal layer for protecting the thin film transistor T and the organic light emitting diode OLED from external impact and preventing moisture from penetrating.

The non-display area NDA of the display panel 100 is disposed at an edge of the display area DA. A gate driver 120 , gate pads GP, panel pads DP, inspection lines 151 to 153 , and lead lines 141 and 142 are provided in the non-display area NDA.

The gate driver 120 may be formed in a gate driver in panel (GIP) method outside one side of the display area DA. However, the present invention is not limited thereto, and the gate driver 120 may be formed on both sides of the display area DA by a GIP method, or manufactured as a driving chip and mounted on a flexible film, and mounted on a flexible film using a tape automated bonding (TAB) method. It may be attached to one side of (100).

The gate pads GP may be provided at first side edges of each of the display panels 100a, 100b, and 100c. Here, the first side may be a lower side of each of the display panels 100a. The gate pads GP are connected to the gate control signal lines GCL. The gate control signal lines GCL connect the gate pads GP and the gate driver 120 .

The panel pads DP, like the gate pads GP, may be provided at first side edges of each of the display panels 100a, 100b, and 100c. In this case, one side of the panel pads DP may be connected to the data lines DL, and the other side of the panel pads DP may be connected to the lead lines 141 and 142 . These panel pads DP may be data pads.

The lead lines 141 and 142 connect the panel pads DP and the inspection lines 151 to 153 . The lead lines 141 and 142 may be provided between the panel pads DP of the display panel 100 and the inspection line 151 of at least one of the inspection lines 151 to 153 . The lead lines 141 and 142 may be formed to cross the two display panels. That is, the lead lines 141 and 142 may extend from a first side of any one of the display panels and may be formed on a second side of another display panel adjacent to the one of the display panels. For example, the lead lines 141 and 142 are connected to the panel pads DP provided on the first side of the first display panel 100a. The lead lines 141 and 142 are connected to the inspection lines 151 to 153 provided on the second side of the third display panel 100a adjacent to the first side of the first display panel 100a. Accordingly, the lead lines 141 and 142 may extend from the first side of the first display panel 100a adjacent to each other and may be formed on the second side of the third display panel 100c. That is, the lead lines 141 and 142 may be formed to cross the first side of the first display panel 100a and the second side of the third display panel 100c adjacent to each other.

The lead lines 141 and 142 include first and second lead lines 141 and 142 . The first and second lead lines 141 and 142 are alternately disposed. For example, the lead lines 141 and 142 may be alternately disposed in the order of the first lead line 141 , the second lead line 142 , and the first lead line 141 . One side of each of the first and second lead lines 141 and 142 is connected to each of the panel pads DP. The other end of each of the first and second lead lines 141 and 142 is connected to at least one inspection line 151 .

The first lead line 141 may be provided on the same layer as the light blocking layer 125 provided under the thin film transistor T in the display area DA. The light blocking layer 125 is disposed under the gate electrode GE and is insulated from the gate electrode GE by at least one buffer layer 133 . The second lead line 142 is disposed on the same layer as the gate lines GL. The gate lines GL are disposed below the data lines DL. The gate lines GL cross the data lines DL and are insulated from the data lines DL by the gate insulating layer GI. In this case, the second lead line 142 may be disposed on the same layer as the gate lines GL. A passivation layer PAS and a planarization layer may be provided on the first and second lead lines 141 and 142 .

In the exemplary embodiment of the present invention, the first and second lead lines 141 and 142 connected to the panel pads DP are alternately disposed with each other, and the first and second lead lines 141 and 142 are formed on different layers. is placed on In addition, a passivation layer PAS and a planarization layer PAC are provided on the first and second lead lines 141 and 142 . As a result, in the embodiment of the present invention, since the passivation layer PAS and the planarization layer PAC protect the first and second lead lines 141 and 142 , in order to expose the panel pads DP, the passivation layer It is possible to prevent loss of the first and second lead lines 141 and 142 by the laser in a process of removing a portion of the PAS and the planarization layer PAC.

In addition, in the embodiment of the present invention, since the passivation layer (PAS) and the planarization layer (PAC) provided on the first and second lead lines 141 and 142 serve as a protective layer, the It is possible to reduce line defects caused by foreign substances generated in the process of scribing each of the provided display panels. These lead lines will be described later with reference to FIGS. 4 to 7 .

The inspection lines 151 to 153 may be provided on the edge of the second side facing the first side of each of the display panels 100a, 100b, and 100c. Here, the second side may be an upper side of each of the display panels 100a. The inspection lines 151 to 153 connect the inspection pads IP, the panel pads DP of the display panel 100 adjacent to the inspection lines 151 to 153, and the gate pads GP. For example, the panel pads DP and gate pads GP provided on the first side of the first display panel 100a are the inspection lines 151 to 153 provided on the second side of the third display panel 100c. ) can be associated with In addition, the panel pads DP and gate pads GP provided on the first side of the second display panel 100b are connected to the inspection lines 151 to 153 provided on the second side of the first display panel 100a. can be connected The test pads IP may be provided at a predetermined interval s between each of the display panels 100a , 100b , and 100c and display panels adjacent in the second direction as shown in FIG. 1 , but is not limited thereto. . In FIG. 2 , only three inspection lines 151 to 153 are illustrated for convenience of description, but the number of inspection lines is not limited thereto.

In the description of the present invention, the present invention has been described by taking the case where the panel pads are data pads as an example, but the present invention is not limited thereto. For example, the embodiment of the present invention may be applied even when the gate driver 120 is manufactured as a driving chip, mounted on a flexible film, and attached to one side of the display panel 100 by a tape automated bonding (TAB) method. In this case, the panel pads according to an embodiment of the present invention may be gate pads, and one side of the panel pads may be connected to the gate lines.

FIG. 4 is a plan view illustrating in detail area A of FIG. 2 according to an embodiment of the present invention. 5 is a cross-sectional view taken along line I-I' of FIG. 4 . FIG. 6 is a cross-sectional view taken along line II-II' of FIG. 4 . 7 is a cross-sectional view taken along line III-III' of FIG. 4 . Accordingly, the same reference numerals are assigned to the same components, and repeated descriptions of repeated parts in the materials and structures of each component are omitted.

4 to 7 , one side of the panel pads DP may be connected to the data lines DL, and the other side of the panel pads DP may be connected to the lead lines 141 and 142 . The panel pads DP and the lead lines 141 and 142 may be provided in the non-display area NDA of the display panel 100 .

5 , a first buffer layer 131 is provided on the base substrate 110 disposed in the non-display area NDA. A first lead line 141 is provided on the first buffer layer 131 . In this case, the first lead line 141 may be provided on the same layer as the light blocking layer shown in FIG. 3 and may be made of the same material. A second buffer layer 133 and a gate insulating layer GI are sequentially provided on the first lead line 141 . A second lead line 141 is provided on the gate insulating layer GI. In this case, the second lead line 141 may be provided on the same layer as the gate line shown in FIG. 2 and may be made of the same material. The first and second lead lines 141 and 142 may be insulated by the second buffer layer 133 .

As described above, each of the first and second lead lines 141 and 142 may be provided on different layers, and may be alternately disposed. An interlayer insulating layer ILD, a passivation layer PAS, and a planarization layer PAC may be sequentially provided on the first and second lead lines 141 and 142 . An interlayer insulating layer ILD, a passivation layer PAS, and a planarization layer PAC may be sequentially provided on the first and second lead lines 141 and 142 .

The panel pads DP may be provided in the non-display area NDA of the display panel 100 . The panel pads DP are provided on the base substrate 110 as shown in FIG. 6 . A buffer layer 130 and a gate insulating layer GI are sequentially provided on the base substrate 110 . In this case, the second lead line 142 may be connected to the other side of the panel pad DP. For example, each of the panel pads DP may include first and second panel pads DP1 and DP2. In this case, the first panel pad DP1 may be disposed on the same layer as the gate line and may be connected to the second lead line 142 . The second panel pad DP2 is disposed on the same layer as the data line DL and may be connected to the data line DL.

The first and second panel pads DP1 and DP2 may be connected through the pad part contact hole PCNT. In this case, the data line DL connected to the second panel pad DP2 and the second lead line 142 connected to the first panel pad DP1 may be electrically connected to each other. The protective electrode 150 may be provided on the panel pad DP. The protective electrode 150 serves to protect the panel pad DP. In the exemplary embodiment of the present invention, the panel pad DP composed of two layers is illustrated, but the configuration of the panel pad DP may be variously changed.

The first lead line 141 may be connected to the other side of the panel pads DP as shown in FIGS. 4 and 7 . In this case, the other side of the panel pad DP may be connected to a portion of the first lead line 141 provided on the base substrate 110 . In this case, in the second buffer layer 133 , the gate insulating layer GI, and the interlayer insulating layer ILD provided on the first lead line 141 , a lead part contact hole exposing a portion of the first lead line 141 ( LCNT) is provided. The other side of the panel pad DP is electrically connected to the first lead line 141 through the lead contact hole LCNT.

In the embodiment of the present invention, the first and second lead lines 141 and 142 are alternately disposed. In addition, the first lead line 141 is provided on the same layer as the light blocking layer 125 , and the second lead line 142 is provided on the same layer as the gate line. Accordingly, a passivation layer PAS and a planarization layer PAC protecting the first and second lead lines 141 and 142 may be provided on the first and second lead lines 141 and 142 . As a result, in the embodiment of the present invention, since the passivation layer PAS and the planarization layer PAC protect the first and second lead lines 141 and 142 , the passivation layer is used to expose the panel pads DP. Loss of the first and second lead lines 141 and 142 by the laser in a process of irradiating the laser to the PAS and the planarization layer PAC may be prevented.

In addition, in the exemplary embodiment of the present invention, since the passivation layer PAS and the planarization layer PAC protect the first and second lead lines 141 and 142 , each of the display panels provided on the array mother substrate 10 . It is possible to reduce line defects caused by foreign substances generated during the cutting process.

8 is a plan view schematically illustrating a display device according to an exemplary embodiment. In FIG. 8 , the X axis indicates a direction parallel to the gate line, the Y axis indicates a direction parallel to the data line, and the Z axis indicates a height direction of the organic light emitting diode display.

Referring to FIG. 8 , a display device according to an embodiment of the present invention includes a display panel 100 , a source drive integrated circuit (hereinafter referred to as “IC”) 310 , a flexible film 330 , and a circuit board ( 350), and a timing controller 400 .

The display panel 100 includes a display area DA and a non-display area NDA. Gate lines and data lines may be formed in the display area DA, and pixels may be formed at intersections of the gate lines and data lines. The gate driver 120 , gate pads, panel pads, inspection lines, and lead lines are provided in the non-display area NDA. Such a display panel 100 has been described with reference to FIGS. 1 to 7 .

The source drive IC 310 receives digital video data and a source control signal from the timing controller 400 . The source drive IC 310 converts digital video data into analog data voltages according to a source control signal and supplies them to data lines. When the source drive IC 310 is manufactured as a driving chip, it may be mounted on the flexible film 330 using a chip on film (COF) or chip on plastic (COP) method.

Panel pads such as data pads are provided in the non-display area NDA of the display panel 100 . Wires connecting the panel pads and the source drive IC 310 and wirings connecting the panel pads and the wirings of the circuit board 350 may be formed on the flexible film 330 . The flexible film 330 is attached on the panel pads by using an anisotropic conducting film, whereby wirings of the panel pads and the flexible film 330 may be connected.

The circuit board 350 may be attached to the flexible films 330 . A plurality of circuits implemented with driving chips may be mounted on the circuit board 350 . For example, the timing controller 400 may be mounted on the circuit board 350 . The circuit board 350 may be a printed circuit board or a flexible printed circuit board.

The timing controller 400 receives digital video data and a timing signal from an external system board (not shown). The timing controller 400 generates a gate control signal for controlling the operation timing of the gate driver 120 and a source control signal for controlling the source driver ICs 330 based on the timing signal. The timing controller 400 supplies the gate control signal to the gate driver 120 and supplies the source control signal to the source drive ICs 310 .

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications, and changes are possible without departing from the technical matters of the present invention. It will be clear to those who have the knowledge of Therefore, the scope of the present invention is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

100: display panel 110: base substrate
120: gate driver 125: light blocking layer
130: buffer layer 141: first lead line
142: second lead line 150: protective electrode
180: encapsulation layer 190: upper substrate
310: source drive IC 330: flexible film
350: circuit board 400: timing control unit
T: thin film transistor OLED: organic light emitting diode
DL: data line DP: panel pad
GL: gate line P: pixel

Claims (7)

panel pads;
data lines connected to one side of the panel pads;
gate lines insulated from the data lines;
a light blocking layer disposed under the gate lines and insulated from the gate lines by at least one buffer layer; and
and first and second lead lines connected to the other side of the panel pads;
The first and second lead lines are alternately arranged,
The first lead lines are disposed on a different layer from the second lead lines,
The first lead lines are disposed on the same layer as the light blocking layer. delete The method of claim 1,
The second lead lines are disposed on the same layer as the gate lines. The method of claim 1,
A display device further comprising a passivation layer and a planarization layer on the first and second lead lines to protect the first and second lead lines. The method of claim 1,
The first and second lead lines are insulated from each other by the at least one buffer layer. The method of claim 1,
The first lead line is connected to any one of the panel pads through a lead contact hole. The method of claim 1,
The display device further comprising a protective electrode provided on the panel pads.

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