KR20210019675A - Display device and method for manufacturing the same - Google Patents

Abstract

The present invention provides a display device capable of minimizing a gap between sub-pixels and maximizing a light emitting area. According to an embodiment of the present invention, the display device comprises: a substrate; a first electrode provided in each of a first sub-pixel and a second sub-pixel disposed adjacent to the first sub-pixel on the substrate; a buffer layer provided on the first electrode; a light emitting layer provided on the buffer layer; and a second electrode provided on the light emitting layer.

Description

Display device and its manufacturing method {DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to a display device that displays an image.

As the information society develops, demands for display devices for displaying images are increasing in various forms. Accordingly, recently, a liquid crystal display (LCD), a plasma display (PDP), a quantum dot light emitting display (QLED), an organic light emitting display (OLED, organic Various display devices such as Light Emitting Display) are being used.

Recently, a head mounted display including such a display device has been developed. Head Mounted Display (HMD) is a glasses-type monitor device of Virtual Reality (VR) or Augmented Reality in which a focus is formed at a close distance in front of the user's eyes by wearing it in the form of glasses or a helmet. In such a head-mounted display, it is important to reduce the pixel spacing and increase the light emitting area to improve performance.

An object of the present invention is to provide a display device capable of reducing a pixel gap.

Another technical object of the present invention is to provide a display device capable of increasing a light emitting area.

A display device according to an exemplary embodiment of the present invention includes a substrate, a first electrode provided on each of a first sub-pixel on the substrate and a second sub-pixel disposed adjacent to the first sub-pixel, a buffer layer provided on the first electrode, And a light emitting layer provided on the buffer layer and a second electrode provided on the light emitting layer.

A method of manufacturing a display device according to another embodiment of the present invention includes forming an insulating material layer on a substrate, forming a metal material layer on the insulating material layer, and performing an etching process on the metal material layer and the insulating material layer at the same time. And forming a trench by performing a pattern, forming a first electrode pattern for each sub-pixel, and forming a buffer layer on the first electrode and the trench.

In another embodiment of the present invention, a method of manufacturing a display device includes forming an insulating material layer on a substrate, forming a metal material layer on the insulating material layer, and forming a non-conductive material layer on the metal material layer. And forming a trench by simultaneously performing an etching process on the metal material layer, the non-conductive material layer, and the insulating material layer, and patterning the first electrode and the buffer layer for each sub-pixel.

According to the present invention, by simultaneously etching the first electrode and the insulating layer to form a trench, it is possible to minimize the non-emission area. The present invention can minimize the spacing between sub-pixels.

In addition, in the present invention, a buffer layer made of a non-conductive material is formed on the first electrode. In the present invention, since the buffer layer is formed on the edge of the first electrode, it is possible to prevent the luminous efficiency from being lowered by the current concentrated on the edge of the first electrode.

In addition, according to the present invention, by forming a thin buffer layer on the upper surface of the first electrode, even if the buffer layer is formed on the entire upper surface of the first electrode, light emission can be made on the entire upper surface of the first electrode. Accordingly, in the present invention, since all regions in which the first electrode is formed become light emitting regions, the light emitting region can be maximized. The present invention can maximize the aperture ratio to minimize current density and improve device life.

In addition, according to the present invention, by disconnecting the charge generation layer by a trench, even if the interval between the sub-pixels is reduced, leakage current may not be generated between adjacent sub-pixels.

In addition, according to the present invention, a separate process for forming a pattern of the first electrode for each sub-pixel is not required, and a separate mask is not required. Accordingly, in the present invention, the process is simplified and the process cost can be greatly reduced.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below or will be clearly understood by those of ordinary skill in the art from such technology and description.

1 is a perspective view illustrating a display device according to an exemplary embodiment of the present invention.
2 is a plan view schematically showing a first substrate.
3 is a schematic cross-sectional view illustrating an example of a sub-pixel included in a display device according to an exemplary embodiment of the present invention.
4 is a plan view schematically illustrating a first electrode, a buffer layer, and a trench of a plurality of sub-pixels.
5 is a cross-sectional view illustrating an example of II of FIG. 2.
6 is a schematic cross-sectional view illustrating an example of a plurality of sub-pixels included in a display device according to an exemplary embodiment of the present invention.
7 is an enlarged view showing area A of FIG. 5.
8 is a cross-sectional view illustrating another example of II of FIG. 2.
9 is an enlarged view showing area B of FIG. 8.
10 is a flowchart illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention.
11A to 11H are cross-sectional views illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention.
12 is a flowchart illustrating a method of manufacturing a display device according to another exemplary embodiment of the present invention.
13A to 13H are cross-sectional views illustrating a method of manufacturing a display device according to another exemplary embodiment of the present invention.
14A to 14C relate to a display device according to another embodiment of the present invention, which relates to a head mounted display (HMD) device.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to examples described below in detail together with the accompanying drawings. However, the present invention is not limited to the examples disclosed below, but will be implemented in a variety of different forms, and only these examples are intended to complete the disclosure of the present invention, and to those of ordinary skill in the technical field to which the present invention pertains. It is provided to fully inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining examples of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in describing the present invention, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted. When'include','have','consists of' and the like mentioned in the present invention are used, other parts may be added unless'only' is used. In the case of expressing the constituent elements in the singular, it includes the case of including the plural unless specifically stated otherwise.

In interpreting the constituent elements, it is interpreted as including an error range even if there is no explicit description.

In the case of a description of the positional relationship, for example, if the positional relationship of two parts is described as'upper','upper of','lower of','next to','right' Or, unless'direct' is used, one or more other parts may be located between the two parts.

First, second, etc. are used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be a second component within the technical idea of the present invention.

In describing the constituent elements of the present invention, terms such as first and second may be used. These terms are only for distinguishing the component from other components, and the nature, order, order, or number of the component is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, the component may be directly connected or connected to that other component, but other components between each component It is to be understood that is "interposed", or that each component may be "connected", "coupled" or "connected" through other components.

Each of the features of the various examples of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each of the examples can be implemented independently of each other or can be implemented together in an association relationship. .

Hereinafter, an example of a display device according to the present invention will be described in detail with reference to the accompanying drawings. In adding reference numerals to elements of each drawing, the same elements may have the same numerals as possible even if they are indicated on different drawings.

1 is a perspective view illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an embodiment of the present invention includes a display panel 100, a source drive integrated circuit (hereinafter referred to as "IC") 210, a flexible film 220, and a circuit board. (230), and a timing control unit (240).

The display panel 100 includes a first substrate 111 and a second substrate 112. The second substrate 112 may be an encapsulation substrate.

Gate lines, data lines, and pixels are formed on one surface of the first substrate 111 facing the second substrate 112. The pixels are provided in a region defined by an intersection structure of gate lines and data lines.

Each of the pixels may include a light emitting device including a thin film transistor, a first electrode, a light emitting layer, and a second electrode. Each of the pixels supplies a predetermined current to the organic light emitting device according to the data voltage of the data line when a gate signal is input from the gate line using the thin film transistor. Accordingly, the organic light emitting device of each of the pixels can emit light with a predetermined brightness according to a predetermined current. A description of the structure of each of the pixels will be described later with reference to FIGS. 3 to 9.

The display panel 100 may be divided into a display area in which pixels are formed to display an image and a non-display area in which an image is not displayed. Gate lines, data lines, and pixels may be formed in the display area. Gate drivers and pads may be formed in the non-display area.

The gate driver supplies gate signals to the gate lines according to the gate control signal input from the timing controller 240. The gate driver may be formed in a non-display area outside one or both sides of the display area of the display panel 100 in a GIP (gate driver in panel) method. Alternatively, the gate driver may be fabricated as a driving chip, mounted on a flexible film, and attached to a non-display area outside one or both sides of the display area of the display panel 100 in a TAB (tape automated bonding) method.

The source drive IC 210 receives digital video data and a source control signal from the timing controller 240. The source drive IC 210 converts digital video data into analog data voltages according to a source control signal and supplies them to data lines. When the source drive IC 210 is manufactured as a driving chip, it may be mounted on the flexible film 220 in a chip on film (COF) or chip on plastic (COP) method.

Pads such as data pads may be formed in the non-display area of the display panel 100. Wires connecting the pads and the source drive IC 210 and wires connecting the pads and the wires of the circuit board 160 may be formed on the flexible film 220. The flexible film 220 is attached on the pads using an anisotropic conducting film, whereby the pads and the wires of the flexible film 220 may be connected.

The circuit board 230 may be attached to the flexible films 220. The circuit board 230 may be mounted with a plurality of circuits implemented with driving chips. For example, the timing controller 240 may be mounted on the circuit board 230. The circuit board 230 may be a printed circuit board or a flexible printed circuit board.

The timing controller 240 receives digital video data and a timing signal from an external system board through a cable of the circuit board 230. The timing controller 240 generates a gate control signal for controlling the operation timing of the gate driver and a source control signal for controlling the source driver ICs 210 based on the timing signal. The timing controller 240 supplies a gate control signal to the gate driver and supplies a source control signal to the source drive ICs 210.

2 is a plan view schematically illustrating a first substrate, and FIG. 3 is a schematic cross-sectional view illustrating an example of a sub-pixel included in a display device according to an exemplary embodiment.

2 and 3, the first substrate 111 is divided into a display area DA and a non-display area NDA, and a pad area PA in which pads are formed is formed in the non-display area NDA. Can be.

Data lines and gate lines crossing the data lines are formed in the display area DA. Further, in the display area DA, pixels P that display an image in a matrix form are formed in a crossing area between the data lines and the gate lines.

Each of the pixels P may include a plurality of sub-pixels P1, P2, and P3. Each sub-pixel (P1, P2, P3) is a light emitting layer provided between the first electrode 120, the second electrode 140, the first electrode 120 and the second electrode 140, as shown in FIG. It includes (130). When a voltage is applied to each of the first and second electrodes 120 and 140 of each of the sub-pixels P1, P2, and P3, a light emitting layer provided between the first electrode 120 and the second electrode 140 ( 130) may emit light with a predetermined brightness. A description of the configuration of the light emitting layer 130 will be described later with reference to FIG. 6.

Meanwhile, the sub-pixels P1, P2, and P3 included in the display device according to the exemplary embodiment of the present invention include a buffer layer 150 between the first electrode 120 and the emission layer 130 as shown in FIG. 3. Include. The buffer layer 150 is formed on the upper surface of the first electrode 120 and may be made of a non-conductive material. The buffer layer 150 serves to emit light from the entire top surface of the first electrode 120 and prevents a decrease in luminous efficiency due to a current concentrated at the edge of the first electrode 120.

Hereinafter, structures of a plurality of sub-pixels P1, P2, and P3 according to an exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 4 to 7.

4 is a plan view schematically illustrating a first electrode, a buffer layer, and a trench of a plurality of sub-pixels, and FIG. 5 is a cross-sectional view illustrating an example of I-I of FIG. 4. 6 is a schematic cross-sectional view illustrating an example of a plurality of sub-pixels included in a display device according to an exemplary embodiment, and FIG. 7 is an enlarged view illustrating a region A of FIG. 5.

Each of the pixels P may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. The first sub-pixel P1 may be provided to emit red light, the second sub-pixel P2 to emit green light, and the third sub-pixel P3 to emit blue light, but is limited thereto. It is not. Each of the pixels may further include a fourth sub-pixel that emits white (W) light. In addition, the arrangement order of each of the sub-pixels P1, P2, and P3 may be variously changed.

4 to 7, a driving transistor (TFT), an insulating layer 115, a first electrode 120, and a light emitting layer 130 are provided on one surface of the first substrate 111 facing the second substrate 112. , The second electrode 140, the encapsulation layer 160, the color filter 170, the buffer layer 150, and the trench T are formed.

The first substrate 111 may be made of glass or plastic, but is not limited thereto, and may be made of a semiconductor material such as a silicon wafer. The first substrate 111 may be made of a transparent material or an opaque material.

The display device according to the exemplary embodiment of the present invention may be formed in a top emission method in which emitted light is emitted upward, but is not limited thereto. When the display device according to an exemplary embodiment of the present invention is configured in a top emission method in which emitted light is emitted upward, the first substrate 111 may be formed of a transparent material as well as an opaque material. Meanwhile, when the display device according to the exemplary embodiment of the present invention is formed in a so-called bottom emission method in which emitted light is emitted downward, a transparent material may be used for the first substrate 111.

Circuit elements including various signal lines, thin film transistors, capacitors, and the like are formed on the first substrate 111 for each of the pixels P1, P2, and P3. The signal lines may include a gate line, a data line, a power line, and a reference line, and the thin film transistor may include a switching thin film transistor, a driving transistor (TFT), and a sensing thin film transistor.

The switching thin film transistor is switched according to a gate signal supplied to the gate line and serves to supply a data voltage supplied from the data line to the driving thin film transistor.

The driving transistor TFT is switched according to the data voltage supplied from the switching thin film transistor to generate a data current from power supplied from the power line and supply it to the first electrode 120.

The sensing thin film transistor serves to sense a threshold voltage variation of the driving thin film transistor that causes image quality deterioration, and the current of the driving thin film transistor in response to a sensing control signal supplied from the gate wire or a separate sensing wire. Is supplied to the reference wiring.

The capacitor serves to maintain the data voltage supplied to the driving transistor TFT for one frame, and is connected to the gate terminal and the source terminal of the driving transistor TFT, respectively.

The insulating layer 115 is formed on a circuit device including a driving transistor TFT. The insulating layer 115 may be formed of an inorganic layer, for example, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or multiple layers thereof, but is not limited thereto. The insulating layer 115 is formed of an organic film, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like. It can also be formed. Alternatively, the insulating layer 115 may be formed as a multilayer composed of at least one inorganic film and at least one organic film.

The first electrode 120 is patterned for each of the sub-pixels P1, P2, and P3 on the insulating layer 115. One first electrode 121 is formed in the first sub-pixel P1, the other first electrode 122 is formed in the second sub-pixel P2, and another first electrode 122 is formed in the third sub-pixel P3. Another first electrode 123 is formed.

The first electrode 120 is connected to the driving transistor TFT. Specifically, the first electrode 120 is connected to the source terminal or the drain terminal of the driving transistor TFT through the contact hole CH penetrating the insulating layer 115, and a voltage for emitting light is applied.

The first electrode 120 may be formed of at least one of a transparent metal material, a transflective metal material, and a metal material having a high reflectivity.

When the display device is made of a top emission type, the first electrode 120 may be formed of a metal material having a high reflectivity or a stacked structure of a metal material having a high reflectivity and a transparent metal material. For example, the first electrode 120 is a laminated structure of aluminum and titanium (Ti/Al/Ti), a laminated structure of aluminum and ITO (ITO/Al/ITO), an Ag alloy, and a laminated structure of Ag alloy and ITO (ITO /Ag alloy/ITO) can be formed of a highly reflective metal material. The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu).

When the display device is made of a bottom emission type, the first electrode 120 may be a transparent metallic material such as ITO or IZO, or magnesium (Mg), silver (Ag), or Alternatively, it may be formed of a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). The first electrode 120 may be an anode electrode.

The trench T is formed in the insulating layer 115 and the first electrode 120. The trench T may be formed so as to penetrate the first electrode 120 between the sub-pixels P1, P2, and P3, and a part of the insulating layer 115 to be recessed, but is not limited thereto. The trench T may also be formed to penetrate the insulating layer 115. Hereinafter, for convenience of description, the trench T penetrates the first electrode 120 and represents a portion where the insulating layer 115 is cut or penetrated.

More specifically, the trench T may be formed in a direction from the top surface of the first electrode 120 toward the substrate 111. The trench T includes a first surface T1, a second surface T2, and a third surface T3 connecting the first surface T1 and the second surface T2.

The first surface T1 of the trench T may be formed of a side surface 121a of the first electrode 121 provided in one sub-pixel and a first surface 115a of the insulating layer 115. Further, the trench T may be formed to expose the side surface 121a of the first electrode 121 provided in one sub-pixel.

The second surface T2 of the trench T is a side surface 122a of the first electrode 122 provided in another sub-pixel disposed adjacent to the one sub-pixel, and a second surface of the insulating layer 115. It may be made of a surface (115b). The trench T may be formed to expose the side surface 122a of the first electrode 122 provided in the other sub-pixel.

The third surface T3 of the trench T is provided between the first surface T1 and the second surface T2 to connect the first surface T1 and the second surface T2. The third surface T3 of the trench T has one end connected to the first surface T1 and the other end connected to the second surface T2. The third surface T3 of the trench T1 may be formed of a third surface 115c connecting the first surface 115a and the second surface 115b of the insulating layer 115.

The trench T according to an embodiment of the present invention is characterized in that it is formed by simultaneously etching the first electrode 120 and the insulating layer 115.

Specifically, an insulating material layer constituting the insulating layer 115 is formed on the substrate 111, and a metal material layer constituting the first electrode 120 is formed on the insulating material layer. In this case, the metal material layer forming the first electrode 120 may not be patterned for each of the sub-pixels P1, P2, and P3, but may be formed as one of the plurality of sub-pixels P1, P2, and P3.

Next, the trench T may be formed by simultaneously etching the metal material layer forming the first electrode 120 and the insulating material layer forming the insulating layer 115. In addition, the first electrodes 121, 122, and 123 may be patterned for each of the sub-pixels P1, P2, and P3.

The trench T formed by the above-described process is the first electrodes 121, 122, and 123 spaced apart from the first electrodes 121, 122, and 123 formed in the sub-pixels P1, P2, and P3. Each side of the field is exposed.

In this case, the trench T may have a width W equal to the separation distance d1 between the first electrodes 121, 122, and 123. Specifically, the trench T provided between the first sub-pixel P1 and the second sub-pixel P2 is the first electrode 121 and the second sub-pixel P2 provided in the first sub-pixel P1. ) May have the same width W as the separation distance d1 between the first electrodes 122. In addition, the trench T provided between the second sub-pixel P2 and the third sub-pixel P3 is the first electrode 122 and the third sub-pixel P3 provided in the second sub-pixel P2. It may have the same width W as the separation distance d1 between the first electrodes 123 provided in the.

The width of the trench T may be determined in consideration of the thickness of the emission layer 130 and a deposition method. When the emission layer 130 is formed of the first stack 131, the charge generation layer 132, and the second stack 133, the trench T is removed at the same time that the charge generation layer 132 is disconnected from the trench T. 2 At least a portion of the stack 133 may have a width that can be connected in the trench T.

When the width W of the trench T is small, the charge generation layers 132 of adjacent sub-pixels may be connected to each other. Specifically, a trench T is formed between the first sub-pixel P1 and the second sub-pixel P2, and the first stack 131 of the emission layer 130 and the charge generation layer 132 are formed in the trench T. ) And the second stack 133 may be sequentially stacked. For example, when the width W1 of the trench T is formed to be less than 0.09 μm, the first stack 131a stacked on the first sub-pixel P1 and the first stacked stacked on the second sub-pixel P2 One stack 131b may abut each other at the top of the trench T. Accordingly, the charge generation layer 132 stacked on the first stack 131 is connected to each other in the first sub-pixel P1 and the second sub-pixel P2 to leak between adjacent sub-pixels P1 and P2. Current can be generated.

The first stack 131a stacked on the first sub-pixel P1 and the first stack 131b stacked on the second sub-pixel P2 are not connected to each other above the trench T, but are spaced apart from each other. In the display device according to an exemplary embodiment, the width W of the trench T may be formed to be greater than 0.09 μm.

On the other hand, when the width W of the trench T is formed to be large, the second electrodes 140 of adjacent sub-pixels may be disconnected without being connected to each other in the trench T. For example, when the width W of the trench T is larger than 0.20 μm, the second electrode 140 stacked on the first sub-pixel P1 and the second electrode 140 stacked on the second sub-pixel P2 The electrode 140 may be disconnected by the trench T.

In this case, the second electrode 140 stacked on the first sub-pixel P1 may be formed on the first surface T1 of the trench T. The side surface of the charge generation layer 132a provided in the first sub-pixel P1 may be exposed, and in this case, the side surface of the charge generation layer 132a and the second electrode 140 contact each other, resulting in a short circuit (short). Can occur.

The second electrode 140 stacked on the second sub-pixel P2 may be formed on the second surface T2 of the trench T. The side surface of the charge generation layer 132b provided in the second sub-pixel P2 may be exposed. In this case, the side surface of the charge generation layer 132b and the second electrode 140 contact each other, resulting in a short circuit (short). Can occur.

In order that the second electrode 140 stacked on the first sub-pixel P1 and the second electrode 140 stacked on the second sub-pixel P2 can be connected to each other, the display device according to the exemplary embodiment of the present invention is The width W of the trench T may be less than 0.20 μm.

The buffer layer 150 is formed on the first electrode 120 and the trench T. More specifically, the buffer layer 150 is formed to cover the display area DA on the first substrate 111 provided with the first electrode 120 and the trench T. The buffer layer 150 is formed to cover the first electrode 120 and the trench T.

The buffer layer 150 is provided to contact the upper surface of the first electrode 120. In this case, the buffer layer 150 is provided on the entire upper surface of the first electrode 120. The buffer layer 150 is made of a non-conductive material, but may be formed very thin so that holes or electrons of the first electrode 120 can pass to the emission layer 130. The buffer layer 150 may be formed to have a thickness of less than 50 Å. When the buffer layer 150 is formed to be thinner than 50 Å, holes or electrons of the first electrode 120 may pass to the emission layer 130 by tunneling.

Accordingly, the area where the upper surface of the first electrode 120 and the buffer layer 150 are in contact with each other becomes the light emitting area EA. That is, in the display panel 100 according to an exemplary embodiment of the present invention, since all regions in which the first electrode 120 is formed may be the emission area EA, the emission area EA may be maximized.

The buffer layer 150 is provided on the trench T as well as the upper surface of the first electrode 120. Specifically, a side surface of the first electrode 120 and a first surface 115a, a second surface 115b, and a third surface 115c of the insulating layer 115 are exposed in the trench T. The buffer layer 150 is in contact with the side surface of the first electrode 120 exposed in the trench T and the first surface 115a, the second surface 115b, and the third surface 115c of the insulating layer 115. It is equipped.

The buffer layer 150 is provided to contact the side surface of the first electrode 120 to protect the side surface of the first electrode 120. Since the side of the first electrode 120 is covered by the buffer layer 150, it may not come into contact with the charge generation layer 132 of the emission layer 130. Accordingly, it is possible to prevent a short circuit between the charge generation layer 132 and the first electrode 120.

Meanwhile, the buffer layer 150 is formed to extend from the top surface of the first electrode 120 to the side surface of the first electrode 120. That is, the buffer layer 150 is formed to cover the edge of the first electrode 120. Current may be concentrated at the edge of the first electrode 120 due to an edge effect. The buffer layer 150 may prevent the current concentrated at the edge of the first electrode 120 from being transmitted to the emission layer 130 as it is. To this end, the buffer layer 150 may be formed to cover the edge of the first electrode 120 with a thickness of 10 Å or more. When the buffer layer 150 is formed to be thinner than 10 Å, the current concentrated at the edge of the first electrode 120 is transferred to the light emitting layer 130 as it is, thereby reducing luminous efficiency.

Meanwhile, the buffer layer 150 includes not only the first electrodes 121, 122, and 123 provided in each of the sub-pixels P1, P2, and P3, but also a trench provided between the sub-pixels P1, P2, and P3. It is also provided on (T). In the display panel 100 according to the exemplary embodiment of the present invention, since the buffer layer 150 is formed on the entire surface, there is no need to add a separate process for forming the buffer layer 150 or to manufacture a separate mask.

Meanwhile, since the buffer layer 150 is also connected between the sub-pixels P1, P2, and P3, it must be made of a non-conductive material. In the display panel 100 according to an embodiment of the present invention, since the buffer layer 150 is formed of a non-conductive material, leakage current does not occur even when the buffer layer 150 is connected between the sub-pixels P1, P2, and P3. Does not.

For example, the buffer layer 150 is aluminum oxide (Al ₂ O _x ), zinc oxide (ZnO), silicon oxide film (SiOx), silicon nitride film (SiNx), silicon oxynitride film (SiON), monomer, polyimide It can be formed of a resin (polyimide resin) or the like.

The emission layer 130 is formed on the buffer layer 150. The emission layer 130 may be a white emission layer that emits white light. In this case, the emission layer 130 may be a common layer commonly formed in the sub-pixels P1, P2, and P3.

As shown in FIG. 5, the emission layer 130 includes a first stack 131 emitting light of a first color, a second stack 133 emitting light of a second color, and the first stack and the second stack. And a charge generating layer 132 (CGL) provided between the stacks.

The first stack 131 is provided on the buffer layer 150. The first stack 131 includes a first stack 131a formed in the first sub-pixel P1 and a first stack 131b formed in the adjacent second sub-pixel P2. At this time, the first stack 131a formed in the first sub-pixel P1 and the first stack 131b formed in the second sub-pixel P2 have a step difference of the trench T as shown in FIGS. 5 and 7. They are disconnected from each other. The first stack 131a formed in the first sub-pixel P1 and the first stack 131b formed in the second sub-pixel P2 are not connected to each other above the trench T.

The first stack 131 as described above includes the second sub-pixel P2, the third sub-pixel P3, and the trench T provided between the second sub-pixel P2 and the third sub-pixel P3. It can be formed in the same way.

As shown in FIG. 6, the first stack 131 includes a hole injection layer (HIL), a hole transporting layer (HTL), and a first emitting layer emitting light of a first color. ; EML1), and an electron transporting layer (ETL) may be sequentially stacked, but are not limited thereto. The first emission layer EML1 may be at least one of a red emission layer emitting red light, a green emission layer emitting green light, a blue emission layer emitting blue light, and a yellow emission layer emitting yellow light, but is limited thereto. no.

The charge generation layer 132 is provided on the first stack 131. The charge generation layer 132 includes a charge generation layer 132a formed in the first sub-pixel P1 and a charge generation layer 132b formed in the second sub-pixel P2. At this time, the charge generation layer 132a formed in the first sub-pixel P1 and the charge generation layer 132c formed in the second sub-pixel P2 have a step difference of the trench T as shown in FIGS. 5 and 7. They are disconnected from each other. The charge generation layer 132a formed in the first sub-pixel P1 and the charge generation layer 132b formed in the second sub-pixel P2 are not connected to each other over the trench T.

The charge generation layer 132 as described above includes a trench T provided between the second sub-pixel P2, the third sub-pixel P3, and the second sub-pixel P2 and the third sub-pixel P3. It can be formed in the same way.

The charge generation layer 132 includes an N-type charge generation layer for providing electrons to the first stack 131 and a P-type charge generation layer for providing holes in the second stack 133. It can be made of a stacked structure.

The second stack 133 is provided on the charge generation layer 132. The second stack 133 has a structure in which a hole transport layer (HTL), a second emission layer (EML2) emitting light of a second color, an electron transport layer (ETL), and an electron injection layer (EIL) are sequentially stacked. It can be done, but is not necessarily limited thereto. The second emission layer EML2 may be at least one of a red emission layer emitting red light, a green emission layer emitting green light, a blue emission layer emitting blue light, and a yellow emission layer emitting yellow light, but is limited thereto. no.

However, the second emission layer EML2 may emit light having a different color than the first emission layer EML1. For example, the first emission layer EML1 may be a blue emission layer emitting blue light, and the second emission layer EML2 may be a yellow emission layer emitting yellow light. For another example, the first emission layer EML1 may be a blue emission layer emitting blue light, and the second emission layer EML2 may be a red emission layer emitting red light and a green emission layer emitting green light.

Since the charge generation layers 132 of each of the sub-pixels P1, P2, and P3 are disconnected from each other in the trench T, the charge generation layer 132 between adjacent sub-pixels P1, P2, and P3 The electric charge is difficult to move.

In the light emitting layer 130 according to the exemplary embodiment of the present invention, it is possible to minimize the effects of adjacent sub-pixels P1, P2, and P3 due to leakage current.

In addition, the emission layer 130 according to the exemplary embodiment of the present invention may be collectively deposited on the plurality of sub-pixels P1, P2, and P3 without using a separate mask.

Meanwhile, in the display panel 100 according to an exemplary embodiment of the present invention, while the light emitting layer 130 is formed, an air gap (AG) may be formed in the trench T. The first stack 131 of the light emitting layer 130 may be formed to be thick at a place where the buffer layer 150 is bent from the top surface of the first electrode 120 to the side surfaces T1 and T2 of the trench T. More specifically, the thickness of the first stack 131 at the boundary of the top surface of the first electrode 120 and the first side T1 of the trench T is the first side T1 or the bottom of the trench T It may be formed thicker than the thickness of the first stack 131 on the surface T3. In addition, the thickness of the first stack 131 at the boundary between the top surface of the first electrode 120 and the second side surface T2 of the trench T is equal to the second side surface T2 or the bottom surface T3 of the trench T ) May be formed thicker than the thickness of the first stack 131. The inside of the trench T becomes narrower from the bottom to the top, and the air gap AG may be formed as the charge generation layer 132 and the second stack 133 are formed on the first stack 131.

The display panel 100 according to an exemplary embodiment of the present invention refracts light traveling from the light emitting layer 130 to the trench T through the air gap AG formed inside the trench T so that it can be directed forward. I can. The display panel 100 according to the exemplary embodiment of the present invention may improve light efficiency by minimizing loss of light emitted from the light emitting layer 130.

The second electrode 140 is formed on the emission layer 130. The second electrode 140 may be a common layer commonly formed in the sub-pixels P1, P2, and P3.

The second electrode 140 may be made of a transparent metal material, a transflective metal material, or a metal material having a high reflectivity. When the display device is made of a top emission type, the second electrode 140 may be a transparent metallic material such as ITO or IZO that can transmit light, or magnesium (Mg), silver (Ag), or Alternatively, it may be formed of a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). When the display device is made of a bottom emission method, the second electrode 140 includes a laminate structure of aluminum and titanium (Ti/Al/Ti), a laminate structure of aluminum and ITO (ITO/Al/ITO), an Ag alloy, and Ag It may be formed of a metal material having a high reflectivity, such as a laminated structure of alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). The second electrode 140 may be a cathode electrode.

The encapsulation layer 160 may be formed to cover the second electrode 140. The encapsulation layer 160 serves to prevent penetration of oxygen or moisture into the light emitting layer 130 and the second electrode 140. To this end, the encapsulation layer 160 may include at least one inorganic layer and at least one organic layer.

Specifically, the encapsulation layer 160 may include a first inorganic layer and an organic layer. In an embodiment, the encapsulation layer 160 may further include a second inorganic layer.

The first inorganic layer is formed to cover the second electrode 140. The organic layer is formed on the first inorganic layer, and is preferably formed to have a sufficient length to prevent particles from penetrating the first inorganic layer and being introduced into the light emitting layer 130 and the second electrode 140. The second inorganic layer is formed to cover the organic layer.

Each of the first and second inorganic layers may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first and second inorganic layers may be deposited by a chemical vapor deposition (CVD) technique or an atomic layer deposition (ALD) technique, but the present invention is not limited thereto.

The organic film may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The organic film may be formed by a vapor deposition, printing, or slit coating technique using an organic material, but is not limited thereto, and the organic film may be formed by an ink-jet process. .

The color filter 170 is formed on the encapsulation layer 160. The color filter 170 includes a first color filter CF1, a second color filter CF2, and a third color filter CF3 arranged to correspond to each of the sub-pixels P1, P2, and P3. The first color filter CF1 may be a red color filter that transmits red light, the second color filter CF2 may be a green color filter that transmits green light, and the third color filter CF3 is blue light. It may be a blue color filter that transmits light.

The display device according to the exemplary embodiment of the present invention is characterized in that the trench T is formed by simultaneously etching the first electrode 120 and the insulating layer 115.

In a conventional display device, after patterning the first electrode 120 for each of the sub-pixels P1, P2, and P3, banks are formed. In this case, the bank is formed to cover the edge of the first electrode 120 patterned in each of the sub-pixels P1, P2, and P3, thereby defining the emission area EA. That is, in each of the sub-pixels P1, P2, and P3, an area where a bank is not formed and the first electrode 120 is exposed becomes the light emitting area EA. On the other hand, an area other than the emission area EA becomes a non-emission area.

The bank is formed to cover not only the top edge of the first electrode 120 but also the side surface of the first electrode 120, and further, extends to the top surface of the insulating layer 115. In this way, as the bank is formed not only in the first electrode 120 but also in the insulating layer 115, the non-emission area increases. Accordingly, the pixel gap between the sub-pixels P1, P2, and P3 is limited in reducing the value because the bank covers the edge of the first electrode 120 and extends further to consider the area formed on the insulating layer 115. have.

When ultra-high resolution such as a head-mounted display is required, there is a problem that the light emitting area EA of one sub-pixel is very small and the current density is increased, thereby reducing the life of the device.

In the display device according to the exemplary embodiment of the present invention, the first electrode 120 and the insulating layer 115 are simultaneously etched to form a trench T, and a separate bank is not formed. Accordingly, in the display device according to the exemplary embodiment of the present invention, since all regions in which the first electrode 120 is formed become the emission area EA, the emission area EA can be maximized.

In the display device according to the exemplary embodiment of the present invention, since only the area in which the trench T is formed becomes the non-emission area, the interval between the sub-pixels P1, P2, and P3 can be minimized. Furthermore, the display device according to an exemplary embodiment of the present invention maximizes an aperture ratio, thereby minimizing current density and improving device life.

In addition, in the display device according to an exemplary embodiment of the present invention, a separate process for patterning the first electrode 120 for each of the sub-pixels P1, P2, and P3 is not required, and there is no need to manufacture a separate mask. Accordingly, the process of the display device according to the exemplary embodiment of the present invention is simplified, and process cost can be greatly reduced.

In addition, the display device according to the exemplary embodiment of the present invention is characterized in that the buffer layer 150 is formed on the first electrode 120 and the trench T. In this case, the buffer layer 150 may be formed as thin as 10 Å to 50 Å of a non-conductive material.

In the display device according to the exemplary embodiment of the present invention, the buffer layer 150 is formed thinly on the upper surface of the first electrode 120, so that the holes or electrons of the first electrode 120 are tunneling. ). Accordingly, an area in which the upper surface of the first electrode 120 and the buffer layer 150 are in contact with each other may be the emission area EA.

In addition, in the display device according to the exemplary embodiment, the buffer layer 150 may be formed on the side surface of the first electrode 120 to protect the side surface of the first electrode 120. Since the side of the first electrode 120 is covered by the buffer layer 150, it may not come into contact with the charge generation layer 132 of the emission layer 130. Accordingly, it is possible to prevent a short circuit between the charge generation layer 132 and the first electrode 120.

In addition, in the display device according to the exemplary embodiment, the buffer layer 150 is formed to cover the edge of the first electrode 120, so that the current concentrated at the edge of the first electrode 120 is transferred to the light emitting layer 130 as it is. It can be transmitted to prevent the reduction of luminous efficiency.

In addition, in the display device according to the exemplary embodiment of the present invention, since the buffer layer 150 is formed on the entire surface, there is no need to add a separate process for forming the buffer layer 150 or to manufacture a separate mask.

In addition, in the display device according to the exemplary embodiment of the present invention, the charge generation layer 132 of the emission layer 130 may be disconnected by the trench T. Accordingly, in the display device according to an exemplary embodiment of the present invention, the charge generation layer 132 formed on each of the adjacent sub-pixels P1, P2 and P3 is reduced even if the spacing between the sub-pixels P1, P2, and P3 is reduced. Since these are not connected to each other, leakage current may not occur between adjacent sub-pixels P1, P2, and P3.

5 and 7 illustrate that the buffer layer 150 is formed not only on the first electrode 120 but also on the trench T, the present invention is not limited thereto. In another embodiment, the buffer layer 150 may be formed only on the upper surface of the first electrode 120. Hereinafter, a display panel according to another exemplary embodiment will be described with reference to FIGS. 8 and 9.

FIG. 8 is a cross-sectional view showing another example of I-I of FIG. 2, and FIG. 9 is an enlarged view showing region B of FIG. 8.

Referring to FIGS. 8 and 9, a driving transistor (TFT), an insulating layer 115, a first electrode 120, and a light emitting layer 130 are provided on one surface of the first substrate 111 facing the second substrate 112. , The second electrode 140, the encapsulation layer 160, the color filter 170, the buffer layer 150, and the trench T are formed.

The display panel 100 illustrated in FIGS. 8 and 9 is substantially the same as the display panel 100 illustrated in FIGS. 5 to 7 except for the trench T, the buffer layer 150, and the emission layer 130. Do. Hereinafter, the trench T, the buffer layer 150 and the emission layer 130 will be mainly described, and a description of the configuration substantially the same as that of the display panel 100 illustrated in FIGS. 5 to 7 will be omitted.

The buffer layer 150 is formed on the first electrode 120. More specifically, the buffer layer 150 is patterned for each of the sub-pixels P1, P2, and P3 on the first electrode 120. In this case, the buffer layer 150 may be formed to be in contact with the upper surface of the first electrode 120 and to have the same area as the first electrode 120. That is, the end of the buffer layer 150 provided in each of the sub-pixels P1, P2, and P3 may be the same as the end of the first electrode 120.

The buffer layer 150 is made of a non-conductive material, but may be formed very thin so that holes or electrons of the first electrode 120 can pass to the emission layer 130. The buffer layer 150 may be formed to have a thickness of less than 50 Å. When the buffer layer 150 is formed to be thinner than 50 Å, holes or electrons of the first electrode 120 may pass to the emission layer 130 by tunneling.

Accordingly, the area where the upper surface of the first electrode 120 and the buffer layer 150 are in contact with each other becomes the light emitting area EA. That is, in the display panel 100 according to another exemplary embodiment of the present invention, all regions in which the first electrode 120 is formed may be the emission area EA, and thus the emission area EA may be maximized.

이상의 두께로 제1 전극(120)의 가장자리 상에 형성될 수 있다. 버퍼층(150)을 10

보다 얇게 형성하게 되면, 제1 전극(120)의 가장자리에 집중된 전류가 그대로 발광층(130)으로 전달되어 발광효율이 저하될 수 있다.Meanwhile, the buffer layer 150 is formed on the entire upper surface of the first electrode 120. That is, the buffer layer 150 is also formed on the edge of the first electrode 120. Current may be concentrated at the edge of the first electrode 120 due to an edge effect. The buffer layer 150 is formed on the edge of the first electrode 120 to prevent the current concentrated on the edge of the first electrode 120 from being transferred to the emission layer 130 as it is. To this end, the buffer layer 150 is 10

It may be formed on the edge of the first electrode 120 with a thickness of more than that. 10 buffer layer 150

If formed thinner, the current concentrated at the edge of the first electrode 120 is transferred to the light emitting layer 130 as it is, so that the luminous efficiency may decrease.

The buffer layer 150 is a non-conductive material, for example, aluminum oxide (Al ₂ O _x ), zinc oxide (ZnO), silicon oxide film (SiOx), silicon nitride film (SiNx), silicon oxynitride film (SiON), monomer ( monomer), polyimide resin, or the like.

The trench T is formed in the insulating layer 115, the first electrode 120 and the buffer layer 150. The trench T may be formed to penetrate the first electrode 120 and the buffer layer 150 between the sub-pixels P1, P2, and P3, and a part of the insulating layer 115 to be hollow, but must be It is not limited to this. The trench T may also be formed to penetrate the insulating layer 115. Hereinafter, the trench T penetrates the first electrode 120 and the buffer layer 150 for convenience of description, and represents a portion where the insulating layer 115 is cut or penetrated.

More specifically, the trench T may be formed in a direction from the top surface of the first electrode 120 toward the substrate 111. The trench T includes a first surface T1, a second surface T2, and a third surface T3 connecting the first surface T1 and the second surface T2.

The first surface T1 of the trench T is a side surface 151a of the buffer layer 151 provided in one sub-pixel, a side surface 121a of the first electrode 121, and a first surface of the insulating layer 115 It can be made of (115a). The trench T may be formed to expose the side surface 151a of the buffer layer 151 provided in one sub-pixel. Further, the trench T may be formed to expose the side surface 121a of the first electrode 121 provided in one sub-pixel. In this case, the first electrode 121 provided in one sub-pixel may be exposed in the trench T without the side surface 121a being covered by the buffer layer 151 formed on the upper surface 121b.

The second surface T2 of the trench T is a side surface 152a of the buffer layer 152 provided in another sub-pixel disposed adjacent to the one sub-pixel, and a side surface 122a of the first electrode 122 ) And the second surface 115b of the insulating layer 115. The trench T may be formed to expose a side surface 152a of the buffer layer 152 provided in another sub-pixel. Also, the trench T may be formed to expose the side surface 122a of the first electrode 122 provided in the other sub-pixel. In this case, the first electrode 122 provided in the other sub-pixel may be exposed in the trench T without the side surface 122a being covered by the buffer layer 152 formed on the upper surface 122b.

The third surface T3 of the trench T is provided between the first surface T1 and the second surface T2 to connect the first surface T1 and the second surface T2. The third surface T3 of the trench T has one end connected to the first surface T1 and the other end connected to the second surface T2. The third surface T3 of the trench T1 may be formed of a third surface 115c connecting the first surface 115a and the second surface 115b of the insulating layer 115.

The trench T according to another embodiment of the present invention is characterized in that it is formed by simultaneously etching the buffer layer 150, the first electrode 120, and the insulating layer 115.

Specifically, an insulating material layer constituting the insulating layer 115 is formed on the substrate 111, and a metal material layer constituting the first electrode 120 is formed on the insulating material layer. In this case, the metal material layer forming the first electrode 120 may not be patterned for each of the sub-pixels P1, P2, and P3, but may be formed as one of the plurality of sub-pixels P1, P2, and P3.

Next, a non-conductive material layer constituting the buffer layer 150 is formed on the metal material layer constituting the first electrode 120. At this time, the non-conductive material layer constituting the buffer layer 150 is not patterned for each sub-pixel P1, P2, P3 like a metal material layer, but is formed as one in all of the plurality of sub-pixels P1, P2, P3. Can be.

Next, a trench T may be formed by simultaneously etching a non-conductive material layer constituting the buffer layer 150, a metal material layer constituting the first electrode 120, and an insulating material layer constituting the insulating layer 115. In addition, the first electrodes 121, 122, and 123 may be patterned for each of the sub-pixels P1, P2, and P3. In addition, the buffer layer 150 may be patterned on the upper surfaces of each of the first electrodes 121, 122, and 123 provided in the sub-pixels P1, P2, and P3.

The trench T formed by the above-described process is the first electrodes 121, 122, and 123 spaced apart from the first electrodes 121, 122, and 123 formed in the sub-pixels P1, P2, and P3. Each side of the field is exposed.

In this case, the trench T may have a width W equal to the separation distance d1 between the first electrodes 121, 122, and 123. Specifically, the trench T provided between the first sub-pixel P1 and the second sub-pixel P2 is the first electrode 121 and the second sub-pixel P2 provided in the first sub-pixel P1. ) May have the same width W as the separation distance d1 between the first electrodes 122. In addition, the trench T provided between the second sub-pixel P2 and the third sub-pixel P3 is the first electrode 122 and the third sub-pixel P3 provided in the second sub-pixel P2. It may have the same width W as the separation distance d1 between the first electrodes 123 provided in the.

In addition, the trench T exposes side surfaces of each of the buffer layers 150 while separating the buffer layers 150 formed in the sub-pixels P1, P2, and P3 from each other.

In this case, the trench T may have a width W equal to the separation distance d2 between the buffer layers 150. Specifically, the trench T provided between the first sub-pixel P1 and the second sub-pixel P2 is formed in the buffer layer 150 and the second sub-pixel P2 provided in the first sub-pixel P1. It may have the same width W as the separation distance d2 between the provided buffer layers 150. In addition, a trench T provided between the second sub-pixel P2 and the third sub-pixel P3 is provided in the buffer layer 150 and the third sub-pixel P3 provided in the second sub-pixel P2. It may have the same width (W) as the separation distance (d2) between the buffer layer 150.

The width of the trench T may be determined in consideration of the thickness of the emission layer 130 and a deposition method. When the emission layer 130 is formed of the first stack 131, the charge generation layer 132, and the second stack 133, the trench T is removed at the same time that the charge generation layer 132 is disconnected from the trench T. 2 At least a portion of the stack 133 may have a width that can be connected in the trench T.

When the width W of the trench T is small, the charge generation layers 132 of adjacent sub-pixels may be connected to each other. Specifically, a trench T is formed between the first sub-pixel P1 and the second sub-pixel P2, and the first stack 131 of the emission layer 130 and the charge generation layer 132 are formed in the trench T. ) And the second stack 133 may be sequentially stacked. For example, when the width W1 of the trench T is formed to be less than 0.09 μm, the first stack 131a stacked on the first sub-pixel P1 and the first stacked stacked on the second sub-pixel P2 One stack 131b may abut each other at the top of the trench T. Accordingly, the charge generation layer 132 stacked on the first stack 131 is connected to each other in the first sub-pixel P1 and the second sub-pixel P2 to leak between adjacent sub-pixels P1 and P2. Current can be generated.

The first stack 131a stacked on the first sub-pixel P1 and the first stack 131b stacked on the second sub-pixel P2 are not connected to each other above the trench T, but are spaced apart from each other. In the display device according to another exemplary embodiment, the width W of the trench T may be formed to be greater than 0.09 μm.

On the other hand, when the width W of the trench T is formed to be large, the second electrodes 140 of adjacent sub-pixels may be disconnected without being connected to each other in the trench T. For example, when the width W of the trench T is larger than 0.20 μm, the second electrode 140 stacked on the first sub-pixel P1 and the second electrode 140 stacked on the second sub-pixel P2 The electrode 140 may be disconnected by the trench T.

In this case, the second electrode 140 stacked on the first sub-pixel P1 may be formed on the first surface T1 of the trench T. The side surface 121a of the first electrode 121 provided in the first sub-pixel P1 may still be exposed. In this case, the side surface 121a of the first electrode 121 and the second electrode 140 Contact may cause a short circuit (short). Alternatively, the side surface of the charge generation layer 132a provided in the first sub-pixel P1 may still be exposed. In this case, the side surface of the charge generation layer 132a and the second electrode 140 come into contact with each other to cause a short circuit (short circuit). ) May occur.

The second electrode 140 stacked on the second sub-pixel P2 may be formed on the second surface T2 of the trench T. The side surface 121b of the first electrode 121 provided in the second sub-pixel P2 may still be exposed. In this case, the side surface 121b and the second electrode 140 of the first electrode 121 This contact may cause a short circuit (short circuit). Alternatively, the side surface of the charge generation layer 132b provided in the second sub-pixel P2 may still be exposed. In this case, the side surface of the charge generation layer 132b and the second electrode 140 come into contact with each other, causing a short circuit (short circuit). ) May occur.

In order that the second electrode 140 stacked on the first sub-pixel P1 and the second electrode 140 stacked on the second sub-pixel P2 can be connected to each other, the display device according to another exemplary embodiment of the present invention is The width W of the trench T may be less than 0.20 μm.

The emission layer 130 is formed on the buffer layer 150. The emission layer 130 may be a white emission layer that emits white light. In this case, the emission layer 130 may be a common layer commonly formed in the sub-pixels P1, P2, and P3.

As shown in FIG. 8, the emission layer 130 includes a first stack 131 emitting light of a first color, a second stack 133 emitting light of a second color, and the first stack and the second stack. And a charge generating layer 132 (CGL) provided between the stacks.

The first stack 131 is provided on the buffer layer 150. The first stack 131 includes a first stack 131a formed in the first sub-pixel P1 and a first stack 131b formed in the adjacent second sub-pixel P2. At this time, the first stack 131a formed in the first sub-pixel P1 and the first stack 131b formed in the second sub-pixel P2 have a step difference of the trench T as shown in FIGS. 8 and 9. They are disconnected from each other.

In addition, the first stack 131a formed in the first sub-pixel P1 covers the side surface 121a of the first electrode 121 exposed in the trench T. The first stack 131b formed in the second sub-pixel P2 covers the side surface 122a of the first electrode 122 exposed in the trench T. Accordingly, the side surfaces 121a and 122a of the first electrodes 121 and 122 are protected and may not affect each other. Meanwhile, the first stack 131a formed in the first sub-pixel P1 and the first stack 131b formed in the second sub-pixel P2 are not connected to each other above the trench T.

The first stack 131 as described above includes the second sub-pixel P2, the third sub-pixel P3, and the trench T provided between the second sub-pixel P2 and the third sub-pixel P3. It can be formed in the same way.

The first stack 131 includes a hole injection layer (HIL), a hole transport layer (HTL), a first emission layer (EML1) that emits light of a first color, and an electron transport layer. (Electron Transporting Layer; ETL) may be formed in a sequentially stacked structure, but is not limited thereto. The first emission layer EML1 may be at least one of a red emission layer emitting red light, a green emission layer emitting green light, a blue emission layer emitting blue light, and a yellow emission layer emitting yellow light, but is limited thereto. no.

The charge generation layer 132 is provided on the first stack 131. The charge generation layer 132 includes a charge generation layer 132a formed in the first sub-pixel P1 and a charge generation layer 132b formed in the second sub-pixel P2. At this time, the charge generation layer 132a formed in the first sub-pixel P1 and the charge generation layer 132c formed in the second sub-pixel P2 have a step difference of the trench T as shown in FIGS. 8 and 9. They are disconnected from each other. The charge generation layer 132a formed in the first sub-pixel P1 and the charge generation layer 132b formed in the second sub-pixel P2 are not connected to each other over the trench T.

The charge generation layer 132 as described above includes a trench T provided between the second sub-pixel P2, the third sub-pixel P3, and the second sub-pixel P2 and the third sub-pixel P3. It can be formed in the same way.

The charge generation layer 132 includes an N-type charge generation layer for providing electrons to the first stack 131 and a P-type charge generation layer for providing holes in the second stack 133. It can be made of a stacked structure.

The second stack 133 is provided on the charge generation layer 132. The second stack 133 has a structure in which a hole transport layer (HTL), a second emission layer (EML2) emitting light of a second color, an electron transport layer (ETL), and an electron injection layer (EIL) are sequentially stacked. It can be done, but is not necessarily limited thereto. The second emission layer EML2 may be at least one of a red emission layer emitting red light, a green emission layer emitting green light, a blue emission layer emitting blue light, and a yellow emission layer emitting yellow light, but is limited thereto. no.

However, the second emission layer EML2 may emit light having a different color than the first emission layer EML1. For example, the first emission layer EML1 may be a blue emission layer emitting blue light, and the second emission layer EML2 may be a yellow emission layer emitting yellow light. For another example, the first emission layer EML1 may be a blue emission layer emitting blue light, and the second emission layer EML2 may be a red emission layer emitting red light and a green emission layer emitting green light.

Since the charge generation layers 132 of each of the sub-pixels P1, P2, and P3 are disconnected from each other in the trench T, the charge generation layer 132 between adjacent sub-pixels P1, P2, and P3 The electric charge is difficult to move.

In the light emitting layer 130 according to another embodiment of the present invention, it is possible to minimize the influence of adjacent sub-pixels P1, P2, and P3 due to leakage current.

In addition, the emission layer 130 according to another exemplary embodiment of the present invention may be collectively deposited on the plurality of sub-pixels P1, P2, and P3 without using a separate mask.

Meanwhile, in the display panel 100 according to another exemplary embodiment of the present invention, while the light emitting layer 130 is formed, an air gap (AG) may be formed in the trench T. The first stack 131 of the light emitting layer 130 may be thickly formed at a place where the upper surface of the buffer layer 150 is bent toward the side surfaces T1 and T2 of the trench T. More specifically, the thickness of the first stack 131 at the boundary between the upper surface of the buffer layer 150 and the first side T1 of the trench T is the first side T1 or the bottom surface of the trench T It may be formed thicker than the thickness of the first stack 131 in T3). In addition, the thickness of the first stack 131 at the boundary between the upper surface of the buffer layer 150 and the second side T2 of the trench T is at the second side T2 or the bottom surface T3 of the trench T. It may be formed to be thicker than the thickness of the first stack 131. The inside of the trench T becomes narrower from the bottom to the top, and the air gap AG may be formed as the charge generation layer 132 and the second stack 133 are formed on the first stack 131.

The display panel 100 according to another exemplary embodiment of the present invention refracts light traveling from the light emitting layer 130 to the trench T through the air gap AG formed in the trench T so that it can be directed forward. I can. The display panel 100 according to another exemplary embodiment of the present invention may improve light efficiency by minimizing loss of light emitted from the emission layer 130.

The display device according to another exemplary embodiment of the present invention is characterized in that the buffer layer 150, the first electrode 120, and the insulating layer 115 are simultaneously etched to form a trench T.

In the display device according to another exemplary embodiment of the present invention, the buffer layer 150, the first electrode 120, and the insulating layer 115 are simultaneously etched to form a trench T, and a separate bank is not formed. Accordingly, in the display device according to another exemplary embodiment of the present invention, since all regions in which the first electrode 120 is formed become the emission area EA, the emission area EA can be maximized.

In the display device according to another exemplary embodiment of the present invention, since only the area in which the trench T is formed becomes the non-emission area, the spacing between the sub-pixels P1, P2, and P3 can be minimized. Furthermore, the display device according to another exemplary embodiment of the present invention maximizes the aperture ratio, thereby minimizing current density and improving device life.

In addition, in the display device according to another exemplary embodiment of the present invention, there is no need for a separate process for patterning the first electrode 120 for each of the sub-pixels P1, P2, and P3, and there is no need to manufacture a separate mask. Accordingly, the process of the display device according to another exemplary embodiment of the present invention can be simplified, and process cost can be greatly reduced.

In addition, in the display device according to another exemplary embodiment of the present invention, a separate process for forming a pattern of the buffer layer 150 for each of the sub-pixels P1, P2, and P3 is not required, and there is no need to manufacture a separate mask. Accordingly, the process of the display device according to another exemplary embodiment of the present invention can be simplified, and process cost can be greatly reduced.

In addition, in the display device according to another embodiment of the present invention, the buffer layer 150 may be formed of a non-conductive material to be 10 Å to 50 Å thin.

In the display device according to another exemplary embodiment of the present invention, the buffer layer 150 is formed thinly on the upper surface of the first electrode 120, so that holes or electrons of the first electrode 120 are tunneling. ). Accordingly, an area in which the upper surface of the first electrode 120 and the buffer layer 150 are in contact with each other may be the emission area EA.

In addition, in the display device according to another embodiment of the present invention, since the buffer layer 150 is formed on the edge of the top surface of the first electrode 120, the current concentrated on the edge of the first electrode 120 is transferred to the emission layer 130 as it is. Thus, it is possible to prevent the luminous efficiency from being lowered.

In addition, in the display device according to another exemplary embodiment of the present invention, the charge generation layer 132 of the emission layer 130 may be disconnected by the trench T. Accordingly, in the display device according to an exemplary embodiment of the present invention, the charge generation layer 132 formed on each of the adjacent sub-pixels P1, P2 and P3 is reduced even if the spacing between the sub-pixels P1, P2, and P3 is reduced. Since these are not connected to each other, leakage current may not occur between adjacent sub-pixels P1, P2, and P3.

10 is a flowchart illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention, and FIGS. 11A to 11H are cross-sectional views illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention.

First, an insulating material layer 117 constituting the circuit element and the insulating layer 115 is formed on the substrate 111 (S901).

More specifically, as shown in FIG. 11A, a driving thin film transistor TFT is formed on the substrate 111.

Then, the insulating material layer 117 constituting the insulating layer 115 is formed on the driving thin film transistor TFT. The insulating material layer 117 constituting the insulating layer 115 may be formed of an inorganic layer, for example, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or multiple layers thereof, but is not limited thereto. The insulating material layer 117 constituting the insulating layer 115 is an organic film, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyamide resin. It may also be formed of polyimide resin or the like. Alternatively, the insulating layer 115 may be formed as a multilayer composed of at least one inorganic film and at least one organic film.

Next, a metal material layer 125 constituting the first electrode 120 is deposited on the entire surface (S902).

More specifically, as shown in FIG. 11B, a metal material layer 125 constituting the first electrode 120 is deposited on the insulating material layer 117 on the entire surface. In this case, the metal material layer 125 constituting the first electrode 120 is connected to the source terminal or the drain terminal of the driving thin film transistor TFT through a contact hole CH for each of the sub-pixels P1, P2, and P3.

The metal material layer 125 constituting the first electrode 120 may be made of a transparent metal material, a transflective metal material, or a metal material having a high reflectivity. When the display device 100 is formed in a top emission type, the metal material layer 125 constituting the first electrode 120 is a laminated structure of aluminum and titanium (Ti/Al/Ti), and a laminated structure of aluminum and ITO (ITO). /Al/ITO), Ag alloy, and a metal material having high reflectivity such as a stacked structure of Ag alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). When the display device 100 is formed in a lower light emission method, the metal material layer 125 constituting the first electrode 120 is a transparent metal material (TCO, transparent conductive material) such as ITO and IZO capable of transmitting light, Alternatively, it may be formed of a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

Next, a trench T is formed (S903).

More specifically, a trench T is formed by simultaneously etching the insulating material layer 117 and the metal material layer 125 as shown in FIG. 11C. In the display panel 100 according to the exemplary embodiment of the present invention, the trench T may be formed by dry etching the material 125 and the insulating layer 115 constituting the first electrode 120 at a time. At the same time, the first electrodes 121, 122, and 123 may be patterned for each sub-pixel P1, P2, and P3.

The trench T may be formed so as to penetrate the first electrode 120 between the sub-pixels P1, P2, and P3, and a part of the insulating layer 115 to be recessed, but is not limited thereto. The trench T may also be formed to penetrate the insulating layer 115.

The trench T exposes the side surfaces of each of the first electrodes 121, 122, and 123 while separating the first electrodes 121, 122, 123 formed in the sub-pixels P1, P2, and P3 from each other. .

Next, a buffer layer 150 is formed (S904).

More specifically, as shown in FIG. 11D, the buffer layer 150 is formed on the first electrode 120 and the trench T. More specifically, the buffer layer 150 may be formed to cover the display area DA on the first substrate 111 provided with the first electrode 120 and the trench T. The buffer layer 150 may be formed to cover the first electrode 120 and the trench T.

The buffer layer 150 is formed on the upper surface of the first electrode 120 and is also formed on the trench T. Specifically, a side surface of the first electrode 120 and a first surface 115a, a second surface 115b, and a third surface 115c of the insulating layer 115 are exposed in the trench T. The buffer layer 150 is in contact with the side surface of the first electrode 120 exposed in the trench T and the first surface 115a, the second surface 115b, and the third surface 115c of the insulating layer 115. It is equipped.

The buffer layer 150 may be made of a non-conductive material, for example, aluminum oxide (Al ₂ O _x ), zinc oxide (ZnO), silicon oxide film (SiOx), silicon nitride film (SiNx), silicon oxynitride film (SiON) , It may be formed of a monomer, polyimide resin, or the like.

The buffer layer 150 may be formed thinly using an ALD (Atomic Layer Deposition) technique. The buffer layer 150 may be formed thinly on the upper surface of the first electrode 120 to a thickness of less than 50 Å. When the buffer layer 150 is formed to be less than 50 Å thin, holes or electrons of the first electrode 120 may pass to the emission layer 130 by a tunneling phenomenon.

Meanwhile, the buffer layer 150 may be formed to cover an edge of the first electrode 120 with a thickness of 10 Å or more. When the buffer layer 150 is formed to be thinner than 10 Å, the current concentrated at the edge of the first electrode 120 is transferred to the light emitting layer 130 as it is, thereby reducing luminous efficiency.

Next, the light emitting layer 130 is formed (S905).

As shown in FIG. 11E, a light emitting layer 130 is formed on the buffer layer 150. More specifically, the first stack 131 is formed on the buffer layer 150. The first stack 131 may be formed by a deposition process or a solution process. When the first stack 131 is formed by a vapor deposition process, it may be formed using an evaporation method. In this case, the first stack 131 is disconnected due to a step difference in the trench T between the sub-pixels P1, P2, and P3.

The first stack 131 includes a hole injection layer (HIL), a hole transport layer (HTL), a first emission layer (EML1) that emits light of a first color, and an electron transport layer ( Electron Transporting Layer (ETL) may be sequentially stacked.

The first emission layer EML1 may be at least one of a red emission layer emitting red light, a green emission layer emitting green light, a blue emission layer emitting blue light, and a yellow emission layer emitting yellow light, but is limited thereto. no.

Then, a charge generation layer 132 is formed on the first stack 131. In this case, the charge generation layer 132 is disconnected between the sub-pixels P1, P2, and P3 due to the step of the trench T.

The charge generation layer 132 includes an N-type charge generation layer for providing electrons to the first stack 131 and a P-type charge generation layer for providing holes in the second stack 133 It can be made in a structured structure.

Then, a second stack 133 is formed on the charge generation layer 132. The second stack 133 may be formed by a deposition process or a solution process. When the second stack 133 is formed by a vapor deposition process, it may be formed using an evaporation method. In this case, the second stack 133 is connected to each other between the sub-pixels P1, P2, and P3.

The second stack 133 has a structure in which a hole transport layer (HTL), a second emission layer (EML2) emitting light of a second color, an electron transport layer (ETL), and an electron injection layer (EIL) are sequentially stacked. It can be done, but is not necessarily limited thereto. The second emission layer EML2 may be at least one of a red emission layer emitting red light, a green emission layer emitting green light, a blue emission layer emitting blue light, and a yellow emission layer emitting yellow light, but is limited thereto. no.

However, the second emission layer EML2 may emit light having a different color than the first emission layer EML1. For example, the first emission layer EML1 may be a blue emission layer emitting blue light, and the second emission layer EML2 may be a yellow emission layer emitting yellow light. For another example, the first emission layer EML1 may be a blue emission layer emitting blue light, and the second emission layer EML2 may be a red emission layer emitting red light and a green emission layer emitting green light.

Next, the second electrode 140 is formed (S906).

More specifically, as shown in FIG. 11F, the second electrode 140 is formed on the emission layer 130. The second electrode 140 may be formed by a physical vapor deposition method such as sputtering. Alternatively, the second electrode 140 may be formed by using an evaporation method.

The second electrode 140 may be made of a transparent metal material, a transflective metal material, or a metal material having a high reflectivity. When the display device is made of a top emission type, the second electrode 140 may be a transparent metallic material such as ITO or IZO that can transmit light, or magnesium (Mg), silver (Ag), or Alternatively, it may be formed of a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). When the display device is made of a bottom emission method, the second electrode 140 includes a laminate structure of aluminum and titanium (Ti/Al/Ti), a laminate structure of aluminum and ITO (ITO/Al/ITO), an Ag alloy, and Ag It may be formed of a metal material having a high reflectivity, such as a laminated structure of alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). The second electrode 140 may be a cathode electrode.

Next, an encapsulation film 160 is formed (S907).

More specifically, as shown in FIG. 11G, an encapsulation film 160 is formed on the second electrode 140. The encapsulation layer 160 may include a first inorganic layer and an organic layer. In an embodiment, the encapsulation layer 160 may further include a second inorganic layer.

A first inorganic layer is formed on the second electrode 140. Then, an organic film is formed on the first inorganic film. The organic layer is preferably formed to have a sufficient thickness to prevent particles from penetrating the first inorganic layer and being introduced into the emission layer 130 and the second electrode 140. Then, a second inorganic film is formed on the organic film.

Each of the first and second inorganic layers may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first and second inorganic layers may be deposited by a chemical vapor deposition (CVD) technique or an atomic layer deposition (ALD) technique, but the present invention is not limited thereto.

The organic film may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The organic film may be formed by a vapor deposition, printing, or slit coating technique using an organic material, but is not limited thereto, and the organic film may be formed by an ink-jet process. .

Next, a color filter 170 is formed (S908).

More specifically, the color filter 170 is formed on the encapsulation layer 160 as shown in FIG. 11H. The color filter 170 includes a first color filter CF1 disposed to correspond to the first sub-pixel P1, a second color filter CF2 disposed to correspond to the second sub-pixel P2, and a third sub-pixel. A third color filter CF3 disposed to correspond to P3 may be included. The first color filter CF1 may be a red color filter that transmits red light, the second color filter CF2 may be a green color filter that transmits green light, and the third color filter CF3 is blue light. It may be a blue color filter that transmits light.

12 is a flowchart illustrating a method of manufacturing a display device according to another exemplary embodiment of the present invention, and FIGS. 13A to 13H are cross-sectional views illustrating a method of manufacturing a display device according to another exemplary embodiment of the present invention.

First, an insulating material layer 117 constituting the circuit element and the insulating layer 115 is formed on the substrate 111 (S1101).

More specifically, a driving thin film transistor TFT is formed on the substrate 111 as shown in FIG. 13A.

Then, the insulating material layer 117 constituting the insulating layer 115 is formed on the driving thin film transistor TFT. The insulating material layer 117 constituting the insulating layer 115 may be formed of an inorganic layer, for example, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or multiple layers thereof, but is not limited thereto. The insulating material layer 117 constituting the insulating layer 115 is an organic film, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyamide resin. It may also be formed of polyimide resin or the like. Alternatively, the insulating layer 115 may be formed as a multilayer composed of at least one inorganic film and at least one organic film.

Next, a metal material layer 125 forming the first electrode 120 is deposited on the entire surface (S1102).

More specifically, as shown in FIG. 13B, a metal material layer 125 constituting the first electrode 120 is deposited on the insulating material layer 117 on the entire surface. In this case, the metal material layer 125 constituting the first electrode 120 is connected to the source terminal or the drain terminal of the driving thin film transistor TFT through a contact hole CH for each of the sub-pixels P1, P2, and P3.

The metal material layer 125 constituting the first electrode 120 may be made of a transparent metal material, a transflective metal material, or a metal material having a high reflectivity. When the display device 100 is formed in a top emission type, the metal material layer 125 constituting the first electrode 120 is a laminated structure of aluminum and titanium (Ti/Al/Ti), and a laminated structure of aluminum and ITO (ITO). /Al/ITO), Ag alloy, and a metal material having high reflectivity such as a stacked structure of Ag alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). When the display device 100 is formed in a lower light emission method, the metal material layer 125 constituting the first electrode 120 is a transparent metal material (TCO, transparent conductive material) such as ITO and IZO capable of transmitting light, Alternatively, it may be formed of a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

Next, a non-conductive material layer 155 forming the buffer layer 150 is formed (S1103).

More specifically, a non-conductive material layer 155 constituting the buffer layer 150 is deposited on the entire surface of the metal material layer 125 constituting the first electrode 120 as shown in FIG. 13C.

The non-conductive material layer 155 constituting the buffer layer 150 is, for example, aluminum oxide (Al ₂ O _x ), zinc oxide (ZnO), a silicon oxide film (SiOx), a silicon nitride film (SiNx), a silicon oxynitride film (SiON). ), a monomer, a polyimide resin, or the like.

The non-conductive material layer 155 constituting the buffer layer 150 may be thinly formed by an ALD (Atomic Layer Deposition) technique. The non-conductive material layer 155 constituting the buffer layer 150 may be thinly formed on the metal material layer 125 constituting the first electrode 120 to a thickness of 10 Å to less than 50 Å.

Next, a trench T is formed (S1104).

More specifically, as shown in FIG. 13D, a trench T is formed by simultaneously etching the non-conductive material layer 155, the insulating material layer 117, and the metal material layer 125. In the display panel 100 according to the exemplary embodiment, the non-conductive material layer 155 constituting the buffer layer 150, the material 125 constituting the first electrode 120, and the insulating layer 115 are dry-etched at a time. Thus, a trench T can be formed. At the same time, the first electrodes 121, 122, and 123 may be patterned for each sub-pixel P1, P2, and P3. In addition, the buffer layer 150 may be patterned for each of the sub-pixels P1, P2, and P3.

The trench T may be formed to penetrate the first electrode 120 and the buffer layer 150 between the sub-pixels P1, P2, and P3, and a part of the insulating layer 115 to be hollow, but must be It is not limited to this. The trench T may also be formed to penetrate the insulating layer 115.

The trench T exposes the side surfaces of each of the first electrodes 121, 122, and 123 while separating the first electrodes 121, 122, 123 formed in the sub-pixels P1, P2, and P3 from each other. .

In addition, the trench T exposes side surfaces of each of the buffer layers 150 while separating the buffer layers 150 formed in the sub-pixels P1, P2, and P3 from each other.

Next, the light emitting layer 130 is formed (S1105).

13E, the light emitting layer 130 is formed on the buffer layer 150. More specifically, the first stack 131 is formed on the buffer layer 150. The first stack 131 may be formed by a deposition process or a solution process. When the first stack 131 is formed by a vapor deposition process, it may be formed using an evaporation method. In this case, the first stack 131 is disconnected due to a step difference in the trench T between the sub-pixels P1, P2, and P3.

The first stack 131 includes a hole injection layer (HIL), a hole transport layer (HTL), a first emission layer (EML1) that emits light of a first color, and an electron transport layer ( Electron Transporting Layer (ETL) may be sequentially stacked.

The first emission layer EML1 may be at least one of a red emission layer emitting red light, a green emission layer emitting green light, a blue emission layer emitting blue light, and a yellow emission layer emitting yellow light, but is limited thereto. no.

Then, a charge generation layer 132 is formed on the first stack 131. In this case, the charge generation layer 132 is disconnected between the sub-pixels P1, P2, and P3 due to the step of the trench T.

The charge generation layer 132 includes an N-type charge generation layer for providing electrons to the first stack 131 and a P-type charge generation layer for providing holes in the second stack 133 Can be made in a structure

Then, a second stack 133 is formed on the charge generation layer 132. The second stack 133 may be formed by a deposition process or a solution process. When the second stack 133 is formed by a vapor deposition process, it may be formed using an evaporation method. In this case, the second stack 133 is connected to each other between the sub-pixels P1, P2, and P3.

The second stack 133 has a structure in which a hole transport layer (HTL), a second emission layer (EML2) emitting light of a second color, an electron transport layer (ETL), and an electron injection layer (EIL) are sequentially stacked. It can be done, but is not necessarily limited thereto. The second emission layer EML2 may be at least one of a red emission layer emitting red light, a green emission layer emitting green light, a blue emission layer emitting blue light, and a yellow emission layer emitting yellow light, but is limited thereto. no.

However, the second emission layer EML2 may emit light having a different color than the first emission layer EML1. For example, the first emission layer EML1 may be a blue emission layer emitting blue light, and the second emission layer EML2 may be a yellow emission layer emitting yellow light. For another example, the first emission layer EML1 may be a blue emission layer emitting blue light, and the second emission layer EML2 may be a red emission layer emitting red light and a green emission layer emitting green light.

Next, the second electrode 140 is formed (S1106).

More specifically, as shown in FIG. 13F, the second electrode 140 is formed on the emission layer 130. The second electrode 140 may be formed by a physical vapor deposition method such as sputtering. Alternatively, the second electrode 140 may be formed by using an evaporation method.

The second electrode 140 may be made of a transparent metal material, a transflective metal material, or a metal material having a high reflectivity. When the display device is made of a top emission type, the second electrode 140 may be a transparent metallic material such as ITO or IZO that can transmit light, or magnesium (Mg), silver (Ag), or Alternatively, it may be formed of a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). When the display device is made of a bottom emission method, the second electrode 140 includes a laminate structure of aluminum and titanium (Ti/Al/Ti), a laminate structure of aluminum and ITO (ITO/Al/ITO), an Ag alloy, and Ag It may be formed of a metal material having a high reflectivity, such as a laminated structure of alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). The second electrode 140 may be a cathode electrode.

Next, an encapsulation film 160 is formed (S1107).

More specifically, as shown in FIG. 13G, an encapsulation layer 160 is formed on the second electrode 140. The encapsulation layer 160 may include a first inorganic layer and an organic layer. In an embodiment, the encapsulation layer 160 may further include a second inorganic layer.

A first inorganic layer is formed on the second electrode 140. Then, an organic film is formed on the first inorganic film. The organic layer is preferably formed to have a sufficient thickness to prevent particles from penetrating the first inorganic layer and being introduced into the emission layer 130 and the second electrode 140. Then, a second inorganic film is formed on the organic film.

Each of the first and second inorganic layers may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first and second inorganic layers may be deposited by a chemical vapor deposition (CVD) technique or an atomic layer deposition (ALD) technique, but the present invention is not limited thereto.

The organic film may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The organic film may be formed by a vapor deposition, printing, or slit coating technique using an organic material, but is not limited thereto, and the organic film may be formed by an ink-jet process. .

Next, a color filter 170 is formed (S1108).

More specifically, a color filter 170 is formed on the encapsulation layer 160 as shown in FIG. 13H. The color filter 170 includes a first color filter CF1 disposed to correspond to the first sub-pixel P1, a second color filter CF2 disposed to correspond to the second sub-pixel P2, and a third sub-pixel. A third color filter CF3 disposed to correspond to P3 may be included. The first color filter CF1 may be a red color filter that transmits red light, the second color filter CF2 may be a green color filter that transmits green light, and the third color filter CF3 is blue light. It may be a blue color filter that transmits light.

14A to 14C relate to a display device according to another embodiment of the present invention, which relates to a head mounted display (HMD) device. 14A is a schematic perspective view, FIG. 14B is a schematic plan view of a virtual reality (VR) structure, and FIG. 14C is a schematic cross-sectional view of an Augmented Reality (AR) structure.

As can be seen from FIG. 14A, the head mounted display device according to the present invention includes a storage case 10 and a head mounting band 30.

The storage case 10 houses a structure such as a display device, a lens array, and an eyepiece therein.

The head mounting band 30 is fixed to the storage case 10. The head mounting band 30 is illustrated to be formed to surround the upper surface of the user's head and both sides, but is not limited thereto. The head mounting band 30 is for fixing the head mounted display to the user's head, and may be replaced with a structure in the form of an eyeglass frame or a helmet form.

As can be seen from FIG. 14B, the head-mounted display device having a virtual reality (VR) structure according to the present invention includes a left-eye display device 12, a right-eye display device 11, a lens array 13, and a left-eye eyepiece. 20a) and the right eye eyepiece 20b.

The left-eye display device 12, the right-eye display device 11, the lens array 13, and the left-eye eyepiece 20a and right-eye eyepiece 20b are accommodated in the storage case 10 described above.

The left-eye display device 12 and the right-eye display device 11 can display the same image, and in this case, the user can view the 2D image. Alternatively, the left-eye display device 12 may display a left-eye image and the right-eye display device 11 may display a right-eye image. In this case, the user can view a stereoscopic image. Each of the left-eye display device 12 and the right-eye display device 11 may be formed of the display device of FIGS. 1 to 9 described above. In this case, an upper portion corresponding to a surface on which an image is displayed in FIGS. 1 to 9, for example, a color filter 170 faces the lens array 13.

The lens array 13 may be provided between the left eye eye lens 20a and the left eye display device 12 while being spaced apart from each of the left eye eye lens 20a and the left eye display device 12. That is, the lens array 13 may be positioned in front of the left eye eyepiece 20a and behind the left eye display device 12. Also, the lens array 13 may be provided between the right eye eye lens 20b and the right eye display device 11 while being spaced apart from each of the right eye eye lens 20b and the right eye display device 11. That is, the lens array 13 may be positioned in front of the right eye eyepiece 20b and behind the right eye display device 11.

The lens array 13 may be a micro lens array. The lens array 13 may be replaced with a pin hole array. An image displayed on the left-eye display device 12 or the right-eye display device 11 due to the lens array 13 may be enlarged and viewed by the user.

The user's left eye LE may be positioned on the left eyepiece 20a, and the user's right eye RE may be positioned on the right eyepiece 20b.

As can be seen from FIG. 14C, the head mounted display device having an Augmented Reality (AR) structure according to the present invention includes a left-eye display device 12, a lens array 13, a left eye eyepiece 20a, and a transmission reflector 14. , And a transmission window 15. 14C shows only the left-inside configuration for convenience, and the right-inside configuration is also the same as the left-inside configuration.

The left-eye display device 12, the lens array 13, the left-eye eyepiece 20a, the transmission reflection portion 14, and the transmission window 15 are accommodated in the storage case 10 described above.

The left eye display device 12 may be disposed on one side of the transmission reflective unit 14, for example, on the upper side, without covering the transmission window 15. Accordingly, the left-eye display device 12 may provide an image to the transmissive reflector 14 without covering an external background visible through the transmissive window 15.

The left eye display device 12 may be formed of the display device according to FIGS. 1 to 9 described above. In this case, an upper portion corresponding to a surface on which an image is displayed in FIGS. 1 to 9, for example, a color filter 170 faces the transmission reflector 14.

The lens array 13 may be provided between the left eye eyepiece 20a and the transmission reflector 14.

The user's left eye is positioned in the left eye eyepiece 20a.

The transmission reflection part 14 is disposed between the lens array 13 and the transmission window 15. The transmission reflection part 14 may include a reflective surface 14a that transmits part of the light and reflects another part of the light. The reflective surface 14a is formed so that the image displayed on the left eye display device 12 proceeds to the lens array 13. Accordingly, the user can see both an external background and an image displayed by the left eye display device 12 through the transmission layer 15. That is, since the user can view the real background and the virtual image as a single image, an Augmented Reality (AR) can be implemented.

The transmission layer 15 is disposed in front of the transmission reflection portion 14.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting. The scope of protection of the present invention should be interpreted by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

10: display device
111: substrate TFT: driving thin film transistor
115: insulating layer 120: first electrode
130: light emitting layer 131: first stack
132: charge generation layer 133: second stack
140: second electrode 150: buffer layer
160: encapsulation layer 170: color filter

Claims (19)

Board;
A first electrode provided in each of a first sub-pixel and a second sub-pixel disposed adjacent to the first sub-pixel on the substrate;
A buffer layer provided on the first electrode;
A light emitting layer provided on the buffer layer; And
A display device including a second electrode provided on the emission layer. The method of claim 1,
An insulating layer provided between the substrate and the first electrode; And
Further comprising a trench provided between the first sub-pixel and the second sub-pixel,
The trench is formed in the insulating layer and the first electrode. The method of claim 2,
The trench is formed in a direction from an upper surface of the first electrode toward the substrate. The method of claim 2,
The first electrode provided in the first sub-pixel and the first electrode provided in the second sub-pixel are spaced apart from each other,
The trench is formed to expose a side surface of a first electrode provided in the first sub-pixel and a side surface of a first electrode provided in the second sub-pixel. The method of claim 4,
A display device wherein a separation distance between a first electrode provided in the first sub-pixel and a first electrode provided in the second sub-pixel is the same as a width of the trench. The method of claim 1,
The buffer layer is provided to contact an upper surface of a first electrode provided in the first sub-pixel and an upper surface of a first electrode provided in the second sub-pixel. The method of claim 1,
The buffer layer is provided to contact a side surface of a first electrode provided in the first sub-pixel and a side surface of a first electrode provided in the second sub-pixel. The method of claim 2,
The buffer layer is provided on the insulating layer exposed in the trench. The method of claim 1,
The buffer layer is a display device made of a non-conductive material. The method of claim 1,
The light emitting layer includes a first stack, a charge generation layer provided on the first stack, and a second stack provided on the charge generation layer,
The charge generation layer is disconnected between the first sub-pixel and the second sub-pixel by the trench. The method of claim 10,
The second stack is connected to each other between the first sub-pixel and the second sub-pixel. The method of claim 2,
An air gap surrounded by the light emitting layer and the buffer layer is formed in the trench. Forming an insulating material layer on the substrate;
Forming a metal material layer on the insulating material layer;
Simultaneously performing an etching process on the metal material layer and the insulating material layer to form a trench, and patterning a first electrode for each sub-pixel; And
And forming a buffer layer on the first electrode and the trench. The method of claim 13,
The buffer layer is a method of manufacturing a display device covering an upper surface of the first electrode and a side surface of the first electrode. The method of claim 13,
The buffer layer is a display device made of a non-conductive material. The method of claim 13,
Forming a first stack on the buffer layer;
Forming a charge generation layer on the first stack; And
Further comprising forming a second stack on the charge generation layer,
The method of manufacturing a display device in which the charge generation layer is disconnected by the trench. The method of claim 16,
Further comprising forming a second electrode on the second stack,
The second electrode is a method of manufacturing a display device connected to the trench. Forming an insulating material layer on the substrate;
Forming a metal material layer on the insulating material layer;
Forming a layer of a non-conductive material on the metallic material; And
And forming a trench by simultaneously performing an etching process on the metal material layer, the non-conductive material layer, and the insulating material layer, and patterning the first electrode and the buffer layer for each sub-pixel. The method of claim 18,
The method of manufacturing a display device in which the buffer layer is formed to contact an upper surface of the first electrode.

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