KR102640476B1 - Display device and method for manufacturing the same - Google Patents

Abstract

The present invention provides a display device that can minimize the gap between sub-pixels and maximize the light emitting area. A display device according to an embodiment of the present invention includes a substrate, a first electrode provided in each of a first sub-pixel and a second sub-pixel disposed adjacent to the first sub-pixel on the substrate, a buffer layer provided on the first electrode, It includes a light-emitting layer provided on the buffer layer and a second electrode provided on the light-emitting layer.

Description

Display device and method of manufacturing the same {DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to a display device that displays images.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, recently, liquid crystal display (LCD), plasma display panel (PDP), quantum dot light emitting display (QLED), and organic light emitting display (OLED) have been developed. Various display devices such as Light Emitting Display (Light Emitting Display) are being used.

Recently, a head mounted display including such a display device has been developed. Head Mounted Display (HMD) is a virtual reality (VR) or augmented reality glasses-type monitor device that is worn in the form of glasses or a helmet and focuses on a distance near the user's eyes. For these head-mounted displays, it is important to reduce the pixel spacing and increase the light emitting area to improve performance.

The technical task of the present invention is to provide a display device that can reduce pixel spacing.

Another technical problem of the present invention is to provide a display device that can increase the light emitting area.

A display device according to an embodiment of the present invention includes a substrate, a first electrode provided in each of a first sub-pixel and a second sub-pixel disposed adjacent to the first sub-pixel on the substrate, a buffer layer provided on the first electrode, It includes a light-emitting layer provided on the buffer layer and a second electrode provided on the light-emitting layer.

A method of manufacturing a display device according to another embodiment of the present invention includes forming an insulating material layer on a substrate, forming a metal material layer on the insulating material layer, and etching the metal material layer and the insulating material layer simultaneously. It includes forming a trench and patterning the first electrode for each sub-pixel, and forming a buffer layer on the first electrode and the trench.

A method of manufacturing a display device according to another embodiment of the present invention includes forming an insulating material layer on a substrate, forming a metal material layer on the insulating material layer, and forming a non-conductive material layer on the metal material layer. It includes forming a trench by simultaneously performing an etching process on the metal material layer, the non-conductive material layer, and the insulating material layer, and patterning the first electrode and the buffer layer for each sub-pixel.

According to the present invention, the non-emission area can be minimized by simultaneously etching the first electrode and the insulating layer to form a trench. The present invention can minimize the spacing between sub-pixels.

Additionally, the present invention forms a buffer layer made of a non-conductive material on the first electrode. In the present invention, by forming a buffer layer at the edge of the first electrode, it is possible to prevent luminous efficiency from being reduced due to current concentrated on the edge of the first electrode.

In addition, the present invention forms a thin buffer layer on the upper surface of the first electrode, so that light can be emitted from the entire upper surface of the first electrode even if the buffer layer is formed on the entire upper surface of the first electrode. Accordingly, in the present invention, the entire area where the first electrode is formed becomes a light-emitting area, so the light-emitting area can be maximized. The present invention can minimize current density and improve device lifespan by maximizing the aperture ratio.

Additionally, in the present invention, by disconnecting the charge generation layer using a trench, leakage current may not occur between adjacent sub-pixels even if the gap between sub-pixels is reduced.

Additionally, the present invention does not require a separate process for patterning the first electrode for each sub-pixel, and there is no need to manufacture a separate mask. Accordingly, the present invention simplifies the process and significantly reduces the process cost.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention are described below, or can be clearly understood by those skilled in the art from such description and description.

1 is a perspective view showing a display device according to an embodiment of the present invention.
Figure 2 is a plan view schematically showing the first substrate.
Figure 3 is a cross-sectional view schematically showing an example of a sub-pixel included in a display device according to an embodiment of the present invention.
Figure 4 is a plan view schematically showing the first electrode, buffer layer, and trench of a plurality of sub-pixels.
Figure 5 is a cross-sectional view showing an example of II in Figure 2.
Figure 6 is a cross-sectional view schematically showing an example of a plurality of sub-pixels included in a display device according to an embodiment of the present invention.
Figure 7 is an enlarged view showing area A of Figure 5.
FIG. 8 is a cross-sectional view showing another example of II of FIG. 2.
Figure 9 is an enlarged view showing area B of Figure 8.
Figure 10 is a flowchart showing a method of manufacturing a display device according to an embodiment of the present invention.
11A to 11H are cross-sectional views showing a method of manufacturing a display device according to an embodiment of the present invention.
Figure 12 is a flowchart showing a method of manufacturing a display device according to another embodiment of the present invention.
13A to 13H are cross-sectional views showing a method of manufacturing a display device according to another embodiment of the present invention.
14A to 14C relate to a display device according to another embodiment of the present invention, which relates to a head mounted display (HMD) device.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the examples described in detail below along with the accompanying drawings. However, the present invention is not limited to the examples disclosed below and will be implemented in various different forms. These examples only serve to ensure that the disclosure of the present invention is complete and will be provided to those skilled in the art to which the present invention pertains. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining examples of the present invention are illustrative and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the present invention are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

When describing the components of the present invention, terms such as first and second may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there are no other components between each component. It should be understood that may be “interposed” or that each component may be “connected,” “combined,” or “connected” through other components.

Each feature of the various examples of the present invention can be combined or combined with each other, partially or entirely, and various technical interconnections and operations are possible, and each example can be implemented independently of each other or together in a related relationship. .

Hereinafter, an example of a display device according to the present invention will be described in detail with reference to the attached drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings.

1 is a perspective view showing a display device according to an embodiment of the present invention.

Referring to FIG. 1, a display device according to an embodiment of the present invention includes a display panel 100, a source drive integrated circuit (hereinafter referred to as “IC”) 210, a flexible film 220, and a circuit board. 230, and a timing control unit 240.

The display panel 100 includes a first substrate 111 and a second substrate 112. The second substrate 112 may be an encapsulation substrate.

Gate lines, data lines, and pixels are formed on one side of the first substrate 111 facing the second substrate 112. Pixels are provided in an area defined by the intersection structure of gate lines and data lines.

Each of the pixels may include a thin film transistor and a light emitting element including a first electrode, a light emitting layer, and a second electrode. Each of the pixels uses a thin film transistor to supply a predetermined current to the organic light emitting device according to the data voltage of the data line when a gate signal is input from the gate line. Because of this, the organic light emitting element of each pixel can emit light with a predetermined brightness according to a predetermined current. A description of the structure of each pixel will be described later in conjunction with FIGS. 3 to 9.

The display panel 100 can be divided into a display area where pixels are formed to display images and a non-display area where images are not displayed. Gate lines, data lines, and pixels may be formed in the display area. A gate driver and pads may be formed in the non-display area.

The gate driver supplies gate signals to the gate lines according to the gate control signal input from the timing control unit 240. The gate driver may be formed in a non-display area outside one or both sides of the display area of the display panel 100 using a GIP (gate driver in panel) method. Alternatively, the gate driver may be manufactured as a driving chip, mounted on a flexible film, and attached to a non-display area outside one or both sides of the display area of the display panel 100 using a TAB (tape automated bonding) method.

The source drive IC 210 receives digital video data and source control signals from the timing control unit 240. The source drive IC 210 converts digital video data into analog data voltages according to the source control signal and supplies them to the data lines. When the source drive IC 210 is manufactured as a driving chip, it may be mounted on the flexible film 220 using a chip on film (COF) or chip on plastic (COP) method.

Pads such as data pads may be formed in the non-display area of the display panel 100. Wires connecting the pads and the source drive IC 210 and wires connecting the pads and the wires of the circuit board 160 may be formed in the flexible film 220. The flexible film 220 is attached to the pads using an antisotropic conducting film, so that the pads and the wires of the flexible film 220 can be connected.

The circuit board 230 may be attached to the flexible films 220. The circuit board 230 may be equipped with multiple circuits implemented with driving chips. For example, the timing control unit 240 may be mounted on the circuit board 230. The circuit board 230 may be a printed circuit board or a flexible printed circuit board.

The timing control unit 240 receives digital video data and timing signals from an external system board through a cable of the circuit board 230. The timing control unit 240 generates a gate control signal for controlling the operation timing of the gate driver and a source control signal for controlling the source drive ICs 210 based on the timing signal. The timing control unit 240 supplies a gate control signal to the gate driver and a source control signal to the source drive ICs 210.

FIG. 2 is a plan view schematically showing the first substrate, and FIG. 3 is a cross-sectional view schematically showing an example of a sub-pixel included in a display device according to an embodiment of the present invention.

Referring to FIGS. 2 and 3 , the first substrate 111 is divided into a display area (DA) and a non-display area (NDA), and a pad area (PA) where pads are formed is formed in the non-display area (NDA). It can be.

Data lines and gate lines that intersect the data lines are formed in the display area DA. Additionally, in the display area DA, pixels P that display an image in a matrix form are formed in the intersection area of the data lines and the gate lines.

Each of the pixels P may include a plurality of sub-pixels P1, P2, and P3. As shown in FIG. 3, each sub-pixel (P1, P2, P3) includes a first electrode 120, a second electrode 140, and a light emitting layer provided between the first electrode 120 and the second electrode 140. Includes (130). When a voltage is applied to each of the first electrode 120 and the second electrode 140, each sub-pixel (P1, P2, and P3) is formed by forming a light emitting layer ( 130) can emit light at a predetermined brightness. A description of the configuration of the light emitting layer 130 will be described later in conjunction with FIG. 6.

Meanwhile, the sub-pixels P1, P2, and P3 included in the display device according to an embodiment of the present invention have a buffer layer 150 between the first electrode 120 and the light emitting layer 130, as shown in FIG. 3. Includes. The buffer layer 150 is formed on the upper surface of the first electrode 120 and may be made of a non-conductive material. This buffer layer 150 allows light to be emitted from the entire upper surface of the first electrode 120 and at the same time serves to prevent luminous efficiency from being reduced due to current concentrated at the edge of the first electrode 120.

Hereinafter, the structure of a plurality of sub-pixels P1, P2, and P3 according to an embodiment of the present invention will be examined in more detail with reference to FIGS. 4 to 7.

FIG. 4 is a plan view schematically showing the first electrode, buffer layer, and trench of a plurality of sub-pixels, and FIG. 5 is a cross-sectional view showing an example of line II of FIG. 4 . FIG. 6 is a cross-sectional view schematically showing an example of a plurality of sub-pixels included in a display device according to an embodiment of the present invention, and FIG. 7 is an enlarged view showing area A of FIG. 5.

Each of the pixels P may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. The first sub-pixel (P1) may be configured to emit red light, the second sub-pixel (P2) may be configured to emit green light, and the third sub-pixel (P3) may be configured to emit blue light, but are not necessarily limited thereto. That is not the case. Each of the pixels may further include a fourth sub-pixel that emits white (W) light. Additionally, the arrangement order of each sub-pixel (P1, P2, and P3) can be changed in various ways.

4 to 7, on one side of the first substrate 111 facing the second substrate 112, a driving transistor (TFT), an insulating layer 115, a first electrode 120, and a light emitting layer 130 are formed. , the second electrode 140, the encapsulation film 160, the color filter 170, the buffer layer 150, and the trench T are formed.

The first substrate 111 may be made of glass or plastic, but is not necessarily limited thereto, and may be made of a semiconductor material such as a silicon wafer. The first substrate 111 may be made of a transparent material or an opaque material.

The display device according to an embodiment of the present invention may be configured as a top emission method in which emitted light is emitted upward, but is not necessarily limited to this. When the display device according to an embodiment of the present invention is made of a top emission method in which emitted light is emitted upward, the first substrate 111 may be made of an opaque material as well as a transparent material. Meanwhile, when the display device according to an embodiment of the present invention is made of a so-called bottom emission method in which the emitted light is emitted downward, the first substrate 111 may be made of a transparent material.

Circuit elements including various signal wires, thin film transistors, and capacitors are formed on the first substrate 111 for each pixel (P1, P2, and P3). The signal wires may include a gate wire, a data wire, a power wire, and a reference wire, and the thin film transistor may include a switching thin film transistor, a driving transistor (TFT), and a sensing thin film transistor.

The switching thin film transistor switches according to a gate signal supplied to the gate wire and serves to supply the data voltage supplied from the data wire to the driving thin film transistor.

The driving transistor (TFT) switches according to the data voltage supplied from the switching thin film transistor, generates a data current from the power supplied from the power wiring, and supplies it to the first electrode 120.

The sensing thin-film transistor serves to sense the threshold voltage deviation of the driving thin-film transistor, which causes deterioration of image quality, and controls the current of the driving thin-film transistor in response to a sensing control signal supplied from the gate wiring or a separate sensing wiring. is supplied to the above reference wiring.

The capacitor serves to maintain the data voltage supplied to the driving transistor (TFT) for one frame, and is connected to the gate terminal and source terminal of the driving transistor (TFT), respectively.

The insulating layer 115 is formed on a circuit element including a driving transistor (TFT). The insulating layer 115 may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not necessarily limited thereto. The insulating layer 115 is made of an organic film, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. may be formed. Alternatively, the insulating layer 115 may be formed as a multilayer composed of at least one inorganic layer and at least one organic layer.

The first electrode 120 is patterned for each sub-pixel (P1, P2, and P3) on the insulating layer 115. One first electrode 121 is formed in the first sub-pixel (P1), another first electrode 122 is formed in the second sub-pixel (P2), and another first electrode 122 is formed in the third sub-pixel (P3). Another first electrode 123 is formed.

The first electrode 120 is connected to the driving transistor (TFT). Specifically, the first electrode 120 is connected to the source terminal or drain terminal of the driving transistor (TFT) through the contact hole (CH) penetrating the insulating layer 115, and a voltage for emitting light is applied.

The first electrode 120 may be made of at least one of a transparent metal material, a translucent metal material, and a highly reflective metal material.

When the display device is made of a top-emitting type, the first electrode 120 may be made of a highly reflective metal material or a stacked structure of a highly reflective metal material and a transparent metal material. For example, the first electrode 120 has a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an Ag alloy, and a stacked structure of Ag alloy and ITO (ITO). /Ag alloy/ITO) can be formed of a highly reflective metal material. The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

When the display device is made of a bottom-emitting type, the first electrode 120 is made of a transparent metal material (TCO, Transparent Conductive Material) such as ITO or IZO, which can transmit light, or magnesium (Mg), silver (Ag), Alternatively, it may be formed of a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). This first electrode 120 may be an anode electrode.

A trench T is formed in the insulating layer 115 and the first electrode 120. The trench T may be formed to penetrate the first electrode 120 between the sub-pixels P1, P2, and P3 and to recess a portion of the insulating layer 115, but is not limited to this. The trench T may also be formed to penetrate the insulating layer 115. Hereinafter, for convenience of explanation, the trench T refers to a portion that penetrates the first electrode 120 and the insulating layer 115 is dug or penetrated.

More specifically, the trench T may be formed in a direction from the top surface of the first electrode 120 toward the substrate 111 . This trench (T) consists of a first side (T1), a second side (T2), and a third side (T3) connecting the first side (T1) and the second side (T2).

The first surface T1 of the trench T may be formed of the side surface 121a of the first electrode 121 provided in one sub-pixel and the first surface 115a of the insulating layer 115. Additionally, the trench T may be formed to expose the side surface 121a of the first electrode 121 provided in one sub-pixel.

The second surface T2 of the trench T is the side surface 122a of the first electrode 122 provided in one sub-pixel and another sub-pixel disposed adjacent to the second surface T2 of the insulating layer 115. It may be made of a surface 115b. The trench T may be formed to expose the side surface 122a of the first electrode 122 provided in another sub-pixel.

The third surface T3 of the trench T is provided between the first surface T1 and the second surface T2, and connects the first surface T1 and the second surface T2. One end of the third side T3 of the trench T is connected to the first side T1, and the other end is connected to the second side T2. The third surface T3 of the trench T1 may be formed of a third surface 115c connecting the first surface 115a and the second surface 115b of the insulating layer 115.

The trench T according to an embodiment of the present invention is formed by simultaneously etching the first electrode 120 and the insulating layer 115.

Specifically, an insulating material layer forming the insulating layer 115 is formed on the substrate 111, and a metal material layer forming the first electrode 120 is formed on the insulating material layer. At this time, the metal material layer forming the first electrode 120 may not be patterned for each sub-pixel (P1, P2, and P3), but may be formed as one across the plurality of sub-pixels (P1, P2, and P3).

Next, a trench T may be formed by simultaneously etching the metal material layer forming the first electrode 120 and the insulating material layer forming the insulating layer 115. In addition, the first electrodes 121, 122, and 123 may be patterned for each sub-pixel (P1, P2, and P3).

The trench T formed by the above-described process separates the first electrodes 121, 122, and 123 formed in the sub-pixels P1, P2, and P3 from each other, and separates the first electrodes 121, 122, and 123 from each other. Each side is exposed.

At this time, the trench T may have a width W equal to the separation distance d1 between the first electrodes 121, 122, and 123. Specifically, the trench (T) provided between the first sub-pixel (P1) and the second sub-pixel (P2) is connected to the first electrode 121 provided in the first sub-pixel (P1) and the second sub-pixel (P2). ) may have a width (W) equal to the separation distance (d1) between the first electrodes 122 provided in . In addition, the trench T provided between the second sub-pixel P2 and the third sub-pixel P3 is connected to the first electrode 122 provided in the second sub-pixel P2 and the third sub-pixel P3. It may have a width (W) equal to the separation distance (d1) between the first electrodes 123 provided in .

The width of the trench T may be determined considering the thickness and deposition method of the light emitting layer 130. When the light emitting layer 130 is composed of the first stack 131, the charge generation layer 132, and the second stack 133, the trench T is formed when the charge generation layer 132 is disconnected from the trench T. At least a portion of the two stacks 133 may have a width that allows them to be connected in the trench T.

If the width W of the trench T is formed small, the charge generation layers 132 of adjacent sub-pixels may be connected to each other. Specifically, a trench (T) is formed between the first sub-pixel (P1) and the second sub-pixel (P2), and the first stack 131 of the light-emitting layer 130 and the charge generation layer 132 are formed in the trench (T). ) and the second stack 133 may be sequentially stacked. For example, if the width W1 of the trench T is formed as small as less than 0.09㎛, the first stack 131a stacked on the first sub-pixel P1 and the stack 131a stacked on the second sub-pixel P2 1 Stacks 131b may contact each other at the top of the trench T. As a result, the charge generation layer 132 stacked on the first stack 131 is connected to the first sub-pixel (P1) and the second sub-pixel (P2), causing leakage between adjacent sub-pixels (P1, P2). Current may occur.

According to the present invention, the first stack 131a stacked on the first sub-pixel P1 and the first stack 131b stacked on the second sub-pixel P2 are spaced apart from each other without being connected to each other at the top of the trench T. The display device according to one embodiment may form a width (W) of the trench (T) larger than 0.09㎛.

On the other hand, if the width W of the trench T is formed large, the second electrodes 140 of adjacent sub-pixels may be disconnected from each other in the trench T. For example, if the width W of the trench T is formed to be greater than 0.20㎛, the second electrode 140 stacked on the first sub-pixel P1 and the second electrode 140 stacked on the second sub-pixel P2 Even the electrode 140 may be cut off by the trench T.

At this time, the second electrode 140 stacked on the first sub-pixel P1 may be formed on the first surface T1 of the trench T. The side of the charge generation layer 132a provided in the first sub-pixel P1 may be exposed, and in this case, the side of the charge generation layer 132a and the second electrode 140 contact, causing a short circuit. It can happen.

The second electrode 140 stacked on the second sub-pixel P2 may be formed on the second surface T2 of the trench T. The side of the charge generation layer 132b provided in the second sub-pixel P2 may be exposed. In this case, the side of the charge generation layer 132b and the second electrode 140 contact, causing a short circuit. It can happen.

The display device according to an embodiment of the present invention is such that the second electrode 140 stacked on the first sub-pixel P1 and the second electrode 140 stacked on the second sub-pixel P2 are connected to each other. The width (W) of the trench (T) can be formed to be less than 0.20㎛.

The buffer layer 150 is formed on the first electrode 120 and the trench T. More specifically, the buffer layer 150 is formed to cover the display area DA on the first substrate 111 provided with the first electrode 120 and the trench T. The buffer layer 150 is formed to cover the first electrode 120 and the trench T.

The buffer layer 150 is provided to contact the top surface of the first electrode 120. At this time, the buffer layer 150 is provided on the entire upper surface of the first electrode 120. The buffer layer 150 is made of a non-conductive material, but can be formed very thin so that holes or electrons of the first electrode 120 can pass to the light-emitting layer 130. The buffer layer 150 may be formed as thin as less than 50Å. When the buffer layer 150 is formed as thin as less than 50Å, holes or electrons of the first electrode 120 may pass to the light emitting layer 130 by a tunneling phenomenon.

Accordingly, the entire area where the upper surface of the first electrode 120 and the buffer layer 150 are in contact becomes the light emitting area EA. That is, in the display panel 100 according to an embodiment of the present invention, the entire area where the first electrode 120 is formed can become the light-emitting area (EA), thereby maximizing the light-emitting area (EA).

The buffer layer 150 is provided not only on the top surface of the first electrode 120 but also on the trench T. Specifically, the side surface of the first electrode 120 and the first surface 115a, second surface 115b, and third surface 115c of the insulating layer 115 are exposed in the trench T. The buffer layer 150 is in contact with the side surface of the first electrode 120 exposed in the trench T and the first surface 115a, second surface 115b, and third surface 115c of the insulating layer 115. It is provided.

The buffer layer 150 is provided to be in contact with the side surface of the first electrode 120 and protects the side surface of the first electrode 120. Since the side surface of the first electrode 120 is covered by the buffer layer 150, it may not come into contact with the charge generation layer 132 of the light-emitting layer 130. Accordingly, short circuit between the charge generation layer 132 and the first electrode 120 can be prevented.

Meanwhile, the buffer layer 150 is formed to extend from the top surface of the first electrode 120 to the side surface of the first electrode 120. That is, the buffer layer 150 is formed to cover the edge of the first electrode 120. Current may be concentrated at the edge of the first electrode 120 due to an edge effect. The buffer layer 150 can prevent current concentrated at the edge of the first electrode 120 from being transferred to the light emitting layer 130. To this end, the buffer layer 150 may be formed to cover the edge of the first electrode 120 with a thickness of 10 Å or more. If the buffer layer 150 is formed thinner than 10 Å, the current concentrated at the edge of the first electrode 120 may be directly transmitted to the light emitting layer 130, thereby reducing luminous efficiency.

Meanwhile, the buffer layer 150 includes not only the first electrodes 121, 122, and 123 provided in each of the sub-pixels (P1, P2, and P3), but also a trench provided between the sub-pixels (P1, P2, and P3). It is also provided on (T). In the display panel 100 according to an embodiment of the present invention, the buffer layer 150 is formed on the entire surface, so there is no need to add a separate process or manufacture a separate mask to pattern the buffer layer 150.

Meanwhile, since the buffer layer 150 is connected between the sub-pixels (P1, P2, and P3), it must be made of a non-conductive material. The display panel 100 according to an embodiment of the present invention forms the buffer layer 150 of a non-conductive material, so that no leakage current occurs even if the buffer layer 150 is connected between the sub-pixels (P1, P2, and P3). No.

For example, the buffer layer 150 is made of aluminum oxide (Al _{2 O} It may be formed of resin (polyimide resin), etc.

The light emitting layer 130 is formed on the buffer layer 150. The light emitting layer 130 may be a white light emitting layer that emits white light. In this case, the light emitting layer 130 may be a common layer commonly formed in the sub-pixels P1, P2, and P3.

As shown in FIG. 5, the light emitting layer 130 includes a first stack 131 that emits light of a first color, a second stack 133 that emits light of a second color, and the first stack and the second stack. It includes a charge generating layer (CGL) 132 provided between the stacks.

The first stack 131 is provided on the buffer layer 150. The first stack 131 includes a first stack 131a formed in the first sub-pixel P1 and a first stack 131b formed in the adjacent second sub-pixel P2. At this time, the first stack 131a formed in the first sub-pixel P1 and the first stack 131b formed in the second sub-pixel P2 have a step of the trench T as shown in FIGS. 5 and 7. Because of this, they are cut off from each other. The first stack 131a formed in the first sub-pixel P1 and the first stack 131b formed in the second sub-pixel P2 are not connected to each other at the top of the trench T.

The first stack 131 as described above includes a second sub-pixel (P2), a third sub-pixel (P3), and a trench (T) provided between the second sub-pixel (P2) and the third sub-pixel (P3). It can also be formed in the same way.

As shown in FIG. 6, this first stack 131 includes a hole injection layer (HIL), a hole transport layer (HTL), and a first emitting layer (Emitting Layer) that emits light of the first color. ; EML1), and an electron transporting layer (ETL) may be sequentially stacked, but the structure is not necessarily limited thereto. The first light-emitting layer (EML1) may be at least one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but is not necessarily limited thereto. no.

The charge generation layer 132 is provided on the first stack 131. The charge generation layer 132 includes a charge generation layer 132a formed in the first sub-pixel P1 and a charge generation layer 132b formed in the second sub-pixel P2. At this time, the charge generation layer 132a formed in the first sub-pixel P1 and the charge generation layer 132c formed in the second sub-pixel P2 have a step of the trench T as shown in FIGS. 5 and 7. Because of this, they are cut off from each other. The charge generation layer 132a formed in the first sub-pixel P1 and the charge generation layer 132b formed in the second sub-pixel P2 are not connected to each other at the top of the trench T.

The charge generation layer 132 as described above includes the second sub-pixel (P2), the third sub-pixel (P3), and the trench (T) provided between the second sub-pixel (P2) and the third sub-pixel (P3). It can also be formed in the same way.

This charge generation layer 132 includes an N-type charge generation layer for providing electrons to the first stack 131 and a P-type charge generation layer for providing holes to the second stack 133. It may be comprised of a layered structure.

The second stack 133 is provided on the charge generation layer 132. The second stack 133 has a structure in which a hole transport layer (HTL), a second light emitting layer (EML2) that emits light of a second color, an electron transport layer (ETL), and an electron injection layer (EIL) are sequentially stacked. It can be done, but it is not necessarily limited to that. The second light-emitting layer (EML2) may be at least one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but is not necessarily limited thereto. no.

However, the second emitting layer (EML2) may emit light of a different color than the first emitting layer (EML1). For example, the first light-emitting layer (EML1) may be a blue light-emitting layer that emits blue light, and the second light-emitting layer (EML2) may be a yellow light-emitting layer that emits yellow light. For another example, the first light-emitting layer (EML1) may be a blue light-emitting layer that emits blue light, and the second light-emitting layer (EML2) may be a red light-emitting layer that emits red light and a green light-emitting layer that emits green light.

Since the charge generation layer 132 of each of the sub-pixels P1, P2, and P3 is disconnected from each other inside the trench T, the charge generation layer 132 is connected between adjacent sub-pixels P1, P2, and P3. It is difficult for electric charges to move.

The light emitting layer 130 according to an embodiment of the present invention can minimize the influence of adjacent sub-pixels P1, P2, and P3 due to leakage current.

Additionally, the light emitting layer 130 according to an embodiment of the present invention can be deposited on the plurality of sub-pixels P1, P2, and P3 at a time without using a separate mask.

Meanwhile, in the display panel 100 according to an embodiment of the present invention, as the light emitting layer 130 is formed, an air gap (AG) may be formed inside the trench (T). The first stack 131 of the light emitting layer 130 may be formed thick at a place where the buffer layer 150 is bent from the top surface of the first electrode 120 to the sides T1 and T2 of the trench T. More specifically, the thickness of the first stack 131 at the boundary between the top surface of the first electrode 120 and the first side T1 of the trench T is the thickness of the first side T1 or the bottom of the trench T. It may be formed to be thicker than the thickness of the first stack 131 on the surface T3. In addition, the thickness of the first stack 131 at the boundary between the top surface of the first electrode 120 and the second side T2 of the trench T is the second side T2 or bottom surface T3 of the trench T. ) may be formed thicker than the thickness of the first stack 131 in . The inside of the trench T becomes narrower from the bottom to the top, and as the charge generation layer 132 and the second stack 133 are formed on the first stack 131, an air gap AG may be formed.

The display panel 100 according to an embodiment of the present invention refracts the light traveling from the light emitting layer 130 to the trench (T) through the air gap (AG) formed inside the trench (T) so that it can be directed forward. You can. The display panel 100 according to an embodiment of the present invention can improve light efficiency by minimizing the loss of light emitted from the light emitting layer 130.

The second electrode 140 is formed on the light emitting layer 130. The second electrode 140 may be a common layer commonly formed in the sub-pixels P1, P2, and P3.

This second electrode 140 may be made of a transparent metal material, a translucent metal material, or a highly reflective metal material. When the display device is made of a top-emitting type, the second electrode 140 is made of a transparent conductive material (TCO) such as ITO or IZO, which can transmit light, or magnesium (Mg), silver (Ag), Alternatively, it may be formed of a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). When the display device is made of a bottom-emitting type, the second electrode 140 has a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), Ag alloy, and Ag It can be formed of a metal material with high reflectivity, such as a laminated structure of alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). This second electrode 140 may be a cathode electrode.

The encapsulation film 160 may be formed to cover the second electrode 140. The encapsulation film 160 serves to prevent oxygen or moisture from penetrating into the light emitting layer 130 and the second electrode 140. To this end, the encapsulation film 160 may include at least one inorganic film and at least one organic film.

Specifically, the encapsulation film 160 may include a first inorganic film and an organic film. In one embodiment, the encapsulation film 160 may further include a second inorganic film.

The first inorganic layer is formed to cover the second electrode 140. The organic film is formed on the first inorganic film, and is preferably formed with a sufficient length to prevent particles from penetrating the first inorganic film and being introduced into the light emitting layer 130 and the second electrode 140. The second inorganic film is formed to cover the organic film.

Each of the first and second inorganic layers may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first and second inorganic layers may be deposited using a CVD (Chemical Vapor Deposition) technique or an ALD (Atomic Layer Deposition) technique, but are not limited thereto.

The organic film may be formed of acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The organic film may be formed by vapor deposition, printing, or slit coating techniques using organic materials, but is not limited thereto, and the organic film may be formed by an ink-jet process. .

The color filter 170 is formed on the encapsulation film 160. The color filter 170 includes a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) arranged to correspond to each of the sub-pixels (P1, P2, and P3). The first color filter (CF1) may be a red color filter that transmits red light, the second color filter (CF2) may be a green color filter that transmits green light, and the third color filter (CF3) may be a green color filter that transmits blue light. It may be a blue color filter that transmits.

The display device according to an embodiment of the present invention is characterized by forming a trench T by simultaneously etching the first electrode 120 and the insulating layer 115.

In a conventional display device, the first electrode 120 is patterned for each sub-pixel (P1, P2, and P3) and then a bank is formed. At this time, the bank is formed to cover the edge of the first electrode 120 patterned in each of the sub-pixels P1, P2, and P3, and defines the light-emitting area EA. That is, no bank is formed in each sub-pixel (P1, P2, and P3), and the area where the first electrode 120 is exposed becomes the light-emitting area (EA). On the other hand, the area excluding the light emitting area (EA) becomes a non-light emitting area.

The bank is formed to cover not only the upper surface edge of the first electrode 120 but also the side surface of the first electrode 120, and further extends to the upper surface of the insulating layer 115. In this way, as the bank is formed not only in the first electrode 120 but also in the insulating layer 115, the non-emission area increases. Accordingly, the pixel spacing between the sub-pixels (P1, P2, and P3) must be considered because the bank covers the edge of the first electrode 120 and extends further to the area formed in the insulating layer 115, so there is a limit to reducing the number. there is.

When ultra-high resolution is required, such as in a head-mounted display, there is a problem that the emission area (EA) of one sub-pixel becomes very small and the current density increases, which reduces device lifespan.

The display device according to an embodiment of the present invention forms a trench T by simultaneously etching the first electrode 120 and the insulating layer 115, and does not form a separate bank. Accordingly, in the display device according to an embodiment of the present invention, the entire area where the first electrode 120 is formed becomes the light-emitting area EA, and thus the light-emitting area EA can be maximized.

In the display device according to an embodiment of the present invention, only the area where the trench T is formed becomes a non-emission area, so the gap between the sub-pixels P1, P2, and P3 can be minimized. Furthermore, the display device according to an embodiment of the present invention can minimize current density and improve device lifespan by maximizing the aperture ratio.

Additionally, the display device according to an embodiment of the present invention does not require a separate process to form a pattern of the first electrode 120 for each sub-pixel (P1, P2, and P3), and there is no need to manufacture a separate mask. Accordingly, the display device according to an embodiment of the present invention has a simplified process and can significantly reduce process costs.

Additionally, the display device according to an embodiment of the present invention is characterized in that a buffer layer 150 is formed on the first electrode 120 and the trench T. At this time, the buffer layer 150 may be formed of a non-conductive material as thin as 10Å to 50Å.

In the display device according to an embodiment of the present invention, the buffer layer 150 is formed thinly on the upper surface of the first electrode 120, so that holes or electrons of the first electrode 120 are transmitted to the light emitting layer 130 by a tunneling phenomenon. ) can be moved to. Accordingly, the entire area where the upper surface of the first electrode 120 and the buffer layer 150 are in contact can become the light emitting area EA.

Additionally, in the display device according to an embodiment of the present invention, the buffer layer 150 is formed on the side surface of the first electrode 120, thereby protecting the side surface of the first electrode 120. Since the side surface of the first electrode 120 is covered by the buffer layer 150, it may not come into contact with the charge generation layer 132 of the light-emitting layer 130. Accordingly, short circuit between the charge generation layer 132 and the first electrode 120 can be prevented.

In addition, in the display device according to an embodiment of the present invention, the buffer layer 150 is formed to cover the edge of the first electrode 120, so that the current concentrated on the edge of the first electrode 120 is directly transferred to the light emitting layer 130. It is possible to prevent luminous efficiency from being transmitted.

Additionally, since the buffer layer 150 is formed on the entire surface of the display device according to an embodiment of the present invention, there is no need to add a separate process or manufacture a separate mask to pattern the buffer layer 150.

Additionally, in the display device according to an embodiment of the present invention, the charge generation layer 132 of the light emitting layer 130 may be disconnected by the trench T. Accordingly, the display device according to an embodiment of the present invention maintains the charge generation layer 132 formed in each of the adjacent sub-pixels (P1, P2, and P3) even if the gap between the sub-pixels (P1, P2, and P3) is reduced. Since they are not connected to each other, leakage current may not occur between adjacent sub-pixels (P1, P2, and P3).

5 and 7 illustrate that the buffer layer 150 is formed not only on the first electrode 120 but also on the trench T, but is not necessarily limited thereto. In another embodiment, the buffer layer 150 may be formed only on the top surface of the first electrode 120. Hereinafter, a display panel according to another embodiment will be described with reference to FIGS. 8 and 9.

FIG. 8 is a cross-sectional view showing another example of line II-I of FIG. 2, and FIG. 9 is an enlarged view showing area B of FIG. 8.

8 and 9, on one side of the first substrate 111 facing the second substrate 112, a driving transistor (TFT), an insulating layer 115, a first electrode 120, and a light emitting layer 130 are formed. , the second electrode 140, the encapsulation film 160, the color filter 170, the buffer layer 150, and the trench T are formed.

The display panel 100 shown in FIGS. 8 and 9 is substantially the same as the display panel 100 shown in FIGS. 5 to 7 except for the trench T, buffer layer 150, and light emitting layer 130. do. Hereinafter, the trench T, the buffer layer 150, and the light emitting layer 130 will be mainly described, and descriptions of components substantially the same as those of the display panel 100 shown in FIGS. 5 to 7 will be omitted.

The buffer layer 150 is formed on the first electrode 120. More specifically, the buffer layer 150 is patterned for each sub-pixel (P1, P2, and P3) on the first electrode 120. At this time, the buffer layer 150 is in contact with the upper surface of the first electrode 120 and may be formed to have the same area as the first electrode 120. That is, the end of the buffer layer 150 provided in each of the sub-pixels P1, P2, and P3 may be the same as the end of the first electrode 120.

The buffer layer 150 is made of a non-conductive material, but can be formed very thin so that holes or electrons of the first electrode 120 can pass to the light-emitting layer 130. The buffer layer 150 may be formed as thin as less than 50Å. When the buffer layer 150 is formed as thin as less than 50Å, holes or electrons of the first electrode 120 may pass to the light emitting layer 130 by a tunneling phenomenon.

Accordingly, the entire area where the upper surface of the first electrode 120 and the buffer layer 150 are in contact becomes the light emitting area EA. That is, in the display panel 100 according to another embodiment of the present invention, the entire area where the first electrode 120 is formed can become the light-emitting area (EA), thereby maximizing the light-emitting area (EA).

Meanwhile, the buffer layer 150 is formed on the entire upper surface of the first electrode 120. That is, the buffer layer 150 is also formed on the edge of the first electrode 120. Current may be concentrated at the edge of the first electrode 120 due to an edge effect. The buffer layer 150 is formed on the edge of the first electrode 120 to prevent current concentrated at the edge of the first electrode 120 from being directly transferred to the light emitting layer 130. For this purpose, the buffer layer 150 is 10 It may be formed on the edge of the first electrode 120 with a thickness greater than or equal to that of the first electrode 120. The buffer layer 150 is 10 If it is formed thinner, the current concentrated at the edge of the first electrode 120 may be directly transmitted to the light emitting layer 130, thereby reducing luminous efficiency.

This buffer layer 150 is made of a non-conductive material, for example, aluminum oxide (Al ₂ O _x ), zinc oxide (ZnO), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), monomer ( monomer), polyimide resin, etc.

A trench T is formed in the insulating layer 115, the first electrode 120, and the buffer layer 150. The trench T may be formed to penetrate the first electrode 120 and the buffer layer 150 between the sub-pixels P1, P2, and P3, and may be formed so that a portion of the insulating layer 115 is recessed. It is not limited to this. The trench T may also be formed to penetrate the insulating layer 115. Hereinafter, for convenience of explanation, the trench T refers to a portion that penetrates the first electrode 120 and the buffer layer 150 and the insulating layer 115 is hollowed out or penetrated.

More specifically, the trench T may be formed in a direction from the top surface of the first electrode 120 toward the substrate 111 . This trench (T) consists of a first side (T1), a second side (T2), and a third side (T3) connecting the first side (T1) and the second side (T2).

The first surface T1 of the trench T is the side surface 151a of the buffer layer 151 provided in one sub-pixel, the side surface 121a of the first electrode 121, and the first surface of the insulating layer 115. (115a). The trench T may be formed to expose the side surface 151a of the buffer layer 151 provided in one sub-pixel. Additionally, the trench T may be formed to expose the side surface 121a of the first electrode 121 provided in one sub-pixel. At this time, the side surface 121a of the first electrode 121 provided in one sub-pixel may be exposed in the trench T without being covered by the buffer layer 151 formed on the top surface 121b.

The second surface T2 of the trench T is the side surface 152a of the buffer layer 152 provided in one sub-pixel and another sub-pixel disposed adjacent to the first electrode 122. ) and the second surface 115b of the insulating layer 115. The trench T may be formed to expose the side surface 152a of the buffer layer 152 provided in another sub-pixel. Additionally, the trench T may be formed to expose the side surface 122a of the first electrode 122 provided in another sub-pixel. At this time, the side surface 122a of the first electrode 122 provided in another sub-pixel may be exposed in the trench T without being covered by the buffer layer 152 formed on the top surface 122b.

The third surface T3 of the trench T is provided between the first surface T1 and the second surface T2, and connects the first surface T1 and the second surface T2. One end of the third side T3 of the trench T is connected to the first side T1, and the other end is connected to the second side T2. The third surface T3 of the trench T1 may be formed of a third surface 115c connecting the first surface 115a and the second surface 115b of the insulating layer 115.

The trench T according to another embodiment of the present invention is formed by simultaneously etching the buffer layer 150, the first electrode 120, and the insulating layer 115.

Specifically, an insulating material layer forming the insulating layer 115 is formed on the substrate 111, and a metal material layer forming the first electrode 120 is formed on the insulating material layer. At this time, the metal material layer forming the first electrode 120 may not be patterned for each sub-pixel (P1, P2, and P3), but may be formed as one across the plurality of sub-pixels (P1, P2, and P3).

Next, a non-conductive material layer forming the buffer layer 150 is formed on the metal material layer forming the first electrode 120. At this time, the non-conductive material layer forming the buffer layer 150 is not patterned for each sub-pixel (P1, P2, and P3) like a metal material layer, but is formed as one across the plurality of sub-pixels (P1, P2, and P3). It can be.

Next, a trench T may be formed by simultaneously etching the non-conductive material layer forming the buffer layer 150, the metal material layer forming the first electrode 120, and the insulating material layer forming the insulating layer 115. In addition, the first electrodes 121, 122, and 123 may be patterned for each sub-pixel (P1, P2, and P3). Additionally, the buffer layer 150 may be formed in a pattern on the upper surface of each of the first electrodes 121, 122, and 123 provided in the sub-pixels P1, P2, and P3.

The trench T formed by the above-described process separates the first electrodes 121, 122, and 123 formed in the sub-pixels P1, P2, and P3 from each other, and separates the first electrodes 121, 122, and 123 from each other. Each side is exposed.

At this time, the trench T may have a width W equal to the separation distance d1 between the first electrodes 121, 122, and 123. Specifically, the trench (T) provided between the first sub-pixel (P1) and the second sub-pixel (P2) is connected to the first electrode 121 provided in the first sub-pixel (P1) and the second sub-pixel (P2). ) may have a width (W) equal to the separation distance (d1) between the first electrodes 122 provided in . In addition, the trench T provided between the second sub-pixel P2 and the third sub-pixel P3 is connected to the first electrode 122 provided in the second sub-pixel P2 and the third sub-pixel P3. It may have a width (W) equal to the separation distance (d1) between the first electrodes 123 provided in .

Additionally, the trench T separates the buffer layers 150 formed in the sub-pixels P1, P2, and P3 from each other and exposes the side surfaces of each of the buffer layers 150.

At this time, the trench T may have a width W equal to the separation distance d2 between the buffer layers 150. Specifically, the trench T provided between the first sub-pixel P1 and the second sub-pixel P2 is connected to the buffer layer 150 provided in the first sub-pixel P1 and the second sub-pixel P2. It may have a width (W) equal to the separation distance (d2) between the provided buffer layers 150. In addition, the trench T provided between the second sub-pixel P2 and the third sub-pixel P3 is provided in the buffer layer 150 provided in the second sub-pixel P2 and the third sub-pixel P3. It may have a width (W) equal to the separation distance (d2) between the buffer layers 150.

The width of the trench T may be determined considering the thickness and deposition method of the light emitting layer 130. When the light emitting layer 130 is composed of the first stack 131, the charge generation layer 132, and the second stack 133, the trench T is formed when the charge generation layer 132 is disconnected from the trench T. At least a portion of the two stacks 133 may have a width that allows them to be connected in the trench T.

If the width W of the trench T is formed small, the charge generation layers 132 of adjacent sub-pixels may be connected to each other. Specifically, a trench (T) is formed between the first sub-pixel (P1) and the second sub-pixel (P2), and the first stack 131 of the light-emitting layer 130 and the charge generation layer 132 are formed in the trench (T). ) and the second stack 133 may be sequentially stacked. For example, if the width W1 of the trench T is formed as small as less than 0.09㎛, the first stack 131a stacked on the first sub-pixel P1 and the stack 131a stacked on the second sub-pixel P2 1 Stacks 131b may contact each other at the top of the trench T. As a result, the charge generation layer 132 stacked on the first stack 131 is connected to the first sub-pixel (P1) and the second sub-pixel (P2), causing leakage between adjacent sub-pixels (P1, P2). Current may occur.

According to the present invention, the first stack 131a stacked on the first sub-pixel P1 and the first stack 131b stacked on the second sub-pixel P2 are spaced apart from each other without being connected to each other at the top of the trench T. A display device according to another embodiment may form a width (W) of the trench (T) larger than 0.09㎛.

On the other hand, if the width W of the trench T is formed large, the second electrodes 140 of adjacent sub-pixels may be disconnected from each other in the trench T. For example, if the width W of the trench T is formed to be greater than 0.20㎛, the second electrode 140 stacked on the first sub-pixel P1 and the second electrode 140 stacked on the second sub-pixel P2 Even the electrode 140 may be cut off by the trench T.

At this time, the second electrode 140 stacked on the first sub-pixel P1 may be formed on the first surface T1 of the trench T. The side surface 121a of the first electrode 121 provided in the first sub-pixel P1 may still be exposed. In this case, the side surface 121a of the first electrode 121 and the second electrode 140 may be exposed. Contact may cause a short circuit. Alternatively, the side of the charge generation layer 132a provided in the first sub-pixel P1 may still be exposed. In this case, the side of the charge generation layer 132a contacts the second electrode 140, causing a short circuit. ) may occur.

The second electrode 140 stacked on the second sub-pixel P2 may be formed on the second surface T2 of the trench T. The side surface 121b of the first electrode 121 provided in the second sub-pixel P2 may still be exposed. In this case, the side surface 121b of the first electrode 121 and the second electrode 140 This contact may cause a short circuit. Alternatively, the side of the charge generation layer 132b provided in the second sub-pixel P2 may still be exposed. In this case, the side of the charge generation layer 132b contacts the second electrode 140, causing a short circuit. ) may occur.

A display device according to another embodiment of the present invention is such that the second electrode 140 stacked on the first sub-pixel P1 and the second electrode 140 stacked on the second sub-pixel P2 are connected to each other. The width (W) of the trench (T) can be formed to be less than 0.20㎛.

The light emitting layer 130 is formed on the buffer layer 150. The light emitting layer 130 may be a white light emitting layer that emits white light. In this case, the light emitting layer 130 may be a common layer commonly formed in the sub-pixels P1, P2, and P3.

As shown in FIG. 8, the light emitting layer 130 includes a first stack 131 that emits light of a first color, a second stack 133 that emits light of a second color, and the first stack and the second stack. It includes a charge generating layer (132, CGL) provided between the stacks.

The first stack 131 is provided on the buffer layer 150. The first stack 131 includes a first stack 131a formed in the first sub-pixel P1 and a first stack 131b formed in the adjacent second sub-pixel P2. At this time, the first stack 131a formed in the first sub-pixel P1 and the first stack 131b formed in the second sub-pixel P2 have a step of the trench T as shown in FIGS. 8 and 9. Because of this, they are cut off from each other.

And, the first stack 131a formed in the first sub-pixel P1 covers the side surface 121a of the first electrode 121 exposed in the trench T. The first stack 131b formed in the second sub-pixel P2 covers the side surface 122a of the first electrode 122 exposed in the trench T. Accordingly, the side surfaces 121a and 122a of the first electrodes 121 and 122 are protected and may not affect each other. Meanwhile, the first stack 131a formed in the first sub-pixel P1 and the first stack 131b formed in the second sub-pixel P2 are not connected to each other at the top of the trench T.

The first stack 131 as described above includes a second sub-pixel (P2), a third sub-pixel (P3), and a trench (T) provided between the second sub-pixel (P2) and the third sub-pixel (P3). It can also be formed in the same way.

This first stack 131 includes a hole injection layer (HIL), a hole transport layer (HTL), a first emitting layer (EML1) that emits light of the first color, and an electron transport layer. (Electron Transporting Layer; ETL) may be formed in a sequentially stacked structure, but it is not necessarily limited thereto. The first light-emitting layer (EML1) may be at least one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but is not necessarily limited thereto. no.

The charge generation layer 132 is provided on the first stack 131. The charge generation layer 132 includes a charge generation layer 132a formed in the first sub-pixel P1 and a charge generation layer 132b formed in the second sub-pixel P2. At this time, the charge generation layer 132a formed in the first sub-pixel P1 and the charge generation layer 132c formed in the second sub-pixel P2 have a step of the trench T as shown in FIGS. 8 and 9. Because of this, they are cut off from each other. The charge generation layer 132a formed in the first sub-pixel P1 and the charge generation layer 132b formed in the second sub-pixel P2 are not connected to each other at the top of the trench T.

The charge generation layer 132 as described above includes the second sub-pixel (P2), the third sub-pixel (P3), and the trench (T) provided between the second sub-pixel (P2) and the third sub-pixel (P3). It can also be formed in the same way.

This charge generation layer 132 includes an N-type charge generation layer for providing electrons to the first stack 131 and a P-type charge generation layer for providing holes to the second stack 133. It may be comprised of a layered structure.

The second stack 133 is provided on the charge generation layer 132. The second stack 133 has a structure in which a hole transport layer (HTL), a second light emitting layer (EML2) that emits light of a second color, an electron transport layer (ETL), and an electron injection layer (EIL) are sequentially stacked. It can be done, but it is not necessarily limited to that. The second light-emitting layer (EML2) may be at least one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but is not necessarily limited thereto. no.

However, the second emitting layer (EML2) may emit light of a different color than the first emitting layer (EML1). For example, the first light-emitting layer (EML1) may be a blue light-emitting layer that emits blue light, and the second light-emitting layer (EML2) may be a yellow light-emitting layer that emits yellow light. For another example, the first light-emitting layer (EML1) may be a blue light-emitting layer that emits blue light, and the second light-emitting layer (EML2) may be a red light-emitting layer that emits red light and a green light-emitting layer that emits green light.

Since the charge generation layer 132 of each of the sub-pixels P1, P2, and P3 is disconnected from each other inside the trench T, the charge generation layer 132 is connected between adjacent sub-pixels P1, P2, and P3. It is difficult for electric charges to move.

The light emitting layer 130 according to another embodiment of the present invention can minimize the influence of adjacent sub-pixels P1, P2, and P3 due to leakage current.

Additionally, the light emitting layer 130 according to another embodiment of the present invention can be deposited on the plurality of sub-pixels P1, P2, and P3 at a time without using a separate mask.

Meanwhile, in the display panel 100 according to another embodiment of the present invention, as the light emitting layer 130 is formed, an air gap (AG) may be formed inside the trench (T). The first stack 131 of the light emitting layer 130 may be formed thick at a place where the upper surface of the buffer layer 150 is bent toward the sides (T1, T2) of the trench (T). More specifically, the thickness of the first stack 131 at the boundary between the top surface of the buffer layer 150 and the first side T1 of the trench T is the first side T1 or the bottom surface (T1) of the trench T. It may be formed to be thicker than the thickness of the first stack 131 at T3). In addition, the thickness of the first stack 131 at the boundary between the top surface of the buffer layer 150 and the second side T2 of the trench T is the thickness of the second side T2 or bottom surface T3 of the trench T. It may be formed thicker than the thickness of the first stack 131. The inside of the trench T becomes narrower from the bottom to the top, and as the charge generation layer 132 and the second stack 133 are formed on the first stack 131, an air gap AG may be formed.

The display panel 100 according to another embodiment of the present invention refracts the light traveling from the light emitting layer 130 to the trench (T) through the air gap (AG) formed inside the trench (T) so that it can be directed forward. You can. The display panel 100 according to another embodiment of the present invention can improve light efficiency by minimizing the loss of light emitted from the light emitting layer 130.

A display device according to another embodiment of the present invention is characterized by forming a trench T by simultaneously etching the buffer layer 150, the first electrode 120, and the insulating layer 115.

A display device according to another embodiment of the present invention forms a trench T by simultaneously etching the buffer layer 150, the first electrode 120, and the insulating layer 115, and does not form a separate bank. Accordingly, in the display device according to another embodiment of the present invention, the entire area where the first electrode 120 is formed becomes the light-emitting area EA, and thus the light-emitting area EA can be maximized.

In the display device according to another embodiment of the present invention, only the area where the trench T is formed becomes a non-emission area, so the gap between the sub-pixels P1, P2, and P3 can be minimized. Furthermore, a display device according to another embodiment of the present invention can minimize current density and improve device lifespan by maximizing the aperture ratio.

Additionally, the display device according to another embodiment of the present invention does not require a separate process to form a pattern of the first electrode 120 for each sub-pixel (P1, P2, and P3), and there is no need to manufacture a separate mask. Accordingly, the display device according to another embodiment of the present invention has a simplified process and can significantly reduce process costs.

Additionally, the display device according to another embodiment of the present invention does not require a separate process to pattern the buffer layer 150 for each sub-pixel (P1, P2, and P3), and there is no need to manufacture a separate mask. Accordingly, the display device according to another embodiment of the present invention has a simplified process and can significantly reduce process costs.

Additionally, in a display device according to another embodiment of the present invention, the buffer layer 150 may be formed of a non-conductive material as thin as 10Å to 50Å.

In a display device according to another embodiment of the present invention, the buffer layer 150 is formed thinly on the upper surface of the first electrode 120, so that holes or electrons of the first electrode 120 are transmitted to the light emitting layer 130 by a tunneling phenomenon. ) can be moved to. Accordingly, the entire area where the upper surface of the first electrode 120 and the buffer layer 150 are in contact can become the light emitting area EA.

In addition, in the display device according to another embodiment of the present invention, the buffer layer 150 is formed at the edge of the upper surface of the first electrode 120, so that the current concentrated on the edge of the first electrode 120 is directly transmitted to the light emitting layer 130. This can prevent luminous efficiency from decreasing.

Additionally, in a display device according to another embodiment of the present invention, the charge generation layer 132 of the light emitting layer 130 may be disconnected by the trench T. Accordingly, the display device according to an embodiment of the present invention maintains the charge generation layer 132 formed in each of the adjacent sub-pixels (P1, P2, and P3) even if the gap between the sub-pixels (P1, P2, and P3) is reduced. Since they are not connected to each other, leakage current may not occur between adjacent sub-pixels (P1, P2, and P3).

FIG. 10 is a flowchart showing a method of manufacturing a display device according to an embodiment of the present invention, and FIGS. 11A to 11H are cross-sectional views showing a method of manufacturing a display device according to an embodiment of the present invention.

First, an insulating material layer 117 forming the circuit element and the insulating layer 115 is formed on the substrate 111 (S901).

More specifically, a driving thin film transistor (TFT) is formed on the substrate 111 as shown in FIG. 11A.

Then, an insulating material layer 117 forming the insulating layer 115 is formed on the driving thin film transistor (TFT). The insulating material layer 117 forming the insulating layer 115 may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not necessarily limited thereto. The insulating material layer 117 forming the insulating layer 115 is an organic layer, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide. It may be formed of polyimide resin, etc. Alternatively, the insulating layer 115 may be formed as a multilayer composed of at least one inorganic layer and at least one organic layer.

Next, the metal material layer 125 forming the first electrode 120 is deposited on the entire surface (S902).

More specifically, as shown in FIG. 11B, a metal material layer 125 forming the first electrode 120 is deposited on the entire surface of the insulating material layer 117. At this time, the metal material layer 125 forming the first electrode 120 is connected to the source terminal or drain terminal of the driving thin film transistor (TFT) through the contact hole (CH) for each sub-pixel (P1, P2, and P3).

The metal material layer 125 forming the first electrode 120 may be made of a transparent metal material, a translucent metal material, or a highly reflective metal material. When the display device 100 is made of a top-emitting type, the metal material layer 125 forming the first electrode 120 has a stacked structure of aluminum and titanium (Ti/Al/Ti), or a stacked structure of aluminum and ITO (ITO). /Al/ITO), Ag alloy, and a laminated structure of Ag alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). When the display device 100 is made of a bottom-emitting type, the metal material layer 125 forming the first electrode 120 is a transparent metal material (TCO, Transparent Conductive Material) such as ITO or IZO that can transmit light, Alternatively, it may be formed of a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

Next, a trench (T) is formed (S903).

More specifically, a trench T is formed by simultaneously etching the insulating material layer 117 and the metal material layer 125 as shown in FIG. 11C. In the display panel 100 according to an embodiment of the present invention, a trench T can be formed by dry etching the material 125 forming the first electrode 120 and the insulating layer 115 at once. At the same time, the first electrodes 121, 122, and 123 may be patterned for each sub-pixel (P1, P2, and P3).

The trench T may be formed to penetrate the first electrode 120 between the sub-pixels P1, P2, and P3 and to recess a portion of the insulating layer 115, but is not limited to this. The trench T may also be formed to penetrate the insulating layer 115.

The trench T separates the first electrodes 121, 122, and 123 formed in the sub-pixels P1, P2, and P3 from each other and exposes the side surfaces of each of the first electrodes 121, 122, and 123. .

Next, the buffer layer 150 is formed (S904).

More specifically, a buffer layer 150 is formed on the first electrode 120 and the trench T as shown in FIG. 11D. More specifically, the buffer layer 150 may be formed to cover the display area DA on the first substrate 111 provided with the first electrode 120 and the trench T. The buffer layer 150 may be formed to cover the first electrode 120 and the trench T.

The buffer layer 150 is formed on the upper surface of the first electrode 120 and is also formed on the trench T. Specifically, the side surface of the first electrode 120 and the first surface 115a, second surface 115b, and third surface 115c of the insulating layer 115 are exposed in the trench T. The buffer layer 150 is in contact with the side surface of the first electrode 120 exposed in the trench T and the first surface 115a, second surface 115b, and third surface 115c of the insulating layer 115. It is provided.

The buffer layer 150 may be made of a non-conductive material, for example, aluminum oxide (Al ₂ O _x ), zinc oxide (ZnO), silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). , monomer, polyimide resin, etc.

The buffer layer 150 may be formed thinly using an atomic layer deposition (ALD) technique. The buffer layer 150 may be thinly formed on the upper surface of the first electrode 120 with a thickness of less than 50Å. When the buffer layer 150 is formed as thin as less than 50 Å, holes or electrons of the first electrode 120 may pass to the light emitting layer 130 by a tunneling phenomenon.

Meanwhile, the buffer layer 150 may be formed to cover the edge of the first electrode 120 with a thickness of 10 Å or more. If the buffer layer 150 is formed thinner than 10Å, the current concentrated at the edge of the first electrode 120 may be directly transferred to the light emitting layer 130, thereby reducing luminous efficiency.

Next, the light emitting layer 130 is formed (S905).

As shown in Figure 11e, the light emitting layer 130 is formed on the buffer layer 150. More specifically, the first stack 131 is formed on the buffer layer 150. The first stack 131 may be formed through a deposition process or a solution process. When the first stack 131 is formed through a deposition process, it may be formed using an evaporation method. At this time, the first stack 131 is disconnected due to the step of the trench T between the sub-pixels P1, P2, and P3.

The first stack 131 includes a hole injection layer (HIL), a hole transport layer (HTL), a first emitting layer (EML1) that emits light of the first color, and an electron transport layer ( It may be a structure in which Electron Transporting Layer (ETL) is stacked sequentially.

The first light-emitting layer (EML1) may be at least one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but is not necessarily limited thereto. no.

Then, the charge generation layer 132 is formed on the first stack 131. At this time, the charge generation layer 132 is disconnected between the sub-pixels P1, P2, and P3 due to the step of the trench T.

The charge generation layer 132 is a stack of an N-type charge generation layer for providing electrons to the first stack 131 and a P-type charge generation layer for providing holes to the second stack 133. It can be made up of a structured structure.

Then, the second stack 133 is formed on the charge generation layer 132. The second stack 133 may be formed through a deposition process or a solution process. When the second stack 133 is formed through a deposition process, it may be formed using an evaporation method. At this time, the second stack 133 is connected to the sub-pixels P1, P2, and P3.

The second stack 133 has a structure in which a hole transport layer (HTL), a second light emitting layer (EML2) that emits light of a second color, an electron transport layer (ETL), and an electron injection layer (EIL) are sequentially stacked. It can be done, but it is not necessarily limited to that. The second light-emitting layer (EML2) may be at least one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but is not necessarily limited thereto. no.

However, the second emitting layer (EML2) may emit light of a different color than the first emitting layer (EML1). For example, the first light-emitting layer (EML1) may be a blue light-emitting layer that emits blue light, and the second light-emitting layer (EML2) may be a yellow light-emitting layer that emits yellow light. For another example, the first light-emitting layer (EML1) may be a blue light-emitting layer that emits blue light, and the second light-emitting layer (EML2) may be a red light-emitting layer that emits red light and a green light-emitting layer that emits green light.

Next, the second electrode 140 is formed (S906).

More specifically, the second electrode 140 is formed on the light emitting layer 130 as shown in FIG. 11f. The second electrode 140 may be formed by a physical vapor deposition method such as sputtering. Alternatively, the second electrode 140 may be formed using evaporation.

The second electrode 140 may be made of a transparent metal material, a translucent metal material, or a highly reflective metal material. When the display device is made of a top-emitting type, the second electrode 140 is made of a transparent conductive material (TCO) such as ITO or IZO, which can transmit light, or magnesium (Mg), silver (Ag), Alternatively, it may be formed of a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). When the display device is made of a bottom-emitting type, the second electrode 140 has a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), Ag alloy, and Ag It can be formed of a metal material with high reflectivity, such as a laminated structure of alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). This second electrode 140 may be a cathode electrode.

Next, an encapsulation film 160 is formed (S907).

More specifically, an encapsulation film 160 is formed on the second electrode 140 as shown in FIG. 11g. The encapsulation film 160 may include a first inorganic film and an organic film. In one embodiment, the encapsulation film 160 may further include a second inorganic film.

A first inorganic layer is formed on the second electrode 140. Then, an organic film is formed on the first inorganic film. The organic layer is preferably formed with a sufficient thickness to prevent particles from penetrating the first inorganic layer and entering the light emitting layer 130 and the second electrode 140. Then, a second inorganic film is formed on the organic film.

Each of the first and second inorganic layers may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first and second inorganic layers may be deposited using a CVD (Chemical Vapor Deposition) technique or an ALD (Atomic Layer Deposition) technique, but are not limited thereto.

The organic film may be formed of acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The organic film may be formed by vapor deposition, printing, or slit coating techniques using organic materials, but is not limited thereto, and the organic film may be formed by an ink-jet process. .

Next, the color filter 170 is formed (S908).

More specifically, a color filter 170 is formed on the encapsulation film 160 as shown in FIG. 11h. The color filter 170 includes a first color filter (CF1) arranged to correspond to the first sub-pixel (P1), a second color filter (CF2) arranged to correspond to the second sub-pixel (P2), and a third sub-pixel. It may include a third color filter (CF3) arranged to correspond to (P3). The first color filter (CF1) may be a red color filter that transmits red light, the second color filter (CF2) may be a green color filter that transmits green light, and the third color filter (CF3) may be a green color filter that transmits blue light. It may be a blue color filter that transmits.

FIG. 12 is a flowchart showing a method of manufacturing a display device according to another embodiment of the present invention, and FIGS. 13A to 13H are cross-sectional views showing a method of manufacturing a display device according to another embodiment of the present invention.

First, an insulating material layer 117 forming the circuit element and the insulating layer 115 is formed on the substrate 111 (S1101).

More specifically, a driving thin film transistor (TFT) is formed on the substrate 111 as shown in FIG. 13A.

Then, an insulating material layer 117 forming the insulating layer 115 is formed on the driving thin film transistor (TFT). The insulating material layer 117 forming the insulating layer 115 may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not necessarily limited thereto. The insulating material layer 117 forming the insulating layer 115 is an organic layer, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide. It may be formed of polyimide resin, etc. Alternatively, the insulating layer 115 may be formed as a multilayer composed of at least one inorganic layer and at least one organic layer.

Next, the metal material layer 125 forming the first electrode 120 is deposited on the entire surface (S1102).

More specifically, as shown in FIG. 13B, a metal material layer 125 forming the first electrode 120 is deposited on the entire surface of the insulating material layer 117. At this time, the metal material layer 125 forming the first electrode 120 is connected to the source terminal or drain terminal of the driving thin film transistor (TFT) through the contact hole (CH) for each sub-pixel (P1, P2, and P3).

The metal material layer 125 forming the first electrode 120 may be made of a transparent metal material, a translucent metal material, or a highly reflective metal material. When the display device 100 is made of a top-emitting type, the metal material layer 125 forming the first electrode 120 has a stacked structure of aluminum and titanium (Ti/Al/Ti), or a stacked structure of aluminum and ITO (ITO). /Al/ITO), Ag alloy, and a laminated structure of Ag alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). When the display device 100 is made of a bottom-emitting type, the metal material layer 125 forming the first electrode 120 is a transparent metal material (TCO, Transparent Conductive Material) such as ITO or IZO that can transmit light, Alternatively, it may be formed of a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

Next, a non-conductive material layer 155 forming the buffer layer 150 is formed (S1103).

More specifically, as shown in FIG. 13C, a non-conductive material layer 155 forming the buffer layer 150 is deposited on the entire surface of the metal material layer 125 forming the first electrode 120.

The non-conductive material layer 155 forming the buffer layer 150 is, for example, aluminum oxide (Al ₂ O _x ), zinc oxide (ZnO), silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). ), monomer, polyimide resin, etc.

The non-conductive material layer 155 forming the buffer layer 150 may be formed thinly using an atomic layer deposition (ALD) technique. The non-conductive material layer 155 forming the buffer layer 150 may be formed thinly on the metal material layer 125 forming the first electrode 120 with a thickness of 10 Å to less than 50 Å.

Next, a trench (T) is formed (S1104).

More specifically, as shown in FIG. 13D, a trench T is formed by simultaneously etching the non-conductive material layer 155, the insulating material layer 117, and the metal material layer 125. The display panel 100 according to an embodiment of the present invention is made by dry etching the non-conductive material layer 155 forming the buffer layer 150, the material 125 forming the first electrode 120, and the insulating layer 115 at once. Thus, a trench (T) can be formed. At the same time, the first electrodes 121, 122, and 123 may be patterned for each sub-pixel (P1, P2, and P3). Additionally, the buffer layer 150 may be patterned for each sub-pixel (P1, P2, and P3).

The trench T may be formed to penetrate the first electrode 120 and the buffer layer 150 between the sub-pixels P1, P2, and P3, and may be formed so that a portion of the insulating layer 115 is recessed. It is not limited to this. The trench T may also be formed to penetrate the insulating layer 115.

The trench T separates the first electrodes 121, 122, and 123 formed in the sub-pixels P1, P2, and P3 from each other and exposes the side surfaces of each of the first electrodes 121, 122, and 123. .

Additionally, the trench T separates the buffer layers 150 formed in the sub-pixels P1, P2, and P3 from each other and exposes the side surfaces of each of the buffer layers 150.

Next, the light emitting layer 130 is formed (S1105).

As shown in Figure 13e, the light emitting layer 130 is formed on the buffer layer 150. More specifically, the first stack 131 is formed on the buffer layer 150. The first stack 131 may be formed through a deposition process or a solution process. When the first stack 131 is formed through a deposition process, it may be formed using an evaporation method. At this time, the first stack 131 is disconnected due to the step of the trench T between the sub-pixels P1, P2, and P3.

The first stack 131 includes a hole injection layer (HIL), a hole transport layer (HTL), a first emitting layer (EML1) that emits light of the first color, and an electron transport layer ( It may be a structure in which Electron Transporting Layer (ETL) is stacked sequentially.

The first light-emitting layer (EML1) may be at least one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but is not necessarily limited thereto. no.

Then, the charge generation layer 132 is formed on the first stack 131. At this time, the charge generation layer 132 is disconnected between the sub-pixels P1, P2, and P3 due to the step of the trench T.

The charge generation layer 132 is a stack of an N-type charge generation layer for providing electrons to the first stack 131 and a P-type charge generation layer for providing holes to the second stack 133. It can be made up of a structured structure.

Then, the second stack 133 is formed on the charge generation layer 132. The second stack 133 may be formed through a deposition process or a solution process. When the second stack 133 is formed through a deposition process, it may be formed using an evaporation method. At this time, the second stack 133 is connected to the sub-pixels P1, P2, and P3.

The second stack 133 has a structure in which a hole transport layer (HTL), a second light emitting layer (EML2) that emits light of a second color, an electron transport layer (ETL), and an electron injection layer (EIL) are sequentially stacked. It can be done, but it is not necessarily limited to that. The second light-emitting layer (EML2) may be at least one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but is not necessarily limited thereto. no.

However, the second emitting layer (EML2) may emit light of a different color than the first emitting layer (EML1). For example, the first light-emitting layer (EML1) may be a blue light-emitting layer that emits blue light, and the second light-emitting layer (EML2) may be a yellow light-emitting layer that emits yellow light. For another example, the first light-emitting layer (EML1) may be a blue light-emitting layer that emits blue light, and the second light-emitting layer (EML2) may be a red light-emitting layer that emits red light and a green light-emitting layer that emits green light.

Next, the second electrode 140 is formed (S1106).

More specifically, the second electrode 140 is formed on the light emitting layer 130 as shown in Figure 13f. The second electrode 140 may be formed by a physical vapor deposition method such as sputtering. Alternatively, the second electrode 140 may be formed using evaporation.

The second electrode 140 may be made of a transparent metal material, a translucent metal material, or a highly reflective metal material. When the display device is made of a top-emitting type, the second electrode 140 is made of a transparent conductive material (TCO) such as ITO or IZO, which can transmit light, or magnesium (Mg), silver (Ag), Alternatively, it may be formed of a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). When the display device is made of a bottom-emitting type, the second electrode 140 has a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), Ag alloy, and Ag It can be formed of a metal material with high reflectivity, such as a laminated structure of alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). This second electrode 140 may be a cathode electrode.

Next, an encapsulation film 160 is formed (S1107).

More specifically, an encapsulation film 160 is formed on the second electrode 140 as shown in FIG. 13g. The encapsulation film 160 may include a first inorganic film and an organic film. In one embodiment, the encapsulation film 160 may further include a second inorganic film.

A first inorganic layer is formed on the second electrode 140. Then, an organic film is formed on the first inorganic film. The organic layer is preferably formed with a sufficient thickness to prevent particles from penetrating the first inorganic layer and entering the light emitting layer 130 and the second electrode 140. Then, a second inorganic film is formed on the organic film.

Each of the first and second inorganic layers may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first and second inorganic layers may be deposited using a CVD (Chemical Vapor Deposition) technique or an ALD (Atomic Layer Deposition) technique, but are not limited thereto.

The organic film may be formed of acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The organic film may be formed by vapor deposition, printing, or slit coating techniques using organic materials, but is not limited thereto, and the organic film may be formed by an ink-jet process. .

Next, the color filter 170 is formed (S1108).

More specifically, a color filter 170 is formed on the encapsulation film 160 as shown in FIG. 13h. The color filter 170 includes a first color filter (CF1) arranged to correspond to the first sub-pixel (P1), a second color filter (CF2) arranged to correspond to the second sub-pixel (P2), and a third sub-pixel. It may include a third color filter (CF3) arranged to correspond to (P3). The first color filter (CF1) may be a red color filter that transmits red light, the second color filter (CF2) may be a green color filter that transmits green light, and the third color filter (CF3) may be a green color filter that transmits blue light. It may be a blue color filter that transmits.

14A to 14C relate to a display device according to another embodiment of the present invention, which relates to a head mounted display (HMD) device. FIG. 14A is a schematic perspective view, FIG. 14B is a schematic plan view of a VR (Virtual Reality) structure, and FIG. 14C is a schematic cross-sectional view of an AR (Augmented Reality) structure.

As can be seen in FIG. 14A, the head-mounted display device according to the present invention includes a storage case 10 and a head-mounted band 30.

The storage case 10 stores components such as a display device, a lens array, and an eyepiece lens therein.

The head mounting band 30 is fixed to the storage case 10. The head mounting band 30 is illustrated as being formed to surround the upper surface and both sides of the user's head, but is not limited thereto. The head mounting band 30 is used to secure the head mounted display to the user's head, and can be replaced with a structure in the form of a glasses frame or a helmet.

As can be seen in Figure 14b, the head-mounted display device with a VR (Virtual Reality) structure according to the present invention includes a display device 12 for the left eye, a display device 11 for the right eye, a lens array 13, and a left eyepiece lens ( 20a) and a right eyepiece 20b.

The display device 12 for the left eye and the display device 11 for the right eye, the lens array 13, and the left eyepiece 20a and right eyepiece lens 20b are stored in the storage case 10 described above.

The display device 12 for the left eye and the display device 11 for the right eye can display the same image, and in this case, the user can watch a 2D image. Alternatively, the display device 12 for the left eye may display the left eye image and the display device 11 for the right eye may display the right eye image. In this case, the user may view a three-dimensional image. Each of the display device 12 for the left eye and the display device 11 for the right eye may be made of the display device shown in FIGS. 1 to 9 described above. At this time, the upper portion corresponding to the surface on which the image is displayed in FIGS. 1 to 9, for example, the color filter 170, faces the lens array 13.

The lens array 13 may be provided between the left eyepiece lens 20a and the left eye display device 12 while being spaced apart from each other. That is, the lens array 13 may be located in front of the left eye eyepiece 20a and behind the display device 12 for the left eye. Additionally, the lens array 13 may be provided between the right eyepiece lens 20b and the right eye display device 11 while being spaced apart from each of the right eyepiece lens 20b and the right eye display device 11. That is, the lens array 13 may be located in front of the right eye eyepiece 20b and behind the display device 11 for the right eye.

The lens array 13 may be a micro lens array. The lens array 13 can be replaced with a pin hole array. Due to the lens array 13, the image displayed on the left-eye display device 12 or the right-eye display device 11 may be enlarged and visible to the user.

The user's left eye (LE) may be located in the left eyepiece lens 20a, and the user's right eye (RE) may be located in the right eyepiece lens 20b.

As can be seen in FIG. 14C, the head-mounted display device with an AR (Augmented Reality) structure according to the present invention includes a left-eye display device 12, a lens array 13, a left-eye eyepiece 20a, and a transmission reflector 14. , and a transmission window 15. In Figure 14c, only the left inner configuration is shown for convenience, and the right inner configuration is also the same as the left inner configuration.

The left-eye display device 12, lens array 13, left-eye eyepiece 20a, transmission reflector 14, and transmission window 15 are stored in the storage case 10 described above.

The display device 12 for the left eye may be disposed on one side, for example, on the upper side of the transmission reflection portion 14 without blocking the transmission window 15. Accordingly, the left-eye display device 12 can provide an image to the transparent reflector 14 without blocking the external background seen through the transparent window 15.

The display device 12 for the left eye may be made of the display device according to FIGS. 1 to 9 described above. At this time, the upper portion corresponding to the surface on which the image is displayed in FIGS. 1 to 9, for example, the color filter 170, faces the transmission and reflection portion 14.

The lens array 13 may be provided between the left eyepiece lens 20a and the transmission and reflection unit 14.

The user's left eye is located in the left eye eyepiece 20a.

The transmission reflection portion 14 is disposed between the lens array 13 and the transmission window 15. The transmission reflection unit 14 may include a reflection surface 14a that transmits part of the light and reflects another part of the light. The reflective surface 14a is formed so that the image displayed on the left eye display device 12 progresses to the lens array 13. Accordingly, the user can view both the external background and the image displayed by the left eye display device 12 through the transmission layer 15. In other words, since the user can view the real background and the virtual image as one image by overlapping them, Augmented Reality (AR) can be implemented.

The transmission layer 15 is disposed in front of the transmission reflection portion 14.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

10: display device
111: Substrate TFT: Driving thin film transistor
115: insulating layer 120: first electrode
130: light emitting layer 131: first stack
132: charge generation layer 133: second stack
140: second electrode 150: buffer layer
160: Encapsulation membrane 170: Color filter

Claims (19)

Board;
a first electrode provided in each of a first sub-pixel and a second sub-pixel disposed adjacent to the first sub-pixel on the substrate;
a buffer layer provided on the first electrode;
A light emitting layer provided on the buffer layer; and
It includes a second electrode provided on the light emitting layer,
The buffer layer is formed to cover the entire upper surface of the first electrode. According to paragraph 1,
an insulating layer provided between the substrate and the first electrode; and
Further comprising a trench provided between the first sub-pixel and the second sub-pixel,
The display device wherein the trench is formed in the insulating layer and the first electrode. According to paragraph 2,
The display device wherein the trench is formed in a direction from the top surface of the first electrode toward the substrate. According to paragraph 2,
The first electrode provided in the first sub-pixel and the first electrode provided in the second sub-pixel are spaced apart from each other,
The trench is formed to expose a side surface of the first electrode provided in the first sub-pixel and a side surface of the first electrode provided in the second sub-pixel. According to paragraph 4,
A display device wherein the separation distance between the first electrode provided in the first sub-pixel and the first electrode provided in the second sub-pixel is equal to the width of the trench. According to paragraph 1,
The buffer layer is provided to contact the top surface of the first electrode provided in the first sub-pixel and the top surface of the first electrode provided in the second sub-pixel. According to paragraph 1,
The buffer layer is provided to contact a side of the first electrode provided in the first sub-pixel and a side of the first electrode provided in the second sub-pixel. According to paragraph 2,
The buffer layer is provided on an insulating layer exposed in the trench. According to paragraph 1,
A display device in which the buffer layer is made of a non-conductive material. According to paragraph 2,
The light emitting layer includes a first stack, a charge generation layer provided on the first stack, and a second stack provided on the charge generation layer,
The display device wherein the charge generation layer is cut off by the trench between the first sub-pixel and the second sub-pixel. According to clause 10,
The second stack is connected between the first sub-pixel and the second sub-pixel. According to paragraph 2,
A display device in which an air gap is formed inside the trench, which is surrounded by the light emitting layer and the buffer layer. forming an insulating material layer on a substrate including a display area to cover the entire display area;
forming a metal material layer on the insulating material layer to cover the entire display area;
simultaneously performing an etching process on the metal material layer and the insulating material layer formed to cover the entire display area to form a trench, and patterning the first electrode for each sub-pixel; and
A method of manufacturing a display device including forming a buffer layer on the first electrode and the trench. According to clause 13,
The buffer layer covers a top surface of the first electrode and a side surface of the first electrode. According to clause 13,
A method of manufacturing a display device in which the buffer layer is made of a non-conductive material. According to clause 13,
forming a first stack on the buffer layer;
forming a charge generation layer on the first stack; and
Further comprising forming a second stack on the charge generation layer,
A method of manufacturing a display device in which the charge generation layer is disconnected by the trench. According to clause 16,
Further comprising forming a second electrode on the second stack,
A method of manufacturing a display device wherein the second electrode is connected on the trench. forming an insulating material layer on a substrate including a display area to cover the entire display area;
forming a metal material layer on the insulating material layer to cover the entire display area;
forming a non-conductive material layer on the metal material to cover the entire display area; and
Simultaneously performing an etching process on the metal material layer, the non-conductive material layer, and the insulating material layer formed to cover the entire display area to form a trench, and forming a pattern of the first electrode and the buffer layer for each sub-pixel. A method of manufacturing a display device. According to clause 18,
The buffer layer is formed to contact the top surface of the first electrode.

Images