KR102622790B1 - Display device - Google Patents

Abstract

The present invention provides a display device capable of reducing power consumption. A display device according to an embodiment of the present invention includes a substrate having a first sub-pixel and a second sub-pixel, a first electrode provided in each of the first sub-pixel and the second sub-pixel on the substrate, and a first electrode. a first light-emitting layer that emits light of a first color, a second electrode provided on the first light-emitting layer, a second light-emitting layer provided on the second electrode and emitting light of a second color, and a second electrode provided on the second light-emitting layer. It includes a third electrode. The second electrode is disconnected between the first sub-pixel and the second sub-pixel, the second electrode of the first sub-pixel is electrically connected to the third electrode, and the second electrode of the second sub-pixel is electrically connected to the first electrode. It is connected to

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device that displays images.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, recently, various display devices such as liquid crystal display (LCD), plasma display panel (PDP), and organic light emitting display (OLED) have been used.

Recently, a head mounted display (HMD) including such a display device has been developed. A head-mounted display (HMD) is a virtual reality (VR) or augmented reality glasses-type monitor device that is worn in the form of glasses or a helmet and focuses on a distance near the user's eyes.

In such head-mounted displays, it is difficult to precisely pattern different-colored light emitting layers for each sub-pixel due to the high resolution and tight pixel spacing. To solve this problem, a head-mounted display forms a common layer of a white light-emitting layer composed of a plurality of stacks that emit light of different colors, and can implement different colors by arranging color filters for each sub-pixel. In this case, the head-mounted display has the advantage of not requiring precise mask manufacturing or a precise mask alignment process, but has the problem of consuming a lot of power due to the plurality of stacks.

The present invention provides a display device capable of reducing power consumption.

A display device according to an embodiment of the present invention includes a substrate having a first sub-pixel and a second sub-pixel, a first electrode provided in each of the first sub-pixel and the second sub-pixel on the substrate, and a first electrode. a first light-emitting layer that emits light of a first color, a second electrode provided on the first light-emitting layer, a second light-emitting layer provided on the second electrode and emitting light of a second color, and a second electrode provided on the second light-emitting layer. It includes a third electrode. The second electrode is disconnected between the first sub-pixel and the second sub-pixel, the second electrode of the first sub-pixel is electrically connected to the third electrode, and the second electrode of the second sub-pixel is electrically connected to the first electrode. It is connected to

A display device according to another embodiment of the present invention includes a substrate having a first sub-pixel, a second sub-pixel, and a third sub-pixel, and each of the first sub-pixel, the second sub-pixel, and the third sub-pixel on the substrate. a first electrode, a first light-emitting layer provided on the first electrode and emitting light of a first color, a second electrode provided on the first light-emitting layer, and a first light-emitting layer provided on the second electrode and emitting light of a second color. It includes a second light-emitting layer and a third electrode provided on the second light-emitting layer. The same voltage is applied to the second and third electrodes of the first and third sub-pixels, and the first light-emitting layer provided between the first and second electrodes emits light. The same voltage is applied to the first and second electrodes of the second sub-pixel, and the second light emitting layer provided between the second and third electrodes emits light.

According to the present invention, by forming the first light emitting layer and the second light emitting layer on the entire surface of the sub-pixels without a mask, it is possible to solve the problem of forming different light emitting layers for each sub-pixel using a mask. In other words, the present invention does not require precise mask manufacturing or a precise mask alignment process, and can be applied to high-resolution display devices with tight pixel spacing.

In addition, in the present invention, although the first light emitting layer and the second light emitting layer are formed on the entire surface, only one of the first light emitting layer and the second light emitting layer can emit light from each sub-pixel. Accordingly, the present invention can significantly reduce power consumption compared to making both the first light emitting layer and the second light emitting layer emit light.

In addition, in the present invention, the second electrode is disconnected between sub-pixels using a blocking pattern, and the second electrode of each sub-pixel is connected to any one of the first power line, the second power line, and the second connection electrode. It can be. In the present invention, there is no need to manufacture a separate mask, and by forming the masking pattern at the same time as the first electrode, no separate process is added.

The effects that can be obtained from the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the description below. .

1 is a perspective view showing a display device according to an embodiment of the present invention.
FIG. 2 is a plan view showing the first substrate, source drive IC, flexible film, circuit board, and timing control unit of FIG. 1.
Figure 3 is a plan view schematically showing a first substrate according to the first embodiment of the present invention.
Figure 4 is a cross-sectional view showing an example of II in Figure 3.
FIG. 5 is a cross-sectional view showing an example of line II-II of FIG. 3.
6 is a plan view schematically showing an example of a first sub-pixel and a second sub-pixel.
Figure 7 is a plan view showing a modified example of Figure 6.
Figure 8 is a plan view schematically showing an example of a third sub-pixel.
Figure 9 is a plan view showing a modified example of Figure 8.
FIG. 10 is an enlarged view showing an example of area A of FIG. 4.
FIG. 11 is a cross-sectional view showing an example of line III-III of FIG. 3.
FIG. 12 is a cross-sectional view showing an example of line IV-IV of FIG. 3.
13 is a plan view schematically showing the first substrate of a display panel according to another embodiment of the present invention.
FIG. 14 is a cross-sectional view showing an example of line V-V of FIG. 13.
15 is a plan view schematically showing an example of a first sub-pixel and a second sub-pixel.
Figure 16 is a flowchart for explaining a method of manufacturing a display device according to the first embodiment of the present invention.
17A to 17J are cross-sectional views for explaining a method of manufacturing a display device according to the first embodiment of the present invention.
18A to 18C relate to a display device according to another embodiment of the present invention, which relates to a head mounted display (HMD) device.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. These embodiments only serve to ensure that the disclosure of the present invention is complete, and those skilled in the art It is provided to fully inform the person of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., 'immediately' or 'directly' Unless used, non-consecutive cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

“X-axis direction,” “Y-axis direction,” and “Z-axis direction” should not be interpreted as only geometrical relationships in which the relationship between each other is vertical, and should not be interpreted as a wider range within which the configuration of the present invention can function functionally. It can mean having direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, “at least one of the first, second, and third items” means each of the first, second, or third items, as well as two of the first, second, and third items. It can mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention can be partially or fully combined or combined with each other, various technical interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a perspective view showing a display device according to an embodiment of the present invention. FIG. 2 is a plan view showing the first substrate, source drive IC, flexible film, circuit board, and timing control unit of FIG. 1.

1 and 2, a display device 100 according to an embodiment of the present invention includes a display panel 110, a source drive integrated circuit (hereinafter referred to as “IC”) 140, and a flexible film. It includes 150, a circuit board 160, and a timing control unit 170.

The display panel 110 includes a first substrate 111 and a second substrate 112. The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film.

Gate lines, data lines, and sub-pixels are formed on one side of the first substrate 111 facing the second substrate 112. Sub-pixels are provided in an area defined by the intersection structure of gate lines and data lines.

Each of the sub-pixels may include a thin film transistor and a light-emitting element including an anode electrode, a light-emitting layer, and a cathode electrode. Each of the sub-pixels uses a thin film transistor to supply a predetermined current to the light emitting device according to the data voltage of the data line when a gate signal is input from the gate line. For this reason, when a high potential voltage is applied to the anode electrode and a low potential voltage is applied to the cathode electrode, the light emitting layer of each sub-pixel can emit light with a predetermined brightness according to a predetermined current.

The display panel 110 may be divided into a display area (DA) in which sub-pixels are formed to display images, and a non-display area (NDA) in which images are not displayed. Gate lines, data lines, and sub-pixels may be formed in the display area DA. A gate driver and pads may be formed in the non-display area NDA.

The gate driver supplies gate signals to the gate lines according to the gate control signal input from the timing control unit 170. The gate driver may be formed in the non-display area (DA) outside the display area (DA) on one or both sides of the display panel 110 using a gate driver in panel (GIP) method. Alternatively, the gate driver may be manufactured as a driving chip, mounted on a flexible film, and attached to the non-display area (DA) outside one or both sides of the display area (DA) of the display panel 110 using a TAB (tape automated bonding) method. It may be possible.

The source drive IC 140 receives digital video data and source control signals from the timing control unit 170. The source drive IC 140 converts digital video data into analog data voltages according to the source control signal and supplies them to the data lines. When the source drive IC 140 is manufactured as a driving chip, it may be mounted on the flexible film 150 using a chip on film (COF) or chip on plastic (COP) method.

Pads such as data pads may be formed in the non-display area NDA of the display panel 110. Wires connecting the pads and the source drive IC 140 and wires connecting the pads and the wires of the circuit board 160 may be formed in the flexible film 150. The flexible film 150 is attached to the pads using an anisotropic conducting film, so that the pads and the wiring of the flexible film 150 can be connected.

The circuit board 160 may be attached to the flexible films 150. The circuit board 160 may be equipped with multiple circuits implemented with driving chips. For example, the timing control unit 170 may be mounted on the circuit board 160. The circuit board 160 may be a printed circuit board or a flexible printed circuit board.

The timing control unit 170 receives digital video data and timing signals from an external system board through a cable of the circuit board 160. The timing control unit 170 generates a gate control signal for controlling the operation timing of the gate driver and a source control signal for controlling the source drive ICs 140 based on the timing signal. The timing control unit 170 supplies a gate control signal to the gate driver and a source control signal to the source drive ICs 140.

Embodiment 1

FIG. 3 is a plan view schematically showing the first substrate of the display panel according to the first embodiment of the present invention, FIG. 4 is a cross-sectional view showing an example of II-I of FIG. 3, and FIG. 5 is of II-II of FIG. 3. This is a cross-sectional view showing an example. FIG. 6 is a plan view schematically showing an example of a first sub-pixel and a second sub-pixel, and FIG. 7 is a plan view showing a modified example of FIG. 6 . FIG. 8 is a plan view schematically showing an example of a third sub-pixel, and FIG. 9 is a plan view showing a modified example of FIG. 8. FIG. 10 is an enlarged view showing an example of area A of FIG. 4. FIG. 11 is a cross-sectional view showing an example of line III-III in FIG. 3, and FIG. 12 is a cross-sectional view showing an example of line IV-IV of FIG. 3.

3 to 12, the display panel 110 according to the first embodiment of the present invention includes a first substrate 111, a light blocking layer 210, a first insulating film 220, and a driving thin film transistor 230. , first connection electrodes 241, 242, 360, second connection electrode 250, second insulating film 260, planarization film 270, shielding patterns 281, 282, 283, first electrode 311, 312 and 313, a bank 315, a first light emitting layer (321, 322, 323), a second electrode (331, 332, 333), a second light emitting layer (340), and a third electrode (350).

The first substrate 111 may be made of glass or plastic, but is not necessarily limited thereto, and may be made of a semiconductor material such as a silicon wafer. The first substrate 111 may be made of a transparent material or an opaque material.

The first substrate 111 is divided into a display area (DA) and a non-display area (NDA). The display area DA of the first substrate 111 may be provided with a first sub-pixel (P1), a second sub-pixel (P2), and a third sub-pixel (P3). The first sub-pixel (P1) may be configured to emit red light, the second sub-pixel (P2) may be configured to emit green light, and the third sub-pixel (P3) may be configured to emit blue light, but are not necessarily limited thereto. That is not the case. The display area DA of the substrate 111 may further include a fourth sub-pixel that emits white (W) light. Additionally, the arrangement order of each sub-pixel (P1, P2, and P3) can be changed in various ways.

The display device according to the first embodiment of the present invention may be configured with a so-called bottom emission method in which the emitted light is emitted downward, but is not necessarily limited to this. When the display device according to the first embodiment of the present invention is made of a bottom emission method, the first substrate 111 may be made of a transparent material. Meanwhile, when the display device according to the first embodiment of the present invention is made of a top emission method in which the emitted light is emitted upward, the first substrate 111 may be made of an opaque material as well as a transparent material. It may be possible.

Circuit elements including various signal lines, thin film transistors 230, and capacitors are provided on the first substrate 111 for each sub-pixel (P1, P2, and P3). Signal lines may include gate lines, data lines, power lines, and reference lines.

When a gate signal is input to the gate line, the thin film transistor 230 supplies a predetermined voltage to the first electrodes 311, 312, and 313 according to the data voltage of the data line. This thin film transistor 230 includes an active layer, a gate electrode, a source electrode, and a drain electrode.

An active layer is formed on the first substrate 111. The active layer may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. As shown in FIG. 4, a light blocking layer 210 may be formed between the first substrate 111 and the active layer to block external light incident on the active layer. When the light blocking layer 210 is made of a metal material, the first insulating film 220 may be formed between the active layer and the light blocking layer 210.

A gate insulating film may be formed on the active layer. The gate insulating film may be formed of an inorganic film, for example, a silicon oxide film, a silicon nitride film, or a multilayer thereof.

A gate electrode may be formed on the gate insulating film. The gate electrode is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. It may be a single layer or multiple layers, but is not limited thereto.

An interlayer insulating film may be formed on the gate electrode. The interlayer insulating film may be formed of an inorganic film, for example, a silicon oxide film, a silicon nitride film, or a multilayer thereof.

A source electrode and a drain electrode may be formed on the interlayer insulating film. Each of the source electrode and drain electrode may be connected to the active layer through a contact hole penetrating the gate insulating film and the interlayer insulating film. Each of the source electrode and drain electrode is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a single layer or a multi-layer made of an alloy thereof, but is not limited thereto.

The first connection electrodes 241, 242, and 360 and the second connection electrode 250 are formed on the first substrate 111.

The first connection electrodes 241, 242, and 360 electrically connect the second electrodes 331, 332 and the third electrode 350 of the first sub-pixel (P1) and the second sub-pixel (P2), respectively. More specifically, the first connection electrodes 241, 242, and 360 may include a first power line 241, a second power line 242, and an auxiliary power line 360.

The auxiliary power line 360 extends from the non-display area NDA in the first direction (X-axis direction). As shown in FIGS. 11 and 12, a portion of the auxiliary power line 360 is exposed without being covered by the first insulating film 220, the second insulating film 260, and the planarization film 270, and in the exposed area It can be connected to the third electrode 350.

This auxiliary power line 360 may be formed in the same layer as the light blocking layer 210 and made of the same material, but is not necessarily limited thereto. The auxiliary power line 360 may be formed of the same material on the same layer as any one of the active layer, gate electrode, source electrode, and drain electrode of the thin film transistor 230.

The first power line 241 is disposed on one side of the first sub-pixel P1 in the display area DA and is connected to the second electrode 331 of the first sub-pixel P1. 4 to 7 show that the first power line 241 is disposed between the first sub-pixel (P1) and the third sub-pixel (P3), but the present invention is not necessarily limited to this. The first power line 241 may be disposed between the first sub-pixel (P1) and the second sub-pixel (P2).

The first power line 241 may extend from the display area DA in the second direction (Y-axis direction). The plurality of first sub-pixels P1 may be arranged along the second direction and parallel to the first power line 241. In this case, the first power line 241 is connected to the second electrode 331 of all of the plurality of first sub-pixels (P1) arranged in parallel, or of some of the plurality of first sub-pixels (P1). It can be connected to the second electrode 331.

Meanwhile, the plurality of first sub-pixels P1 may be alternately arranged with the plurality of second sub-pixels P2 along the second direction. In this case, the first power line 241 is connected to the second electrode 331 of all of the plurality of first sub-pixels (P1), or the second electrode (331) of some of the plurality of first sub-pixels (P1). 331) can be accessed. Alternatively, the first power line 241 is connected to the second electrodes 331 and 332 of both the plurality of first sub-pixels P1 and the plurality of second pixels P2, or is connected to the plurality of first sub-pixels (P1) and the second electrodes 331 and 332 of all of the plurality of second pixels (P2). P1) and some of the second electrodes 331 and 332 of the plurality of second pixels P2.

One end of the first power line 241 is connected to the auxiliary power line 360. The first power line 241 may be connected to the auxiliary power line 360 through a contact hole as shown in FIG. 11, but is not necessarily limited thereto.

This first power line 241 may be formed of the same material in the same layer as any one of the active layer, gate electrode, source electrode, and drain electrode of the thin film transistor 230.

As described above, the second electrode 331 and the third electrode 350 of the first sub-pixel P1 are electrically connected to each other through the first power line 241 and the auxiliary power line 360. That is, when a low potential voltage is applied to the third electrode 350, the same low potential voltage as that of the third electrode 350 is applied to the second electrode 331 of the first sub-pixel (P1).

The second power line 242 is disposed on one side of the second sub-pixel P2 in the display area DA and is connected to the second electrode 332 of the second sub-pixel P2. 4 to 7 show that the second power line 242 is disposed between the first sub-pixel (P1) and the second sub-pixel (P2), but the present invention is not necessarily limited thereto. The second power line 242 may be disposed between the second sub-pixel (P2) and the third sub-pixel (P3).

The second power line 242 may be disposed in the display area DA and extend in a second direction (Y-axis direction). The plurality of second sub-pixels P2 may be arranged along the second direction and parallel to the second power line 242. In this case, the second power line 242 is connected to the second electrodes 332 of all of the plurality of second sub-pixels (P2) arranged in parallel, or of some of the plurality of second sub-pixels (P2). It can be connected to the second electrode 332.

Meanwhile, the plurality of second sub-pixels P2 may be alternately arranged with the plurality of first sub-pixels P1 along the second direction. In this case, the second power line 242 is connected to the second electrode 332 of all of the plurality of second sub-pixels P2, or the second electrode of some of the plurality of second sub-pixels P2 ( 332) can be accessed. Alternatively, the second power line 242 is connected to the second electrodes 331 and 332 of both the plurality of first sub-pixels P1 and the plurality of second pixels P2, or is connected to the plurality of first sub-pixels (P1) and the second electrodes 331 and 332 of all of the plurality of second pixels (P2). P1) and some of the second electrodes 331 and 332 of the plurality of second pixels P2.

One end of the second power line 242 is connected to the auxiliary power line 360. The second power line 242 may be connected to the auxiliary power line 360 through a contact hole as shown in FIG. 11, but is not necessarily limited thereto.

This second power line 242 may be formed of the same material on the same layer as any one of the active layer, gate electrode, source electrode, and drain electrode of the thin film transistor 230.

As described above, the second sub-pixel P2 has the second electrode 332 and the third electrode 350 electrically connected to each other through the second power line 242 and the auxiliary power line 360. That is, when a low potential voltage is applied to the third electrode 350, the same low potential voltage as that of the third electrode 350 is applied to the second electrode 332 of the second sub-pixel P2.

The second connection electrode 250 electrically connects the first electrode 313 of the third sub-pixel (P3) and the second electrode 333 of the third sub-pixel (P3).

The second connection electrode 250 is disposed on one side of the third sub-pixel P3 in the display area DA, and connects the first electrode 313 of the third sub-pixel P3 and the third sub-pixel P3. It is connected to the second electrode 333.

4, 5, and 8 show that the second connection electrode 250 is disposed between the second sub-pixel P2 and the third sub-pixel P3, but the present invention is not limited thereto. The second connection electrode 250 may be disposed between the third sub-pixel (P3) and the first sub-pixel (P1).

Additionally, in FIGS. 4, 5, and 8, the second connection electrode 250 is shown as being disposed only on one side of the third sub-pixel P3, but the present invention is not necessarily limited thereto. The second connection electrode 250 may be disposed on multiple sides of the third sub-pixel P3. For example, when the third sub-pixel P3 includes four sides on a plane, the second connection electrode 250 may be disposed on all four sides of the third sub-pixel P3 as shown in FIG. 9. It may be possible. That is, the second connection electrode 250 may be disposed on at least one of the four sides of the third sub-pixel P3.

The second connection electrode 250 may be patterned to correspond to each of the plurality of third sub-pixels P3. At this time, the second connection electrodes 250 formed to correspond to each of the plurality of third sub-pixels P3 are spaced apart as shown in FIG. 3 so as not to be electrically connected to each other. One third sub-pixel (P3) may be connected to one second connection electrode 251, and another third sub-pixel (P3) may be connected to another second connection electrode 252. At this time, one second connection electrode 251 and the other second connection electrode 252 may be patterned and spaced apart so as not to be electrically connected to each other.

This second connection electrode 250 may be formed of the same material on the same layer as any one of the active layer, gate electrode, source electrode, and drain electrode of the thin film transistor 230.

As described above, the first electrode 313 and the second electrode 333 of the third sub-pixel P3 are electrically connected through the second connection electrode 250. That is, when the third high potential voltage is applied to the first electrode 313 of the third sub-pixel (P3), the second electrode 333 of the third sub-pixel (P3) A third high potential voltage equal to that of the first electrode 313 is applied.

The second insulating film 260 is formed on the thin film transistor 230, the first connection electrodes 241, 242, and 360, and the second connection electrode 250 to protect the thin film transistor 230. The second insulating film 260 covers the thin film transistor 230 and exposes a portion of the first connection electrodes 241, 242, 360 and the second connection electrode 250.

More specifically, the second insulating film 260 includes opening areas OA1, OA2, OA3, and OA4 that expose portions of the first connection electrodes 241, 242, and 360 and the second connection electrode 250.

The second insulating layer 260 may include a first opening area OA1 exposing a portion of the first power line 241 as shown in FIGS. 4 and 5 . The first opening area OA1 may be formed along the first power line 241 . At this time, the first opening area OA1 may be formed as one or more patterns having a predetermined length in the second direction (Y-axis direction) on one first power line 241.

Additionally, the second insulating layer 260 may include a second opening area OA2 exposing a portion of the second power line 242 as shown in FIGS. 4 and 5 . The second opening area OA2 may be formed along the second power line 242 . At this time, the second opening area OA2 may be formed as one or more patterns having a predetermined length in the second direction (Y-axis direction) on one second power line 242.

Additionally, the second insulating layer 260 may include a third opening area OA3 exposing a portion of the second connection electrode 250, as shown in FIGS. 4 and 5 . The third opening area OA3 may be formed to surround the third sub-pixel P3. Accordingly, the third opening area OA3 exposes a portion of the second connection electrode 250 in the area where the second connection electrode 250 is formed, and exposes a portion of the second connection electrode 250 in the area where the second connection electrode 250 is not formed. The insulating film 220 is exposed.

Additionally, the second insulating layer 260 may include a fourth opening area OA4 exposing a portion of the auxiliary power line 360, as shown in FIGS. 11 and 12 . The auxiliary power line 360 is partially exposed by the first insulating film 220, and the fourth opening area OA4 may be formed on the exposed auxiliary power line 360.

This second insulating layer 260 may be formed of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, or a multilayer thereof.

The planarization film 270 is formed on the second insulating film 260 to flatten the level difference caused by the thin film transistor 230. At this time, the planarization film 270 is not formed on the opening areas OA1, OA2, OA3, and OA4 of the second insulating film 260. Accordingly, a portion of the first connection electrodes 241, 242, and 360 and the second connection electrode 250 may still be exposed.

The planarization film 270 may have a smaller formation area than the second insulating film 260 . Accordingly, the planarization film 270 may expose a portion of the second insulating film 260. At this time, the second insulating film 260 may be exposed without being covered by the planarization film 270 in areas adjacent to the opening areas OA1, OA2, OA3, and OA4.

This planarization film 270 may be formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. You can.

The first electrodes 311, 312, and 313 are patterned for each sub-pixel (P1, P2, and P3) on the planarization film 270. One first electrode 311 is formed in the first sub-pixel (P1), another first electrode 312 is formed in the second sub-pixel (P2), and another first electrode 312 is formed in the third sub-pixel (P3). Another first electrode 313 is formed.

The first electrodes 311, 312, and 313 are connected to the source or drain electrode of the thin film transistor 230 through contact holes (CH1, CH2, CH3) penetrating the second insulating film 260 and the planarization film 270. do. The first electrode 311 of the first sub-pixel P1 is connected to the source electrode or drain electrode of the thin film transistor 230 through the contact hole CH1, and a first high potential voltage is applied. The first electrode 312 of the second sub-pixel P2 is connected to the source electrode or drain electrode of the thin film transistor 230 through the contact hole CH2, and a second high potential voltage is applied. The first electrode 313 of the third sub-pixel P3 is connected to the source electrode or drain electrode of the thin film transistor 230 through the contact hole CH3, and a third high potential voltage is applied.

Meanwhile, the first electrode 313 of the third sub-pixel P3 is connected to the second connection electrode 250 through the contact hole CH4 penetrating the second insulating film 260.

The first electrodes 311, 312, and 313 may be made of a transparent metal material, a translucent metal material, or a highly reflective metal material. When the display device 100 is made of a bottom-emitting type, the first electrodes 311, 312, and 313 are made of a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or magnesium (Mg). ), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the display device 100 is made of a top-emitting type, the first electrodes 311, 312, and 313 have a stacked structure of aluminum and titanium (Ti/Al/Ti) or a stacked structure of aluminum and ITO (ITO/Al/ITO). ), Ag alloy, and a laminated structure of Ag alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). These first electrodes 311, 312, and 313 may be anode electrodes.

The covering patterns 281, 282, and 283 are formed on the second insulating layer 260 to cover portions of the opening areas OA1, OA2, and OA3 of the second insulating layer 260. The blocking patterns 281, 282, and 283 include a first blocking pattern 281, a second blocking pattern 282, and a third blocking pattern 283.

The first blocking pattern 281 is formed on the second insulating film 260 that is exposed and not covered by the planarization film 270, and is formed on the first opening area OA1 exposing a portion of the first power line 241. It includes a protrusion 281a that protrudes to partially cover the part. At this time, the protrusion 281a of the first blocking pattern 281 is spaced apart from the first power line 241 to form a space between it and the first power line 241.

The first blocking pattern 281 is formed close to a sub-pixel disposed adjacent to the first sub-pixel P1 with the first opening area OA1 in between. The first opening area OA1 exposing the first power line 241 may be disposed between the first sub-pixel P1 and the third sub-pixel P3, but is not necessarily limited thereto.

When the first opening area OA1 of the second insulating layer 260 is disposed between the third sub-pixel P3 and the first sub-pixel P1, the first blocking pattern 281 has the protrusion 281a 3 The sub-pixel P3 may protrude in a direction toward the first opening area OA1. Accordingly, a portion of the first opening area OA1 adjacent to the third sub-pixel P3 is covered by the first blocking pattern 281, and the first power line 241 is also covered by the first blocking pattern 281. covered by The remaining area of the first opening area OA1 adjacent to the first sub-pixel P1 still exposes the first power line 241.

The first blocking pattern 281 may be formed along the first power line 241 like the first opening area OA1. At this time, the first blocking pattern 281 may be formed as a plurality of patterns with a predetermined length in the second direction (Y-axis direction) on one first power line 241, as shown in FIG. It is not necessarily limited to this. As shown in FIG. 7 , the first blocking pattern 281 may be formed as a single line pattern extending in the second direction (Y-axis direction) on one first power line 241.

Meanwhile, the first blocking pattern 281 may be formed of the same material in the same layer as the first electrodes 311, 312, and 313, but is not necessarily limited thereto.

The first blocking pattern 281 may be formed of the same material in the same layer as the first electrodes 311, 312, and 313, as shown in FIGS. 4 and 5. At this time, the first blocking pattern 281 may be formed to be spaced apart from the first electrodes 311, 312, and 313.

When the first opening area OA1 of the second insulating layer 260 is disposed between the third sub-pixel P3 and the first sub-pixel P1, the first blocking pattern 281 is located between the third sub-pixel P3 ) is spaced apart from the first electrode 313 of the third sub-pixel P3 and is not electrically connected to the first electrode 313 of the third sub-pixel P3. The first blocking pattern 281 may be formed on the planarization film 270 as well as the second insulating film 260 that is exposed and not covered by the planarization film 270 .

In this case, the display device forms the first blocking pattern 281 in the same layer and with the same material as the first electrodes 311, 312, and 313, so that the first blocking pattern 281 is formed without adding a separate process. is formed

However, it is not necessarily limited to this, and the first blocking pattern 281 may be formed on a different layer from the first electrodes 311, 312, and 313. The first blocking pattern 281 may be formed between the second insulating film 260 and the planarization film 270.

The second blocking pattern 282 is formed on the second insulating film 260 that is exposed and not covered by the planarization film 270, and is formed on the second opening area OA2 exposing a portion of the second power line 242. It includes a protrusion 282a that protrudes to partially cover the part. At this time, the protrusion 282a of the second blocking pattern 282 is spaced apart from the second power line 242 to form a space between the second power line 242 and the second power line 242 .

The second blocking pattern 282 is formed close to the sub-pixel disposed adjacent to the second sub-pixel P2 with the second opening area OA2 in between. The second opening area OA2 exposing the second power line 242 may be disposed between the first sub-pixel P1 and the second sub-pixel P2, but is not necessarily limited thereto.

When the second opening area OA2 of the second insulating layer 260 is disposed between the first sub-pixel P1 and the second sub-pixel P2, the second blocking pattern 282 has the protrusion 282a 1 The sub-pixel P1 may protrude in a direction toward the second opening area OA2. Accordingly, a portion of the second opening area OA2 adjacent to the first sub-pixel P1 is covered by the second blocking pattern 282, and the second power line 242 is also covered by the second blocking pattern 282. covered by The remaining area of the second opening area OA2 adjacent to the second sub-pixel P12 still exposes the second power line 242.

The second blocking pattern 282 may be formed along the second power line 242 like the second opening area OA2. At this time, the second blocking pattern 282 may be formed as a plurality of patterns with a predetermined length in the second direction (Y-axis direction) on one second power line 242, as shown in FIG. 6. It is not necessarily limited to this. As shown in FIG. 7 , the second blocking pattern 282 may be formed as a single line pattern extending in the second direction (Y-axis direction) on one second power line 242.

Meanwhile, the second shielding pattern 282 may be formed of the same material in the same layer as the first electrodes 311, 312, and 313, but is not necessarily limited thereto.

The second blocking pattern 282 may be formed of the same material in the same layer as the first electrodes 311, 312, and 313, as shown in FIGS. 4 and 5. At this time, the second blocking pattern 282 may be formed to be spaced apart from the first electrodes 311, 312, and 313.

When the second opening area OA2 of the second insulating layer 260 is disposed between the first sub-pixel P1 and the second sub-pixel P2, the second blocking pattern 282 is located between the first sub-pixel P1 and the second opening area OA2. ) is spaced apart from the first electrode 311 of the first sub-pixel P1 and is not electrically connected to the first electrode 311 of the first sub-pixel P1. The second blocking pattern 282 may be formed on the planarization film 270 as well as the second insulating film 260 that is exposed and not covered by the planarization film 270 .

In this case, the display device forms the second blocking pattern 282 in the same layer as the first electrodes 311, 312, and 313 with the same material, so that the second blocking pattern 282 is formed without adding a separate process. is formed

However, it is not necessarily limited to this, and the second shielding pattern 282 may be formed on a different layer from the first electrodes 311, 312, and 313. The second shielding pattern 282 may be formed between the second insulating film 260 and the planarization film 270.

The third shielding pattern 283 is formed on the second insulating film 260 that is exposed and not covered by the planarization film 270, and is formed on the third opening area OA3 exposing a portion of the second connection electrode 250. It includes a protrusion 283a that protrudes to partially cover the part. At this time, the protrusion 283a of the third shielding pattern 283 is spaced apart from the second connection electrode 250 to form a space between the second connection electrode 250 and the second connection electrode 250 .

The third blocking pattern 283 is formed close to a sub-pixel disposed adjacent to the third sub-pixel P3 with the third opening area OA3 in between. The third opening area OA3 exposing the second connection electrode 250 is between the first sub-pixel P1 and the third sub-pixel P3 and between the second sub-pixel P2 and the third sub-pixel P3. It may be placed in between, but is not necessarily limited to this.

When the third opening area OA3 of the second insulating film 260 is disposed between the first sub-pixel P1 and the third sub-pixel P3, the third blocking pattern 283 has the protrusion 283a. 1 The sub-pixel P1 may protrude in a direction toward the third opening area OA3. Accordingly, a portion of the third opening area OA3 adjacent to the first sub-pixel P1 is covered by the third blocking pattern 283, and the second connection electrode 250 or the first insulating film 220 is also covered. It is covered by the third blocking pattern 283. The remaining area of the third opening area OA2 adjacent to the third sub-pixel P3 still exposes the second connection electrode 250 or the first insulating layer 220.

Additionally, when the third opening area OA3 of the second insulating film 260 is disposed between the second sub-pixel P2 and the third sub-pixel P3, the third blocking pattern 283 has a protrusion 283a. may protrude from the second sub-pixel P2 in a direction toward the third opening area OA3. Accordingly, a portion of the third opening area OA3 adjacent to the second sub-pixel P2 is covered by the third blocking pattern 283, and the second connection electrode 250 or the first insulating film 220 is also covered. It is covered by the third blocking pattern 283. The remaining area of the third opening area OA2 adjacent to the third sub-pixel P3 still exposes the second connection electrode 250 or the first insulating layer 220.

As shown in FIGS. 8 and 9 , the third blocking pattern 283 may be formed to surround the third sub-pixel P3 like the third opening area OA3. The second electrode 333 of the third sub-pixel (P3) is connected to the second electrode 331 of the first sub-pixel (P1) and the second electrode of the second sub-pixel (P2) by the third blocking pattern 283. It can be disconnected from (332). In the display device according to the first embodiment of the present invention, the third blocking pattern 283 is formed to surround the third sub-pixel (P3), so that the second electrode 333 of the third sub-pixel (P3) is connected to the first sub-pixel (P3). The second electrode 331 of the pixel P1 and the second electrode 332 of the second sub-pixel P2 are not electrically connected to each other.

Meanwhile, the third shielding pattern 283 may be formed of the same material in the same layer as the first electrodes 311, 312, and 313, but is not necessarily limited thereto.

The third blocking pattern 283 may be formed of the same material in the same layer as the first electrodes 311, 312, and 313, as shown in FIGS. 4 and 5. At this time, the third shielding pattern 283 may be formed to be spaced apart from the first electrodes 311, 312, and 313.

When the third opening area OA3 of the second insulating layer 260 is disposed between the first sub-pixel P1 and the third sub-pixel P3, the third blocking pattern 283 is located between the first sub-pixel P1 and P3. ) is spaced apart from the first electrode 311 of the first sub-pixel P1 and is not electrically connected to the first electrode 311 of the first sub-pixel P1. The third shielding pattern 283 may be formed on the planarization film 270 as well as the second insulating film 260 that is exposed and not covered by the planarization film 270 .

Additionally, when the third opening area OA3 of the second insulating film 260 is disposed between the second sub-pixel P2 and the third sub-pixel P3, the third blocking pattern 283 is located between the second sub-pixel P2 and the third sub-pixel P3. It is disposed to be spaced apart from the second electrode 312 of (P2) and is not electrically connected to the second electrode 312 of the second sub-pixel (P2). The third shielding pattern 283 may be formed on the planarization film 270 as well as the second insulating film 260 that is exposed and not covered by the planarization film 270 .

In this case, the display device forms the third blocking pattern 283 in the same layer as the first electrodes 311, 312, and 313 with the same material, so that the third blocking pattern 283 is formed without adding a separate process. is formed

However, it is not necessarily limited to this, and the third shielding pattern 283 may be formed on a different layer from the first electrodes 311, 312, and 313. The third shielding pattern 283 may be formed between the second insulating film 260 and the planarization film 270.

The bank 315 may be formed on the planarization film 270 to cover the ends of the first electrodes 311, 312, and 313. Accordingly, the problem of lowering luminous efficiency due to current concentration at the ends of the first electrodes 311, 312, and 313 can be prevented.

Meanwhile, the bank 315 is not formed on the opening areas OA1, OA2, OA3, and OA4 of the second insulating film 260. Accordingly, a portion of the first connection electrodes 241, 242, and 360 and the second connection electrode 250 may still be exposed.

Additionally, the bank 315 may also be formed on the blocking patterns 281, 282, and 283. At this time, the bank 315 may be formed so that the protrusions 281a, 282a, and 283a of each of the blocking patterns 281, 282, and 283 are exposed without being covered.

When the bank 315 is formed to cover the protrusions 281a, 282a, and 283a of each of the blocking patterns 281, 282, and 283, the first light emitting layer 321 of each of the sub-pixels P1, P2, and P3 322, 323) can be connected to each other without being disconnected. Additionally, the second electrodes 331, 332, and 333 of each of the sub-pixels P1, P2, and P3 may be connected to each other without being disconnected. Accordingly, the second electrode 331 of the first sub-pixel (P1) is not connected to the first power line 241, and the second electrode 332 of the second sub-pixel (P2) is not connected to the second power line (241). 242), and a problem may occur in which the second electrode 333 of the third sub-pixel P3 cannot be connected to the second connection electrode 250.

In the display device according to the first embodiment of the present invention, the bank 315 is formed to expose the protrusions 281a, 282a, and 283a of each of the blocking patterns 281, 282, and 283 without covering them to prevent this problem from occurring. It has to be.

The bank 315 defines a light-emitting area in each of the plurality of sub-pixels (P1, P2, and P3). That is, the exposed area of the first electrodes 311, 312, and 313 where the bank 315 is not formed in each sub-pixel (P1, P2, and P3) becomes the light emitting area. The bank 315 may be made of a relatively thin inorganic insulating film, but may also be made of a relatively thick organic insulating film.

The first light emitting layers 321, 322, and 323 are formed on the first electrodes 311, 312, and 313. The first light emitting layers 321, 322, and 323 may be formed on the bank 315. The first light emitting layers 321, 322, and 323 may include a hole transporting layer, a light emitting layer, and an electron transporting layer. In this case, holes and electrons in the first light-emitting layers 321, 322, and 323 move to the light-emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light-emitting layer to emit light in a predetermined color.

The first light-emitting layer (321, 322, 323) may be any one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but must be It is not limited to this.

The first light emitting layers 321, 322, and 323 are disconnected between the first sub-pixel (P1), the second sub-pixel (P2), and the third sub-pixel (P3). Masking patterns 281, 282, and 283 are provided between the first sub-pixel (P1), the second sub-pixel (P2), and the third sub-pixel (P3). The first light emitting layers 321, 322, and 323 may be separated from each other by the blocking patterns 281, 282, and 283.

More specifically, the first light emitting layers 321, 322, and 323 may be separated between the first sub-pixel (P1) and the second sub-pixel (P2) by the second blocking pattern 282. When the first light-emitting layer 321, 322, and 323 is deposited on the entire surface without a mask, the first light-emitting layer 321 deposited on the first sub-pixel P1 has a second blocking pattern (as shown in FIGS. 4 and 10). Due to the step between the protrusion 282a of the second power line 242 and the protrusion 282a of the second shielding pattern 282, the second power line 242 may be broken on the protrusion 282a of the second shielding pattern 282. The first light emitting layer 322 deposited on the second sub-pixel P2 is formed in the space between the protrusion 282a of the second blocking pattern 282 and the second power line 242, as shown in FIGS. 4 and 10. may flow into and be formed under the protrusion 282a of the second blocking pattern 282.

In the display device according to the first embodiment of the present invention, it is preferable that the first light emitting layer 321 of the first sub-pixel (P1) and the first light emitting layer 322 of the second sub-pixel (P2) are disconnected from each other without contacting each other. do. For this reason, when the second electrodes 331, 332, and 333 are entirely deposited on the first light emitting layers 321, 322, and 323, the second electrode 332 deposited on the second sub-pixel P2 is the second electrode 332. A space for inflow can be secured between the protrusion 282a of the blocking pattern 282 and the first light emitting layer 322 of the second sub-pixel P2.

Additionally, the first light emitting layers 321, 322, and 323 may be separated between the second sub-pixel P2 and the third sub-pixel P3 by the third blocking pattern 283. When the first light-emitting layer 321, 322, and 323 is deposited on the entire surface without a mask, the first light-emitting layer 322 deposited on the second sub-pixel P2 has a third blocking pattern (as shown in FIGS. 4 and 10). Due to the step between the protrusion 283a of the third shielding pattern 283 and the second connection electrode 250, the protrusion 283a of the third shielding pattern 283 may be broken. The first light emitting layer 323 deposited on the third sub-pixel P3 is formed in the space between the protrusion 283a of the third blocking pattern 283 and the second connection electrode 250, as shown in FIGS. 4 and 10. may flow into and be formed under the protrusion 283a of the third blocking pattern 283.

In the display device according to the first embodiment of the present invention, it is preferable that the first light emitting layer 322 of the second sub-pixel (P2) and the first light emitting layer 323 of the third sub-pixel (P3) are disconnected from each other without contacting each other. do. For this reason, when the second electrodes 331, 332, and 333 are entirely deposited on the first light emitting layers 321, 322, and 323, the second electrode 333 deposited on the third sub-pixel P3 is the third electrode 333. A space for inflow can be secured between the protrusion 283a of the blocking pattern 283 and the first light emitting layer 323 of the third sub-pixel P3.

Additionally, the first light emitting layers 321, 322, and 323 may be disconnected between the first sub-pixel (P1) and the third sub-pixel (P3) by the third blocking pattern 283 and the first blocking pattern 281. there is. As shown in FIG. 5 , a third blocking pattern 283 and a first blocking pattern 281 may be formed to be spaced apart between the first sub-pixel (P1) and the third sub-pixel (P3). At this time, the first blocking pattern 281 includes a protrusion 281a that protrudes from the third sub-pixel P3 toward the first sub-pixel P1 and covers a portion of the first opening area OA1. The third blocking pattern 283 includes a protrusion 283a that protrudes from the first sub-pixel P1 toward the third sub-pixel P3 and blocks a portion of the third opening area OA3.

When the first light-emitting layer 321, 322, and 323 is deposited on the entire surface without a mask, the first light-emitting layer 323 deposited on the third sub-pixel P3 has a third blocking pattern (as shown in FIGS. 5 and 10). 283) may flow into the space between the protrusion 283a and the first insulating film 220, and may be formed under the protrusion 283a of the third shielding pattern 283. The first light emitting layer 321 deposited on the first sub-pixel P1 is formed in the space between the protrusion 281a of the first blocking pattern 281 and the first power line 241, as shown in FIGS. 5 and 10. may flow into and be formed under the protrusion 281a of the first blocking pattern 281.

The second electrodes 331, 332, and 333 are formed on the first light emitting layers 321, 322, and 323. The second electrodes 331, 332, and 333 are disconnected between the first sub-pixel (P1), the second sub-pixel (P2), and the third sub-pixel (P3). Masking patterns 281, 282, and 283 are provided between the first sub-pixel (P1), the second sub-pixel (P2), and the third sub-pixel (P3). The second electrodes 331, 332, and 333 may be separated from each other by the shielding patterns 281, 282, and 283.

More specifically, the second electrodes 331, 332, and 333 may be separated between the first sub-pixel (P1) and the second sub-pixel (P2) by the second blocking pattern 282. When the second electrodes 331, 332, and 333 are deposited on the entire surface, the second electrode 331 deposited on the first sub-pixel P1 has a second covering pattern 282 as shown in FIGS. 4 and 10. The second shielding pattern 282 may be broken on the protrusion 282a due to a step difference between the protrusion 282a and the second power line 242.

The second electrode 332 deposited on the second sub-pixel P2 is located in the space between the protrusion 282a of the second blocking pattern 282 and the first light emitting layer 322, as shown in FIGS. 4 and 10. It may flow in and be formed under the protrusion 282a of the second blocking pattern 282. At this time, the second electrode 332 of the second sub-pixel P2 may be deposited under the protrusion 282a of the second shielding pattern 282 to have a larger area than the first light emitting layer 322. Accordingly, the second electrode 332 of the second sub-pixel P2 may be connected to the second power line 242.

Since the second electrode 332 of the second sub-pixel P2 is connected to the second power line 242, the second electrode 332 and the second sub-pixel P2 are connected to each other through the second power line 242 and the auxiliary power line 360. The three electrodes 350 may be electrically connected. For this reason, when a low potential voltage is applied to the third electrode 350, the same low potential voltage as that of the third electrode 350 may be applied to the second electrode 332 of the second sub-pixel P2. At this time, the second electrode 332 of the second sub-pixel P2 may be a cathode electrode.

4 and 10 show that the second electrode 331 of the first sub-pixel (P1) and the second electrode 332 of the second sub-pixel (P2) are disconnected rather than in contact with each other, but this is not necessarily limited to this. It doesn't work. The second electrodes 331 and 332 of each of the first sub-pixel (P1) and the second sub-pixel (P2) serve as cathode electrodes, and a common voltage may be applied thereto. The second electrodes 331 and 332 of the first sub-pixel (P1) and the second sub-pixel (P2) are formed to be in contact with each other and may be electrically connected to each other.

Additionally, the second electrodes 331, 332, and 333 may be separated between the second sub-pixel P2 and the third sub-pixel P3 by the third blocking pattern 283. When the second electrodes 331, 332, and 333 are deposited on the entire surface, the second electrode 332 deposited on the second sub-pixel P2 has a third covering pattern 283 as shown in FIGS. 4 and 10. The third shielding pattern 283 may be broken on the protrusion 283a due to a step between the protrusion 283a and the first light emitting layer 323.

The second electrode 333 deposited on the third sub-pixel P3 is located in the space between the protrusion 283a of the third blocking pattern 283 and the first light-emitting layer 323, as shown in FIGS. 4 and 10. It may flow in and be formed under the protrusion 283a of the third blocking pattern 283. At this time, the second electrode 333 of the third sub-pixel P3 may be deposited under the protrusion 283a of the third shielding pattern 283 over an area larger than that of the first light emitting layer 323. Accordingly, the second electrode 333 of the third sub-pixel P3 may be connected to the second connection electrode 250.

Since the second electrode 333 of the third sub-pixel P3 is connected to the second connection electrode 250, the second electrode 333 and the first electrode 313 are electrically connected to each other through the second connection electrode 250. It can be connected to . Due to this, when the third high potential voltage is applied to the first electrode 313, the second electrode 333 of the third sub-pixel P3 will be applied with the same third high potential voltage as the first electrode 313. You can. At this time, the second electrode 333 of the third sub-pixel P3 may be an anode electrode.

In the display device according to the first embodiment of the present invention, it is preferable that the second electrode 332 of the second sub-pixel (P2) and the second electrode 333 of the third sub-pixel (P3) are disconnected without contacting each other. do. As previously described, the second electrode 332 of the second sub-pixel P2 is a cathode electrode, and the second electrode 333 of the third sub-pixel P3 is an anode electrode. In this case, when the second electrode 332 of the second sub-pixel (P2) and the second electrode 333 of the third sub-pixel (P3) come into contact, the second electrode 332 of the second sub-pixel (P2) A short circuit occurs between and the second electrode 333 of the third sub-pixel P3, preventing the display device from operating normally.

Additionally, the second electrodes 331, 332, and 333 may be disconnected between the first sub-pixel (P1) and the third sub-pixel (P3) by the third blocking pattern 283 and the first blocking pattern 281. there is.

When the second electrodes 331, 332, and 333 are deposited on the entire surface, the second electrode 333 deposited on the third sub-pixel P3 has a third covering pattern 283 as shown in FIGS. 5 and 10. may flow into the space between the protrusion 283a and the first light emitting layer 323 and be formed under the protrusion 283a of the third blocking pattern 283.

At this time, the second electrode 333 of the third sub-pixel P3 may be deposited under the protrusion 283a of the third shielding pattern 283 over an area larger than that of the first light emitting layer 323. Although FIG. 5 shows that the second connection electrode 250 is not formed between the first sub-pixel (P1) and the third sub-pixel (P3), the present invention is not necessarily limited to this. As shown in FIG. 9, a second connection electrode 250 may be formed between the first sub-pixel (P1) and the third sub-pixel (P3). In this case, the second electrode 333 of the third sub-pixel (P3) may be connected to the second connection electrode 250 between the first sub-pixel (P1) and the third sub-pixel (P3).

The second electrode 331 deposited on the first sub-pixel P1 is located in the space between the protrusion 281a of the first blocking pattern 281 and the first light emitting layer 321, as shown in FIGS. 5 and 10. It may flow in and be formed under the protrusion 281a of the first blocking pattern 281.

At this time, the second electrode 331 of the first sub-pixel P1 may be deposited under the protrusion 281a of the first shielding pattern 281 over an area larger than that of the first light emitting layer 321. Accordingly, the second electrode 331 of the first sub-pixel P1 may be connected to the first power line 241.

Since the second electrode 331 of the first sub-pixel P1 is connected to the first power line 241, the second electrode 331 and the second electrode 331 are connected through the first power line 241 and the auxiliary power line 360. The three electrodes 350 may be electrically connected. For this reason, when a low potential voltage is applied to the third electrode 350, the same low potential voltage as that of the third electrode 350 may be applied to the second electrode 331 of the first sub-pixel (P1). At this time, the second electrode 331 of the first sub-pixel (P1) may be a cathode electrode.

The second electrodes 331, 332, and 333 are made of a transparent metal material (TCO, Transparent Conductive Material) such as ITO or IZO, which can transmit light, or magnesium (Mg), silver (Ag), or magnesium (Mg). It may be formed of a semi-transmissive conductive material such as an alloy of silver (Ag).

The second light emitting layer 340 is formed on the second electrodes 331, 332, and 333. The second light emitting layer 340 may include a hole transporting layer, a light emitting layer, and an electron transporting layer. In this case, holes and electrons in the second light-emitting layer 340 move to the light-emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light-emitting layer to emit light in a predetermined color.

The second light-emitting layer 340 may be any one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but is not necessarily limited thereto. .

However, the second light-emitting layer 340 may emit light of a different color from the first light-emitting layer 321, 322, and 323. When the first light-emitting layers 321, 322, and 323 are light-emitting layers that emit light of a first color, the second light-emitting layer 340 may be a light-emitting layer that emits light of a second color different from the first color. For example, the first light-emitting layer 321, 322, and 323 may be a yellow light-emitting layer that emits yellow light, and the second light-emitting layer 340 may be a blue light-emitting layer that emits blue light.

Unlike the first emission layers 321, 322, and 323, the second light-emitting layer 340 is connected between the first sub-pixel (P1), the second sub-pixel (P2), and the third sub-pixel (P3). The second light emitting layer 340 may be formed while partially filling the space between the blocking patterns 281, 282, and 283 and the second electrodes 331, 332, and 333. At this time, an air gap AG may be formed in the space not filled with the second light emitting layer 340 between the blocking patterns 281, 282, and 283 and the second electrodes 331, 332, and 333.

The third electrode 350 is formed on the second light emitting layer 340. The third electrode 350 may be made of a transparent metal material, a translucent metal material, or a highly reflective metal material. When the display device 100 is made of a bottom-emitting type, the third electrode 350 has a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), and Ag alloy. , and a laminated structure of Ag alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). When the display device 100 is made of a top-emitting type, the third electrode 350 is made of a transparent conductive material (TCO) such as ITO or IZO, which can transmit light, or magnesium (Mg) or silver ( It may be formed of a semi-transmissive conductive material such as Ag) or an alloy of magnesium (Mg) and silver (Ag). This third electrode 350 may be a cathode electrode.

The display device according to the first embodiment of the present invention is characterized in that only one of the first emission layers 321, 322, and 323 and the second emission layer 340 emits light in each of the sub-pixels P1, P2, and P3.

More specifically, the first light emitting layer 321 of the first sub-pixel P1 emits light. Since the second electrode 331 of the first sub-pixel P1 is connected to the first power line 241, the second electrode 331 and the second electrode 331 are connected through the first power line 241 and the auxiliary power line 360. 3 Electrodes 350 are electrically connected. When a low potential voltage is applied to the third electrode 350, the same low potential voltage as that of the third electrode 350 is applied to the second electrode 331 of the first sub-pixel (P1). Accordingly, the second light emitting layer 340 provided between the second electrode 331 and the third electrode 350 of the first sub-pixel P1 does not emit light.

Meanwhile, when a first high-potential voltage is applied to the first electrode 311 and a low-potential voltage is applied to the second electrode 331, the first sub-pixel P1 is connected to the first electrode 311 and the second electrode 311. The first light emitting layer 321 provided between 331 emits light with a predetermined brightness according to a predetermined current.

The first light emitting layer 322 emits light in the second sub-pixel P2. Since the second electrode 332 of the second sub-pixel P2 is connected to the second power line 242, the second electrode 332 and the second sub-pixel P2 are connected to each other through the second power line 242 and the auxiliary power line 360. 3 Electrodes 350 are electrically connected. When a low potential voltage is applied to the third electrode 350, the same low potential voltage as that of the third electrode 350 is applied to the second electrode 332 of the second sub-pixel P2. Accordingly, the second light emitting layer 340 provided between the second electrode 332 and the third electrode 350 of the second sub-pixel P2 does not emit light.

Meanwhile, when a second high-potential voltage is applied to the first electrode 312 and a low-potential voltage is applied to the second electrode 332, the second sub-pixel P2 is connected to the first electrode 312 and the second electrode. The first light emitting layer 322 provided between 332 emits light with a predetermined brightness according to a predetermined current.

That is, the first sub-pixel (P1) and the second sub-pixel (P2) both emit light of the same color from the first emission layers 321 and 322. The display device according to the first embodiment of the present invention may be further equipped with a color filter (not shown) to emit light of different colors from the first sub-pixel (P1) and the second sub-pixel (P2). .

The color filter (not shown) may include a first color filter arranged to correspond to the first sub-pixel P1 and a second color filter arranged to correspond to the second sub-pixel P2. The first color filter and the second color filter may transmit light of different colors.

For example, the first light-emitting layer 321, 322, and 323 may be a yellow light-emitting layer that emits yellow light. The first color filter may be a red color filter that transmits red light, and the second color filter may be a green color filter that transmits green light. Accordingly, the first sub-pixel (P1) can emit red light, and the second sub-pixel (P2) can emit green light.

This color filter may be placed below the first electrodes 311, 312, and 313 or above the third electrode 350, depending on the light emission method of the display device 100. When the display device 100 is a bottom-emitting type, a color filter may be provided under the first electrodes 311, 312, and 313. When the display device 100 is a top-emitting type, a color filter may be provided on the third electrode 350.

The second light emitting layer 340 emits light in the third sub-pixel P3. Since the second electrode 333 of the third sub-pixel P3 is connected to the second connection electrode 250, the first electrode 313 and the second electrode 333 are electrically connected to each other through the second connection electrode 250. It is connected to When the third high potential voltage is applied to the first electrode 313, the same third high potential voltage as that of the first electrode 313 is applied to the second electrode 333 of the third sub-pixel P3. Accordingly, the first light emitting layer 323 provided between the first electrode 313 and the second electrode 333 of the third sub-pixel P3 does not emit light.

Meanwhile, when the third high-potential voltage is applied to the second electrode 333 and the low-potential voltage is applied to the third electrode 350, the third sub-pixel P3 is connected to the second electrode 333 and the third electrode. The second light emitting layer 340 provided between 350 emits light with a predetermined brightness according to a predetermined current.

For example, the third sub-pixel P3 may be a blue light-emitting layer that emits blue light. In this case, the display device 100 can implement a blue sub-pixel without providing a separate color filter at a position corresponding to the third sub-pixel P3.

As described above, the display device 100 according to the first embodiment of the present invention causes only the first light emitting layers 321, 322, and 323 to emit light in the first sub-pixel (P1) and the second sub-pixel (P2), Only the second light emitting layer 340 may emit light in the third sub-pixel P3. For this reason, the display device 100 according to the first embodiment of the present invention significantly reduces power consumption compared to a case where all the first light-emitting layers 321, 322, 323 and the second light-emitting layer 340 emit light in all sub-pixels. It can be reduced significantly.

In addition, the display device 100 according to the first embodiment of the present invention has the first emission layer 321, 322, 323 and the second emission layer 340 in the sub-pixels P1, P2, and P3 on the front surface without a mask. form Accordingly, the display device 100 according to the first embodiment of the present invention can solve the problem of forming different light-emitting layers in patterns for each sub-pixel (P1, P2, and P3) using a mask.

In addition, the display device 100 according to the first embodiment of the present invention uses the blocking patterns 281, 282, and 283 so that the second electrodes 331, 332, and 333 are connected to the sub-pixels (P1, P2, and P3). Make sure there is a disconnect between them. The display device 100 according to the first embodiment of the present invention forms blocking patterns 281, 282, and 283, and includes a first light emitting layer on the first substrate 111 on which the blocking patterns 281, 282, and 283 are formed. (321, 322, 323) and second electrodes (331, 332, 333) are formed on the front surface without a mask. The first light-emitting layers 321, 322, and 323 and the second electrodes 331, 332, and 333 are separated from the sub-pixels P1, P2, and P3 by the blocking patterns 281, 282, and 283. In particular, the second electrodes 331, 332, and 333 are connected to the first power line 241, the second power line 242, and the first power line 241 below the protrusions 281a, 282a, and 283a of the blocking patterns 281, 282, and 283. It is connected to one of the two connection electrodes 250.

Referring to FIG. 10, the display device 100 according to the first embodiment of the present invention has the second electrodes 331, 332, and 333 disconnected between the sub-pixels P1, P2, and P3, and the second light emitting layer. The thickness T1 of the second insulating film 260 may be designed so that the sub-pixels 340 can be connected without being disconnected between the sub-pixels P1, P2, and P3. At this time, the thickness T1 of the second insulating film 260 is the protrusions 281a, 282a, and 283a of the blocking patterns 281, 282, and 283, the first power line 241, the second power line 242, and the second power line 242. It may correspond to the separation distance between any one of the two connection electrodes 250.

The thickness T1 of the second insulating film 260 is designed to be greater than the sum of the thickness T3 of the first light emitting layer 321, 322, and 323 and the thickness T2 of the second electrodes 331, 332, and 333. You can. Accordingly, the display device 100 according to the first embodiment of the present invention can prevent the second electrodes 331, 332, and 333 from being connected to each other between the sub-pixels (P1, P2, and P3).

The thickness T1 of the second insulating film 260 is the thickness T3 of the first light-emitting layers 321, 322, and 323, the thickness T2 of the second electrodes 331, 332, and 333, and the second light-emitting layer 340. ) can be designed to be smaller than the sum of the thicknesses (T4). Accordingly, the display device 100 according to the first embodiment of the present invention can prevent the second light emitting layer 340 from being disconnected between the sub-pixels P1, P2, and P3.

Meanwhile, in the display device 100 according to the first embodiment of the present invention, the length L1 of the protrusions 281a, 282a, and 283a of the blocking patterns 281, 282, and 283 can be appropriately designed. If the length L1 of the protrusions 281a, 282a, and 283a of the covering patterns 281, 282, and 283 becomes too long, they may sag downward due to their weight. In this case, there is enough space for the first light emitting layer (321, 322, 323) and the second electrode (331, 332, 333) to be formed under the protrusions (281a, 282a, 283a) of the blocking pattern (281, 282, 283). This may not be secured.

On the other hand, if the length L1 of the protrusions 281a, 282a, and 283a of the blocking patterns 281, 282, and 283 is too short, the second electrodes 331, 332, and 333, the first power line 241, and the 2 The contact area with either the power line 242 or the second connection electrode 250 may be reduced. In this case, resistance may increase between the second electrodes 331, 332, and 333 and any one of the first power line 241, the second power line 242, and the second connection electrode 250.

Second embodiment

FIG. 13 is a plan view schematically showing the first substrate of the display panel according to the second embodiment of the present invention, FIG. 14 is a cross-sectional view showing an example of V-V of FIG. 13, and FIG. 15 is a first sub-pixel and This is a plan view schematically showing an example of a second sub-pixel.

13 to 15, the display panel 110 according to the second embodiment of the present invention includes a first substrate 111, a light blocking layer 210, a first insulating film 220, and a driving thin film transistor 230. , first connection electrodes 241, 242, 360, second connection electrode 250, second insulating film 260, planarization film 270, shielding patterns 281, 282, 283, first electrode 311, 312 and 313, a bank 315, a first light emitting layer (321, 322, 323), a second electrode (331, 332, 333), a second light emitting layer (340), and a third electrode (350).

The display panel 110 according to the second embodiment of the present invention is as shown in FIGS. 3 to 12 in that the first power line 241 and the second power line 242 of the first connection electrode are formed integrally. There is a difference from the display panel 110 according to the first embodiment of the present invention. Accordingly, the display panel 110 according to the second embodiment of the present invention has the configurations shown in FIGS. 3 to 12 excluding the first connection electrodes 241, 242, and 360 and the blocking patterns 281, 282, and 283. The configurations of the display panel 110 according to the first embodiment of the present invention are substantially the same. Hereinafter, the first substrate 111, the light blocking layer 210, the first insulating film 220, the driving thin film transistor 230, and the second insulating film 260 of the display panel 110 according to the second embodiment of the present invention. , planarization film 270, first electrodes (311, 312, 313), bank 315, first light emitting layer (321, 322, 323), second electrode (331, 332, 333), second light emitting layer (340) ), and the third electrode 350 will be omitted.

The first connection electrodes 241 , 242 , and 360 and the second connection electrode 250 are formed on the first substrate 111 .

The first connection electrodes 241, 242, and 360 electrically connect the second electrodes 331, 332 and the third electrode 350 of the first sub-pixel (P1) and the second sub-pixel (P2), respectively. More specifically, the first connection electrodes 241, 242, and 360 may include a first power line 241, a second power line 242, and an auxiliary power line 360.

The auxiliary power line 360 extends from the non-display area NDA in the first direction (X-axis direction). A portion of the auxiliary power line 360 is exposed without being covered by the first insulating film 220, the second insulating film 260, and the planarization film 270, and can be connected to the third electrode 350 in the exposed area. .

The first power line 241 is disposed between the first sub-pixel (P1) and the second sub-pixel (P2) in the display area (DA) and is connected to the second electrode 331 of the first sub-pixel (P1). do. The second power line 242 is disposed between the first sub-pixel (P1) and the second sub-pixel (P2) in the display area (DA) and is connected to the second electrode 332 of the second sub-pixel (P2). do. At this time, the display device 100 according to the second embodiment of the present invention is characterized in that the first power line 241 and the second power line 242 are formed integrally.

The first power line 241 and the second power line 242 may extend from the display area DA in a second direction (Y-axis direction). One end of the first power line 241 and the second power line 242 is connected to the auxiliary power line 360. At this time, the first power line 241 and the second power line 242 may be connected to the auxiliary power line 360 through a contact hole, but are not necessarily limited to this.

The first power line 241 and the second power line 242 may be formed of the same material in the same layer as any one of the active layer, gate electrode, source electrode, and drain electrode of the thin film transistor 230.

As described above, the first sub-pixel (P1) is connected to the second electrode 331 and the third electrode 350 through the first power line 241, the second power line 242, and the auxiliary power line 360. This is electrically connected. That is, when a low potential voltage is applied to the third electrode 350, the same low potential voltage as that of the third electrode 350 is applied to the second electrode 331 of the first sub-pixel (P1).

In the second sub-pixel P2, the second electrode 332 and the third electrode 350 are electrically connected through the first power line 241, the second power line 242, and the auxiliary power line 360. . That is, when a low potential voltage is applied to the third electrode 350, the same low potential voltage as that of the third electrode 350 is applied to the second electrode 332 of the second sub-pixel P2.

The covering patterns 281, 282, and 283 are formed on the second insulating layer 260 to cover portions of the opening areas OA1, OA2, and OA3 of the second insulating layer 260. The blocking patterns 281, 282, and 283 include a first blocking pattern 281, a second blocking pattern 282, and a third blocking pattern 283.

The first blocking pattern 281 is provided between the first sub-pixel (P1) and the second sub-pixel (P2). In particular, the first blocking pattern 281 is formed between the first opening area OA1 exposing a part of the first power line 241 and the second opening area OA2 exposing a part of the second power line 242. It is formed on the second insulating film 260 formed in .

The first blocking pattern 281 includes a protrusion 281a that protrudes to cover a portion of the first opening area OA1. At this time, the protrusion 281a of the first blocking pattern 281 is spaced apart from the first power line 241 to form a space between it and the first power line 241.

The protrusion 281a of the first blocking pattern 281 may protrude in a direction from the second sub-pixel P2 toward the first sub-pixel P1. Accordingly, a portion of the first opening area OA1 adjacent to the second sub-pixel P2 is covered by the first blocking pattern 281, and the first power line 241 is also covered by the first blocking pattern 281. covered by The remaining area of the first opening area OA1 adjacent to the first sub-pixel P1 still exposes the first power line 241.

The first blocking pattern 281 may be formed along the first power line 241 like the first opening area OA1. At this time, the first blocking pattern 281 may be formed as a plurality of patterns having a predetermined length in the second direction (Y-axis direction) on the first power line 241, but is not necessarily limited thereto. The first blocking pattern 281 may be formed as a single line pattern extending in the second direction (Y-axis direction) on one first power line 241.

Meanwhile, the first blocking pattern 281 may be formed of the same material in the same layer as the first electrodes 311, 312, and 313, but is not necessarily limited thereto.

The second blocking pattern 282 is provided between the first sub-pixel (P1) and the second sub-pixel (P2). In particular, the second blocking pattern 282 is formed between the first opening area OA1 exposing a part of the first power line 241 and the second opening area OA2 exposing a part of the second power line 242. It is formed on the second insulating film 260 formed in . At this time, in the display device 100 according to the second embodiment of the present invention, the first blocking pattern 281 and the second blocking pattern 282 may be formed integrally.

The second blocking pattern 282 includes a protrusion 282a that protrudes to cover a portion of the second opening area OA2. At this time, the protrusion 282a of the second blocking pattern 282 is spaced apart from the second power line 242 to form a space between the second power line 242 and the second power line 242 .

The protrusion 282a of the second blocking pattern 282 may protrude in a direction from the first sub-pixel P1 to the second sub-pixel P2. Accordingly, a portion of the second opening area OA2 adjacent to the first sub-pixel P1 is covered by the second blocking pattern 282, and the second power line 242 is also covered by the second blocking pattern 282. covered by The remaining area of the second opening area OA2 adjacent to the second sub-pixel P2 still exposes the second power line 242.

The second blocking pattern 282 may be formed along the second power line 242 like the second opening area OA2. At this time, the second blocking pattern 282 may be formed as a plurality of patterns having a predetermined length in the second direction (Y-axis direction) on the second power line 242, but is not necessarily limited thereto. The second blocking pattern 282 may be formed as a single line pattern extending in the second direction (Y-axis direction) on one second power line 242.

Meanwhile, the second shielding pattern 282 may be formed of the same material in the same layer as the first electrodes 311, 312, and 313, but is not necessarily limited thereto.

FIG. 16 is a flowchart for explaining the manufacturing method of the display device according to the first embodiment of the present invention, and FIGS. 17A to 17J are cross-sectional views for explaining the manufacturing method for the display device according to the first embodiment of the present invention. .

First, the thin film transistor 230, the first connection electrodes 241, 242, and 360, and the second connection electrode 250 are formed on the first substrate 111 as shown in FIG. 17A (S1601).

More specifically, a light blocking layer 210 is formed on the first substrate 111. The light blocking layer 210 is intended to block external light incident on the active layer of the thin film transistor 230 to be arranged for each sub-pixel (P1, P2, and P3), and is located at a position corresponding to the active layer of the thin film transistor 230. is formed The light blocking layer 210 may be formed of a metal material. When the light blocking layer 210 is formed of a metal material, the auxiliary power line 360 may be formed on the first substrate 111 on the same layer as the light blocking layer 210 and made of the same material.

Then, the first insulating film 220 is formed on the light blocking layer 210. The first insulating layer 220 may be formed of an inorganic layer, for example, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof.

Then, a thin film transistor 230, a first power line 241, a second power line 242, and a second connection electrode 250 are formed on the first insulating film 220.

An active layer is formed on the first insulating film 220. The active layer may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material.

A gate insulating film may be formed on the active layer. The gate insulating film may be formed of an inorganic film, for example, a silicon oxide film, a silicon nitride film, or a multilayer thereof.

A gate electrode may be formed on the gate insulating film. The gate electrode is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. It may be a single layer or multiple layers, but is not limited thereto.

An interlayer insulating film may be formed on the gate electrode. The interlayer insulating film may be formed of an inorganic film, for example, a silicon oxide film, a silicon nitride film, or a multilayer thereof.

A source electrode and a drain electrode may be formed on the interlayer insulating film. Each of the source electrode and drain electrode may be connected to the active layer through a contact hole penetrating the gate insulating film and the interlayer insulating film. Each of the source electrode and drain electrode is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a single layer or a multi-layer made of an alloy thereof, but is not limited thereto.

Meanwhile, the first power line 241, the second power line 242, and the second connection electrode 250 may be formed of the same material on the same layer as the source electrode and the drain electrode.

Next, the second insulating film 260 is formed as shown in FIG. 17B (S1602).

More specifically, a second insulating film 260 is formed on the thin film transistor 230, the first connection electrodes 241, 242, and 360, and the second connection electrode 250.

The second insulating film 260 may have a contact hole that exposes a portion of the source electrode or drain electrode of the thin film transistor 230, but is not necessarily limited thereto. The contact hole may be formed through a later process.

The second insulating film 260 may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof, but is not limited thereto.

Next, a planarization film 270 is formed as shown in FIG. 17C (S1603).

More specifically, a planarization film 270 is formed on the second insulating film 260. The planarization film 270 is formed on the second insulating film 260 to flatten the level difference caused by the thin film transistor 230. The planarization film 270 is patterned to expose a portion of the second insulating film 260 disposed in the area where the first power line 241, the second power line 242, and the second connection electrode 250 are formed. It can be.

The planarization film 270 may have a contact hole that exposes a portion of the source electrode or drain electrode of the thin film transistor 230, but is not necessarily limited thereto. The contact hole may be formed through a later process.

The planarization film 270 may be formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. there is.

Next, first electrodes 311, 312, and 313 and shielding patterns 281, 282, and 283 are formed as shown in FIG. 17D (S1604).

More specifically, first electrodes 311, 312, and 313 are formed for each sub-pixel (P1, P2, and P3) on the planarization film 270. The first electrodes 311, 312, and 313 are connected to the source electrode or drain electrode of the thin film transistor 230 through a contact hole.

The first electrodes 311, 312, and 313 may be made of a transparent metal material, a translucent metal material, or a highly reflective metal material. When the display device 100 is made of a bottom-emitting type, the first electrodes 311, 312, and 313 are made of a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or magnesium (Mg). ), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the display device 100 is made of a top-emitting type, the first electrodes 311, 312, and 313 have a stacked structure of aluminum and titanium (Ti/Al/Ti) or a stacked structure of aluminum and ITO (ITO/Al/ITO). ), Ag alloy, and a laminated structure of Ag alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). These first electrodes 311, 312, and 313 may be anode electrodes.

Shielding patterns 281, 282, and 283 are formed on the planarization film 270 to be spaced apart from the first electrodes 311, 312, and 313. Masking patterns 281, 282, and 283 are also formed on a portion of the second insulating film 260 that is exposed and not covered by the planarization film 270.

The covering patterns 281, 282, and 283 may be formed simultaneously with the same material as the first electrodes 311, 312, and 313.

Next, a bank 315 is formed as shown in FIG. 17e (S1605).

More specifically, a bank 315 is formed to cover the ends of each of the first electrodes 311, 312, and 313. The bank 315 includes a second insulating film 260 and shielding patterns 281, 282, and 283 disposed in an area where the first power line 241, the second power line 242, and the second connection electrode 250 are formed. A pattern may be formed so that a portion of is exposed.

Next, opening areas OA1, OA2, and OA3 are formed in the second insulating film 260 as shown in FIG. 17F (S1606).

More specifically, an etching process is performed to form opening areas OA1, OA2, and OA3 in the second insulating film 260. At this time, the etching process may be a wet etch process, and an etchant that can etch the second insulating film 260 but cannot etch the covering patterns 281, 282, and 283 may be used. Accordingly, the covering patterns 281, 282, and 283 are not etched, and only the exposed second insulating film 260 is etched, thereby forming an undercut structure.

The second insulating film 260 includes a first opening area (OA1) exposing a portion of the first power line 241 and a second opening area (OA2) exposing a portion of the second power line 242 through an etching process. , and a third opening area OA3 exposing a portion of the second connection electrode 250 may be formed.

Next, the first light emitting layers 321, 322, and 323 are formed as in 17g (S1607).

More specifically, first light emitting layers 321, 322, and 323 are formed on the first electrodes 311, 312, and 313 and the shielding patterns 281, 282, and 283. The first light emitting layers 321, 322, and 323 may be formed through a deposition process or a solution process. When the first light emitting layers 321, 322, and 323 are formed through a deposition process, they may be formed using an evaporation method.

The first light emitting layer (321, 322, 323) is separated between the first sub-pixel (P1), the second sub-pixel (P2), and the third sub-pixel (P3) by the blocking patterns (281, 282, 283). . The first light emitting layers 321, 322, and 323 may be broken on the blocking patterns 281, 282, and 283. Additionally, the first light emitting layers 321, 322, and 323 may be formed under the blocking patterns 281, 282, and 283 by flowing into the space formed below the blocking patterns 281, 282, and 283.

The first light-emitting layer (321, 322, 323) may be any one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but must be It is not limited to this.

Next, second electrodes 331, 332, and 333 are formed as shown in FIG. 17h (S1608).

More specifically, second electrodes 331, 332, and 333 are formed on the first light emitting layer (321, 322, and 323). The second electrodes 331, 332, and 333 are separated between the first sub-pixel (P1), the second sub-pixel (P2), and the third sub-pixel (P3) by the blocking patterns 281, 282, and 283. . The second electrodes 331, 332, and 333 may be broken on the covering patterns 281, 282, and 283. Additionally, the second electrodes 331, 332, and 333 may be formed under the blocking patterns 281, 282, and 283 by flowing into the space formed below the blocking patterns 281, 282, and 283.

The second electrodes 331, 332, and 333 may be formed by a physical vapor deposition method such as sputtering. A film formed by a physical vapor deposition method such as sputtering has excellent step coverage characteristics. Accordingly, the second electrodes 331, 332, and 333 may be formed with a larger area than the first light emitting layers 321, 322, and 323 formed using evaporation. Accordingly, the second electrodes 331, 332, and 333 are connected to any of the first power line 241, the second power line 242, and the second connection electrode 250 under the blocking patterns 281, 282, and 283. Can be connected to one.

The second electrodes 331, 332, and 333 are made of a transparent metal material (TCO, Transparent Conductive Material) such as ITO or IZO, which can transmit light, or magnesium (Mg), silver (Ag), or magnesium (Mg). It may be formed of a semi-transmissive conductive material such as an alloy of silver (Ag).

Next, the second light emitting layer 340 is formed as shown in Figure 17i (S1609).

More specifically, the second light emitting layer 340 is formed on the second electrodes 331, 332, and 333. The second light emitting layer 340 may be formed through a deposition process or a solution process. When the second light emitting layer 340 is formed through a deposition process, it may be formed using an evaporation method.

The second light emitting layer 340 is connected between the first sub-pixel (P1), the second sub-pixel (P2), and the third sub-pixel (P3). The second light emitting layer 340 may be formed while partially filling the space between the blocking patterns 281, 282, and 283 and the second electrodes 331, 332, and 333. At this time, an air gap AG may be formed in the space not filled with the second light emitting layer 340 between the blocking patterns 281, 282, and 283 and the second electrodes 331, 332, and 333.

The second light-emitting layer 340 may be any one of a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, a blue light-emitting layer that emits blue light, and a yellow light-emitting layer that emits yellow light, but is not necessarily limited thereto. .

However, the second light-emitting layer 340 may emit light of a different color from the first light-emitting layer 321, 322, and 323. When the first light-emitting layers 321, 322, and 323 are light-emitting layers that emit light of a first color, the second light-emitting layer 340 may be a light-emitting layer that emits light of a second color different from the first color. For example, the first light-emitting layer 321, 322, and 323 may be a yellow light-emitting layer that emits yellow light, and the second light-emitting layer 340 may be a blue light-emitting layer that emits blue light.

Next, the third electrode 350 is formed as shown in Figure 17j (S1610).

More specifically, the third electrode 350 is formed on the second light emitting layer 340. The third electrode 350 may be formed by a physical vapor deposition method such as sputtering. Alternatively, the third electrode 350 may be formed using evaporation.

The third electrode 350 may be made of a transparent metal material, a translucent metal material, or a highly reflective metal material. When the display device 100 is made of a bottom-emitting type, the third electrode 350 has a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), and Ag alloy. , and a laminated structure of Ag alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). When the display device 100 is made of a top-emitting type, the third electrode 350 is made of a transparent conductive material (TCO) such as ITO or IZO, which can transmit light, or magnesium (Mg) or silver ( It may be formed of a semi-transmissive conductive material such as Ag) or an alloy of magnesium (Mg) and silver (Ag). This third electrode 350 may be a cathode electrode.

18A to 18C relate to a display device according to another embodiment of the present invention, which relates to a head mounted display (HMD) device. FIG. 18A is a schematic perspective view, FIG. 18B is a schematic plan view of a VR (Virtual Reality) structure, and FIG. 18C is a schematic cross-sectional view of an AR (Augmented Reality) structure.

As can be seen in FIG. 18A, the head-mounted display device according to the present invention includes a storage case 10 and a head-mounted band 30.

The storage case 10 stores components such as a display device, a lens array, and an eyepiece lens therein.

The head mounting band 30 is fixed to the storage case 10. The head mounting band 30 is illustrated as being formed to surround the upper surface and both sides of the user's head, but is not limited thereto. The head mounting band 30 is used to secure the head mounted display to the user's head, and can be replaced with a structure in the form of a glasses frame or a helmet.

As can be seen in Figure 18b, the head-mounted display device with a VR (Virtual Reality) structure according to the present invention includes a display device 12 for the left eye, a display device 11 for the right eye, a lens array 13, and a left eyepiece lens ( 20a) and a right eyepiece 20b.

The display device 12 for the left eye and the display device 11 for the right eye, the lens array 13, and the left eyepiece 20a and right eyepiece lens 20b are stored in the storage case 10 described above.

The display device 12 for the left eye and the display device 11 for the right eye can display the same image, and in this case, the user can watch a 2D image. Alternatively, the display device 12 for the left eye may display the left eye image and the display device 11 for the right eye may display the right eye image. In this case, the user may view a three-dimensional image. Each of the display device 12 for the left eye and the display device 11 for the right eye may be made of the display device shown in FIGS. 1 to 14 described above. At this time, the upper portion corresponding to the surface on which the image is displayed in FIGS. 1 to 14, for example, a color filter layer (not shown), faces the lens array 13.

The lens array 13 may be provided between the left eyepiece lens 20a and the left eye display device 12 while being spaced apart from each other. That is, the lens array 13 may be located in front of the left eye eyepiece 20a and behind the display device 12 for the left eye. Additionally, the lens array 13 may be provided between the right eyepiece lens 20b and the right eye display device 11 while being spaced apart from each of the right eyepiece lens 20b and the right eye display device 11. That is, the lens array 13 may be located in front of the right eye eyepiece 20b and behind the display device 11 for the right eye.

The lens array 13 may be a micro lens array. The lens array 13 can be replaced with a pin hole array. Due to the lens array 13, the image displayed on the left-eye display device 12 or the right-eye display device 11 may be enlarged and visible to the user.

The user's left eye (LE) may be located in the left eyepiece lens 20a, and the user's right eye (RE) may be located in the right eyepiece lens 20b.

As can be seen in FIG. 18C, the head-mounted display device with an AR (Augmented Reality) structure according to the present invention includes a left-eye display device 12, a lens array 13, a left-eye eyepiece 20a, and a transmission reflector 14. , and a transmission window 15. In Figure 18c, only the left inner configuration is shown for convenience, and the right inner configuration is also the same as the left inner configuration.

The left-eye display device 12, lens array 13, left-eye eyepiece 20a, transmission reflector 14, and transmission window 15 are stored in the storage case 10 described above.

The display device 12 for the left eye may be disposed on one side, for example, on the upper side of the transmission reflection portion 14 without blocking the transmission window 15. Accordingly, the left-eye display device 12 can provide an image to the transparent reflector 14 without blocking the external background seen through the transparent window 15.

The display device 12 for the left eye may be made of the display device according to FIGS. 1 to 14 described above. At this time, the upper portion corresponding to the surface on which the image is displayed in FIGS. 1 to 14, for example, a color filter (not shown), faces the transmission and reflection portion 14.

The lens array 13 may be provided between the left eyepiece lens 20a and the transmission and reflection unit 14.

The user's left eye is located in the left eye eyepiece 20a.

The transmission reflection portion 14 is disposed between the lens array 13 and the transmission window 15. The transmission reflection unit 14 may include a reflection surface 14a that transmits part of the light and reflects another part of the light. The reflective surface 14a is formed so that the image displayed on the left eye display device 12 progresses to the lens array 13. Accordingly, the user can view both the external background and the image displayed by the left eye display device 12 through the transmission layer 15. In other words, since the user can view the real background and the virtual image as one image by overlapping them, Augmented Reality (AR) can be implemented.

The transmission layer 15 is disposed in front of the transmission reflection portion 14.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: display device 110: display panel
111: first substrate 112: second substrate
140: Source drive IC 150: Flexible film
160: circuit board 170: timing control unit
210: light blocking layer 220: first insulating film
230: thin film transistor 241: first power line
242: second power line 250: second connection electrode
260: second insulating film 270: planarization film
281, 282, 283: Shielding pattern 311, 312, 313: First electrode
321, 322, 323: first light emitting layer 331, 332, 333: second electrode
340: second light emitting layer 350: third electrode

Claims (40)

a substrate having a display area on which first and second sub-pixels are arranged and a non-display area surrounding the display area;
a first electrode provided in each of the first sub-pixel and the second sub-pixel on the substrate;
a first light emitting layer provided on the first electrode and emitting light of a first color;
a second electrode provided on the first light emitting layer;
a second light emitting layer provided on the second electrode and emitting light of a second color;
a third electrode provided on the second light emitting layer; and
It includes a first connection electrode electrically connecting a second electrode of the first sub-pixel and a third electrode of the first sub-pixel,
The second electrode is disconnected between the first sub-pixel and the second sub-pixel,
The second electrode of the first sub-pixel is electrically connected to the third electrode, and the second electrode of the second sub-pixel is electrically connected to the first electrode,
The first connection electrode is,
a first power line connected to a second electrode of the first sub-pixel; and
an auxiliary power line disposed in the non-display area and connected to each of the first power line and a third electrode of the first sub-pixel;
The first power line is disposed in the display area and connected to the second electrode of the first sub-pixel, extends from the display area to the auxiliary power line disposed in the non-display area, and has one end connected to the auxiliary power line. Connected display device. According to paragraph 1,
A display device in which the first sub-pixel emits light from the first light-emitting layer, and the second sub-pixel emits light from the second light-emitting layer. According to paragraph 2,
The second light emitting layer is a display device that emits blue light. According to paragraph 1,
The first light emitting layer is disconnected between the first sub-pixel and the second sub-pixel. According to paragraph 1,
The second light emitting layer is connected between the first sub-pixel and the second sub-pixel. According to paragraph 1,
The third electrode is connected between the first sub-pixel and the second sub-pixel. delete delete delete According to paragraph 1,
It is provided in each of the first sub-pixel and the second sub-pixel, and further includes a driving transistor including an active layer, a gate electrode, a source electrode, and a drain electrode,
The first power line is formed on the same layer as one of the active layer, the gate electrode, the source electrode, and the drain electrode. According to clause 10,
It further includes a first insulating film provided on the driving transistor and the first power line, and having a first opening area exposing a portion of the first power line,
A display device wherein the second electrode of the first sub-pixel is connected to the first power line in the first opening area. According to clause 11,
The display device further includes a first blocking pattern provided on the first insulating film and having a protruding protrusion formed to cover a portion of the first opening area. According to clause 12,
A display device in which the first blocking pattern is formed simultaneously with the same material as the first electrode. According to clause 13,
The first blocking pattern is spaced apart from the first electrode. According to clause 12,
The first blocking pattern is formed along the first power line in the display area. According to clause 12,
A display device wherein the second electrode of the first sub-pixel is connected to the first power line under the first blocking pattern. According to paragraph 1,
The display device further includes a second connection electrode electrically connecting the first electrode of the second sub-pixel to the second electrode of the second sub-pixel. According to clause 17,
The second connection electrode is provided between the first sub-pixel and the second sub-pixel. According to clause 17,
It is provided in each of the first sub-pixel and the second sub-pixel, and further includes a driving transistor including an active layer, a gate electrode, a source electrode, and a drain electrode,
The second connection electrode is formed on the same layer as one of the active layer, the gate electrode, the source electrode, and the drain electrode. According to clause 19,
It further includes a first insulating film provided on the driving transistor and the second connection electrode and having a second opening area exposing a portion of the second connection electrode,
A display device wherein the second electrode of the second sub-pixel is connected to the second connection electrode in the second opening area. According to clause 20,
A display device wherein the first electrode of the second sub-pixel is connected to the second connection electrode through a contact hole penetrating the first insulating film. According to clause 20,
The display device further includes a second blocking pattern provided on the first insulating film and having a protruding protrusion to cover a portion of the second opening area. According to clause 22,
A display device in which the second blocking pattern is formed simultaneously with the same material as the first electrode. According to clause 23,
The second blocking pattern is spaced apart from the first electrode. According to clause 22,
The second blocking pattern is formed to surround the second sub-pixel. According to clause 22,
The display device wherein the first light emitting layer is disconnected between the first sub-pixel and the second sub-pixel by the second blocking pattern. According to clause 22,
The display device wherein the second electrode is disconnected between the first sub-pixel and the second sub-pixel by the second blocking pattern. According to clause 27,
A display device wherein the second electrode of the second sub-pixel is connected to the second connection electrode under the second blocking pattern. a substrate having a display area on which a first sub-pixel, a second sub-pixel, and a third sub-pixel are arranged, and a non-display area surrounding the display area;
a first electrode provided in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel on the substrate;
a first light emitting layer provided on the first electrode and emitting light of a first color;
a second electrode provided on the first light emitting layer;
a second light emitting layer provided on the second electrode and emitting light of a second color;
a third electrode provided on the second light emitting layer;
a first connection electrode electrically connecting the second electrode of the first sub-pixel, the second electrode of the third sub-pixel, and the third electrode; and
A second connection electrode electrically connects the first electrode of the second sub-pixel to the second electrode of the second sub-pixel,
The same first voltage is applied to the second electrode and the third electrode of the first sub-pixel and the third sub-pixel,
The second sub-pixel has the same second voltage applied to the first electrode and the second electrode,
The first connection electrode is,
a first power line connected to a second electrode of the first sub-pixel;
a second power line connected to a second electrode of the third sub-pixel; and
an auxiliary power line disposed in the non-display area and connected to each of the first power line, the second power line, and the third electrode;
The first power line is disposed in the display area and connected to a second electrode of the first sub-pixel, extends from the display area to the auxiliary power line, and has one end connected to the auxiliary power line,
The second power line is arranged in parallel with the first power line in the display area, connects to the second electrode of the third sub-pixel, extends from the display area to the auxiliary power line, and has one end of the auxiliary power line. A display device connected to. According to clause 29,
The first sub-pixel and the third sub-pixel emit light from a first light-emitting layer provided between the first electrode and the second electrode,
The second sub-pixel is a display device in which a second light-emitting layer provided between the second electrode and the third electrode emits light. According to clause 29,
The second electrode is disconnected between the first sub-pixel, the second sub-pixel, and the third sub-pixel. According to clause 29,
The first light emitting layer is disconnected between the first sub-pixel, the second sub-pixel, and the third sub-pixel. According to clause 29,
The second light emitting layer is connected between the first sub-pixel, the second sub-pixel, and the third sub-pixel. According to clause 29,
A second electrode of each of the first sub-pixel and the third sub-pixel is electrically connected to the third electrode,
A display device wherein the second electrode of the second sub-pixel is electrically connected to the first electrode. According to clause 29,
The second light emitting layer is a display device that emits blue light. delete delete delete According to clause 29,
A display device in which the first power line and the second power line are spaced apart from each other, and a first sub-pixel or a third sub-pixel is disposed between the first power line and the second power line. According to clause 29,
The first power line and the second power line are disposed between the first sub-pixel and the third sub-pixel and are formed as one body.

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