KR20210053654A - Display device - Google Patents

Abstract

The present invention provides a display device capable of reducing power consumption. The display device according to one embodiment of the present invention includes a substrate including a display area in which a first sub-pixel and a second sub-pixel are disposed and a non-display area surrounding the display area; a first electrode provided on each of the first sub-pixel and the second sub-pixel on the substrate; a first light emitting layer provided on the first electrode to emit light of a first color; a second electrode provided on the first light emitting layer; a second light emitting layer provided on the second electrode to emit light of a second color; a third electrode provided on the second light emitting layer; a connection electrode provided between the substrate and the first electrode and electrically connecting the second electrode and the third electrode or electrically connecting the first electrode and the second electrode; a first layer provided on the connection electrode and including an opening region for exposing a part of the connection electrode; and a second layer provided on the first layer and including a protrusion protruding to cover a portion of the opening area. The connection electrode has a step difference in the opening region.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device that displays an image.

As the information society develops, demands for display devices for displaying images are increasing in various forms. Accordingly, in recent years, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been used.

In the organic light emitting display device, it is difficult to precisely pattern light emitting layers of different colors for each sub-pixel. To solve this problem, the organic light emitting display device may implement a different color by forming a white emission layer consisting of a plurality of stacks emitting light of different colors as a common layer, and disposing a color filter for each sub-pixel. In this case, the organic light emitting display device has an advantage that a precise mask fabrication or a precise mask alignment process is not required, but there is a problem in that a large amount of power is consumed due to a plurality of stacks.

The present invention provides a display device capable of reducing power consumption.

A display device according to an embodiment of the present invention includes a substrate including a display area in which a first sub-pixel and a second sub-pixel are disposed, and a non-display area surrounding the display area, and a first sub-pixel and a second sub-pixel on the substrate. A first electrode provided on each, a first emission layer provided on the first electrode to emit light of a first color, a second electrode provided on the first emission layer, and a second color light provided on the second electrode A second light emitting layer emitting light, a third electrode provided on the second light emitting layer, provided between the substrate and the first electrode, and electrically connecting the second electrode and the third electrode, or electrically connecting the first electrode and the second electrode A first layer provided on the connection electrode and including an opening region exposing a portion of the connection electrode, and a second layer provided on the first layer and including a protrusion protruding to cover a part of the opening region Includes. The connecting electrode has a step difference in the open area.

A display device according to another exemplary embodiment of the present invention includes a metal pattern provided on a substrate, a first layer provided on the metal pattern and having an opening area exposing a part of the metal pattern, and an opening area provided on the first layer. And a second layer including a protruding portion protruding to cover a portion of the. The metal pattern has a step difference in the opening area.

According to the present invention, by forming the first emission layer and the second emission layer on the sub-pixels without a mask on the entire surface, it is possible to solve the problem of forming patterns of different emission layers for each sub-pixel using a mask. That is, the present invention does not require a precise mask fabrication or a precise mask alignment process, and can be applied to a high-resolution display device having a dense pixel gap.

In addition, although the first emission layer and the second emission layer are formed on the entire surface of the present invention, only one of the first emission layer and the second emission layer may emit light in each of the sub-pixels. Accordingly, the present invention can significantly reduce power consumption compared to emitting light of both the first and second emission layers.

In addition, according to the present invention, the second electrode is disconnected between the sub-pixels using the undercut structure, and the second electrode of each of the sub-pixels is connected to any one of the first connection electrode, the first connection electrode, and the second connection electrode. Can be. In the present invention, there is no need to manufacture a separate mask.

In addition, in the present invention, by forming the connecting electrode to have a step and adjusting the step of the connecting electrode, whether the first light-emitting layer, the second electrode, the second light-emitting layer, and the third electrode are connected can be freely controlled without limiting the thickness of the second insulating layer. I can.

In particular, the present invention can implement the effect of reducing the thickness of the second insulating film by having a step difference in the connection electrode even if the thickness of the second insulating film provided below is not reduced among the layers constituting the undercut structure. Accordingly, according to the present invention, it is possible to ensure that each of the second emission layer and the third electrode is connected without being disconnected even between sub-pixels on which the undercut structure is disposed.

The effects obtainable in the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those of ordinary skill in the art from the following description. .

1 is a perspective view illustrating a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a plan view showing a first substrate, a source drive IC, a flexible film, a circuit board, and a timing controller of FIG. 1.
3 is a schematic plan view of a first substrate of a display panel according to an exemplary embodiment.
4 is a cross-sectional view illustrating an example of II of FIG. 3.
5 is a cross-sectional view illustrating an example of II-II of FIG. 3.
6 is a plan view schematically illustrating an example of a first sub-pixel and a second sub-pixel.
7 is a plan view showing a modified example of FIG. 6.
8 is a plan view schematically illustrating an example of a third sub-pixel.
9 is a plan view showing a modified example of FIG. 8.
10 is an enlarged view showing an example of area A of FIG. 4.
11 is an enlarged view showing another example of area A of FIG. 4.
12 is an enlarged view showing another example of area A of FIG. 4.
13 is an enlarged view showing a modified example of FIG. 10.
14 is an enlarged view showing another modified example of FIG. 10.
15 is a cross-sectional view illustrating an example of III-III of FIG. 3.
16 is a cross-sectional view showing an example of IV-IV of FIG. 3.
17A to 17C relate to a display device according to another embodiment of the present invention, which relates to a head mounted display (HMD) device.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments are intended to complete the disclosure of the present invention, and those skilled in the art to which the present invention pertains It is provided to fully inform the person of the scope of the invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same elements throughout the specification. In addition, in describing the present invention, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When'include','have','consists of' and the like mentioned in the present specification are used, other parts may be added unless'only' is used. In the case of expressing the constituent elements in the singular, it includes the case of including the plural unless specifically stated otherwise.

In interpreting the constituent elements, it is interpreted as including an error range even if there is no explicit description.

In the case of a description of the positional relationship, for example, if the positional relationship of two parts is described as'upper','upper of','lower of','next to','right' Or, unless'direct' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, when a temporal predecessor relationship is described as'after','following','after','before', etc.,'right' or'direct' It may also include cases that are not continuous unless this is used.

First, second, etc. are used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be a second component within the technical idea of the present invention.

"X-axis direction", "Y-axis direction" and "Z-axis direction" should not be interpreted only as a geometrical relationship in which the relationship between each other is vertical, and is wider than within the range in which the configuration of the present invention can function functionally. It can mean having directionality.

The term “at least one” is to be understood as including all possible combinations from one or more related items. For example, the meaning of “at least one of the first item, the second item, and the third item” means that each of the first item, the second item, or the third item, as well as the first item, the second item, and the third item, It may mean a combination of all items that can be presented from more than one.

Each of the features of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments can be implemented independently of each other or can be implemented together in a related relationship. May be.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view illustrating a display device according to an exemplary embodiment of the present invention. FIG. 2 is a plan view showing a first substrate, a source drive IC, a flexible film, a circuit board, and a timing controller of FIG. 1.

1 and 2, a display device 100 according to an embodiment of the present invention includes a display panel 110, a source drive integrated circuit (hereinafter referred to as "IC") 140, and a flexible film. 150, a circuit board 160, and a timing control unit 170.

The display panel 110 includes a first substrate 111 and a second substrate 112. The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film.

The display device 100 may be formed in a so-called bottom emission method in which the emitted light is emitted downward, but is not limited thereto. When the display device 100 according to an exemplary embodiment of the present invention is formed in a bottom emission type, a transparent material is used for the first substrate 111, and an opaque material is used for the second substrate 112 as well as a transparent material. Can be. On the other hand, when the display device 100 according to an embodiment of the present invention is formed in a top emission method in which the emitted light is emitted upward, the first substrate 111 is formed of not only a transparent material but also an opaque material. A transparent material may be used for the second substrate 112 and the second substrate 112 may be used.

Gate lines, data lines, and sub-pixels are formed on one surface of the first substrate 111 facing the second substrate 112. The sub-pixels are provided in a region defined by an intersection structure of gate lines and data lines.

Each of the sub-pixels may include a light emitting device including a thin film transistor, an anode electrode, a light emitting layer, and a cathode electrode. Each of the sub-pixels supplies a predetermined current to the light emitting device according to the data voltage of the data line when a gate signal is input from the gate line using the thin film transistor. Accordingly, when a high potential voltage is applied to the anode electrode and a low potential voltage is applied to the cathode electrode, the light emitting layers of each of the sub-pixels can emit light with a predetermined brightness according to a predetermined current.

The display panel 110 may be divided into a display area DA in which sub-pixels are formed to display an image and a non-display area NDA that does not display an image. Gate lines, data lines, and sub-pixels may be formed in the display area DA. Gate drivers and pads may be formed in the non-display area NDA.

The gate driver supplies gate signals to the gate lines according to the gate control signal input from the timing controller 170. The gate driver may be formed in a non-display area DA on one or both sides of the display area DA of the display panel 110 in a GIP (gate driver in panel) method. Alternatively, the gate driver is manufactured as a driving chip, mounted on a flexible film, and attached to a non-display area DA outside one or both sides of the display area DA of the display panel 110 in a TAB (tape automated bonding) method. May be.

The source drive IC 140 receives digital video data and a source control signal from the timing controller 170. The source drive IC 140 converts digital video data into analog data voltages according to a source control signal and supplies them to data lines. When the source drive IC 140 is manufactured as a driving chip, it may be mounted on the flexible film 150 in a chip on film (COF) or chip on plastic (COP) method.

Pads such as data pads may be formed in the non-display area NDA of the display panel 110. Wires connecting the pads and the source drive IC 140 and wires connecting the pads and the wires of the circuit board 160 may be formed on the flexible film 150. The flexible film 150 is attached on the pads using an anisotropic conducting film, whereby the wires of the flexible film 150 may be connected to the pads.

The circuit board 160 may be attached to the flexible films 150. The circuit board 160 may be mounted with a plurality of circuits implemented with driving chips. For example, the timing controller 170 may be mounted on the circuit board 160. The circuit board 160 may be a printed circuit board or a flexible printed circuit board.

The timing controller 170 receives digital video data and a timing signal from an external system board through a cable of the circuit board 160. The timing controller 170 generates a gate control signal for controlling an operation timing of the gate driver and a source control signal for controlling the source driver ICs 140 based on the timing signal. The timing controller 170 supplies a gate control signal to the gate driver and supplies a source control signal to the source drive ICs 140.

FIG. 3 is a plan view schematically illustrating a first substrate of a display panel according to an exemplary embodiment, FIG. 4 is a cross-sectional view illustrating an example of II of FIG. 3, and FIG. 5 is a diagram of II-II of FIG. 3. It is a cross-sectional view showing an example. 6 is a plan view schematically illustrating an example of a first sub-pixel and a second sub-pixel, and FIG. 7 is a plan view illustrating a modified example of FIG. 6. 8 is a plan view schematically illustrating an example of a third sub-pixel, and FIG. 9 is a plan view illustrating a modified example of FIG. 8. FIG. 10 is an enlarged view showing an example of area A of FIG. 4, FIG. 11 is an enlarged view showing another example of area A of FIG. 4, and FIG. 12 is an enlarged view showing another example of area A of FIG. 4 to be. 13 is an enlarged view showing a modified example of FIG. 10, and FIG. 14 is an enlarged view showing another modified example of FIG. 10. 15 is a cross-sectional view showing an example of III-III of FIG. 3, and FIG. 16 is a cross-sectional view showing an example of IV-IV of FIG. 3.

3 to 16, the display panel 110 according to an exemplary embodiment of the present invention includes a first substrate 111, a stepped layer 200, a light blocking layer 210, a first insulating layer 220, and a driving method. Thin film transistor 230, connection electrodes 240 and 250, auxiliary power line 360, planarization layer 270, second insulating layer 260, shielding pattern 280, first electrode 310, bank 315 ), a first emission layer 320, a second electrode 330, a second emission layer 340, and a third electrode 350.

The first substrate 111 may be made of glass or plastic, but is not limited thereto, and may be made of a semiconductor material such as a silicon wafer. The first substrate 111 may be made of a transparent material or an opaque material.

The first substrate 111 is divided into a display area DA and a non-display area NDA. A first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 may be provided in the display area DA of the first substrate 111. The first sub-pixel P1 emits red light, the second sub-pixel P2 emits green light, and the third sub-pixel P3 may be provided to emit blue light, but is limited thereto. It is not. A fourth sub-pixel emitting white (W) light may be further provided in the display area DA of the substrate 111. In addition, the arrangement order of each of the sub-pixels P1, P2, and P3 may be variously changed.

Hereinafter, for convenience of description, the first sub-pixel P1 is a red pixel emitting red light, the second sub-pixel P2 is a green pixel emitting green light, and the third sub-pixel P3 is It will be described as being a blue pixel emitting blue light.

Circuit elements including various signal lines, thin film transistors 230, and capacitors are provided on the first substrate 111 for each of the sub-pixels P1, P2, and P3. The signal lines may include a gate line, a data line, a power line, and a reference line.

When a gate signal is input to the gate line, the thin film transistor 230 supplies a predetermined voltage to the first electrode 310 according to the data voltage of the data line. 4 and 5 schematically illustrate the driving thin film transistor 230 as one layer. However, this is only for convenience of description, and the driving thin film transistor 230 is composed of a plurality of layers. The thin film transistor 230 includes an active layer, a gate electrode, a source electrode, and a drain electrode.

Specifically, an active layer is formed on the first substrate 111. The active layer may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. A light blocking layer 210 for blocking external light incident on the active layer may be formed between the first substrate 111 and the active layer as illustrated in FIG. 4. When the light blocking layer 210 is formed of a metal material, a buffer layer may be formed between the active layer and the light blocking layer 210.

A gate insulating layer may be formed on the active layer. The gate insulating layer may be formed of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, or multiple layers thereof.

A gate electrode may be formed on the gate insulating layer. The gate electrode is made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. It may be made of a single layer or multiple layers, but is not limited thereto.

An interlayer insulating film may be formed on the gate electrode. The interlayer insulating film may be formed of an inorganic film, for example, a silicon oxide film, a silicon nitride film, or multiple films thereof.

A source electrode and a drain electrode may be formed on the interlayer insulating layer. Each of the source electrode and the drain electrode may be connected to the active layer through a contact hole penetrating through the gate insulating layer and the interlayer insulating layer. Each of the source electrode and the drain electrode is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or It may be a single layer or multiple layers made of an alloy thereof, but is not limited thereto.

The connection electrodes 240 and 250 are formed on the first substrate 111. Specifically, the connection electrodes 240 and 250 may be formed of the same material on the same layer as any one of the active layer, the gate electrode, the source electrode, and the drain electrode of the thin film transistor 230.

The connection electrodes 240 and 250 are disposed on one side of each of the sub-pixels P1, P2, and P3 to electrically connect the second electrode 330 and the third electrode 350, or the first electrode 310 and The second 330 is electrically connected.

Specifically, the connection electrode 240 includes a first connection electrode 240 electrically connecting the second electrode 330 and the third electrode 350, and the first electrode 310 and the second electrode 330. And a second connection electrode 250 electrically connected to each other.

The first connection electrode 240 is disposed on one side of each of the first sub-pixel P1 and the second sub-pixel P2. For example, one first connection electrode 241 may be formed on one side of the first sub-pixel P1, and another first connection electrode 242 may be formed on one side of the second sub-pixel P2. . When a fourth sub-pixel emitting white (W) light is further provided, another first connection electrode 240 may be disposed on one side of the fourth sub-pixel.

The first connection electrodes 241 and 242 electrically connect the second electrodes 331 and 332 and the third electrode 350 of the first sub-pixel P1 and the second sub-pixel P2, respectively. The first connection electrodes 241 and 242 may electrically connect the second electrodes 331 and 332 to the third electrode 350 through the auxiliary power line 360 provided in the non-display area NDA.

The auxiliary power line 360 is formed to extend in the first direction (X-axis direction) in the non-display area NDA. As shown in FIGS. 15 and 16, the auxiliary power line 360 is partially exposed without being covered by the first insulating layer 220, the second insulating layer 260, and the planarization layer 270, and in the exposed area. It can be connected to the third electrode 350.

The auxiliary power line 360 may be formed of the same material on the same layer as the light blocking layer 210, but is not limited thereto. The auxiliary power line 360 may be formed of the same material on the same layer as any one of the active layer, the gate electrode, the source electrode, and the drain electrode of the thin film transistor 230.

One first connection electrode 241 is disposed on one side of the first sub-pixel P1 in the display area DA, and connects to the second electrode 331 of the first sub-pixel P1. 4 and 5 show that the first connection electrode 241 is disposed between the first sub-pixel P1 and the third sub-pixel P3, but is not limited thereto. The first connection electrode 241 may be disposed between the first sub-pixel P1 and the second sub-pixel P2.

The first connection electrode 241 may be formed to extend in the second direction (Y-axis direction) in the display area DA. The plurality of first sub-pixels P1 may be disposed in a second direction in parallel with the first connection electrode 241. In this case, the first connection electrode 241 is connected to the second electrode 331 of all of the plurality of first sub-pixels P1 arranged in parallel, or some of the plurality of first sub-pixels P1 It can be connected to the second electrode 331.

Meanwhile, the plurality of first sub-pixels P1 may be alternately disposed with the plurality of second sub-pixels P2 along the second direction. In this case, the first connection electrode 241 is connected to the second electrode 331 of all of the plurality of first sub-pixels P1, or the second electrode of some of the plurality of first sub-pixels P1 ( 331). Alternatively, the first connection electrode 241 is connected to the second electrodes 331 and 332 of all of the plurality of first sub-pixels P1 and the plurality of second pixels P2, or the plurality of first sub-pixels ( Some of the second electrodes 331 and 332 among the P1s and the plurality of second pixels P2 may be connected.

One end of the first connection electrode 241 is connected to the auxiliary power line 360. The first connection electrode 241 may be connected to the auxiliary power line 360 through a contact hole as illustrated in FIG. 15, but is not limited thereto.

The first connection electrode 241 may be formed of the same material on the same layer as any one of the active layer, the gate electrode, the source electrode, and the drain electrode of the thin film transistor 230.

As described above, in the first sub-pixel P1, the second electrode 331 and the third electrode 350 are electrically connected through the first connection electrode 241 and the auxiliary power line 360. That is, when a low potential voltage is applied to the third electrode 350, the second electrode 331 of the first sub-pixel P1 is applied with the same low potential voltage as the third electrode 350.

The other first connection electrode 242 is disposed on one side of the second sub-pixel P2 in the display area DA to connect to the second electrode 332 of the second sub-pixel P2. 4 and 5 illustrate that the first connection electrode 242 is disposed between the first sub-pixel P1 and the second sub-pixel P2, but is not limited thereto. The first connection electrode 242 may be disposed between the second sub-pixel P2 and the third sub-pixel P3.

The first connection electrode 242 is disposed in the display area DA, and may be formed to extend in a second direction (Y-axis direction). The plurality of second sub-pixels P2 may be disposed in a second direction in parallel with the first connection electrode 242. In this case, the first connection electrode 242 is connected to the second electrode 332 of all of the plurality of second sub-pixels P2 arranged in parallel, or some of the plurality of second sub-pixels P2 It can be connected to the second electrode 332.

Meanwhile, the plurality of second sub-pixels P2 may be alternately disposed with the plurality of first sub-pixels P1 along the second direction. In this case, the first connection electrode 242 is connected to the second electrode 332 of all of the plurality of second sub-pixels P2, or the second electrode of some of the plurality of second sub-pixels P2 ( 332). Alternatively, the first connection electrode 242 is connected to the second electrodes 331 and 332 of all of the plurality of first sub-pixels P1 and the plurality of second pixels P2, or the plurality of first sub-pixels ( P1) and some of the second electrodes 331 and 332 among the plurality of second pixels P2 may be connected.

One end of the first connection electrode 242 is connected to the auxiliary power line 360. The first connection electrode 242 may be connected to the auxiliary power line 360 through a contact hole as illustrated in FIG. 15, but is not limited thereto.

The first connection electrode 242 may be formed of the same material on the same layer as any one of the active layer, the gate electrode, the source electrode, and the drain electrode of the thin film transistor 230.

As described above, in the second sub-pixel P2, the second electrode 332 and the third electrode 350 are electrically connected through the first connection electrode 242 and the auxiliary power line 360. That is, when a low potential voltage is applied to the third electrode 350, the second electrode 332 of the second sub-pixel P2 is applied with the same low potential voltage as the third electrode 350.

The second connection electrode 250 is disposed on one side of the third sub-pixel P3. The second connection electrode 250 is disposed on one side of the third sub-pixel P3 in the display area DA, and the first electrode 313 and the third sub-pixel P3 of the third sub-pixel P3 It is connected to the second electrode 333 of.

4 and 5 illustrate that the second connection electrode 250 is disposed between the second sub-pixel P2 and the third sub-pixel P3, the present invention is not limited thereto. The second connection electrode 250 may be disposed between the third sub-pixel P3 and the first sub-pixel P1.

4, 5, and 8 illustrate that the second connection electrode 250 is disposed only on one side of the third sub-pixel P3, the present invention is not limited thereto. The second connection electrode 250 may be disposed on a plurality of sides of the third sub-pixel P3. For example, when the third sub-pixel P3 includes four sides in a plane, the second connection electrode 250 is disposed on all four sides of the third sub-pixel P3 as shown in FIG. 9. May be. As a result, the second connection electrode 250 may be disposed on at least one of the four sides of the third sub-pixel P3.

The second connection electrode 250 may be patterned to correspond to each of the plurality of third sub-pixels P3. In this case, the second connection electrodes 250 formed to correspond to each of the plurality of third sub-pixels P3 are spaced apart from each other as shown in FIG. 3 so as not to be electrically connected to each other. One third sub-pixel P3 may be connected to one second connection electrode 251, and the other third sub-pixel P3 may be connected to another second connection electrode 252. In this case, one second connection electrode 251 and the other second connection electrode 252 may be patterned, and may be spaced apart so as not to be electrically connected to each other.

The second connection electrode 250 may be formed of the same material on the same layer as any one of the active layer, the gate electrode, the source electrode, and the drain electrode of the thin film transistor 230.

As described above, in the third sub-pixel P3, the first electrode 313 and the second electrode 333 are electrically connected through the second connection electrode 250. That is, when the third high potential voltage is applied to the first electrode 313 of the third sub-pixel P3, the second electrode 333 of the third sub-pixel P3 is The same third high potential voltage as the first electrode 313 is applied.

The second insulating layer 260 is formed on the thin film transistor 230, the first connection electrode 240 and the second connection electrode 250 to protect the thin film transistor 230. The second insulating layer 260 covers the thin film transistor 230 and at the same time exposes a part of the first connection electrode 240 and the second connection electrode 250.

More specifically, the second insulating layer 260 includes a plurality of opening regions OA1, OA2, and OA3 exposing a portion of the first connection electrode 240 and the second connection electrode 250.

The second insulating layer 260 includes a first opening area OA1 exposing a part of the first connection electrode 241 disposed on one side of the first sub-pixel P1 as shown in FIGS. 4 and 5. can do. The first opening area OA1 may be formed along the first connection electrode 241. In this case, the first opening area OA1 may be formed in one or a plurality of patterns having a predetermined length in the second direction (Y-axis direction) on the first connection electrode 241.

In addition, the second insulating layer 260 is a second opening area OA2 exposing a part of the first connection electrode 242 disposed on one side of the second sub-pixel P2 as shown in FIGS. 4 and 5. It may include. The second opening area OA2 may be formed along the first connection electrode 242. In this case, the second opening area OA2 may be formed in one or more patterns having a predetermined length in the second direction (Y-axis direction) on the first connection electrode 242.

In addition, the second insulating layer 260 is a third opening area OA3 exposing a part of the second connection electrode 250 disposed on one side of the third sub-pixel P3 as shown in FIGS. 4 and 5. It may include. The third opening area OA3 may be formed to surround the third sub-pixel P3. Accordingly, the third opening region OA3 exposes a part of the second connection electrode 250 in the region where the second connection electrode 250 is formed, and the first connection electrode 250 is formed in the region where the second connection electrode 250 is not formed. The insulating layer 220 is exposed.

The second insulating layer 260 may be formed of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, or multiple layers thereof.

The planarization layer 270 is formed on the second insulating layer 260 to planarize a step due to the thin film transistor 230. In this case, the planarization layer 270 is not formed on the opening regions OA1, OA2, and OA3 of the second insulating layer 260. Accordingly, a portion of the first connection electrode 240 and the second connection electrode 250 may still be exposed.

The planarization layer 270 may have a smaller formation area than the second insulating layer 260. Accordingly, the planarization layer 270 may expose a part of the second insulating layer 260. In this case, the second insulating layer 260 may be exposed in a region adjacent to the opening regions OA1, OA2, and OA3 without being covered by the planarization layer 270.

The planarization film 270 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. I can.

The first electrode 310 is patterned for each of the sub-pixels P1, P2, and P3 on the planarization layer 270. One first electrode 311 is formed in the first sub-pixel P1, the other first electrode 312 is formed in the second sub-pixel P2, and another first electrode 312 is formed in the third sub-pixel P3. Another first electrode 313 is formed.

The first electrodes 311, 312, 313 are connected to the source electrode or the drain electrode of the thin film transistor 230 through contact holes CH1, CH2, and CH3 penetrating the second insulating layer 260 and the planarization layer 270. do. The first electrode 311 of the first sub-pixel P1 is connected to the source electrode or the drain electrode of the thin film transistor 230 through the contact hole CH1 to apply a first high potential voltage. The first electrode 312 of the second sub-pixel P2 is connected to the source electrode or the drain electrode of the thin film transistor 230 through the contact hole CH2 to apply a second high potential voltage. The first electrode 313 of the third sub-pixel P3 is connected to the source electrode or the drain electrode of the thin film transistor 230 through the contact hole CH3 to apply a third high potential voltage.

Meanwhile, the first electrode 313 of the third sub-pixel P3 is connected to the second connection electrode 250 through a contact hole CH4 penetrating the second insulating layer 260.

The first electrodes 311, 312, and 313 may be made of a transparent metal material, a transflective metal material, or a metal material having a high reflectivity. When the display device 100 is formed in a bottom emission type, the first electrodes 311, 312, 313 are transparent metallic materials such as ITO and IZO that can transmit light, or magnesium (Mg). ), silver (Ag), or a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). When the display device 100 is formed in a top emission type, the first electrodes 311, 312, and 313 have a laminated structure of aluminum and titanium (Ti/Al/Ti), and a laminated structure of aluminum and ITO (ITO/Al/ITO). ), Ag alloy, and a metal material having a high reflectivity such as a stacked structure of Ag alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). These first electrodes 311, 312, and 313 may be anode electrodes.

The shielding patterns 281, 282, and 283 are formed on the second insulating layer 260 to cover portions of the opening regions OA1, OA2, and OA3 of the second insulating layer 260. The covering patterns 281, 282, 283 include a first covering pattern 281, a second covering pattern 282, and a third covering pattern 283.

The first shielding pattern 281 may be formed on the exposed second insulating layer 260 without being covered by the planarization layer 270. The first covering pattern 281 includes a protruding portion 281a that protrudes to cover a part of the first opening area OA1. At this time, the protrusion 281a of the first blocking pattern 281 is spaced apart from the first connection electrode 241 disposed on one side of the first sub-pixel P1, and is spaced apart from the first connection electrode 241. To form.

The first blocking pattern 281 is formed close to the sub-pixel disposed adjacent to the first sub-pixel P1 with the first opening area OA1 interposed therebetween. The first opening area OA1 exposing the first connection electrode 241 disposed on one side of the first sub-pixel P1 may be disposed between the first sub-pixel P1 and the third sub-pixel P3. However, it is not necessarily limited thereto.

When the first opening area OA1 of the second insulating layer 260 is disposed between the third sub-pixel P3 and the first sub-pixel P1, the protrusion 281a of the first blocking pattern 281 is The third sub-pixel P3 may protrude in a direction toward the first opening area OA1. Accordingly, a partial area of the first opening area OA1 adjacent to the third sub-pixel P3 is covered by the first shielding pattern 281, and the first connection electrode exposed from the first opening area OA1 ( A part of the 241 may be covered by the first blocking pattern 281. The first connection electrode 241 may still be exposed in the remaining areas of the first opening area OA1 adjacent to the first sub-pixel P1.

The first shielding pattern 281 may be formed along the first connection electrode 241 like the first opening area OA1. In this case, the first covering pattern 281 may be formed as a plurality of patterns having a predetermined length in the second direction (Y-axis direction) on one first connection electrode 241 as shown in FIG. 6. It is not necessarily limited to this. The first blocking pattern 281 may be formed as a single line pattern extending in a second direction (Y-axis direction) on one first connection electrode 241 as shown in FIG. 7.

Meanwhile, the first shielding pattern 281 may be formed of the same material on the same layer as the first electrodes 311, 312, and 313. In this case, the first shielding pattern 281 is formed to be spaced apart from the first electrodes 311, 312, 313 and is not electrically connected to the first electrodes 311, 312, 313.

When the first blocking pattern 281 is formed on the same layer as the first electrodes 311, 312, 313, the first blocking pattern 281 is exposed without being covered by the planarization layer 270 and the planarization layer 270 The second insulating layer 260 may be formed. In this case, the display device 100 forms the first shielding pattern 281 with the same material on the same layer as the first electrodes 311, 312, and 313, so that the first shielding pattern ( 281) is formed.

However, the present invention is not necessarily limited thereto, and the first shielding pattern 281 may be formed on a layer different from the first electrodes 311, 312, and 313. The first shielding pattern 281 may be formed between the second insulating layer 260 and the planarization layer 270.

The second shielding pattern 282 may be formed on the exposed second insulating layer 260 without being covered by the planarization layer 270. The second covering pattern 282 includes a protruding portion 282a protruding to cover a part of the second opening area OA2. At this time, the protrusion 282a of the second blocking pattern 282 is spaced apart from the first connection electrode 242 disposed on one side of the second sub-pixel P2, and is spaced apart from the first connection electrode 242. To form.

The second blocking pattern 282 is formed close to the sub-pixel disposed adjacent to the second sub-pixel P2 with the second opening area OA2 interposed therebetween. The second opening area OA2 exposing the first connection electrode 242 disposed on one side of the second sub-pixel P2 may be disposed between the first sub-pixel P1 and the second sub-pixel P2. However, it is not necessarily limited thereto.

When the second opening area OA2 of the second insulating layer 260 is disposed between the first sub-pixel P1 and the second sub-pixel P2, the protrusion 282a of the second blocking pattern 282 is The first sub-pixel P1 may protrude in a direction toward the second opening area OA2. Accordingly, a partial area of the second opening area OA2 adjacent to the first sub-pixel P1 is covered by the second shielding pattern 282, and the first connection electrode exposed in the second opening area OA2 ( A part of 242 is covered by the second masking pattern 282. The first connection electrode 242 may still be exposed in the remaining area of the second opening area OA2 adjacent to the second sub-pixel P2.

The second covering pattern 282 may be formed along the first connection electrode 242 like the second opening area OA2. In this case, the second covering pattern 282 may be formed as a plurality of patterns having a predetermined length in the second direction (Y-axis direction) on one first connection electrode 242 as shown in FIG. 6. It is not necessarily limited to this. The second blocking pattern 282 may be formed as a single line pattern extending in a second direction (Y-axis direction) on one first connection electrode 242 as shown in FIG. 7.

Meanwhile, the second shielding pattern 282 may be formed of the same material on the same layer as the first electrodes 311, 312, and 313. In this case, the second shielding pattern 282 is formed to be spaced apart from the first electrodes 311, 312, and 313 and is not electrically connected to the first electrodes 311, 312, and 313.

When the second shielding pattern 282 is formed on the same layer as the first electrodes 311, 312, and 313, the second shielding pattern 282 is exposed without being covered by the planarization layer 270 and the planarization layer 270. The second insulating layer 260 may be formed. In this case, the display device 100 forms the second shielding pattern 282 on the same layer as the first electrodes 311, 312, and 313 of the same material, so that the second shielding pattern ( 282) is formed.

However, the present invention is not necessarily limited thereto, and the second shielding pattern 282 may be formed on a layer different from the first electrodes 311, 312, and 313. The second shielding pattern 282 may be formed between the second insulating layer 260 and the planarization layer 270.

The third blocking pattern 283 may be formed on the exposed second insulating layer 260 without being covered by the planarization layer 270. The third covering pattern 283 includes a protruding portion 283a protruding to cover a part of the third opening area OA3. At this time, the protrusion 283a of the third covering pattern 283 is spaced apart from the second connection electrode 250 disposed on at least one side of the third sub-pixel P3, and between the second connection electrode 250 and the second connection electrode 250. To form a space.

The third blocking pattern 283 is formed close to the sub-pixel disposed adjacent to the third sub-pixel P3 with the third opening area OA3 interposed therebetween. The third opening area OA3 exposing the second connection electrode 250 is between the first sub-pixel P1 and the third sub-pixel P3, and the second sub-pixel P2 and the third sub-pixel P3 It may be disposed between, but is not necessarily limited thereto.

When the third opening area OA3 of the second insulating layer 260 is disposed between the first sub-pixel P1 and the third sub-pixel P3, the protrusion 283a of the third blocking pattern 283 is It may protrude from one sub-pixel P1 toward the third opening area OA3. Accordingly, a partial area of the third opening area OA3 adjacent to the first sub-pixel P1 is covered by the third masking pattern 283 and the second connection electrode exposed in the third opening area OA3 ( 250) or a part of the first insulating layer 220 is covered by the third shielding pattern 283. The second connection electrode 250 or the first insulating layer 220 may still be exposed in the remaining areas of the third opening area OA2 adjacent to the third sub-pixel P3.

In addition, when the third opening area OA3 of the second insulating layer 260 is disposed between the second sub-pixel P2 and the third sub-pixel P3, the third shielding pattern 283 may be the protrusion 283a. May protrude from the second sub-pixel P2 toward the third opening area OA3. Accordingly, a portion of the third opening area OA3 adjacent to the second sub-pixel P2 is covered by the third masking pattern 283 and the second connection electrode exposed in the third opening area OA3 ( 250) or a part of the first insulating layer 220 is covered by the third shielding pattern 283. The second connection electrode 250 or the first insulating layer 220 may still be exposed in the remaining areas of the third opening area OA2 adjacent to the third sub-pixel P3.

The third blocking pattern 283 may be formed to surround the third sub-pixel P3 like the third opening area OA3 as illustrated in FIGS. 8 and 9. The second electrode 333 of the third sub-pixel P3 is the second electrode 331 of the first sub-pixel P1 and the second electrode of the second sub-pixel P2 by the third shielding pattern 283 It can be cut off from (332).

In the display device 100 according to an embodiment of the present invention, the second electrode 333 of the third sub-pixel P3 is formed by forming the third shielding pattern 283 to surround the third sub-pixel P3. The second electrode 331 of the first sub-pixel P1 and the second electrode 332 of the second sub-pixel P2 are not electrically connected to each other. Accordingly, in the display device 100 according to an exemplary embodiment, the second electrode 333 of the third sub-pixel P3 and the second electrode 331 of the first sub-pixel P1 are provided on the same layer. ) And the second electrode 332 of the second sub-pixel P2 may be applied with different voltages. While the second electrode 333 of the third sub-pixel P3 is applied with a high potential voltage as an anode electrode, the second electrode 331 of the first sub-pixel P1 and the second electrode 333 of the second sub-pixel P2 are The second electrode 332 is a cathode electrode and may be applied with a low potential voltage.

Meanwhile, the third shielding pattern 283 may be formed of the same material on the same layer as the first electrodes 311, 312, and 313. At this time, the third shielding pattern 283 is formed to be spaced apart from the first electrodes 311, 312, 313 and is not electrically connected to the first electrodes 311, 312, 313.

When the third blocking pattern 283 is formed on the same layer as the first electrodes 311, 312, and 313, the third blocking pattern 283 is exposed without being covered by the planarization layer 270 and the planarization layer 270. The second insulating layer 260 may be formed. In this case, the display device 100 forms the third shielding pattern 283 from the same material on the same layer as the first electrodes 311, 312, and 313, so that a third shielding pattern ( 283) is formed.

However, the present invention is not necessarily limited thereto, and the third shielding pattern 283 may be formed on a layer different from the first electrodes 311, 312, and 313. The third shielding pattern 283 may be formed between the second insulating layer 260 and the planarization layer 270.

The bank 315 may be formed on the planarization layer 270 to cover ends of the first electrodes 311, 312, and 313. Accordingly, it is possible to prevent a problem in that the luminous efficiency is lowered due to the concentration of current at the ends of the first electrodes 311, 312, 313.

Also, the bank 315 may be formed on at least a portion of the shielding patterns 281, 282, and 283. At this time, the bank 315 is formed so that the protrusions 281a, 282a, 283a of each of the covering patterns 281, 282, 283 can be exposed without being covered, as shown in FIGS. I can. That is, the bank 315 may not be formed on the opening regions OA1, OA2, and OA3 of the second insulating layer 260. However, it is not necessarily limited thereto.

In another embodiment, in the display device 100, the shielding patterns 281, 282, and 283 may be omitted. In this case, the bank 315 may be formed to cover a part of each of the opening regions OA1, OA2, and OA3 of the second insulating layer 260 as shown in FIG. 13. That is, the bank 315 may include a protrusion protruding to cover a portion of each of the opening regions OA1, OA2, and OA3. In this case, the bank 315 is formed on the opening regions OA1, OA2, and OA3 of the second insulating layer 260, and may serve the same as the shielding patterns 281, 282, and 283.

In another embodiment, the bank 315 may be formed on the protrusions 281a, 282a, and 283a of each of the covering patterns 281, 282, and 283 as shown in FIG. 14. When the shielding patterns 281, 282, and 283 are formed under the bank 315 in this way, it is possible to prevent the projections of the bank 315 from sagging.

The bank 315 defines a light emitting area in each of the plurality of sub-pixels P1, P2, and P3. That is, in each of the sub-pixels P1, P2, and P3, the exposed area of the exposed first electrodes 311, 312, and 313 without the bank 315 formed becomes a light emitting area. The bank 315 may be formed of an inorganic insulating layer having a relatively thin thickness, but may be formed of an organic insulating layer having a relatively thick thickness.

The first emission layer 320 is formed on the first electrode 310. The first emission layer 320 may be formed on the bank 315. The first emission layer 320 may include a hole transporting layer, a light emitting layer, and an electron transporting layer. In this case, in the first emission layer 321, 322, and 323, holes and electrons move to the emission layer through the hole transport layer and the electron transport layer, respectively, and are combined with each other in the emission layer to emit light in a predetermined color.

The first emission layer 320 may be any one of a red emission layer emitting red light, a green emission layer emitting green light, a blue emission layer emitting blue light, and a yellow emission layer emitting yellow light, but is not limited thereto. .

The first emission layers 321, 322, 323 are provided on each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3, and the first sub-pixel P1 and the second sub-pixel P1 The pixel P2 and the third sub-pixel P3 may be disconnected without being continuously connected. Shielding patterns 281, 282, and 283 are provided between the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3. The first emission layers 321, 322, 323 may be disconnected by the shielding patterns 281, 282, 283.

More specifically, the first emission layers 321 and 322 may be disconnected without being continuously connected between the first sub-pixel P1 and the second sub-pixel P2 by the second shielding pattern 282. When the first emission layers 321, 322, and 323 are completely deposited without a mask, the first emission layer 321 deposited on the first sub-pixel P1 is formed in a second masking pattern ( Due to the step difference between the protrusion 282a of 282 and the first connection electrode 242, it may be cut off on the protrusion 282a of the second covering pattern 282.

Meanwhile, the first emission layer 322 deposited on the second sub-pixel P2 is between the protrusion 282a of the second shielding pattern 282 and the first connection electrode 242 as shown in FIGS. 4 and 10. And may be formed under the protrusion 282a of the second covering pattern 282.

In the display device 100 according to the exemplary embodiment of the present invention, the first emission layer 321 of the first sub-pixel P1 and the first emission layer 322 of the second sub-pixel P2 are disconnected without contacting each other. It is desirable. Accordingly, when the second electrodes 331, 332, and 333 are completely deposited on the first emission layers 321, 322, 323, the second electrode 332 deposited on the second sub-pixel P2 is A space through which the protrusion 282a of the covering pattern 282 and the first emission layer 322 of the second sub-pixel P2 can be introduced may be secured.

Also, the first emission layers 322 and 323 may be disconnected without being continuously connected between the second sub-pixel P2 and the third sub-pixel P3 by the third shielding pattern 283. When the first emission layers 321, 322, and 323 are completely deposited without a mask, the first emission layer 322 deposited on the second sub-pixel P2 is formed with a third masking pattern ( Due to the step difference between the protrusion 283a of the 283 and the second connection electrode 250, it may be cut off on the protrusion 283a of the third covering pattern 283.

Meanwhile, the first emission layer 323 deposited on the third sub-pixel P3 is between the protrusion 283a of the third masking pattern 283 and the second connection electrode 250 as shown in FIGS. 4 and 10. And may be formed under the protrusion 283a of the third blocking pattern 283.

In the display device 100 according to the exemplary embodiment, the first emission layer 322 of the second sub-pixel P2 and the first emission layer 323 of the third sub-pixel P3 do not contact each other and are disconnected. It is desirable. Accordingly, when the second electrodes 331, 332, and 333 are completely deposited on the first emission layers 321, 322, 323, the second electrode 333 deposited on the third sub-pixel P3 is A space through which the protrusion 283a of the covering pattern 283 and the first emission layer 323 of the third sub-pixel P3 can be introduced may be secured.

Also, the first emission layers 321 and 323 may be disconnected between the first sub-pixel P1 and the third sub-pixel P3 by the third blocking pattern 283 and the first blocking pattern 281. As illustrated in FIG. 5, between the first sub-pixel P1 and the third sub-pixel P3, a third masking pattern 283 and a first blocking pattern 281 may be formed to be spaced apart from each other. In this case, the first blocking pattern 281 includes a protrusion 281a protruding from the third sub-pixel P3 in the direction of the first sub-pixel P1 to cover a part of the first opening area OA1. The third blocking pattern 283 includes a protrusion 283a protruding from the first sub-pixel P1 toward the third sub-pixel P3 to cover a part of the third opening area OA3.

When the first emission layers 321, 322, and 323 are completely deposited without a mask, the first emission layer 323 deposited on the third sub-pixel P3 is formed with a third masking pattern ( The protrusion 283a of 283 may be introduced into the space between the first insulating layer 220 and may be formed under the protrusion 283a of the third blocking pattern 283. The first emission layer 321 deposited on the first sub-pixel P1 is a space between the protrusion 281a of the first shielding pattern 281 and the first connection electrode 241 as shown in FIGS. 5 and 10. And may be formed under the protrusion 281a of the first covering pattern 281.

The second electrode 330 is formed on the first emission layer 320. The second electrodes 331, 332, and 333 are provided in each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3, and the first sub-pixel P1 and the second sub-pixel P1 The pixel P2 and the third sub-pixel P3 may be disconnected without being continuously connected. Shielding patterns 281, 282, and 283 are provided between the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3. The second electrodes 331, 332, and 333 may be disconnected by the shielding patterns 281, 282, and 283.

More specifically, the second electrodes 331 and 332 may be disconnected without being continuously connected between the first sub-pixel P1 and the second sub-pixel P2 by the second shielding pattern 282. When the second electrodes 331, 332, and 333 are deposited on the entire surface, the second electrode 331 deposited on the first sub-pixel P1 becomes the second shielding pattern 282 as shown in FIGS. 4 and 10. It may be cut off on the protrusion 282a of the second covering pattern 282 due to a step difference between the protrusion 282a and the first connection electrode 242 of

The second electrode 332 deposited on the second sub-pixel P2 is a space between the protrusion 282a of the second shielding pattern 282 and the first emission layer 322 as shown in FIGS. 4 and 10. It may be introduced and formed under the protrusion 282a of the second covering pattern 282. In this case, the second electrode 332 of the second sub-pixel P2 may be deposited in a larger area than the first emission layer 322 under the protrusion 282a of the second covering pattern 282. Accordingly, the second electrode 332 of the second sub-pixel P2 may be connected to the first connection electrode 242.

In the second sub-pixel P2, since the second electrode 332 is connected to the first connection electrode 242, the second electrode 332 and the second electrode 332 are connected through the first connection electrode 242 and the auxiliary power line 360. The three electrodes 350 may be electrically connected. Accordingly, when a low potential voltage is applied to the third electrode 350, the second electrode 332 of the second sub-pixel P2 may be applied with the same low potential voltage as the third electrode 350. In this case, the second electrode 332 of the second sub-pixel P2 may be a cathode electrode.

4 and 10 show that the second electrode 331 of the first sub-pixel P1 and the second electrode 332 of the second sub-pixel P2 are disconnected without contacting each other, but are limited thereto. It doesn't work. The second electrodes 331 and 332 of each of the first and second sub-pixels P1 and P2 are cathode electrodes, and a common voltage may be applied thereto. The second electrodes 331 and 332 of each of the first sub-pixel P1 and the second sub-pixel P2 are formed to contact each other and may be electrically connected to each other.

Also, the second electrodes 332 and 333 may be disconnected without being continuously connected between the second sub-pixel P2 and the third sub-pixel P3 by the third shielding pattern 283. When the second electrodes 331, 332, and 333 are deposited on the entire surface, the second electrode 332 deposited on the second sub-pixel P2 is formed in the third shielding pattern 283 as shown in FIGS. 4 and 10. It may be cut off on the protrusion 283a of the third covering pattern 283 due to a step difference between the protrusion 283a of and the first emission layer 323.

The second electrode 333 deposited on the third sub-pixel P3 is a space between the protrusion 283a of the third masking pattern 283 and the first emission layer 323 as shown in FIGS. 4 and 10. It may be introduced and formed under the protrusion 283a of the third blocking pattern 283. In this case, the second electrode 333 of the third sub-pixel P3 may be deposited in a larger area than the first emission layer 323 under the protrusion 283a of the third blocking pattern 283. Accordingly, the second electrode 333 of the third sub-pixel P3 may be connected to the second connection electrode 250.

In the third sub-pixel P3, since the second electrode 333 is connected to the second connection electrode 250, the second electrode 333 and the first electrode 313 are electrically connected to each other through the second connection electrode 250. Can be connected to. Accordingly, when the third high potential voltage is applied to the first electrode 313, the second electrode 333 of the third sub-pixel P3 is applied with the same third high potential voltage as the first electrode 313. I can. In this case, the second electrode 333 of the third sub-pixel P3 may be an anode electrode.

In the display device 100 according to the exemplary embodiment, the second electrode 332 of the second sub-pixel P2 and the second electrode 333 of the third sub-pixel P3 do not contact each other and are disconnected. It is desirable. As described above, in the second sub-pixel P2, the second electrode 332 is a cathode electrode, and in the third sub-pixel P3, the second electrode 333 is an anode electrode. In this case, when the second electrode 332 of the second sub-pixel P2 and the second electrode 333 of the third sub-pixel P3 come into contact, the second electrode 332 of the second sub-pixel P2 A short circuit occurs between the second electrode 333 of the third sub-pixel P3 and the display device is not normally driven.

In addition, the second electrodes 331 and 333 are not continuously connected between the first sub-pixel P1 and the third sub-pixel P3 by the third blocking pattern 283 and the first blocking pattern 281. It can be broken. When the second electrodes 331, 332, and 333 are deposited on the entire surface, the second electrode 333 deposited on the third sub-pixel P3 becomes the third shielding pattern 283 as shown in FIGS. 5 and 10. May flow into the space between the protrusion 283a of the first emission layer 323 and the first emission layer 323, and may be formed under the protrusion 283a of the third blocking pattern 283.

In this case, the second electrode 333 of the third sub-pixel P3 may be deposited in a larger area than the first emission layer 323 under the protrusion 283a of the third blocking pattern 283. 5 illustrates that the second connection electrode 250 is not formed between the first sub-pixel P1 and the third sub-pixel P3, but is not limited thereto. As illustrated in FIG. 9, a second connection electrode 250 may be formed between the first sub-pixel P1 and the third sub-pixel P3. In this case, the second electrode 333 of the third sub-pixel P3 may be connected to the second connection electrode 250 between the first sub-pixel P1 and the third sub-pixel P3.

The second electrode 331 deposited on the first sub-pixel P1 is a space between the protrusion 281a of the first shielding pattern 281 and the first emission layer 321 as shown in FIGS. 5 and 10. It may be introduced and formed under the protrusion 281a of the first covering pattern 281. In this case, the second electrode 331 of the first sub-pixel P1 may be deposited in a larger area than the first emission layer 321 under the protrusion 281a of the first blocking pattern 281. Accordingly, the second electrode 331 of the first sub-pixel P1 may be connected to the first connection electrode 241.

In the first sub-pixel P1, since the second electrode 331 is connected to the first connection electrode 241, the second electrode 331 and the second electrode 331 are connected to the second electrode 331 through the first connection electrode 241 and the auxiliary power line 360. The three electrodes 350 may be electrically connected. Accordingly, when a low potential voltage is applied to the third electrode 350, the second electrode 331 of the first sub-pixel P1 may be applied with the same low potential voltage as the third electrode 350. In this case, the second electrode 331 of the first sub-pixel P1 may be a cathode electrode.

The second electrodes 331, 332, 333 are transparent metallic materials such as ITO and IZO that can transmit light, or magnesium (Mg), silver (Ag), or magnesium (Mg). It may be formed of a semi-transmissive conductive material such as an alloy of silver (Ag).

The second emission layer 340 is formed on the second electrode 330. The second emission layer 340 may include a hole transporting layer, a light emitting layer, and an electron transporting layer. In this case, in the second emission layer 340, holes and electrons move to the emission layer through the hole transport layer and the electron transport layer, respectively, and are combined with each other in the emission layer to emit light in a predetermined color.

The second emission layer 340 may be any one of a red emission layer emitting red light, a green emission layer emitting green light, a blue emission layer emitting blue light, and a yellow emission layer emitting yellow light, but is not limited thereto. .

However, the second emission layer 340 may emit light of a different color than the first emission layer 320. When the first emission layer 320 is an emission layer that emits light of a first color, the second emission layer 340 may be an emission layer that emits light of a second color different from the first color. For example, the first emission layer 320 may be a yellow emission layer emitting yellow light, and the second emission layer 340 may be a blue emission layer emitting blue light.

The second emission layer 340 is provided on each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3, and unlike the first emission layer 320, the first sub-pixel P1 , The second sub-pixel P2 and the third sub-pixel P3 are connected to each other. The second emission layer 340 may be formed while partially filling the space between the shielding patterns 281, 282, 283 and the second electrodes 331, 332, 333. In this case, an air gap AG may be formed in a space between the covering patterns 281, 282, 283 and the second electrodes 331, 332, and 333 in which the second emission layer 340 is not filled.

The third electrode 350 is formed on the second emission layer 340. The third electrode 350 may be made of a transparent metal material, a transflective metal material, or a metal material having a high reflectivity. When the display device 100 is made of a bottom emission method, the third electrode 350 is a laminated structure of aluminum and titanium (Ti/Al/Ti), a laminated structure of aluminum and ITO (ITO/Al/ITO), and Ag alloy , And a metal material having a high reflectivity such as a stacked structure of Ag alloy and ITO (ITO/Ag alloy/ITO). The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). When the display device 100 is made of a top emission type, the third electrode 350 is a transparent metal material such as ITO or IZO that can transmit light, or a transparent conductive material (TCO), or magnesium (Mg), silver ( Ag), or may be formed of a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). The third electrode 350 may be a cathode electrode.

As described above, in the display device 100 according to an exemplary embodiment of the present invention, a metal pattern, for example, connection electrodes 240 and 250 may be provided on the first substrate 111. In addition, the display device 100 according to an exemplary embodiment may include a first layer, for example, a second insulating layer 260 including an opening area exposing a part of the metal pattern on the metal pattern. In addition, the display device 100 according to an exemplary embodiment includes a second layer, for example, a covering pattern 280 including a protrusion on the first layer to cover a part of the opening area of the first layer. Can be provided. In this case, the first layer and the second layer may have an undercut structure.

The display device 100 according to an exemplary embodiment of the present invention uses an undercut structure consisting of a first layer and a second layer to form a first emission layer 320 and a second electrode between the sub-pixels P1, P2, and P3. Allows 330 to be disconnected without being connected to each other. In addition, the display device 100 according to an exemplary embodiment of the present invention includes the second emission layer 330 and the second emission layer 330 between the sub-pixels P1, P2, and P3 on which the undercut structure consisting of a first layer and a second layer is disposed. 3 The electrodes 340 are to be connected to each other.

In order to have such a structure, the thickness of the first layer may be set in consideration of the thickness of each of the first emission layer 320, the second electrode 330, the second emission layer 330, and the third electrode 340. have. When the thickness of the first layer is large, the second emission layer 330 may be disconnected without being connected to each other in addition to the first emission layer 320 and the second electrode 330 between the sub-pixels P1, P2, and P3. In this case, a short circuit may occur when the third electrode 350 comes into contact with the second electrode 330 or the connection electrodes 240 and 250 under the second layer.

이하의 두께를 가질 필요가 있다. 그러나, 제1 층은 제품에 따라 3500

이하의 두께로 줄이는데 한계가 있을 수 있다.To prevent this, the first layer has a thickness at which the second emission layer 330 can be connected between the sub-pixels P1, P2, and P3, for example, 3500

It is necessary to have the following thickness. However, the first layer is 3500 depending on the product

There may be limitations in reducing to the following thickness.

The display device 100 according to the exemplary embodiment of the present invention may have an effect of reducing the thickness of the first layer by forming the connection electrodes 240 and 250 to have a step difference. Specifically, in the display device 100 according to an exemplary embodiment of the present invention, the connection electrodes 240 and 250 may have a step difference in the opening regions OA1, OA2 and OA3 of the second insulating layer 260.

The first layer may be a second insulating layer 260 provided in the display device 100 according to an embodiment of the present invention, and the second layer may be a cover provided in the display device according to an embodiment of the present invention. It may be a pattern 280, but is not necessarily limited thereto. The second layer may be a single layer including the blocking pattern 280, or may be a plurality of layers including the blocking pattern 280 and the banks 315. Alternatively, the second layer may be a single layer including only the bank 315. Hereinafter, for convenience of description, it will be described that the second insulating layer 260 is the first layer and the covering pattern 280 is the second layer, but the present invention is not limited thereto.

Meanwhile, in FIGS. 10 to 14, the first connection electrode 242 and the second shielding pattern 282 disposed on one side of the second sub-pixel P2 are illustrated, but the descriptions below will be made in the first sub-pixel P1. The same may be applied to the first connection electrode 241 and the first shielding pattern 281 disposed on one side of ). In addition, the description of the first connection electrode 242 and the second shielding pattern 282 below is the second connection electrode 250 and the third shielding pattern disposed on at least one side of the third sub-pixel P3. The same can be applied to (283). Hereinafter, redundant descriptions will be omitted.

As illustrated in FIG. 10, a portion of the upper surface of the first connection electrode 240 is exposed in the first and second opening regions OA1 and OA2 of the second insulating layer 260. The exposed upper surface of the first connection electrode 240 includes a first surface 240a, a second surface 240b, and a third surface 240c. In this case, the first surface 240a of the first connection electrode 240 has a first height, and the second surface 240b of the first connection electrode 240 has a second height greater than the first height. Here, the height may be a vertical distance from the top surface of the first substrate 111. The third surface 240c of the first connection electrode 240 may be an inclined surface connecting the first surface 240a and the second surface 240b, but is not limited thereto. The third surface 240c of the first connection electrode 240 may be a concave surface connecting the first surface 240a and the second surface 240b as shown in FIG. 12.

The first surface 240a of the first connection electrode 240 overlaps at least a portion of the protrusion 280a of the covering pattern 280. In one embodiment, the first surface 240a of the first connection electrode 240 may overlap a part of the protrusion 280a of the covering pattern 280. In this case, the first surface 240a of the first connection electrode 240 may have an area smaller than the protrusion 280a of the covering pattern 280. In this case, the second surface 240b of the first connection electrode 240 may overlap the rest of the protrusion 282a of the covering pattern 282.

In another embodiment, the first surface 240a of the first connection electrode 240 may overlap all of the protrusions 280a of the covering pattern 280. The first surface 240a of the first connection electrode 240 may have the same area as the protrusion 280a of the covering pattern 280 or may have a larger area than the protrusion 280a of the covering pattern 280. In this case, the second surface 240b of the first connection electrode 240 may not overlap with the protrusion 280a of the covering pattern 280.

The first surface 240a of the first connection electrode 240 is provided under the protrusion 280a of the covering pattern 280. In this case, a height difference between the first surface 240a of the first connection electrode 240 and the lower surface of the protrusion 280a of the covering pattern 280 is the same as the thickness of the second insulating layer 260.

Meanwhile, the second surface 240b of the first connection electrode 240 may or may not be provided under the protrusion 280a of the covering pattern 280. In this case, the lower surface of the protrusion 280a of the covering pattern 280 must have a third height greater than the second height of the second surface 240b of the first connection electrode 240. That is, the second surface 240b of the first connection electrode 240 is formed at a height lower than the lower surface of the protrusion 280a of the covering pattern 280. This is for the first emission layer 320 and the second electrode 330 to flow into the space between the protrusion 280a of the covering pattern 280 and the first connection electrode 240.

Meanwhile, since the height of the second surface 240b of the first connection electrode 240 is larger than the first surface 240a of the first connection electrode 240, the second surface 240b of the first connection electrode 240 ) And the height difference between the lower surface of the protrusion 280a of the covering pattern 280 may be smaller than the thickness of the second insulating layer 260.

In the display device 100 according to an exemplary embodiment of the present invention, by adjusting the height of the second surface 240b of the first connection electrode 240, the first emission layer ( 320), the connection between the second electrode 330, the second emission layer 330, and the third electrode 340 may be controlled depending on the product.

Specifically, in the display device 100 according to the exemplary embodiment, the first emission layer 320 and the second electrode 330 are disconnected without being connected between the sub-pixels P1, P2, and P3. 2 The height of the second surface 240b of the first connection electrode 240 may be adjusted so that the emission layer 330 and the third electrode 340 may be connected to each other. That is, the display device 100 according to the exemplary embodiment of the present invention can reduce the separation distance between the first connection electrode 240 and the protrusion 280a of the covering pattern 280 without reducing the thickness of the second insulating layer 260. Can be adjusted.

Accordingly, in the display device 100 according to an exemplary embodiment, whether the first emission layer 320, the second electrode 330, the second emission layer 330, and the third electrode 340 are connected on the undercut structure. May be freely adjusted without limiting the thickness of the second insulating layer 260. The display device 100 according to an exemplary embodiment of the present invention may be applied to various products having a limit on the thickness of the second insulating layer 260.

Meanwhile, in the display device 100 according to an exemplary embodiment of the present invention, a step may be formed in the first connection electrode 240 and the second connection electrode 250 by using the stepped layer 200. For example, the stepped layer 200 may be patterned between the first substrate 111 and the first insulating layer 220. The stepped layer 200 includes a first stepped layer 201, a second stepped layer 202 and a third stepped layer 203.

The first stepped layer 201 may be formed along the first connection electrode 241 to overlap the first connection electrode 241 disposed on one side of the first sub-pixel P1. The first stepped layer 201 may not overlap with the first blocking pattern 281 as shown in FIG. 6, but is not limited thereto. The first stepped layer 201 may overlap a part of the first blocking pattern 281.

The first stepped layer 201 may be formed in a plurality of patterns having a predetermined length in the second direction (Y-axis direction) under the first connection electrode 241 as shown in FIG. 6, but is limited thereto. It doesn't work. As shown in FIG. 7, the first stepped layer 201 may be formed in a single line pattern extending in a second direction (Y-axis direction) under one first connection electrode 241.

The second stepped layer 202 may overlap with the first connection electrode 242 disposed on one side of the second sub-pixel P2 and may be formed along the first connection electrode 242. The second stepped layer 202 may not overlap with the second blocking pattern 282 as shown in FIG. 6, but is not limited thereto. The second stepped layer 202 may overlap a part of the second blocking pattern 282.

The second stepped layer 202 may be formed in a plurality of patterns having a predetermined length in the second direction (Y-axis direction) under the first connection electrode 242 as shown in FIG. 6, but is limited thereto. It doesn't work. The second stepped layer 202 may be formed as a single line pattern extending in the second direction (Y-axis direction) under the first connection electrode 242 as shown in FIG. 7.

The third stepped layer 203 overlaps the second connection electrode 250 disposed on at least one side of the third sub-pixel P3 as shown in FIGS. 8 and 9 to form the third sub-pixel P3. It can be formed to surround. The third stepped layer 203 may not overlap with the third blocking pattern 283, but is not limited thereto. The third stepped layer 203 may overlap a part of the third blocking pattern 283.

On the stepped layer 200, as shown in FIG. 10, a second insulating layer 220 including a buffer layer 222 and an interlayer insulating layer 224 may be sequentially formed. In this case, the buffer layer 222 and the interlayer insulating layer 224 may be formed on the stepped layer 200 to have a predetermined thickness. Due to the step difference generated by the stepped layer 200, the interlayer insulating layer 224 may also have a step equal to the thickness T1 of the stepped layer 200.

The connection electrodes 240 and 250 are formed on the interlayer insulating layer 224. Since the connection electrodes 240 and 250 are formed along a level difference between the interlayer insulating layer 224, the connection electrodes 240 and 250 also have a level difference.

As described above, the connection electrodes 240 and 250 have a step difference in the opening regions OA1, OA2, and OA3 of the second insulating layer 260, and the first surface 240a and the first surface having a first height. It includes a second surface 240b having a second height greater than the height, and a third surface 240c connecting the first surface 240a and the second surface 240b. The connection electrodes 240 and 250 may have a second surface 240b having a height greater than that of the first surface 240a in a region overlapping the stepped layer 200.

4, 5, and 10 illustrate that the connection electrodes 240 and 250 are provided on the front surface of the stepped layer 200, the present invention is not limited thereto.

The connection electrodes 240 and 250 may be provided on a part of the stepped layer 200 as shown in FIG. 11. The connection electrodes 240 and 250 may have a step difference due to the stepped layer 200 even if only a part of the stepped layer 200 is overlapped.

Meanwhile, in FIGS. 4, 5, and 10, it is shown that both the buffer layer 222 and the interlayer insulating layer 224 are formed to cover the stepped layer 200, but are not limited thereto.

보다 큰 경우에는 버퍼막(222) 및 층간 절연막(224) 중 적어도 하나가 단차층(200) 상에 형성되지 않을 수 있다. 연결전극(240, 250)은 단차층(200)의 두께(T2)가 충분히 두껍기 때문에 버퍼막(222) 및 층간 절연막(224) 중 적어도 하나가 형성되지 않더라도 개구 영역(OA1, OA2, OA3)에서 단차를 가질 수 있다.At least one of the buffer layer 222 and the interlayer insulating layer 224 may not be formed on the stepped layer 200 as shown in FIG. 12. The thickness T2 of the stepped layer 200 illustrated in FIG. 12 may be thicker than the thickness T1 of the stepped layer 200 illustrated in FIGS. 10 and 11. For example, the thickness T2 of the stepped layer 200 is 3500

In a larger case, at least one of the buffer layer 222 and the interlayer insulating layer 224 may not be formed on the stepped layer 200. Since the connection electrodes 240 and 250 have a sufficiently thick thickness T2 of the stepped layer 200, even if at least one of the buffer layer 222 and the interlayer insulating layer 224 is not formed, It can have a step difference.

For example, the interlayer insulating layer 224 may not be formed on the stepped layer 200. In this case, a step difference may occur in the connection electrodes 240 and 250 by each of the interlayer insulating layer 224 and the stepped layer 200. The connection electrodes 240 and 250 may have a concave third surface 240c formed between the first surface 240a overlapping the interlayer insulating layer 224 and the second surface 240b overlapping the stepped layer 200. have.

Meanwhile, the stepped layer 200 may be formed of the same material in the same layer as the light blocking layer 210.

The display device 100 according to an exemplary embodiment of the present invention is characterized in that only one of the first emission layer 320 and the second emission layer 340 emit light from each of the sub-pixels P1, P2, and P3.

More specifically, in the first sub-pixel P1, only the first emission layer 321 of the first emission layer 321 and the second emission layer 340 may emit light. In the first sub-pixel P1, since the second electrode 331 is connected to the first connection electrode 241, the second electrode 331 and the second electrode 331 are connected to the second electrode 331 through the first connection electrode 241 and the auxiliary power line 360. The three electrodes 350 may be electrically connected. When a low potential voltage is applied to the third electrode 350, the second electrode 331 of the first sub-pixel P1 may be applied with the same low potential voltage as the third electrode 350. Accordingly, in the first sub-pixel P1, the second emission layer 340 provided between the second electrode 331 and the third electrode 350 may not emit light.

Meanwhile, in the first sub-pixel P1, when a first high potential voltage is applied to the first electrode 311 and a low potential voltage is applied to the second electrode 331, the first electrode 311 and the second electrode The first emission layer 321 provided between the 331 may emit light with a predetermined brightness according to a predetermined current.

Only the first emission layer 322 of the first emission layer 322 and the second emission layer 340 may emit light in the second sub-pixel P2. In the second sub-pixel P2, since the second electrode 332 is connected to the first connection electrode 242, the second electrode 332 and the second electrode 332 are connected through the first connection electrode 242 and the auxiliary power line 360. The three electrodes 350 may be electrically connected. When a low potential voltage is applied to the third electrode 350, the second electrode 332 of the second sub-pixel P2 may be applied with the same low potential voltage as the third electrode 350. Accordingly, in the second sub-pixel P2, the second emission layer 340 provided between the second electrode 332 and the third electrode 350 may not emit light.

Meanwhile, in the second sub-pixel P2, when a second high potential voltage is applied to the first electrode 312 and a low potential voltage is applied to the second electrode 332, the first electrode 312 and the second electrode The first emission layer 322 provided between 332 may emit light with a predetermined brightness according to a predetermined current.

That is, the first sub-pixel P1 and the second sub-pixel P2 may both emit light of the same color from the first emission layers 321 and 322. The display device 100 according to an exemplary embodiment of the present invention may further include a color filter (not shown) to emit light of different colors from the first sub-pixel P1 and the second sub-pixel P2. I can.

The color filter (not shown) may include a first color filter disposed to correspond to the first sub-pixel P1 and a second color filter disposed to correspond to the second sub-pixel P2. The first color filter and the second color filter may transmit light of different colors.

For example, the first emission layers 321, 322, and 323 may be yellow emission layers that emit yellow light. The first color filter may be a red color filter that transmits red light, and the second color filter may be a green color filter that transmits green light. Accordingly, the first sub-pixel P1 may emit red light, and the second sub-pixel P2 may emit green light.

The color filter may be disposed under the first electrodes 311, 312, and 313 or on the third electrode 350 according to the light emission method of the display device 100. When the display device 100 is a bottom emission type, a color filter may be provided under the first electrodes 311, 312, and 313. When the display device 100 is a top emission type, a color filter may be provided on the third electrode 350.

Only the second emission layer 340 of the first emission layer 323 and the second emission layer 340 may emit light in the third sub-pixel P3. In the third sub-pixel P3, since the second electrode 333 is connected to the second connection electrode 250, the first electrode 313 and the second electrode 333 are electrically connected to each other through the second connection electrode 250. Can be connected to. When the third high potential voltage is applied to the first electrode 313, the second electrode 333 of the third sub-pixel P3 may be applied with the same third high potential voltage as the first electrode 313. Accordingly, in the third sub-pixel P3, the first emission layer 323 provided between the first electrode 313 and the second electrode 333 may not emit light.

Meanwhile, in the third sub-pixel P3, when a third high potential voltage is applied to the second electrode 333 and a low potential voltage is applied to the third electrode 350, the second electrode 333 and the third electrode The second emission layer 340 provided between 350 may emit light with a predetermined brightness according to a predetermined current.

For example, the third sub-pixel P3 may be a blue emission layer emitting blue light. In this case, the display device 100 may implement a blue sub-pixel without a separate color filter at a position corresponding to the third sub-pixel P3.

As described above, in the display device 100 according to an exemplary embodiment of the present invention, only the first emission layers 321 and 322 emit light in the first sub-pixel P1 and the second sub-pixel P2, and the third sub-pixel P1 and the second sub-pixel P2 emit light. Only the second emission layer 340 may emit light in the pixel P3. Accordingly, the display device 100 according to an exemplary embodiment of the present invention significantly reduces power consumption compared to emitting all of the first emission layers 321, 322, 323 and the second emission layer 340 in all sub-pixels. Can be reduced.

In addition, in the display device 100 according to an exemplary embodiment, the first emission layers 321, 322, 323 and the second emission layer 340 are formed on the entire surface of the sub-pixels P1, P2, and P3 without a mask. do. Accordingly, the display device 100 according to an exemplary embodiment of the present invention can solve a problem in that different light emitting layers are patterned for each of the sub-pixels P1, P2, and P3 using a mask.

In addition, the display device 100 according to an exemplary embodiment of the present invention uses a first layer and a second layer having an undercut structure to provide the first emission layer 320 and the first emission layer between the sub-pixels P1, P2, and P3. 2 Make sure that the electrode 330 is disconnected without being connected. For example, in the display device 100 according to the exemplary embodiment, the second insulating layer 260 and the covering pattern 280 may have an undercut structure. The display device 100 according to an exemplary embodiment of the present invention includes a first emission layer 320 and a second electrode on the first substrate 111 on which the second insulating layer 260 and the shielding pattern 280 having an undercut structure are formed. 330 may be formed on the entire surface without a mask. The first emission layer 320 and the second electrode 330 may be disconnected between the sub-pixels P1, P2, and P3 due to the undercut structure.

In the display device 100 according to an exemplary embodiment of the present invention, the connection electrodes 240 and 250 are formed to have a step difference in the opening regions OA1, OA2 and OA3 of the second insulating layer 260. In the display device 100 according to an exemplary embodiment of the present invention, the first emission layer 320, the second electrode 330, the second emission layer 330, and the undercut structure are formed by using a step difference between the connection electrodes 240 and 250. Whether or not the third electrode 340 is connected may be freely controlled without limiting the thickness of the second insulating layer 260. Accordingly, the display device 100 according to an exemplary embodiment of the present invention may be applied to various products having a limit on the thickness of the second insulating layer 260.

Meanwhile, in the display device 100 according to an exemplary embodiment of the present invention, a stepped layer 200 may be formed between the first substrate 111 and the connection electrodes 240 and 250. In the display device 100 according to an exemplary embodiment of the present invention, the step difference between the connection electrodes 240 and 250 may be easily adjusted by using the thickness of the stepped layer 200.

17A to 17C relate to a display device according to another embodiment of the present invention, which relates to a head mounted display (HMD) device. 17A is a schematic perspective view, FIG. 17B is a schematic plan view of a virtual reality (VR) structure, and FIG. 17C is a schematic cross-sectional view of an Augmented Reality (AR) structure.

As can be seen from FIG. 17A, the head mounted display device according to the present invention includes a storage case 10 and a head mounting band 30.

The storage case 10 houses components such as a display device, a lens array, and an eyepiece therein.

The head mounting band 30 is fixed to the storage case 10. The head mounting band 30 is illustrated to be formed to surround the upper surface of the user's head and both sides, but is not limited thereto. The head mounting band 30 is for fixing the head mounted display to the user's head, and may be replaced with a structure in the form of an eyeglass frame or a helmet.

As can be seen from FIG. 17B, the head-mounted display device having a virtual reality (VR) structure according to the present invention includes a left-eye display device 12, a right-eye display device 11, a lens array 13, and a left-eye eyepiece. 20a) and a right eye eyepiece 20b.

The left-eye display device 12, the right-eye display device 11, the lens array 13, and the left-eye eyepiece 20a and the right-eye eyepiece 20b are accommodated in the storage case 10 described above.

The left-eye display device 12 and the right-eye display device 11 may display the same image, and in this case, the user may view the 2D image. Alternatively, the left-eye display device 12 may display a left-eye image and the right-eye display device 11 may display a right-eye image. In this case, the user can view a stereoscopic image. Each of the left-eye display device 12 and the right-eye display device 11 may be formed of the display device of FIGS. 1 to 16 described above. In this case, an upper portion corresponding to a surface on which an image is displayed in FIGS. 1 to 16, for example, a color filter layer (not shown) faces the lens array 13.

The lens array 13 may be provided between the left-eye eyepiece 20a and the left-eye display device 12 while being spaced apart from each of the left-eye eyepiece 20a and the left-eye display device 12. That is, the lens array 13 may be positioned in front of the left eye eyepiece 20a and behind the left eye display device 12. In addition, the lens array 13 may be provided between the right eye eye lens 20b and the right eye display device 11 while being spaced apart from each of the right eye eye lens 20b and the right eye display device 11. That is, the lens array 13 may be located in front of the right eye eyepiece 20b and behind the right eye display device 11.

The lens array 13 may be a micro lens array. The lens array 13 may be replaced with a pin hole array. An image displayed on the left-eye display device 12 or the right-eye display device 11 due to the lens array 13 may be enlarged and viewed by the user.

The user's left eye LE may be positioned on the left eyepiece 20a, and the user's right eye RE may be positioned on the right eyepiece 20b.

As can be seen from FIG. 17C, the head mounted display device having an Augmented Reality (AR) structure according to the present invention includes a left-eye display device 12, a lens array 13, a left eye eyepiece 20a, and a transmission reflector 14. , And a transmission window 15. In FIG. 17C, for convenience, only the left-inside configuration is shown, and the right-inside configuration is the same as the left-inside configuration.

The left-eye display device 12, the lens array 13, the left-eye eyepiece 20a, the transmission reflection portion 14, and the transmission window 15 are accommodated in the storage case 10 described above.

The left eye display device 12 may be disposed on one side of the transmission reflective unit 14, for example, on the upper side, without covering the transmission window 15. Accordingly, the left-eye display device 12 may provide an image to the transmissive reflector 14 without covering an external background visible through the transmissive window 15.

The left eye display device 12 may be formed of the display device according to FIGS. 1 to 16 described above. In this case, an upper portion corresponding to a surface on which an image is displayed in FIGS. 1 to 16, for example, a color filter (not shown), faces the transmission reflector 14.

The lens array 13 may be provided between the left eye eyepiece 20a and the transmission reflector 14.

The user's left eye is located in the left eye eyepiece 20a.

The transmission reflection part 14 is disposed between the lens array 13 and the transmission window 15. The transmission reflection part 14 may include a reflective surface 14a that transmits a part of light and reflects another part of the light. The reflective surface 14a is formed so that the image displayed on the left eye display device 12 proceeds to the lens array 13. Accordingly, the user can see both an external background and an image displayed by the left eye display device 12 through the transmission layer 15. That is, since the user can view the real background and the virtual image as a single image, an Augmented Reality (AR) can be implemented.

The transmissive layer 15 is disposed in front of the transmissive reflective portion 14.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting. The scope of protection of the present invention should be interpreted by the claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

100: display device 110: display panel
111: first substrate 112: second substrate
140: source drive IC 150: flexible film
160: circuit board 170: timing control unit
200: stepped layer 210: light-shielding layer
220: first insulating layer 230: thin film transistor
240: first connecting electrode 250: second connecting electrode
260: second insulating film 270: planarization film
281, 282, 283: shielding pattern 311, 312, 313: first electrode
321, 322, 323: first emission layer 331, 332, 333: second electrode
340: second emission layer 350: third electrode

Claims (18)

A substrate including a display area in which first and second sub-pixels are disposed, and a non-display area surrounding the display area;
A first electrode provided in each of the first sub-pixel and the second sub-pixel on the substrate;
A first emission layer provided on the first electrode to emit light of a first color;
A second electrode provided on the first emission layer;
A second emission layer provided on the second electrode to emit light of a second color;
A third electrode provided on the second emission layer;
A connection electrode provided between the substrate and the first electrode and electrically connecting the second electrode and the third electrode or electrically connecting the first electrode and the second electrode;
A first layer provided on the connection electrode and including an opening region exposing a portion of the connection electrode; And
A second layer provided on the first layer and including a protruding portion protruding to cover a part of the opening area,
The connection electrode has a step difference in the opening area. The method of claim 1,
The connection electrode has a portion of an upper surface exposed in the opening area, and the exposed upper surface includes a first surface and a second surface having a height greater than that of the first surface. The method of claim 2,
The exposed upper surface of the connection electrode includes a third surface connecting the first surface and the second surface, and the third surface is inclined or concave. The method of claim 2,
The second surface of the connection electrode is smaller in height than the lower surface of the second layer. The method of claim 1,
Further comprising a stepped layer provided between the connection electrode and the substrate,
The connection electrode has a level difference in the opening area by the level difference layer. The method of claim 5,
One end of the stepped layer is disposed under the connection electrode exposed in the opening area. The method of claim 1,
The connection electrode includes a first connection electrode disposed on one side of the first sub-pixel,
A display device in which a second electrode provided in the first sub-pixel is electrically connected to the third electrode through the first connection electrode. The method of claim 7,
The second electrode of the first sub-pixel is connected to the first connection electrode under the second layer. The method of claim 7,
Further comprising an auxiliary power line disposed in the non-display area and connected to the third electrode,
The first connection electrode is connected to the second electrode of the first sub-pixel disposed in the display area, extends from the display area to the auxiliary power line disposed in the non-display area, and is connected to the auxiliary power line. Display device. The method of claim 1,
The connection electrode includes a second connection electrode disposed on one side of the second sub-pixel,
A display device in which a second electrode provided in the second sub-pixel is electrically connected to a first electrode provided in the second sub-pixel through the second connection electrode. The method of claim 10,
The second electrode of the second sub-pixel is connected to the second connection electrode under the second layer. The method of claim 10,
An opening area is formed in the first layer to surround the second sub-pixel. The method of claim 1,
The second layer is formed on the same layer as the first electrode and includes a metal layer spaced apart from the first electrode. The method of claim 1,
Further comprising a bank covering the end of the first electrode,
The second layer includes an organic layer extending from the bank. The method of claim 1,
A driving transistor provided in each of the first and second sub-pixels and including an active layer, a gate electrode, a source electrode, and a drain electrode,
The connection electrode is formed on the same layer as one of the active layer, the gate electrode, the source electrode, and the drain electrode. The method of claim 1,
The first sub-pixel emits only the first emission layer, and the second sub-pixel emits only the second emission layer. The method of claim 1,
A display device in which a second emission layer provided on the connection electrode is connected to a second emission layer provided on the second layer. A metal pattern provided on the substrate;
A first layer provided on the metal pattern and having an opening region exposing a portion of the metal pattern; And
A second layer provided on the first layer and including a protruding portion protruding to cover a part of the opening area,
The metal pattern has a step difference in the opening area.

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