KR20210006482A - Display device and method for fabricating the same - Google Patents

Abstract

Provided is a display device for improving defects occurring in a touch line wiring patterning process, which comprises: a base layer; an element layer disposed on the base layer and including light emitting elements; an encapsulation layer disposed on the element layer; an input detection layer disposed on the encapsulation layer and including electrodes and signal wires electrically connected to the electrodes, respectively; a sub-layer spaced disposed on the base layer and spaced apart from the element layer, and including a first portion having a first thickness, a second portion having a second thickness smaller than the first thickness, and a third portion disposed between the first portion and the second portion; and a capping pattern disposed on the third portion of the sub-layer.

Description

Display device and its manufacturing method TECHNICAL FIELD

The present invention relates to a display device and a method of manufacturing the same, and more particularly, to a display device and a method of manufacturing the same, in which defects occurring in a touch line wiring patterning process are improved.

Various display devices used in multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, and game consoles have been developed. Input devices for display devices include a keyboard or a mouse. In addition, recently, display devices have a touch sensing unit as an input device.

The present invention relates to a display device and a method of manufacturing the same, and more particularly, to a display device and a method of manufacturing the same, in which defects occurring in a touch line wiring patterning process are improved.

A display device according to an embodiment of the present invention includes a base layer, a device layer disposed on the base layer and including light-emitting elements, an encapsulation layer disposed on the device layer, and electrodes and the electrodes. An input sensing layer including signal wires electrically connected to each of the input sensing layers, a first portion disposed on the base layer, spaced apart from the element layer, and having a first thickness, and a second thickness having a second thickness less than the first thickness A sub-layer including a portion, and a third portion disposed between the first portion and the second portion, and a capping pattern disposed on the third portion of the sub-layer.

The input sensing layer includes a first insulating layer disposed directly on the encapsulation layer, the first insulating layer extends toward the sub-layer to cover the sub-layer, and the capping pattern is the first insulating layer Can be placed on top.

The input sensing layer may further include a second insulating layer disposed on the first insulating layer and covering the capping pattern.

On a plane, the encapsulation layer may be spaced apart from the sub-layer.

The sub-layer includes a first layer and a second layer disposed over the second layer, each of the first portion and the third portion includes the first layer and the second layer, and the second The portion may comprise the first layer.

When viewed on a plane, the capping pattern may overlap the third portion.

When viewed in plan view, the capping pattern may overlap the first portion and the third portion.

The capping pattern may include a conductive material.

The capping pattern may include the same material as the signal lines.

The signal wires may be spaced apart from the capping pattern, and the signal wires may overlap the second portion.

The sub-layer may extend in a first direction, and a portion of the signal lines overlapping the sub-layer may extend in a second direction crossing the first direction.

The sub-layer may be spaced apart from the electrodes.

A display device according to an embodiment of the present invention includes a base layer, a device layer disposed on the base layer and including light emitting devices, an encapsulation layer disposed on the device layer, an input sensing layer disposed on the encapsulation layer, and the base layer. It may include a sub-layer disposed above and including a stepped portion, and a capping pattern disposed on the stepped portion of the sub-layer.

The input sensing layer includes a first insulating layer disposed directly on the encapsulation layer, the first insulating layer extends toward the sub-layer to cover the sub-layer, and the capping pattern is formed on the first insulating layer. Can be placed.

The input sensing layer may further include a second insulating layer disposed on the first insulating layer and covering the capping pattern.

The encapsulation layer may be spaced apart from the sub-layer. .

The present invention prevents leakage of organic materials inside the bank during phosphorus etching due to insufficient thickness of the photoresist layer formed on the boundary by forming a capping pattern on the inclined boundary portion of the bank, resulting in phenomena such as film lifting. It can be prevented from occurring.

1 is a perspective view illustrating a first operation of a display device according to an exemplary embodiment of the present invention.
2A is a perspective view illustrating a second operation of a display device according to an exemplary embodiment of the present invention.
2B is a perspective view illustrating a third operation of a display device according to an exemplary embodiment of the present invention.
2C is a cross-sectional view of a display device according to an exemplary embodiment of the present invention.
3A and 3B are perspective views of a display device according to an exemplary embodiment of the present invention.
4A is a cross-sectional view of a display module according to an embodiment of the present invention.
4B is a plan view of an organic light emitting display panel according to an exemplary embodiment of the present invention.
5 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present invention.
6A and 6B are partial cross-sectional views of an organic light emitting display panel according to an exemplary embodiment of the present invention.
7A to 7C are cross-sectional views of thin film encapsulation layers according to an embodiment of the present invention.
8A is a cross-sectional view of a touch sensing unit according to an embodiment of the present invention.
8B to 8E are plan views of a touch sensing unit according to an embodiment of the present invention.
8F is a partially enlarged view of the AA area of FIG. 8E.
9 is a cross-sectional view taken along line AA′ of FIG. 8E.
10A is a cross-sectional view taken along line BB′ of FIG. 8E.
10B is a cross-sectional view of a bank BAK according to another embodiment of the present invention.
11 is a perspective view of a portion of the bank.
12A to 12G are diagrams illustrating a process of forming a first capping pattern on a bank.
13A to 13C are plan views for explaining another embodiment of the present invention.
14 is a cross-sectional view for explaining another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present specification, when a component (or region, layer, part, etc.) is referred to as “on”, “connected”, or “coupled” to another component, it is directly connected/ It means that it can be combined or a third component can be arranged between them.

The same reference numerals refer to the same elements. In addition, in the drawings, thicknesses, ratios, and dimensions of components are exaggerated for effective description of technical content. “And/or” includes all combinations of one or more that the associated configurations may be defined.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. These terms are used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In addition, terms such as "below", "bottom", "above", "upper", and the like are used to describe the relationship between components shown in the drawings. The terms are relative concepts and are described based on the directions indicated in the drawings.

Terms such as "comprise" or "have" are intended to designate the presence of a feature, number, step, action, component, part, or combination thereof described in the specification, and one or more other features, numbers, or steps. It is to be understood that it does not preclude the possibility of addition or presence of, operations, components, parts, or combinations thereof.

1 is a perspective view illustrating a first operation of a display device DD according to an exemplary embodiment of the present invention. 2A is a perspective view illustrating a second operation of the display device DD according to an exemplary embodiment of the present invention. 2B is a perspective view illustrating a third operation of the display device DD according to an exemplary embodiment of the present invention.

As illustrated in FIG. 1, in the first operation mode, the display surface IS on which the image IM is displayed is parallel to a plane defined by the first and second direction axes DR1 and DR2. The third direction axis DR3 indicates the normal direction of the display surface IS, that is, the thickness direction of the display device DD. The front surface (or upper surface) and the rear surface (or lower surface) of each member are divided by a third direction axis DR3. However, the directions indicated by the first to third direction axes DR1, DR2, and DR3 are relative concepts and may be converted to other directions. Hereinafter, the first to third directions refer to the same reference numerals as directions indicated by the first to third direction axes DR1, DR2, and DR3, respectively.

1, 2A, and 2B illustrate a foldable display device as an example of the flexible display device DD. However, the present invention may be a rollable display device or a banded display device, and is not particularly limited. In addition, although the flexible display device is illustrated in the present embodiment, the present invention is not limited thereto. The display device DD according to the present exemplary embodiment may be a flat rigid display device. The flexible display device DD according to the present invention may be used in large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as mobile phones, tablets, car navigation systems, game consoles, and smart watches.

As illustrated in FIG. 1, the display surface IS of the flexible display device DD may include a plurality of areas. The flexible display device DD includes a display area DD-DA in which the image IM is displayed and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA is an area in which an image is not displayed. 1 illustrates a vase as an example of the image IM. As an example, the display area DD-DA may have a rectangular shape. The non-display area DD-NDA may surround the display area DD-DA. However, the present invention is not limited thereto, and the shape of the display area DD-DA and the shape of the non-display area DD-NDA may be relatively designed.

1, 2A, and 2B, the display device DD may include a plurality of areas defined according to an operation type. The display device DD includes a bending area BA that is bent on the basis of the bending axis BX, a first non-bending area NBA1 that is not bent, and a second non-bending area NBA2. Can include. As shown in FIG. 2A, the display device DD is inner bending so that the display surface IS of the first non-bending area NBA1 and the display surface IS of the second non-bending area NBA2 face each other. -bending). As shown in FIG. 2B, the display device DD may be outer-bending so that the display surface IS is exposed to the outside.

In an exemplary embodiment of the present invention, the display device DD may include a plurality of bending areas BA. In addition, the bending area BA may be defined to correspond to a form in which the user manipulates the display device DD. For example, unlike FIGS. 2A and 2B, the bending area BA may be defined parallel to the first direction axis DR1 or may be defined in a diagonal direction. The area of the bending area BA is not fixed and may be determined according to the radius of curvature. In an embodiment of the present invention, the display device DD may be configured to repeat only the operation modes shown in FIGS. 1 and 2A.

2C is a cross-sectional view of a display device DD according to an exemplary embodiment of the present invention. 2 illustrates a cross section defined by the second direction axis DR2 and the third direction axis DR3.

As shown in Figure 2c, The display device DD includes a protective film PM, a display module DM, an optical member LM, a window WM, a first adhesive member AM1, a second adhesive member AM2, and a third adhesive member. (AM3) is included. The display module DM is disposed between the protective film PM and the optical member LM. The optical member LM is disposed between the display module DM and the window WM. The first adhesive member AM1 couples the display module DM and the protective film PM, the second adhesive member AM2 couples the display module DM and the optical member LM, and the third adhesive member AM3 couples the optical member LM and the window WM.

The protective film PM protects the display module DM. The protective film PM provides a first outer surface OS-L exposed to the outside, and provides an adhesive surface adhered to the first adhesive member AM1. The protective film PM prevents external moisture from penetrating into the display module DM and absorbs an external shock.

The protective film PM may include a plastic film as a base substrate. Protective film (PM) is polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), poly Phenylene sulfide (PPS), polyarylate (polyarylate), polyimide (PI, polyimide), polycarbonate (PC, polycarbonate), poly(arylene ethersulfone)) and combinations thereof It may include a plastic film including any one selected from the group consisting of.

The material constituting the protective film PM is not limited to plastic resins, and may include an organic/inorganic composite material. The protective film PM may include a porous organic layer and an inorganic material filled in the pores of the organic layer. The protective film PM may further include a functional layer formed on the plastic film. The functional layer may include a resin layer. The functional layer may be formed by a coating method. In an embodiment of the present invention, the protective film PM may be omitted.

The window WM may include a plastic film. The window WM may have a multi-layered structure. The window WM may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. The window WM may further include a bezel pattern. The multilayer structure may be formed through a continuous process or an adhesion process using an adhesive layer.

The optical member LM reduces reflectance of external light. The optical member LM may include at least a polarizing film. The optical member LM may further include a retardation film. In an embodiment of the present invention, the optical member LM may be omitted.

The display module DM may include an organic light emitting display panel DP and a touch sensing unit TS. The touch sensing unit TS is directly disposed on the organic light emitting display panel DP. In the present specification, "directly arranged" means that it is formed by a continuous process, excluding attachment using a separate adhesive layer.

The organic light-emitting display panel DP generates an image (IM, see FIG. 1) corresponding to the input image data. The organic light emitting display panel DP provides a first display panel surface BS1-L and a second display panel surface BS1-U facing in the thickness direction DR3. In the present embodiment, the organic light emitting display panel DP has been exemplarily described, but the display panel is not limited thereto.

The touch sensing unit TS acquires coordinate information of an external input. The touch sensing unit TS may detect an external input using a capacitive method.

Although not shown separately, the display module DM according to an embodiment of the present invention may further include an antireflection layer. The antireflection layer may include a color filter or a stacked structure of a conductive layer/insulating layer/conductive layer. The antireflection layer may reduce external light reflectance by absorbing, destructive interference, or polarizing light incident from the outside. The antireflection layer may replace the function of the optical member LM.

Each of the first adhesive member AM1, the second adhesive member AM2, and the third adhesive member AM3 is an optically clear adhesive film (OCA) or optically clear adhesive resin (OCR) Alternatively, it may be an organic adhesive layer such as a pressure sensitive adhesive film (PSA). The organic adhesive layer may include an adhesive material such as polyurethane-based, polyacrylic-based, polyester-based, polyepoxy-based, and polyvinyl acetate-based. As a result, the organic adhesive layer corresponds to one of the organic layers.

Although not shown separately, the display device DD may further include a frame structure supporting the functional layers to maintain the states shown in FIGS. 1, 2A, and 2B. The frame structure may include an articulated structure or a hinge structure.

3A and 3B are perspective views of a display device DD-1 according to an exemplary embodiment of the present invention. 3A illustrates the display device DD-1 in an unfolded state, and FIG. 3B illustrates the display device DD-1 in a bent state.

The display device DD-1 may include one bending area BA and one non-bending area NBA. The non-display area DD-NDA of the display device DD-1 may be bent. However, in an exemplary embodiment of the present invention, the bending area of the display device DD-1 may be changed.

Unlike the display device DD illustrated in FIGS. 1, 2A, and 2B, the display device DD-1 according to the present exemplary embodiment may be fixed and operated in one form. The display device DD-1 may operate in a bent state as illustrated in FIG. 3B. The display device DD-1 may be fixed to a frame or the like in a bent state, and the frame may be coupled to the housing of the electronic device.

The display device DD-1 according to the present exemplary embodiment may have the same cross-sectional structure as illustrated in FIG. 2C. However, the non-bending area NBA and the bending area BA may have different stacked structures. The non-bending area NBA may have the same cross-sectional structure as shown in FIG. 2C, and the bending area BA may have a different cross-sectional structure than that shown in FIG. 2C. The optical member LM and the window WM may not be disposed in the bending area BA. That is, the optical member LM and the window WM may be disposed only in the non-bending area NBA. The second adhesive member AM2 and the third adhesive member AM3 may also be not disposed in the bending area BA.

4A is a cross-sectional view of a display module DM according to an embodiment of the present invention. 4B is a plan view of an organic light emitting display panel DP according to an exemplary embodiment of the present invention. 5 is an equivalent circuit diagram of a pixel PX according to an exemplary embodiment of the present invention. 6A and 6B are partial cross-sectional views of an organic light emitting display panel DP according to an exemplary embodiment of the present invention.

As shown in FIG. 4A, the organic light emitting display panel DP includes a base layer SUB, a circuit layer DP-CL disposed on the base layer SUB, a device layer DP-OLED, and a thin film encapsulation. Layer (TFE). The base layer SUB may include at least one plastic film. The base layer SUB is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic/inorganic composite material substrate.

The circuit layer DP-CL may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the circuit layer DP-CL may constitute signal lines or a control circuit of a pixel. The device layer DP-OLED includes organic light emitting diodes. The thin film encapsulation layer (TFE) includes an inorganic layer and an organic layer. The thin film encapsulation layer TFE may include at least two inorganic layers and an organic layer disposed therebetween. The inorganic layers protect the light emitting device layer (DP-OLED) from moisture/oxygen, and the organic layer protects the light emitting device layer (DP-OLED) from foreign substances such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxy nitride layer, and a silicon oxide layer. The organic layer may include an acrylic organic material, but is not limited thereto.

The touch sensing unit TS is directly disposed on the thin film encapsulation layer TFE. The touch sensing unit TS includes touch sensors and touch signal lines. The touch sensors and the touch signal lines may have a single layer or multilayer structure.

The touch sensors and touch signal lines may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The touch sensors and the touch signal lines may include a metal layer, such as molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The touch sensors and the touch signal lines may have the same layer structure or different layer structures. Details of the touch sensing unit TS will be described later.

4B is a plan view of an organic light emitting display panel DP according to an embodiment of the present invention, and FIG. 5 is an equivalent circuit diagram of a pixel PX according to an embodiment of the present invention.

As shown in FIG. 4B, the organic light emitting display panel DP includes a display area DA and a non-display area NDA on a plane. The display area DA and the non-display area NDA of the organic light emitting display panel DP are the display area DD-DA (see FIG. 1) and the non-display area DD-NDA of the display device DD (see FIG. 1). , See FIG. 1) respectively. The display area DA and the non-display area NDA of the organic light emitting display panel DP are the display area DD-DA (see FIG. 1A) and the non-display area DD-NDA of the display device DD (see FIG. 1). , See FIG. 1), and may be changed according to the structure/design of the organic light emitting display panel DP.

The organic light emitting display panel DP includes a plurality of pixels PX. An area in which the plurality of pixels PX are disposed is defined as the display area DA. In the present embodiment, the non-display area NDA may be defined along the edge of the display area DA.

The organic light emitting display panel DP includes gate lines GL, data lines DL, emission lines EL, control signal lines SL-D, initialization voltage lines SL-Vint, and voltage lines. SL-VDD), and a first pad PD1, and a power supply line E-VSS.

The gate lines GL are respectively connected to a corresponding pixel PX among the plurality of pixels PX, and the data lines DL are respectively connected to a corresponding pixel PX among the plurality of pixels PX. do. Each of the emission lines EL may be arranged in parallel with a corresponding one of the gate lines GL. The control signal line SL-D may provide control signals to the gate driving circuit GDC. The initialization voltage line SL-Vint may provide an initialization voltage to the plurality of pixels PX. The voltage line SL-VDD is connected to the plurality of pixels PX and may provide a first voltage to the plurality of pixels PX. The voltage line SL-VDD may include a plurality of lines extending in the first direction DR1 and a plurality of lines extending in the second direction DR2. The power supply line E-VSS may be disposed in the non-display area NDA to surround three side surfaces of the display area DA. A common voltage (eg, a second voltage) may be provided to the plurality of pixels PX of the power supply line E-VSS. The common voltage may be a voltage lower than the first voltage.

A gate driving circuit GDC to which the gate lines GL and the light emitting lines EL are connected may be disposed on one side of the non-display area NDA. Some of the gate lines GL, the data lines DL, the emission lines EL, the control signal line SL-D, the initialization voltage line SL-Vint, and the voltage line are disposed on the same layer, Some are placed on different layers.

The first pad PD may be connected to ends of the data lines DL, the control signal line SL-D, the initialization voltage line SL-Vint, and the voltage line SL-VDD.

FIG. 5 exemplarily illustrates an i-th pixel PXi connected to a k-th data line DLk among a plurality of data lines DL (refer to FIG. 4B ).

The i-th pixel PXi includes an organic light emitting diode OLED and a pixel driving circuit that controls the organic light emitting diode. The driving circuit may include seven thin film transistors T1 to T7 and one storage capacitor Cst.

The driving transistor controls the driving current supplied to the organic light emitting diode (OLED). The output electrode of the second transistor T2 is electrically connected to the organic light emitting diode OLED. The output electrode of the second transistor T2 may directly contact the anode of the organic light emitting diode OLED or may be connected via another transistor (the sixth transistor T6 in this embodiment).

The control electrode of the control transistor may receive a control signal. The control signals applied to the i-th pixel PXi include the i-1th gate signal Si-1, the i-th gate signal Si, the i+1th gate signal Si+1, and the data signal Dk. And an i-th emission control signal Ei. In an embodiment of the present invention, the control transistor may include a first transistor T1 and third to seventh transistors T3 to T7.

The first transistor T1 includes an input electrode connected to the k-th data line DLk, a control electrode connected to the i-th gate line GLi, and an output electrode connected to the output electrode of the second transistor T2. do. The first transistor T1 is turned on by a gate signal Si (hereinafter referred to as i-th gate signal) applied to the i-th gate line GLi, and a data signal Dk applied to the k-th data line DLk Is provided to the storage capacitor Cst. 6A is a partial cross-sectional view of an organic light emitting display panel according to an exemplary embodiment of the present invention. 6B is a partial cross-sectional view of an organic light emitting display panel according to an exemplary embodiment of the present invention. Specifically, FIG. 6A is a cross-sectional view of a portion corresponding to the first transistor T1 of the equivalent circuit shown in FIG. 5. 6B is a cross-sectional view of portions corresponding to the second transistor T2, the sixth transistor T6 and the organic light emitting diode OLED of the equivalent circuit shown in FIG. 5.

6A and 6B, a circuit layer DP-CL is disposed on the base layer SUB. Although not shown separately, functional layers may be further disposed on one surface of the base layer SUB. The functional layers include at least one of a barrier layer and a buffer layer.

On the base layer SUB, the semiconductor pattern OSP1 of the first transistor T1 (hereinafter referred to as a first semiconductor pattern), the semiconductor pattern of the second transistor T2 (hereinafter referred to as OSP2: a second semiconductor pattern), and a sixth transistor T6 ) Of the semiconductor pattern OSP6 (hereinafter referred to as a sixth semiconductor pattern) is disposed. The first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6 may be selected from amorphous silicon, polysilicon, and metal oxide semiconductors.

A first insulating layer 10 may be disposed on the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6. 6B and 6C exemplarily show that the first insulating layer 10 is provided in the form of a layer covering the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6. However, the first insulating layer 10 may be provided as a pattern disposed corresponding to the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6.

The first insulating layer 10 may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer, a silicon oxy nitride layer, and a silicon oxide layer.

On the first insulating layer 10, the control electrode GE1 (hereinafter, the first control electrode) of the first transistor T1, the control electrode GE2 (hereinafter, the second control electrode) of the second transistor T2, and the sixth A control electrode GE6 (hereinafter, a sixth control electrode) of the transistor T6 is disposed. The first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6 may be manufactured according to the same photolithography process as the gate lines GL (refer to FIG. 5A).

A second insulating layer 20 may be disposed on the first insulating layer 10 to cover the first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6. The second insulating layer 20 may provide a flat top surface. The second insulating layer 20 may include an organic material and/or an inorganic material.

On the second insulating layer 20, the input electrode SE1 (hereinafter, the first input electrode) and the output electrode DE1 (first output electrode) of the first transistor T1, and the input electrode of the second transistor T2 ( SE2: hereinafter, a second input electrode) and an output electrode (DE2: a second output electrode), an input electrode (SE6: hereinafter, a sixth input electrode) and an output electrode (DE6: a sixth output electrode) of the sixth transistor T6 ) Is placed.

The first input electrode SE1 and the first output electrode DE1 have a first through hole CH1 and a second through hole CH2 penetrating the first insulating layer 10 and the second insulating layer 20. They are respectively connected to the first semiconductor pattern OSP1 through. The second input electrode SE2 and the second output electrode DE2 have a third through hole CH3 and a fourth through hole CH4 penetrating the first insulating layer 10 and the second insulating layer 20. They are respectively connected to the second semiconductor pattern OSP2. The sixth input electrode SE6 and the sixth output electrode DE6 have a fifth through hole CH5 and a sixth through hole CH6 penetrating the first insulating layer 10 and the second insulating layer 20. They are respectively connected to the sixth semiconductor pattern OSP6 through. Meanwhile, in another embodiment of the present invention, the first transistor T1, the second transistor T2, and the sixth transistor T6 may be transformed into a bottom gate structure.

On the second insulating layer 20, the first input electrode SE1, the second input electrode SE2, the sixth input electrode SE6, the first output electrode DE1, the second output electrode DE2, 6 A third insulating layer 30 covering the output electrode DE6 is disposed. The third insulating layer 30 includes an organic layer and/or an inorganic layer. In particular, the third insulating layer 30 may contain an organic material to provide a flat surface.

Any one of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may be omitted depending on the circuit structure of the pixel. Each of the second insulating layer 20 and the third insulating layer 30 may be defined as an interlayer. The interlayer insulating layer is disposed between the conductive pattern disposed below and the conductive pattern disposed thereon based on the interlayer insulating layer to insulate the conductive patterns.

A pixel defining layer PDL and an organic light emitting diode OLED are disposed on the third insulating layer 30. An anode AE is disposed on the third insulating layer 30. The anode AE is connected to the sixth output electrode DE6 through a seventh through hole CH7 penetrating the third insulating layer 30. An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a portion of the anode AE.

The pixels PX (shown in FIG. 4B) may be disposed in a pixel area on a plane. The pixel area may include an emission area PXA and a non-emission area NPXA adjacent to the emission area PXA. The non-emission area NPXA may surround the light-emitting area PXA. In this embodiment, the light emitting area PXA is defined to correspond to a partial area of the anode AE exposed by the opening OP.

The hole control layer HCL may be commonly disposed in the light-emitting area PXA and the non-emissive area NPXA. Although not shown separately, a common layer such as the hole control layer HCL may be commonly formed in the plurality of pixels PX (refer to FIG. 5A ).

An organic light emitting layer EML is disposed on the hole control layer HCL. The organic emission layer EML may be disposed in a region corresponding to the opening OP. That is, the organic emission layer EML may be formed separately on each of the plurality of pixels PX. In the present embodiment, the patterned organic emission layer EML is illustrated as an example, but the organic emission layer EML may be commonly disposed on the plurality of pixels PX. In this case, the organic light emitting layer EML may generate white light. In addition, the organic light emitting layer EML may have a multilayer structure.

An electron control layer ECL is disposed on the organic emission layer EML. Although not shown separately, the electronic control layer ECL may be commonly formed in the plurality of pixels PX (refer to FIG. 4B ).

The cathode CE is disposed on the electron control layer ECL. The cathode CE is commonly disposed on the plurality of pixels PX.

A thin film encapsulation layer TFE is disposed on the cathode CE. The thin film encapsulation layer TFE is commonly disposed on the plurality of pixels PX. The thin film encapsulation layer TFE includes at least one inorganic layer and at least one organic layer. The thin film encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers alternately stacked. In an embodiment of the present invention, the thin film encapsulation layer TFE may directly cover the cathode CE.

7A to 7C are cross-sectional views of thin film encapsulation layers TFE1, TFE2, and TFE3 according to an embodiment of the present invention. Hereinafter, thin film encapsulation layers TFE1, TFE2, and TFE3 according to exemplary embodiments will be described with reference to FIGS. 7A to 7C.

As shown in FIG. 7A, the thin film encapsulation layer TFE1 may include n inorganic thin films IOL1 to IOLn including the first inorganic thin film IOL1 in contact with the cathode (CE, see FIG. 6A). .

The first inorganic thin film IOL1 is defined as a lower inorganic thin film, and inorganic thin films other than the first inorganic thin film IOL1 among the n inorganic thin films IOL1 to IOLn may be defined as upper inorganic thin films.

The thin film encapsulation layer TFE1 includes n-1 organic thin films OL1 to OLn-1, and n-1 organic thin films OL1 to OLn-1 are n inorganic thin films IOL1 to IOLn. And can be placed alternately. The n-1 organic thin films OL1 to OLn-1 may have a thickness greater than that of the n inorganic thin films IOL1 to IOLn on average.

Each of the n inorganic thin films IOL1 to IOLn may have a single layer including one material, or a multilayer including a different material. Each of the n-1 organic thin films OL1 to OLn-1 may be formed by depositing organic monomers. Organic monomers may include acrylic monomers. In an embodiment of the present invention, the thin film encapsulation layer TFE1 may further include an nth organic thin film.

As illustrated in FIGS. 7B and 7C, the inorganic thin films included in each of the thin film encapsulation layers TFE2 and TFE3 may have the same or different inorganic materials, and may have the same or different thickness. The organic thin films included in each of the thin film encapsulation layers TFE2 and TFE3 may have the same or different organic materials, and may have the same or different thickness.

As shown in FIG. 7B, the thin film encapsulation layer TFE2 includes a first inorganic thin film IOL1, a first organic thin film OL1, a second inorganic thin film IOL2, and a second organic thin film OL2 sequentially stacked. , And a third inorganic thin film (IOL3).

The first inorganic thin film IOL1 may have a two-layer structure. The first sub-layer S1 and the second sub-layer S2 may include different inorganic materials.

As shown in FIG. 7C, the thin film encapsulation layer TFE3 may include a first inorganic thin film IOL10, a first organic thin film OL1, and a second inorganic thin film IOL20 that are sequentially stacked. The first inorganic thin film IOL10 may have a two-layer structure. The first sub-layer S10 and the second sub-layer S20 may include different inorganic materials. The first organic thin film OL1 may be an organic layer containing a polymer, and the second inorganic thin film IOL20 may have a two-layer structure. The second inorganic thin film IOL20 may include a first sub-layer S100 and a second sub-layer S200 deposited in different deposition environments. The first sub-layer S100 may be deposited under a low power supply condition, and the second sub-layer S200 may be deposited under a high power supply condition. The first sub-layer S100 and the second sub-layer S200 may include the same inorganic material.

8A is a cross-sectional view of a touch sensing unit TS according to an embodiment of the present invention. 8B to 8E are plan views of a touch sensing unit TS according to an embodiment of the present invention.

As shown in FIG. 8A, the touch sensing unit TS includes a lower insulating layer TS-LIL, an intermediate insulating layer TS-MIL, a first conductive layer TS-CL1, and an upper insulating layer TS-HIL. ), and a second conductive layer TS-CL2. The lower insulating layer TS-LIL is directly disposed on the encapsulation layer TFE. The first conductive layer TS-CL1 is directly disposed on the lower insulating layer TS-LIL. However, the present invention is not limited thereto, and another inorganic layer (eg, a buffer layer) may be further disposed between the first conductive layer TS-CL1 and the lower insulating layer TS-LIL.

Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 may have a single layer structure or may have a multilayer structure stacked along the third direction axis DR3. The multilayered conductive layer may include at least two or more of transparent conductive layers and metal layers. The multilayered conductive layer may include metal layers including different metals. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, and alloys thereof.

Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 includes a plurality of patterns. Hereinafter, it will be described that the first conductive layer TS-CL1 includes first conductive patterns, and the second conductive layer TS-CL2 includes second conductive patterns. Each of the first conductive patterns and the second conductive patterns may include touch electrodes and touch signal lines.

Each of the lower insulating layer TS-LIL, the intermediate insulating layer TS-MIL, and the upper insulating layer TS-HIL may include an inorganic material or an organic material. The inorganic material may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic material includes at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin siloxane resin, polyimide resin, polyamide resin, and perylene resin can do.

Each of the lower insulating layer TS-LIL, the intermediate insulating layer TS-MIL, and the upper insulating layer TS-HIL may have a single layer or multilayer structure. Each of the lower insulating layer TS-LIL, the intermediate insulating layer TS-MIL, and the upper insulating layer TS-HIL may have at least one of an inorganic layer and an organic layer. The inorganic layer and the organic layer may be formed by a chemical vapor deposition method.

The intermediate insulating layer TS-MIL is sufficient to insulate the first conductive layer TS-CL1 and the second conductive layer TS-CL2, and the shape thereof is not limited. The shape of the intermediate insulating layer TS-MIL may be changed according to the shapes of the first and second conductive patterns. The intermediate insulating layer TS-MIL may entirely cover the thin film encapsulation layer TFE or may include a plurality of insulating patterns. It is sufficient if the plurality of insulating patterns overlap the first connection parts CP1 or the second connection parts CP2 to be described later.

Although the two-layer type touch sensing unit is illustrated as an example in the present embodiment, the present invention is not limited thereto. The single-layered touch sensing unit includes a conductive layer and an insulating layer covering the conductive layer. The conductive layer includes touch sensors and touch signal lines connected to the touch sensors. The single-layered touch sensing unit may acquire coordinate information in a self-cap method.

As shown in FIG. 8B, the touch sensing unit TS includes a first touch signal connected to the first touch electrodes TE1-1 to TE1-5 and the first touch electrodes TE1-1 to TE1-5. The second touch signal lines TL2 connected to the lines TL1, the second touch electrodes TE2-1 to TE2-4, and the second touch electrodes TE2-1 to TE2-4, and the first A second pad PD2 connected to the touch signal lines TL1 and the second touch signal lines TL2 may be included. In FIG. 8B, a touch sensing unit TS including five first touch electrodes TE1-1 to TE1-5 and four second touch electrodes TE2-1 to TE2-4 is illustrated as an example. However, it is not limited thereto.

Each of the first touch electrodes TE1-1 to TE1-5 may have a mesh shape in which a plurality of touch openings are defined. Each of the first touch electrodes TE1-1 to TE1-5 includes a plurality of first touch sensor units SP1 and a plurality of first connection units CP1. The first touch sensor units SP1 are arranged along the second direction DR2. Each of the first connection units CP1 connects two adjacent first touch sensor units SP1 among the first touch sensor units SP1. Although not specifically shown, the first touch signal lines TL1 may also have a mesh shape.

The second touch electrodes TE2-1 to TE2-4 insulately cross the first touch electrodes TE1-1 to TE1-5. Each of the second touch electrodes TE2-1 to TE2-4 may have a mesh shape in which a plurality of touch openings are defined. Each of the second touch electrodes TE2-1 to TE2-4 includes a plurality of second touch sensor units SP2 and a plurality of second connection units CP2. The second touch sensor units SP2 are arranged along the first direction DR1. Each of the second connection units CP2 connects two adjacent second touch sensor units SP2 among the second touch sensor units SP2. The second touch signal lines TL2 may also have a mesh shape.

The first touch electrodes TE1-1 to TE1-5 and the second touch electrodes TE2-1 to TE2-4 are electrostatically coupled. As touch sensing signals are applied to the first touch electrodes TE1-1 to TE1-5, capacitors are formed between the first touch sensor units SP1 and the second touch sensor units SP2.

A plurality of first touch sensor units (SP1), a plurality of first connection units (CP1), and first touch signal lines (TL1), a plurality of second touch sensor units (SP2), a plurality of second connection units ( CP2) and some of the second touch signal lines TL2 are formed by patterning the first conductive layer TS-CL1 shown in FIG. 8A, and other parts are formed by patterning the second conductive layer TS shown in FIG. 8A. -CL2) can be formed by patterning.

In order to electrically connect the conductive patterns disposed on other layers, a contact hole may be formed through the intermediate insulating layer TS-MIL shown in FIG. 8A. Hereinafter, a touch sensing unit TS according to an exemplary embodiment will be described with reference to FIGS. 8C to 8E.

As shown in FIG. 8C, first conductive patterns are disposed on the lower insulating layer TS-LIL. The first conductive patterns may include bridge patterns CP1. Bridge patterns CP1 are directly disposed on the lower insulating layer TS-LIL. The bridge patterns CP1 correspond to the second connection parts CP2 shown in FIG. 8B.

As shown in FIG. 8D, an intermediate insulating layer TS-MIL covering the bridge patterns CP1 is disposed on the lower insulating layer TS-LIL. Touch contact holes TCH partially exposing the bridge patterns CP1 are defined in the intermediate insulating layer TS-MIL. Touch contact holes TCH may be formed by a photolithography process.

As shown in FIG. 8E, second conductive patterns are disposed on the first touch insulating layer TS-IL1. The second conductive patterns include a plurality of first touch sensor units SP1, a plurality of first connection units CP1, and first touch signal lines TL1, a plurality of second touch sensor units SP2, and a second It may include touch signal lines TL2. Although not shown separately, an upper insulating layer TS-HIL covering the second conductive patterns is disposed on the intermediate insulating layer TS-MIL.

In another embodiment of the present invention, the first conductive patterns may include first touch electrodes TE1-1 to TE1-5 and first touch signal lines TL1. The second conductive patterns may include second touch electrodes TE2-1 to TE2-4 and second touch signal lines TL2. In this case, the contact holes CH are not defined in the first touch insulating layer TS-IL1.

In addition, in an embodiment of the present invention, the first conductive patterns and the second conductive patterns may be interchanged with each other. That is, the second conductive patterns may include the bridge patterns CP1.

8F is a partially enlarged view of the AA area of FIG. 8E.

As shown in FIG. 8F, the first touch sensor unit SP1 overlaps the non-emission area NPXA. The first touch sensor unit SP1 includes a plurality of first extension portions SP1-A and a fifth direction extending in a fifth direction DR5 crossing the first direction DR1 and the second direction DR2. And a plurality of second extension portions SP1-B extending in the sixth direction DR6 crossing the DR5). The plurality of first extension parts SP1-A and the plurality of second extension parts SP1-B may be defined as mesh lines. The line width of the mesh line may be several microns.

The plurality of first extension parts SP1-A and the plurality of second extension parts SP1-B are connected to each other to form a plurality of touch openings TS-OP. In other words, the first touch sensor unit SP1 has a mesh shape including a plurality of touch openings TS-OP. Although the touch openings TS-OP are shown to correspond to the light emitting regions PXA one-to-one, the present invention is not limited thereto. One touch opening TS-OP may correspond to two or more light emitting regions PXA.

The size of the emission areas PXA may vary. For example, among the emission areas PXA, the size of the emission areas PXA providing blue light and the emission areas PXA providing red light may be different. Accordingly, the sizes of the touch openings TS-OP may also vary. In FIG. 8F, various sizes of the emission regions PXA are illustrated as an example, but the present invention is not limited thereto. The sizes of the light-emitting regions PXA may be the same, and the sizes of the touch openings TS-OP may be the same.

Since the contents of the first touch sensor unit SP1 can be equally applied to the second touch sensor unit SP2, a description of the second touch sensor unit SP2 will be omitted.

The above touch sensing unit has been described, and the dam and the bank will be described with reference to FIGS. 8B and 8E.

8B and 8E, the dam DAM is disposed on a non-display area NDA (hereinafter, referred to as a peripheral area) of a base layer (SUB, hereinafter referred to as a substrate). In more detail, the dam DAM may have a closed loop shape on a plane and may have a shape surrounding the display area. However, the shape of the dam (DAM) is not limited thereto, and may be transformed into various shapes. In addition, there may be a plurality of dams (DAM). For example, a plurality of dams DAM that surround the display area and are spaced apart from each other on a plane may be disposed in the peripheral area NDA.

The bank BAK is disposed in the peripheral area NDA of the substrate SUB adjacent to the dam DAM. The bank BAK is disposed between the second pad PD2 and the dam DAM. In more detail, the bank BAK may have a bar shape on a plane, but is not limited thereto and may be variously modified.

The first touch signal lines TL1 and TL1 and the second touch signal lines TL2 and TL2 are extended to be disposed on the dam DAM and the bank BAK, and are connected to the second pad PD2. The dam (DAM) and the bank (BAK) will be described in detail in FIGS. 9 to 11.

9 is a cross-sectional view taken along line A-A' of FIG. 8E. 10A is a cross-sectional view taken along line B-B' of FIG. 8E. 10B is a cross-sectional view of a bank BAK according to another embodiment of the present invention. 11 is a perspective view of a portion of the bank BAK. Referring to FIGS. 9 to 11, the dam DAM may include an upper portion DAMU and a lower portion DAMD. The upper portion DAMU is disposed on the lower portion DAMD. In more detail, the upper portion DAMU may be disposed in contact with the upper surface of the lower portion DAMD. The lower portion DAMD may be formed by the same process as the third insulating layer 30 (see FIG. 6A). That is, the lower portion DAMD may be disposed on the same layer as the third insulating layer 30. The lower portion DAMD may be an organic layer and/or an inorganic layer. In particular, the lower portion DAMD may include an organic material to provide a flat surface.

The upper portion DAMU may be formed by the same process as the pixel defining layer PDL. That is, the upper portion DAMU may be disposed on the same layer as the pixel defining layer PDL. The upper portion DAMU may include an organic material. For example, the upper portion DAMU may include an organic material such as polyimide.

The dam DAM may have a protruding shape in a cross section by combining the lower portion DAMD and the upper portion DAMU. The dam (DAM) may function to control the flow of the organic thin film material formed in the encapsulation layer (TFE). For example, when the encapsulation layer TFE illustrated in FIG. 9 is the encapsulation layer TFE3 illustrated in FIG. 7C, the dam DAM may control the flow of monomers in the first organic thin film OL1, and 1 The movement of the organic thin film OL1 in the first direction DR1 may be controlled by the dam DAM. Accordingly, the first inorganic thin film IOL10 of the encapsulation layer TFE may be directly disposed on the dam DAM, and the second inorganic thin film IOL20 may be disposed directly on the first inorganic thin film IOL.

The banks BAK may be disposed at a predetermined distance apart from the dam DAM in the first direction DR1. The bank BAK includes a first bank part BANK1, a boundary part BOR, and a second bank part BANK2. The boundary portion BOR is disposed between the first bank portion BANK1 and the second bank portion BANK2.

The first bank part BANK1 may include an upper part BU and a lower part BD. The upper portion BU is disposed on the lower portion BD. In more detail, the upper part BU may be disposed in contact with the upper surface of the lower part BD. The lower part BD may be formed by the same process as the third insulating layer 30 (see FIG. 6A). That is, the lower part BD may be disposed on the same layer as the third insulating layer 30. The lower part BD may be an organic layer and/or an inorganic layer. In particular, the lower part BD may include an organic material to provide a flat surface.

The upper portion BU may be formed by the same process as the pixel defining layer PDL. The upper portion BU may be disposed on the same layer as the pixel defining layer PDL. The upper portion BU may include a portion corresponding to the pixel definition layer PDL and a spacer SPC. The spacer SPC may be formed simultaneously with a portion corresponding to the pixel defining layer PDL. In an example of the present invention, the spacer SPC may be disposed on the pixel defining layer PDL. That is, the first bank part BANK1 may have a height greater than that of the dam DAM. The upper portion BU may include an organic material. For example, the upper portion BU may include an organic material such as polyimide.

The boundary portion BOR may also include an upper portion BRU and a lower portion BRD, similarly to the first bank portion BANK1. The rest of the description is the same as that of the first bank part BANK1, so it will be omitted.

The second bank portion BANK2 may be formed by the same process as the third insulating layer 30. That is, the second bank portion BANK2 may be disposed on the same layer as the third insulating layer 30. The second bank portion BANK2 may be an organic layer and/or an inorganic layer.

The boundary portion BOR may be provided in plurality. A second bank portion BANK2 may be disposed between two adjacent boundary portions BOR among the boundary portions BOR. The height of the second bank portion BANK2 may be smaller than the heights of the first bank portion BANK1 and the boundary portion BOR.

In conclusion, the lower part BD of the first bank part BANK1, the lower part BRD of the boundary part BOR, and the second bank part BANK2 may be integrally formed.

As the second bank portion BANK2 and the boundary portion BOR are formed, the bank BAK is the bank (Bank) due to the scratches generated by the mask in the process of supporting the mask used to form the encapsulation layer TFE. BAK) It is possible to prevent defective patterning of the touch signal line occurring on the upper surface.

12A to 12G are diagrams illustrating a process of forming the first capping pattern CAP1 on the bank BAK.

As illustrated in FIG. 12A, a lower insulating layer TS-LIL may be formed on the bank BAK. The lower insulating layer TS-LIL may be formed on the bank BAK through a deposition process.

As illustrated in FIG. 12B, an intermediate insulating layer TS-MIL may be formed on the lower insulating layer TS-LIL through a deposition process.

As illustrated in FIG. 12C, a conductive layer CODL to be formed of a first capping pattern CAP1 and touch signal lines TL1 and TL2 to be described later may be formed on the intermediate insulating layer TS-MIL. The conductive layer CODL may be formed on the intermediate insulating layer TS-MIL through a deposition process. The conductive layer CODL may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The conductive layer CODL may include a metal layer, such as molybdenum, silver, titanium, copper, aluminum, or an alloy thereof.

Referring to FIG. 12D, a photoresist layer PRE may be formed on the conductive layer CODL, and the rest except for the portion where the first capping pattern CAP1 and the touch signal lines TL1 and TL2 are to be formed. Can be exposed.

Referring to FIG. 12E, an etching process may be performed on the conductive layer CODL corresponding to the exposed portion ELA. For example, the conductive layer CODL corresponding to the exposed portion ELA may be etched through a dry etching process.

Referring to FIG. 12F, after the etching process is performed, the photoresist layer PRE may be removed through a strip process. Since the photoresist layer PRE is removed, a first capping pattern CAP1 may be formed between the intermediate insulating layer TS-MIL and the upper insulating layer TS-HIL, corresponding to the boundary portion BOR, and the second First touch signal lines TL1 and second touch signal lines TL2 may be formed between the intermediate insulating layer TS-MIL and the upper insulating layer TS-HIL in correspondence with the bank part BANK2. have.

10A, 11, and 12F, between the intermediate insulating layer TS-MIL and the upper insulating layer TS-HIL so that the first capping pattern CAP1 and the touch signal lines TL1 and TL2 are covered. Can be formed in The upper insulating layer TS-HIL may be formed on the intermediate insulating layer TS-MIL through a deposition process.

As the first capping pattern CAP1 is formed in correspondence with the boundary part BOR, the organic material inside the bank BAK is leaked during the etching process due to the lack of thickness of the photoresist layer PRE formed on the boundary part BOR. As a result, phenomena such as film lifting can be prevented from occurring.

In addition, as shown in FIG. 10B, the first capping pattern CAP1 ′ corresponds to the first bank part BANK1 and the boundary part BOR, and is formed between the intermediate insulating layer TS-MIL and the upper insulating layer TS-HIL. The first capping pattern CAP1 is not limited thereto, and may be deformed into various shapes. For example, in an embodiment of the present invention, it has been described that the touch signal lines TL1 and TL2 and the first capping pattern CAP1 are formed on the intermediate insulating layer TS-MIL, but as described above, touch The signal lines TL1 and TL2 may also be formed on the lower insulating layer TS-LIL. In this case, the first capping pattern CAP1 is the lower insulating layer TS-LIL and the intermediate insulating layer TS. -MIL) may be formed between.

13A to 13C are plan views for explaining another embodiment of the present invention. 14 is a cross-sectional view for explaining another embodiment of the present invention.

As illustrated in FIG. 13A, dummy lines DUL may be disposed on the lower insulating layer TS-LIL. The dummy lines DUL may overlap the touch signal lines TL1 and TL2 shown in FIG. 8E. Each of the dummy lines DUL is connected in parallel with each of the above-described touch signal lines TL1 and TL2 to reduce a resistance of a line through which a signal is transmitted, thereby increasing touch sensing sensitivity.

Since the method of forming the dummy lines DUL is the same as the method of forming the touch signal lines TL1 and TL2 described above, a description will be omitted.

As shown in FIG. 13B, dummy contact holes DCH partially exposing the above-described touch signal lines TL1 and TL2 may be defined in the intermediate insulating layer TS-MIL. The dummy contact holes DCH may be formed by a photolithography process. Each of the dummy lines DUL of FIG. 13A may be connected in parallel to each of the touch signal lines TL1 and TL2 through dummy contact holes DCH.

13C, since the dummy lines DUL overlap the touch signal lines TL1 and TL2, after the first touch signal lines TL1 and the second touch signal lines TL2 are formed, It may not be shown in plan view. Each of the dummy lines DUL may be connected to the second pad PD2 ′ to which the corresponding touch signal lines TL1 and TL2 are connected.

Referring to FIG. 14, a second capping pattern CAP2 may be disposed between the lower insulating layer TS-LIL and the intermediate insulating layer TS-MIL in correspondence with the boundary part BOR, and the second bank part ( In correspondence with BANK2), dummy lines DUL may be disposed between the lower insulating layer TS-LIL and the intermediate insulating layer TS-MIL. The second capping pattern CAP2 and the dummy lines DUL may be formed by the same process, and the formation process is the same as the process of forming the first capping pattern CAP1 and the touch signal lines TL1 and TL2. Omit the bar.

Since the second capping pattern CAP2 is formed, it is possible to prevent defects such as the above-described film lifting.

In the present specification, the dummy lines DUL have been described as being disposed on the lower insulating layer TS-LIL and the intermediate insulating layer TS-MIL, but these may be variously modified. For example, the touch signal lines TL1 and TL2 may be disposed on the lower insulating layer TS-LIL and the intermediate insulating layer TS-MIL, and the dummy lines DUL may be formed of the intermediate insulating layer TS. -MIL) and the upper insulating layer (TS-HIL) may be disposed between.

Although the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art or those of ordinary skill in the art will not depart from the spirit and scope of the present invention described in the claims to be described later. It will be understood that various modifications and changes can be made to the present invention within the scope of the invention.

Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

TS-LIL: lower insulating layer BAK: bank
TS-MIL: intermediate insulating layer BANK2: second bank portion
TS-HIL: upper insulating layer CAP1: first capping pattern

Claims (16)

Base layer;
An element layer disposed on the base layer and including light-emitting elements;
An encapsulation layer disposed on the device layer;
An input sensing layer disposed on the encapsulation layer and including electrodes and signal wires electrically connected to the electrodes, respectively;
A first portion disposed on the base layer, spaced apart from the device layer, and having a first thickness, a second portion having a second thickness less than the first thickness, and between the first portion and the second portion A sub-layer comprising the disposed third portion; And
A display device including a capping pattern disposed on the third portion of the sub-layer. The method of claim 1,
The input sensing layer includes a first insulating layer disposed directly on the encapsulation layer,
The first insulating layer extends toward the sub-layer, covers the sub-layer, and the capping pattern is disposed on the first insulating layer. The method of claim 2,
The input sensing layer further includes a second insulating layer disposed on the first insulating layer and covering the capping pattern. The method of claim 1,
On a plane, the encapsulation layer is spaced apart from the sub-layer. The method of claim 1,
The sub-layer comprises a first layer and a second layer disposed over the second layer,
Each of the first portion and the third portion includes the first layer and the second layer, and the second portion includes the first layer. The method of claim 1,
When viewed on a plane, the capping pattern overlaps the third portion. The method of claim 1,
When viewed on a plane, the capping pattern overlaps the first portion and the third portion. The method of claim 1,
The capping pattern includes a conductive material. The method of claim 1,
The capping pattern includes the same material as the signal lines. The method of claim 1,
The signal wires are spaced apart from the capping pattern, and the signal wires overlap the second portion. The method of claim 1,
The sub-layer extends in a first direction, and a portion of the signal lines overlapping the sub-layer extends in a second direction crossing the first direction. The method of claim 1,
The sub-layer is spaced apart from the electrodes. Base layer;
An element layer disposed on the base layer and including light-emitting elements;
An encapsulation layer disposed on the device layer;
An input sensing layer disposed on the encapsulation layer;
A sub-layer disposed on the base layer and including a step portion; And
A display device including a capping pattern disposed on the stepped portion of the sub-layer. The method of claim 13,
The input sensing layer includes a first insulating layer disposed directly on the encapsulation layer,
The first insulating layer extends toward the sub-layer to cover the sub-layer, and the capping pattern is disposed on the first insulating layer. The method of claim 14,
The input sensing layer further includes a second insulating layer disposed on the first insulating layer and covering the capping pattern. The method of claim 13,
The encapsulation layer is spaced apart from the sub-layer.

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