KR20200082404A - Display device - Google Patents

Abstract

An embodiment of the present invention relates to a display device. According to an embodiment of the present invention, provided is the display device capable of measuring a scan signal without destructive analysis. According to an embodiment of the present invention, provided is the display device capable of measuring a change of the scan signal over time in real-time by forming a test line which can externally measure the scan signal of a gate driving circuit through a dummy pad.

Description

Display device {DISPLAY DEVICE}

An embodiment of the present invention relates to a display device.

As the information society develops, various demands for a display device displaying an image are increasing, and various types such as a liquid crystal display (LCD), an organic light emitting diode display (OLED display), etc. Display devices are being utilized.

A liquid crystal display device (LCD) is a device that displays an image using optical anisotropy of a liquid crystal, and is widely used because it has advantages such as thinness, small size, low power consumption, and high image quality. In addition, the organic light emitting display device uses an organic light emitting diode that emits light by itself, and accordingly, it has attracted attention as a next generation display device because it has advantages such as fast response speed, high luminous efficiency, high luminance, and large viewing angle.

Such display devices include gate driving circuits, data driving circuits, display panels, and timing controllers. The display panel may be an organic light emitting panel or a liquid crystal panel, and the gate driving circuit may be formed of an integrated circuit (IC) and then mounted on the display panel in the form of a chip on film (COF) or a tape carrier package (TCP). . Recently, a gate in panel (GIP) method in which a gate driving circuit is embedded in a display panel is widely used.

In a GIP structured display device, a data driving circuit is formed in a chip form and attached to a display panel in a TCP or COF manner, and a plurality of gates and data lines defining a liquid crystal cell intersect in a pixel array area displaying an image on the display panel. Is formed. In addition, a gate driving circuit composed of a plurality of thin film transistor (TFT) elements may be provided outside the pixel array region.

The gate driving circuit includes a shift register, which may include a plurality of stages outputting a scan signal SCAN to a plurality of gate lines. The stage may be configured in various forms, and each transistor may be driven using a clock signal CLK.

At this time, the scan signal SCAN applied to the plurality of gate lines through the shift register may be delayed in charging and discharging time as the use time of the display device increases, so the display device of the GIP type display device may be delayed. In evaluating reliability, it is important to measure the waveform change of the scan signal (SCAN).

Conventionally, in order to measure the waveform of the scan signal (SCAN) output through the shift register, after destroying some areas such as a color filter (CF) located at the top in a state in which manufacturing of the display device is completed, the scan signal is A breakdown analysis method was used to measure the voltage of the drain node or source node of the transistor outputting (SCAN).

However, when such a destructive analysis method is used, it is impossible to measure a scan signal (SCAN) over time with the same sample because the sample (display device) to be measured is damaged. And, there is a problem that can not measure the scan signal (SCAN) in real time.

An object of an embodiment of the present invention is to provide a display device capable of measuring a scan signal without destructive analysis.

An object of an embodiment of the present invention is to provide a display device capable of measuring a change in a scan signal over time in real time by forming a test line capable of externally measuring a scan signal of a gate driving circuit through a dummy pad. .

In one aspect, a display device according to an exemplary embodiment of the present invention includes a display area in which a plurality of gate lines and a plurality of data lines are crossed, a plurality of subpixels are disposed, a gate driving circuit driving a plurality of gate lines, A data driving circuit driving a plurality of data lines, a pad region to which the data driving circuit and the flexible circuit board are bonded, and a scan signal output terminal and a pad region of the gate driving circuit supplying scan signals to the plurality of gate lines are arranged. It may include a test line connected between the dummy pads.

The display device of the present invention can measure a scan signal through a dummy pad to which a test line is connected.

The subpixel is a light-emitting diode, a driving transistor driving the light-emitting diode, a switching transistor electrically connected between the gate node and the data line of the driving transistor, and electrically connected between the source node or the drain node of the driving transistor and the reference voltage line. It may include a storage capacitor that is electrically connected between the sensing transistor, the gate node of the switching transistor, and the source node or the drain node.

The pad area is connected to the data line, and the first pad area is formed where the first pads are connected to the scan signal output terminal of the data driving circuit, and the second pad is formed from the second pads which are connected to the input terminal of the data driving circuit. It may include an area and a third pad area where third pads that are bonded to the output terminal of the flexible circuit board are formed.

The first pad may be a data pad.

The third pad may include a dummy pad.

The gate driving circuit is composed of a plurality of stages that supply a scan signal to the gate line for one frame, and the plurality of stages are pull-up transistors that output a scan pulse or gate off voltage according to the clock signal and the scan pulses of the other stages. And pull-down transistors.

The test line can be electrically connected to a pull-up transistor that outputs a scan pulse or gate-off voltage and a source or drain node of the pull-down transistor.

The test line may be made of the same material as the source or drain node of the pull-up transistor and pull-down transistor that outputs a scan pulse or gate-off voltage.

The gate driving circuit may be formed in a gate-in-panel method embedded in a display panel formed in a display area.

Test lines may be formed on the top of the active layer and the bottom of the insulating layer constituting the gate driving circuit.

According to an embodiment of the present invention, it is possible to provide a display device capable of measuring a scan signal without being subjected to destruction analysis.

According to an embodiment of the present invention, by providing a test line capable of externally measuring the scan signal of the gate driving circuit through the dummy pad, a display device capable of measuring the change in the scan signal over time in real time is provided. Can.

1 is a view showing a schematic configuration of an organic light emitting display device according to an embodiment of the present invention.
2 is an exemplary diagram schematically showing a shift register configuration inside a gate driving circuit in the display device according to the present invention.
3 is a diagram illustrating an exemplary circuit diagram of a stage constituting a shift register inside a gate driving circuit in the display device of the present invention.
4 is a view showing a state of change of a scan pulse applied to a gate line from a shift register of a gate driving circuit as the use time of the display device increases.
5 is a view showing an example of a top view of a GIP-type display device according to an embodiment of the present invention.
6 is a diagram illustrating a cross-sectional example of an outer area NA in a GIP-type display device.
7 is a schematic block diagram of a pad area in a display device according to an exemplary embodiment of the present invention.
FIG. 8 is a plan view illustrating a test line formed between a shift register output terminal of a gate driving circuit and a pad constituting a pad area in a display device according to an exemplary embodiment of the present invention.
9 is a view illustrating a cross-sectional view when a test line capable of measuring a scan pulse is formed in an outer region in a display device according to an exemplary embodiment of the present invention.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the present embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains. It is provided to fully inform the holder of the scope of the invention, and the invention is only defined by the scope of the claims.

In addition, the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. When'include','have','consist of', etc. mentioned in this specification are used, other parts may be added unless'~man' is used. When a component is expressed in singular, it may include a case in which plural is included unless specifically stated.

In addition, in interpreting the components in the embodiments of the present invention, it should be interpreted as including an error range even if there is no explicit description.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only for distinguishing the component from other components, and the nature, order, order, or number of the component is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, the component may be directly connected to or connected to the other component, but different components between each component It should be understood that the "intervenes" may be, or each component may be "connected", "coupled" or "connected" through other components. In the case of the description of the positional relationship, for example, when the positional relationship of two parts is described as'~top','~upper','~bottom','~side', etc.,'right' Alternatively, one or more other parts may be located between the two parts unless'direct' is used.

In addition, components in the embodiments of the present invention are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

In addition, the features (configurations) in the embodiments of the present invention may be partially or wholly combined with each other or combined or separated, and technically various interlocking and driving are possible, and each embodiment is independently performed with respect to each other. It may be possible or it may be implemented together in an association relationship.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a schematic configuration of a display device according to an embodiment of the present invention.

Referring to FIG. 1, the display device of the present invention includes a display panel 100, a gate driving circuit 200 and a data driving circuit 300 embedded in the display panel 100; And a timing controller 400.

Subpixels (SPs) may be formed in each of the crossing regions of the plurality of gate lines (GL) and the plurality of data lines (DL), and the structure of the subpixels (SP) is a type of display device. It can be changed in various ways depending on. When the display device is an organic light emitting display device, the subpixel SP is connected to the organic light emitting diode OLED, the data line DL and the gate line GL to control the organic light emitting diode OLED. It may include a thin film transistor (TFT), and a storage capacitor (Cst).

The scan signal SCAN required to drive the subpixel SP may vary according to the resolution of the display panel 100. For example, in the case of a display device having a resolution of 2,160 X 3,840, 2,160 gate lines GL and 3,840 data lines DL may be provided. In this case, 2,160 through 2,160 gate lines GL The scan signals SCAN may be applied to the subpixel SP. In addition, various kinds of control signals, such as a light emission signal EM for controlling the light emission time of the light emitting device, may be supplied to the subpixel SP in addition to the scan signal SCAN.

The scan signal SCAN may include a scan pulse for turning on the transistor disposed in the subpixel SP and a gate-off voltage for turning off the transistor in the subpixel SP while the scan pulse is not supplied. have. The scan pulse corresponds to an output voltage Vout in the form of a pulse that is sequentially supplied to each gate line GL from the shift register 250 constituting the gate driving circuit 200.

In the case of a liquid crystal display (LCD), the display panel 100 may be a liquid crystal panel in which a liquid crystal layer is formed between two glass substrates. In this case, a plurality of data lines DL and a plurality of gate lines GL intersected therein, a data line DL and an area where the gate lines GL intersect the lower glass substrate of the display panel 100. A plurality of thin film transistors (TFT) formed in the subpixel SP, a plurality of pixel electrodes formed in the subpixel SP to charge the data voltage, and a pixel electrode for driving the liquid crystal charged in the liquid crystal layer Touch electrodes may be formed.

The display panel 100 may be divided into a display area AA and a surrounding outer area NA, and the gate driving circuit 200 including the shift register 250 may include an outer area NA of the display panel 100. It is mounted on.

The gate driving circuit 200 is mounted in the display panel 100 by a gate in panel (GIP) method. In order to control the gate driving circuit 200, the gate control signal GCS applied from the timing controller 400 includes a gate start pulse GSP, a gate start signal VST, a gate shift clock GSC, and a gate output enable. The signal GOE and the gate clock GCLK may be included.

The gate driving circuit 200 sequentially supplies the scan pulse Vout to the gate line GL of the display panel 100 in response to the gate control signal GCS input from the timing controller 400. Accordingly, the thin film transistor TFT formed on the gate line GL to which the scan pulse Vout is input is turned on, and an image is displayed through the corresponding subpixel SP.

The supply of the scan pulse Vout through the gate line GL is performed by the shift register 250 constituting the gate driving circuit 200. That is, the shift register 250 sequentially uses the gate start signal VST and the gate clock GCLK transmitted from the timing controller 400 to sequentially scan pulse Vout to the gate line GL for one frame. To supply. Here, one frame refers to a period in which one image is displayed through the display panel 100.

The scan pulse Vout is transmitted as a voltage at a level capable of turning on the thin film transistor TFT formed on the subpixel SP, and during the remaining period during which the scan pulse Vout is not supplied in one frame, the thin film transistor ( A gate-off voltage capable of turning off the TFT) is transmitted through the gate line GL.

The data driving circuit 300 converts digital image data DATA transmitted from the timing controller 400 into an analog data voltage, and the thin film transistor TFT of the subpixel SP is turned according to the data control signal DCS. -The analog data voltage is supplied through the data line DL for each horizontal period (1H) that is turned on. The data control signal DCS transmitted from the timing controller 400 to the data driving circuit 300 includes a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE, and a source clock SCLK. ) May include

The data driving circuit 300 may be connected to the display panel 100 in the form of a chip on film (COF), or may be directly mounted on the display panel 100 or directly formed on the display panel 100. The number of data driving circuits 300 may be variously set according to the size of the display panel 100 or the resolution of the display panel 100.

The data driving circuit 300 includes a shift register, a latch, a digital analog converter (DAC), and an output buffer to convert digital image data DATA into an analog data voltage and supply it to the data line DL. can do. The shift register outputs a sampling signal using the data control signal DCS received from the timing controller 400, and the latch temporarily stores digital image data DATA sequentially received from the timing controller 400. A, it performs the function of simultaneously outputting to the digital-to-analog converter (DAC). The digital-to-analog converter (DAC) converts and outputs digital image data DATA transmitted from the latch to an analog data voltage. The output buffer supplies the analog data voltage transmitted from the digital-to-analog converter (DAC) to the data line DL according to the source output enable signal (SOE) transmitted from the timing controller 400. The data driving circuit 300 may be formed as a single integrated circuit (IC) together with the timing controller 400.

The timing controller 400 uses a timing signal input from an external host system, for example, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), and a data enable signal (DE), to generate a gate driving circuit. A gate control signal (GCS) for controlling the operation timing of the (200) and a data control signal (DCS) for controlling the operation timing of the data driving circuit (300) are generated, and digital to be transmitted to the data driving circuit (300) Generate image data (DATA).

To this end, the timing controller 400 includes a receiving unit for receiving image data and timing signals transmitted from a host system, a control signal generating unit for generating various control signals, a data alignment unit for reordering image data, and a control signal And an output unit for outputting the image data to the data driving circuit 300 and the gate driving circuit 200.

2 is an exemplary diagram schematically showing a shift register configuration inside a gate driving circuit in the display device according to the present invention.

Referring to FIG. 2, the shift register 250 is configured to include a number of stages 252 corresponding to the number of gate lines GL, or a plurality of gate lines GL corresponds to one stage 252 It can be configured as much as possible. Here, a plurality of stages 252 are configured to drive the subpixel SP formed in each gate line GL by transmitting one scan pulse Vout through one gate line GL. It shows the case.

For example, in the case of a display device having a resolution of 2,160 X 3,840, since 2,160 gate lines GL are formed, 2,160 stages 252 are disposed in the shift register 250, and each stage 252 The scan pulse Vout may be supplied to the gate line GL.

3 is a diagram illustrating an exemplary circuit diagram of a stage constituting a shift register inside a gate driving circuit in the display device of the present invention.

Referring to FIG. 3, the plurality of stages 252 constituting the shift register 250 are turned on or off according to the logical state of the Q node, and outputs a scan pulse Vout in the turned-on state. A pull-up transistor T6 and a pull-down transistor T7n outputting a gate-off voltage while the scan pulse Vout is not output may be included. Here, the n-th stage 252 for supplying the scan pulse Vout(n) to the n-th gate line GL is illustrated as an example.

The n-th stage 252 outputs the scan pulse Vout(n) to the n-th gate line GLn using the n-th clock signal CLK(n), and the scan pulse Vout(n) is output. After that, the gate-off voltage may be output to the n-th gate line GLn by alternately using the n+4th clock signal CLK(n+4) and the n-th clock signal CLK(n). At this time, the internal circuit configuration of the stage 252 may be variously changed, and the clock signal CLK and the gate-off voltage for outputting the n-th scan pulse Vout(n) may be output according to the internal circuit configuration. The clock signal CLK may be changed in various ways.

Here, the nth scan pulse Vout(n) is n by using the nth clock signal CLK(n) input after the scan pulse Vout(n-3) is output in the n-3th stage. The case of outputting to the second gate line GLn is shown.

The first transistor T1 receives an n-3th scan pulse Vout(n-3) output from the n-3th stage as an input, and a pull-up output of the nth scan pulse Vout(n). It performs a function of charging the gate node (Q node) of the transistor T6, and the pull-up transistor T6 boosts the n-th clock signal CLK(n) through the Q node to n-th The scan pulse Vout(n) is output.

Here, the 3n transistor T3n receives an n+4th scan pulse (Vout(n+4)) output from the n+4th stage and discharges charges charged in the Q node. , The 3r transistor T3r performs a function of discharging the Q node charge of the entire shift register 252. In addition, the 3c transistor T3c operates at a timing when the n-2th clock signal CLK(n-2) is input to discharge the charge of the Q node to the gate line connected to the n-2th stage. Perform a function.

The pull-down transistor T7n is turned on by an n-th clock signal CLK(n) supplied after the n-th scan pulse Vout(n) is output to output a gate-off voltage. In addition, the 7c transistor T7c is turned on by the n+4th clock signal CLK(n+4) having a phase opposite to the n-th clock signal CLK(n), so that the base voltage VSS ) Is output to the gate line GLn. The ground voltage VSS will be the gate off voltage.

4 is a view showing a state of change of a scan pulse applied to a gate line from a shift register of a gate driving circuit as the use time of the display device increases.

Referring to FIG. 4, the scan pulse Vout applied to the display panel 100 through the gate line GL from the shift register 252 inside the gate driving circuit 200 is charged to the Q node in the initial stage of the display device. Since (charging) and discharging are performed at a high speed, the image quality displayed on the display panel 100 may be stably maintained, but the charging and discharging time of the Q node may be delayed as the use time increases. Can.

As a result, an image of an accurate luminance is not displayed on the sub-pixel SP constituting the display panel 100, so that the display quality may deteriorate. To this end, there is a need for a method capable of measuring the scan pulse Vout output from the shift register 250 in the gate driving circuit 200 in real time.

5 is a view showing an example of a top view of a GIP-type display device according to an embodiment of the present invention.

Referring to FIG. 5, in a GIP-type display device, the display panel 100 may be divided into a display area AA and a surrounding outer area NA. A subpixel SP is formed at a point where the plurality of gate lines GL and the plurality of data lines DL intersect in the display area AA, and sequentially applies a gate signal to the plurality of gate lines DL. The gate driving circuit 200, a data driving circuit 300 connected to the data line DL to apply a data signal, and a timing controller 400 controlling the gate driving circuit 200 and the data driving circuit 300 It includes.

The outer area NA is located at one end of the display panel 100 and includes a pad area PA including a gate pad G-Pad and a data pad D-Pad, and one end of the gate line GL. The gate driving area GCA may be divided into a signal input area SIA located on one side of the gate driving area GCA. The gate driving circuit 200 may include a gate driving area GCA and a signal input area SIA.

Here, the data pad D-Pad may be provided in a one-to-one correspondence to the data line DL. The gate pad (G-Pad) is connected to the timing controller 400 through a connection wiring provided in the data driving circuit 300, and timing signals (GSP, GSC, GOE) and voltage signals (VGH, VGL) related to gate driving are provided. , VSS applies a shifted gate signal to each gate line GL according to a corresponding clock through the gate driving circuit 200.

The stage 252 formed of a plurality of transistors and capacitors may be positioned in the gate driving area GCA. The gate pad G-Pad and the gate driving circuit 200 are connected to each other through a gate link G-Link, and signals applied from the gate pad G-Pad are gated through the gate link G-Link. It is distributed to each stage 252 of the driving area GCA.

The display device of the present invention is a flexible printed circuit (FPC) located in the pad area PA from the output terminal of the stage 252 outputting the scan pulse Vout via the data pad D-Pad. By forming a test line (T-Line) to connect the dummy pad of the, it is possible to measure the scan pulse (Vout) in real time at any time.

Accordingly, the source or drain node of the pull-up transistor T6 and the pull-down transistor T7n outputting the scan pulse Vout from the stage 252 and the data pad D-Pad formed in the pad area PA. ) To form a test line (T-Line). In addition, the test line T-Line is formed to extend to the dummy pad DM-Pad from the FPC pads F-Pad of the flexible circuit board FPC via the data pad D-Pad. It is possible to measure the scan pulse (Vout) through (DM-Pad).

6 is a diagram illustrating a cross-sectional example of an outer area NA in a GIP-type display device.

Referring to FIG. 6, the outer area NA of the GIP-type display device may include a gate driving area GCA and a pad area PA. In addition, a pull-up transistor T6 or a pull-down is applied to the output line applying the scan pulse Vout to the gate line GL in the stage 252 constituting the shift register 250 of the gate driving circuit 200. Since the transistor T7n may be connected, the transistor formed in the gate driving region GCA may be a pull-up transistor T6 or a pull-down transistor T7n.

The transistors formed in the gate driving region GCA include a gate electrode G on the base substrate and a gate insulating layer GIN covering the gate electrode G, an active layer AL formed on the gate insulating layer GIN, A source electrode S and a drain electrode D formed on both sides of the active layer AL may be included. A first insulating layer that can planarize a surface by coating an insulating material including silicon oxide (SiOx) or silicon nitride (SiNx) on the gate insulating layer GIN including the source electrode S and the drain electrode D. The second insulating layer INS2 is formed on the layer INS1 and the upper portion. The first insulating layer INS1 and the second insulating layer INS2 may be referred to as one insulating layer INS. The sealing material Seal bonds the color filter CF and the insulating layer INS of the gate driving area GCA, for example, the second insulating layer INS2.

As described above, in order to measure the scan pulse Vout output from each stage 252 of the shift register 250 formed in the gate driving area GCA while the display device is assembled, the upper color filter CF is used. The voltage of the source electrode or the drain electrode of the transistor had to be measured through the contact hole CH formed in the gate driving region GCA.

However, when such a destructive analysis method is used, the display device that is a measurement target of the scan pulse Vout, that is, the scan signal SCAN, is compelled to be damaged. SCAN) was impossible to measure, and there was a problem in that it was impossible to measure the scan signal (SCAN) in real time.

In order to solve this, the display device of the present invention is a gate driving circuit 200 via a data pad (D-Pad) from a dummy pad of a flexible printed circuit (FPC) located in the pad area PA. By forming a test line (T-Line) connected to the output terminal of the shift register 250, it is possible to measure the scan pulse Vout in real time at any time.

7 is a schematic block diagram of a pad area in a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 7, in the display device of the present invention, the gate driving circuit 200 may include one or more gate driver integrated circuits (GDIC). When implemented in a GIP method, the display panel 100 ) May be embedded in a bezel area.

Also, the data driving circuit 300 may include one or more source driver integrated circuits (SDICs), and the source driver integrated circuits (SDICs) may include a Tape Automated Bonding (TAB) method or Chip On Glass) may be connected to a bonding pad of the display panel 100 or may be directly disposed on the display panel 100. In some cases, each source driver integrated circuit (SDIC) may be integrated and disposed in the display panel 100. In addition, each source driver integrated circuit (SDIC) may be implemented by a COF (Chip On Film) method, in this case, each source driver integrated circuit (SDIC) is mounted on a circuit film, through the circuit film display panel It may be electrically connected to the data line (DL) of (100).

The pad area PA includes a first pad area PA1 to which output terminals of the source drive integrated circuit SDIC are bonded, a second pad area PA2 to which input terminals of the source drive integrated circuit SDIC are bonded, and softness. The third pad region PA3 to which the output terminals of the circuit board FPC are bonded may be formed.

In this case, the data pad D-Pad that supplies the data voltage to the display panel 100 through the data line DL corresponds to the first pad PAD1 formed in the first pad area PA1. The data pad (D-Pad) is connected 1:1 with the data line (DL) and can be connected to the output terminal of the source drive integrated circuit (SDIC) in the form of an anisotropic conductive film (ACF), and the source drive integrated circuit (SDIC) ) Transfers the data voltage output from the data line DL.

In the second pad Pad2 formed in the second pad area PA2, input terminals of the source drive integrated circuit SDIC may be bonded in the form of ACF.

The third pad (Pad3) formed in the third pad area (PA3) corresponds to the FPC pad (F-Pad) connected to the second pad (Pad2) through the FPC link (F-Link) of the outer area (PA), , It may be bonded in the form of ACF and the output terminal of the flexible circuit board (FPC). The FPC link (F-Link) may be formed in a line pattern crossing between the second pad area PA2 and the third pad area PA3, and the input terminal of the source drive integrated circuit (SDIC) and the flexible circuit board ( FPC)'s output terminal can be connected 1:1. Alternatively, the same signal is supplied to the input terminals of M (M is a positive integer greater than or equal to 1) source drive integrated circuits (SDIC) through N (N is a positive integer greater than or equal to 1) output terminals on a flexible circuit board (FPC). In this case, the FPC link will connect the input terminal of the source drive integrated circuit (SDIC) and the output terminal of the FPC with M:N.

The second pad area PA2 corresponds to a connection pad area connecting the data pad D-Pad of the source driver integrated circuit SDIC and the FPC pad F-Pad of the third pad area PA3. , May be omitted when configuring the pad area PA. When the second pad area PA2 is omitted, the data pad D-Pad of the first pad area PA1 and the dummy pad DM- of the third pad area PA3 by the FPC link F-Link Pad) may be connected directly.

The input and output terminals of the source drive integrated circuit (SDIC) and the output terminals of the flexible circuit board (FPC) are bonded to the pad area PA in the form of ACF.

The display device of the present invention is the first pad (Pad1) to the third pad (Pad3) formed in the pad area PA to measure the output terminal voltage of the shift register 250 constituting the gate driving circuit 200 To form a test line (T-Line) through, it is possible to measure the scan pulse (Vout) output from the shift register 250 through this.

FIG. 8 is a plan view illustrating a test line formed between a shift register output terminal of a gate driving circuit and a pad constituting a pad area in a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the display device of the present invention is a flexible circuit board (FPC) located in the pad area PA in order to measure the scan pulse Vout generated in the shift register 250 of the gate driving circuit 200. Of the FPC pads (F-Pads) bonded to the output terminals of ), extra unused dummy pads (DM-Pads) can be used.

The dummy pad (DM-Pad) may be made of one or more, depending on the type and model of the display device, and may have various structures according to the position and arrangement of the gate driving circuit 200 or the data driving circuit 300. have. In particular, in a structure in which the gate driving circuit 200 is located on both sides of the display panel 100, the gate driving circuit 200 may be disposed on the left and right portions of the display panel 100, respectively. Accordingly, a dummy pad (DM-Pad) that is not connected to a specific signal line among FPC pads (F-Pad) is selected as a terminal for measuring the scan pulse (Vout), and the test line (T) through which the scan pulse (Vout) is transmitted -Line).

In order to measure the scan pulse Vout output from the shift register 250 of the gate driving circuit 200, a pull-up transistor T6 or a pull-down transistor constituting the stage 252 of the shift register 250 is measured. The test line T-Line extending from the source node or the drain node of (T7n) includes a data pad (D-Pad) of the first pad area PA1 and a second pad (Pad2) of the second pad area PA2. It may be connected to the dummy pad DM-Pad in the third pad area PA3 via. The test line (T-Line) may be made of a conductive metal pattern.

In this case, the data pad D-Pad to which the test line T-Line is connected may be newly arranged for the measurement of the scan pulse Vout, or the data pad D-Pad connected to the data line DL. The scan pulse Vout may be measured through the dummy pad DM-Pad of the FPC during a time period in which data voltage is not applied to the subpixel SP.

9 is a view illustrating a cross-sectional view when a test line capable of measuring a scan pulse is formed in an outer region in a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 9, in the display device of the present invention, the gate driving area GCA and the pad area PA may be formed in the outer area NA. In addition, the source node of the pull-up transistor T6 is applied to the output terminal applying the scan pulse Vout to the gate line GL in the stage 252 constituting the shift register 250 of the gate driving circuit 200 and The source node of the pull-down transistor T7n may be connected. Therefore, the transistor formed in the gate driving region GCA may be a pull-up transistor T6 or a pull-down transistor T7n.

In the pull-up transistor T6 or the pull-down transistor T7n, a gate electrode G is formed on the base substrate, a gate insulating layer GIN covering the gate electrode G, and an upper portion of the gate insulating layer GIN. The active layer AL may be formed, and source electrodes S and drain electrodes D formed on both sides of the active layer AL may be included. At this time, since the scan pulse Vout can be transmitted through the source node or the drain node of the pull-up transistor T6 and the pull-down transistor T7n, the test line T for measuring the scan pulse Vout -Line) will be formed to contact the source or drain node of the pull-up transistor T6 and the pull-down transistor T7n.

Meanwhile, since the test line T-Line is made of a conductive material such as a source node or a drain node of the pull-up transistor T6 and the pull-down transistor T7n, the pull-up transistor T6 and pull- In the process of forming the source node or the drain node of the down transistor T7n, the test line T-Line may be simultaneously formed by extending it to the data pad D-Pad. Alternatively, after forming the source node or the drain node of the pull-up transistor T6 and the pull-down transistor T7n, which output the scan pulse Vout, or make contact with a portion of the upper portion, or test line T -Line) may be formed first, and then a source node or a drain node of the pull-up transistor T6 and the pull-down transistor T7n may be formed to contact a portion of the test line T-Line.

At this time, the test line (T-Line) may be formed on any layer constituting the gate driving area (GCA), the insulation from the gate link (G-Link) that can be disposed in the gate driving area (GCA). It needs to be secured. Accordingly, when forming the gate insulating layer GIN and the active layer AL, the stage 252 constituting the shift register 250 of the gate driving circuit 200 as well as the gate link G-Link and the pad region ( It is preferable to extend the gate insulating layer GIN and the active layer AL to the data pad D-Pad located in the PA.

Accordingly, the data pad D-Pad of the pad area PA from the source node or the drain node of the pull-up transistor T6 and the pull-down transistor T7n constituting the stage 252 of the shift register 250. Until the gate insulating layer GIN and the active layer AL are extended, a test line T-Line may be formed thereon. At this time, the test line (T-Line) is located between the active layer (AL) and the insulating layer (INS), the lower space of the sealing material (Seal) to join the color filter (CF) and the gate driving region (GCA) Will be formed on.

The test line T-Line may extend through the gate driving area GCA to a specific data pad D-Pad positioned in the pad area PA. The data pad D-Pad to which the test line T-Line is connected may be a pad connected to the data line DL or a newly added pad to measure the scan pulse Vout.

The data pad D-Pad to which the test line T-Line is connected is a dummy pad positioned in the third pad area PA3 via an arbitrary second pad Pad2 located in the second pad area PA2. (DM-Pad). The dummy pad DM-Pad to which the test line T-Line is connected may be one or a plurality of dummy pads depending on the structure of the gate driving circuit 200.

Therefore, the display device of the present invention is a scan pulse (Vout) applied to the display panel 100 through the dummy pad (DM-Pad) of the FPC connected to the test line (T-Line) to measure the scan pulse (Vout) ) Can be measured in real time at the desired time. In addition, there is an advantage that does not have to destroy the color filter (CF) formed on the top of the display device to measure the scan pulse (Vout).

The above description is merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may make various modifications and variations without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain the scope of the technical spirit of the present invention. The scope of protection of the present invention should be interpreted by the claims below, and all technical spirits within the equivalent range should be interpreted as being included in the scope of the present invention.

100: display panel 200: gate driving circuit
300: data driving circuit 400: timing controller
250: shift register 252: stage

Claims (12)

A display area in which a plurality of gate lines and a plurality of data lines are crossed, and a plurality of subpixels are disposed;
A gate driving circuit driving the plurality of gate lines;
A data driving circuit driving the plurality of data lines;
A pad region to which the data driving circuit and a flexible circuit board are bonded; And
And a test line connecting a scan signal output terminal of the gate driving circuit and a dummy pad disposed in the pad area.
According to claim 1,
A display device capable of measuring the scan signal through the dummy pad to which the test line is connected.
According to claim 1,
The sub-pixel
Light emitting diodes;
A driving transistor driving the light emitting diode;
A switching transistor electrically connected between the gate node of the driving transistor and the data line;
A sensing transistor electrically connected between a source node or a drain node of the driving transistor and a reference voltage line; And
And a storage capacitor electrically connected between a gate node of the switching transistor and a source node or a drain node.
According to claim 1,
The pad area
A first pad area connected to the data line and formed with first pads connected to a scan signal output terminal of the data driving circuit; And
A display device comprising a second pad area connected to the data pad and forming second pads that are connected to an output terminal of the flexible circuit board.
According to claim 4,
The first pad is a data pad display device.
According to claim 4,
The second pad includes the dummy pad.
According to claim 4,
And a connection pad area connecting the first pad area and the second pad area.
According to claim 1,
The gate driving circuit
It consists of a plurality of stages that supply a scan signal to the gate line during one frame,
The plurality of stages
A display device comprising a pull-up transistor and a pull-down transistor that output a scan pulse or a gate-off voltage according to a clock signal and scan pulses of different stages.
The method of claim 8,
The test line
A display device electrically connected to a source node or a drain node of a pull-up transistor and a pull-down transistor that outputs the scan pulse or gate off voltage.
The method of claim 9,
The test line
A display device made of the same material as a source node or a drain node of a pull-up transistor and a pull-down transistor that outputs the scan pulse or gate-off voltage.
According to claim 1,
The gate driving circuit
A display device formed by a gate-in-panel method embedded in a display panel formed in the display area.
According to claim 1,
The test line
A display device formed on an upper portion of an active layer and a lower portion of an insulating layer constituting the gate driving circuit.

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