KR20200080787A - Display apparatus - Google Patents

Abstract

The display device according to the present application includes: a pixel having a pixel circuit having a driving transistor and a light emitting element connected to the pixel circuit, and driven through a refresh period and a hold period; a data line selectively supplying a data voltage or a first reset voltage to a first node which is a source electrode of the driving transistor; and a reset line which supplies a second reset voltage to a second node which is an anode electrode of the light emitting element, wherein the pixel circuit receives the first reset voltage from the first node and the second reset voltage from the second node through at least one reset period during the hold period.

Description

Display device {DISPLAY APPARATUS}

The present application relates to a display device.

2. Description of the Related Art Display devices are widely used as display screens for notebook computers, tablet computers, smart phones, portable display devices, and portable information devices in addition to display devices for televisions or monitors. Such a display device includes a liquid crystal display device and a light emitting display device. The light-emitting display device is drawing attention as a next-generation display device because it displays an image using a self-luminous element, has a high-speed response speed, has low power consumption, and has no problem in viewing angle.

The light emitting display device includes a display panel having a plurality of pixels displaying an image, a gate driver supplying gate signals to pixels, and a data driver supplying data voltages to pixels. In addition, the plurality of pixels includes a light emitting element and a pixel circuit driving the light emitting element.

The pixel circuit is driven through a refresh period and a hold period in one frame. The pixel circuit may initialize the data voltage in the refresh period. Specifically, the pixel circuit can control the initialization rate and update rate of the data voltage by adjusting the period of the refresh period, and can prevent degradation of the driving transistor and the light emitting element. For example, when displaying a still image in which the data voltage need not be updated quickly, the pixel circuit can be driven at a low speed by reducing the initialization rate and update rate of the data voltage and reduce power consumption.

When the pixel circuit is driven at a low speed, the length of one frame section may increase. Accordingly, the length of the hold period in which the input data voltage is maintained may increase, and the pixel circuit may supply the driving current to the light emitting element while maintaining the light-emitting control signal continuously turned on in the hold period. have. In addition, as the length (or frame period) of one frame section increases, the length between adjacent refresh periods may also increase, and a decrease in luminance of the light emitting element may be perceived by the viewer's eyes. In addition, when the pixel circuit receives the data voltage of a low gray level, even after the refresh period is over, the driving current becomes low and a charging delay phenomenon in which the time at which the voltage of the anode electrode recovers to the target value increases may occur. have. Accordingly, a pixel driven at a low speed has a problem in that a flicker occurs due to a decrease in luminance and a delay in charging, thereby reducing visibility.

This application prevents the occurrence of flicker and visually prevents flicker by resetting the voltage of the anode electrode of the light emitting element through at least one reset period of the hold period separately from the refresh period for updating the data voltage during low-speed driving of the pixel. It is to provide a display device that can be improved.

In addition, the present application resets each of the source electrode of the driving transistor and the anode electrode of the light emitting element to different voltages when the pixel is driven at a low speed, so that charging time and falling width of the voltage of the anode electrode of the light emitting element ( It is to provide a display device capable of independently controlling the drop width).

In addition, the present application reduces the luminance of the light emitting element by controlling the voltage of the anode electrode of the light emitting element during at least one reset period during the hold period to correspond to the voltage of the anode electrode of the light emitting element during the refresh period. It is to provide a display device capable of preventing the viewer from being perceived by the viewer and removing flicker.

The display device according to the present application includes a pixel circuit having a driving transistor, a light emitting element connected to the pixel circuit, and a pixel driven through a refresh period and a hold period, a data voltage or a first voltage applied to a first node as a source electrode of the driving transistor. A data line selectively supplying a reset voltage, and a reset line supplying a second reset voltage to a second node that is an anode electrode of the light emitting element, wherein the pixel circuit is configured to perform the first through a reset period of at least one of the hold periods. The node receives the first reset voltage and the second node receives the second reset voltage.

Specific details of other examples are included in the detailed description and drawings.

The display device according to the present application generates flicker by resetting the voltage of the anode electrode of the light emitting element through at least one reset period of the hold period separately from the refresh period for updating the data voltage when the pixel is driven at a low speed. It can prevent and improve your vision.

The display device according to the present application resets each of the source electrode of the driving transistor and the anode electrode of the light emitting element to different voltages when driving the pixel at a low speed, thereby charging and falling the charging time of the voltage of the anode electrode of the light emitting element You can control the width (Drop width) independently.

The display device according to the present application controls the voltage of the anode electrode of the light emitting element in at least one reset period during the hold period to correspond to the voltage of the anode electrode of the light emitting element in the refresh period, when the pixel is driven at a low speed. It is possible to prevent the decrease in luminance from being perceived by the viewer's eyes and remove flicker.

In addition to the effects of the present application mentioned above, other features and advantages of the present application are described below, or will be clearly understood by those skilled in the art from the description and description.

1 is a view showing a display device according to an example of the present application.
2 is a circuit diagram illustrating pixels in the display device according to the first embodiment.
3 is a waveform diagram illustrating driving of a pixel circuit and a light emitting element in a pixel of the display device illustrated in FIG. 2.
4 is a diagram illustrating driving of a pixel circuit and a light emitting element in a refresh period in the pixels of the display device shown in FIG. 2.
5 is a diagram illustrating driving of a pixel circuit and a light emitting element in a light emission period during a hold period in a pixel of the display device illustrated in FIG. 2.
FIG. 6 is a diagram illustrating driving of a pixel circuit and a light emitting element in at least one reset period of a hold period in a pixel of the display device illustrated in FIG. 2.
7 is a diagram illustrating a process of controlling a voltage of an anode electrode of a light emitting element based on first and second reset voltages in a pixel of the display device illustrated in FIG. 2.
8 is a circuit diagram illustrating pixels in the display device according to the second embodiment.
9 is a waveform diagram illustrating driving of a pixel circuit and a light emitting element in a pixel of the display device illustrated in FIG. 8.

Advantages and features of the present application, and a method of achieving them will be clarified with reference to examples described below in detail together with the accompanying drawings. However, the present invention is not limited to the examples disclosed below, but will be implemented in various different forms, only the examples allow the disclosure of the present invention to be complete, and to those skilled in the art to which the present invention pertains. It is provided to fully inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining examples of the present application are exemplary, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in the description of the present application, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present application, the detailed description will be omitted. When'include','have','consist of' and the like mentioned in the present application are used, other parts may be added unless'~man' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship of two parts is described as'~top','~upper','~bottom','~side', etc.,'right' Alternatively, one or more other parts may be located between the two parts unless'direct' is used.

In the case of the description of the time relationship, for example,'after','following','~after','~before', etc., when the temporal sequential relationship is described,'right' or'direct' It may also include cases that are not continuous unless it is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

In describing the components of the present application, terms such as first and second may be used. These terms are only for distinguishing the component from other components, and the essence, order, order, or number of the component is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, the component may be directly connected to or connected to the other component, but different components between each component It should be understood that the "intervenes", or each component may be "connected", "coupled" or "connected" through other components.

Each of the features of the various examples of the present application may be partially or totally combined or combined with each other, technically various interlocking and driving may be possible, and each of the examples may be independently implemented with respect to each other or may be implemented together in an associative relationship. .

Hereinafter, preferred examples of the light emitting display device according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to the components of each drawing, the same components may have the same reference numerals as possible even though they are displayed on different drawings.

1 is a plan view illustrating a display device according to an example of the present application.

Referring to FIG. 1, the display device includes a display panel 100, a timing controller 300, a data driving circuit 500, and a scan driving circuit 700.

The display panel 100 may include a plurality of data lines DL, a plurality of scan lines SL, a plurality of voltage supply lines VL, and a plurality of pixels P.

Each of the plurality of data lines DL may be elongated along the first direction and may be spaced apart from each other along the second direction crossing the first direction. Each of the scan lines SL may be elongated along the second direction and may be spaced apart from each other along the first direction. Each of the plurality of voltage supply lines VL extends long along the first direction and may be spaced apart from each other along the second direction.

Each of the plurality of pixels P may be disposed for each pixel area defined by the scan line SL, the data line DL, and the voltage supply line VL disposed on the display area of the display panel 100.

According to an example, the plurality of pixels P may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. For example, red, green, and blue sub-pixels arranged along the length direction of the scan line SL (or data line DL) may constitute a unit pixel displaying one image. Additionally, the unit pixel may further include a white pixel.

According to an example, each of the plurality of pixels P may include a pixel circuit having a driving transistor, and a light emitting device connected to the pixel circuit.

The light emitting device may be interposed between the first electrode (or anode electrode) connected to the pixel circuit and the second electrode (or cathode electrode) connected to the common power source. According to an example, the light emitting device may include an organic light emitting device, a quantum dot light emitting device, an inorganic light emitting device, or a micro light emitting diode device. Such a light emitting device emits light in proportion to the amount of data current supplied from a pixel circuit, thereby emitting color light having a predetermined luminance.

The pixel circuit may drive the light emitting device by controlling the driving current flowing through the light emitting device based on the scan signal and the control signal. The configuration of the pixel circuit will be described in detail in FIG. 2 below.

The timing controller 300 may generate pixel data corresponding to each of the plurality of pixels P based on the image signal. The timing controller 300 may generate a data control signal based on the timing synchronization signal and provide it to the data driving circuit 500. According to an example, the timing controller 300 may generate a scan control signal including a start signal and a plurality of scan clock signals based on the timing synchronization signal and provide the scan control signal to the scan driving circuit 700. The timing controller 300 may additionally generate a plurality of carry clock signals according to the driving method of the scan driving circuit 700 and provide them to the scan driving circuit 700.

The data driving circuit 500 may be connected to a plurality of data lines DL provided on the display panel 100. The data driving circuit 500 may receive pixel data and a data control signal provided from the timing control unit 300 and receive a plurality of reference gamma voltages provided from the power supply circuit. The data driving circuit 500 may convert pixel data into an analog type pixel-specific data signal using a data control signal and a plurality of reference gamma voltages, and supply the converted pixel-specific data signal to a corresponding data line DL. .

The scan driving circuit 700 may be connected to a plurality of scan lines SL provided on the display panel 100. Specifically, the scan driving circuit 700 may generate a scan signal according to a predetermined order based on the scan control signal supplied from the timing controller 300 and supply the scan signal to the corresponding scan line SL.

According to an example, the scan driving circuit 700 may be integrated on one edge or both edges of the substrate according to a manufacturing process of the thin film transistor and connected one to one with a plurality of scan lines SL. For example, the scan driving circuit 700 may be configured in an integrated circuit and mounted on a substrate or mounted on a flexible circuit film to be connected one-to-one with a plurality of scan lines SL.

2 is a circuit diagram illustrating pixels in the display device according to the first embodiment.

Referring to FIG. 2, each of the plurality of pixels P may include a pixel circuit PC having a driving transistor Tdr, and a light emitting device LED connected to the pixel circuit PC.

The pixel circuit PC may drive the light emitting device LED by controlling the driving current ILED flowing through the light emitting device LED. According to an example, the pixel circuit PC may include driving transistors Tdr, first and second initialization transistors Ti1 and Ti2, data supply transistors Tds, reset transistor Tr, and first and second light emission control. Transistors Tec1 and Tec2, and a storage capacitor Cst.

The driving transistor Tdr may control the driving current ILED flowing through the light emitting device LED. The driving transistor Tdr may selectively connect the third node N3 and the first node N1. Specifically, the driving transistor Tdr is connected between the third node N3 and the first node N1 to provide a driving current ILED to the light emitting device LED. For example, the drain electrode of the driving transistor Tdr is connected to the third node N3, the source electrode of the driving transistor Tdr is connected to the first node N1, and the gate electrode of the driving transistor Tdr is May be connected to the fourth node N4.

The drain electrode of the driving transistor Tdr may be connected to the source electrode of the second emission control transistor Tec2 and the drain electrode of the second initialization transistor Ti2 through the third node N3. The source electrode of the driving transistor Tdr may be connected to the drain electrode of the first light emission control transistor Tec1 and the source electrode of the data supply transistor Tds through the first node N1. In addition, the gate electrode of the driving transistor Tdr may be connected to the source electrode of the second initialization transistor Ti2 and one end of the storage capacitor Cst through the fourth node N4. Accordingly, the driving transistor Tdr is turned on based on the voltage of the fourth node N4 to provide the driving current ILED provided from the third node N3 to the first node N1.

The first initialization transistor Ti1 is turned on based on the first scan signal SC1(n) to electrically connect the first voltage supply line VL1 and the second node N2. Here, the first voltage supply line VL1 may correspond to an initialization line that provides the initialization voltage Vini to the second node N2. Specifically, the drain electrode of the first initialization transistor Ti1 is connected to the first voltage supply line VL1, the source electrode of the first initialization transistor Ti1 is connected to the second node N2, and the first initialization The gate electrode of the transistor Ti1 may be connected to the first scan line SL1.

The drain electrode of the first initialization transistor Ti1 may receive the initialization voltage Vini from the first voltage supply line VL1. The source electrode of the first initialization transistor Ti1 is the source electrode of the first light emission control transistor Tec1, the source electrode of the reset transistor Tr, and the other end of the storage capacitor Cst through the second node N2. And it may be connected to the anode electrode of the light emitting device (LED). The gate electrode of the first initialization transistor Ti1 may receive the first scan signal SC1(n) from the first scan line SL1. Accordingly, the first initialization transistor Ti1 may be turned on based on the first scan signal SC1(n) to provide the initialization voltage Vini to the second node N2.

The second initialization transistor Ti2 is turned on based on the first scan signal SC1(n) to electrically connect the third node N3 and the fourth node N4. Specifically, the drain electrode of the second initialization transistor Ti2 is connected to the third node N3, the source electrode of the second initialization transistor Ti2 is connected to the fourth node N4, and the second initialization transistor ( The gate electrode of Ti2) may be connected to the first scan line SL1.

The drain electrode of the second initialization transistor Ti2 may be connected to the source electrode of the second light emission control transistor Tec2 and the drain electrode of the driving transistor Tdr through the third node N3. The source electrode of the second initialization transistor Ti2 may be connected to the gate electrode of the driving transistor Tdr and one end of the storage capacitor Cst through the fourth node N4. The gate electrode of the second initialization transistor Ti2 may receive the first scan signal SC1(n) from the first scan line SL1. Accordingly, the second initialization transistor Ti2 may be turned on based on the first scan signal SC1(n) to provide the voltage of the third node N3 to the fourth node N4.

The data supply transistor Tds is turned on based on the second scan signal SC2(n) to electrically connect the data line DL and the first node N1. Specifically, the drain electrode of the data supply transistor Tds is connected to the data line DL, the source electrode of the data supply transistor Tds is connected to the first node N1, and the gate of the data supply transistor Tds is The electrode may be connected to the second scan line SL2.

The drain electrode of the data supply transistor Tds may be supplied with a data voltage Vdata or a first reset voltage Vp1 from the data line DL. The source electrode of the data supply transistor Tds may be connected to the source electrode of the driving transistor Tdr and the drain electrode of the first light emission control transistor Tec1 through the first node N1. In addition, the gate electrode of the data supply transistor Tds may receive the second scan signal SC2(n) from the second scan line SL2.

According to an example, the pixel circuit PC may be driven through a refresh period and a hold period, and may be driven through a plurality of light emission periods and at least one reset period during the hold period. According to an example, the drain electrode of the data supply transistor Tds may receive the data voltage Vdata in the refresh period and may be supplied with the first reset voltage Vp1 in at least one reset period. Accordingly, the data supply transistor Tds is turned on based on the second scan signal SC2(n) to provide the data voltage Vdata or the first reset voltage Vp1 to the first node N1. Can.

According to an example, the reset transistor Tr is turned on based on the second scan signal SC2(n) to electrically connect the second voltage supply line VL2 and the second node N2. . Specifically, the drain electrode of the reset transistor Tr is connected to the second voltage supply line VL2, the source electrode of the reset transistor Tr is connected to the second node N2, and the gate of the reset transistor Tr The electrode may be connected to the second scan line SL2.

The drain electrode of the reset transistor Tr may receive the second reset voltage Vp2 from the second voltage supply line VL2. That is, the second voltage supply line VL2 may correspond to a reset line. In addition, the source electrode of the reset transistor Tr is the source electrode of the first light emission control transistor Tec1 through the second node N2, the source electrode of the first initialization transistor Ti1, the other end of the storage capacitor Cst, And it may be connected to the anode electrode of the light emitting device (LED). The gate electrode of the reset transistor Tr may receive the second scan signal SC2(n) from the second scan line SL2.

According to another example, the reset transistor Tr is turned on based on a separate scan signal different from the second scan signal SC2(n), so that the second voltage supply line VL2 and the second node N2 are turned on. Can be electrically connected. That is, each of the data supply transistor Tds and the reset transistor Tr is independently turned on, so that the reset transistor Tr is the second reset voltage Vp2 at a time independent of the supply time of the first reset voltage Vp1. ) To the second node N2. According to an example, the pixel circuit PC may be driven through a refresh period and a hold period, and a plurality of light emission periods and at least one reset period during the hold period It can be driven through. According to an example, the drain electrode of the reset transistor Tr may be supplied with the second reset voltage Vp2 during the refresh period and at least one reset period. Therefore, the reset transistor Tr may be turned on based on the second scan signal SC2(n) to provide the second reset voltage Vp2 to the second node N2.

The first emission control transistor Tec1 is turned on based on the first emission signal EM1 to electrically connect the first node N1 and the second node N2. Specifically, the drain electrode of the first emission control transistor Tec1 is connected to the first node N1, the source electrode of the first emission control transistor Tec1 is connected to the second node N2, and the first emission The gate electrode of the control transistor Tec1 may be connected to the first emission control line EML1.

The drain electrode of the first emission control transistor Tec1 may be connected to the source electrode of the driving transistor Tdr and the source electrode of the data supply transistor Tdr through the first node N1, and the first emission control transistor The source electrode of (Tec1) is the source electrode of the reset transistor (Tr) through the second node (N2), the other end of the storage capacitor (Cst), the source electrode of the first initialization transistor (Ti1), and the light emitting device (LED) It can be connected to the anode electrode. In addition, the gate electrode of the first emission control transistor Tec1 may receive the first emission signal EM1 from the first emission control line EML1. Accordingly, the first emission control transistor Tec1 is turned on based on the first emission signal EM1 to provide the voltage of the first node N1 to the second node N2.

The second emission control transistor Tec2 is turned on based on the second emission signal EM2 to electrically connect the driving power EVDD and the third node N3. Specifically, the drain electrode of the second emission control transistor Tec2 is connected to the driving power supply EVDD, the source electrode of the second emission control transistor Tec2 is connected to the third node N3, and the second emission control The gate electrode of the transistor Tec2 may be connected to the second emission control line EML2.

The drain electrode of the second emission control transistor Tec2 may be supplied with a driving voltage VDD from the driving power supply EVDD. The source electrode of the second light emission control transistor Tec2 may be connected to the drain electrode of the driving transistor Tdr and the drain electrode of the second initialization transistor Ti2 through the third node N3. In addition, the gate electrode of the second emission control transistor Tec2 may receive the second emission signal EM2 from the second emission control line EML2. Therefore, the second emission control transistor Tec2 is turned on based on the second emission signal EM2 to provide the driving voltage VDD to the third node N3.

The storage capacitor Cst may be connected between the fourth node N4 and the second node N2. Specifically, the storage capacitor Cst may control the voltage of the fourth node N4 by storing the difference voltage between the fourth node N4 and the second node N2. For example, even when the second initialization transistor Ti2 is turned off, the voltage of the fourth node N4 may be kept constant by a potential difference between one end and the other end of the storage capacitor Cst. As a result, the storage capacitor Cst can control the operation of the driving transistor Tdr by maintaining the voltage of the fourth node N4 constant even when the second initialization transistor Ti2 is turned off.

3 is a waveform diagram illustrating driving of a pixel circuit and a light emitting element in a pixel of the display device illustrated in FIG. 2.

Referring to FIG. 3, each of the plurality of pixels P may be driven through a refresh period and a hold period within one frame. In addition, the refresh period may include an initialization period P1, an on-bias stress period P2, and a programming/sampling period P3. In addition, the hold period may include a plurality of light emission periods ET and at least one reset period RT. Also, at least one reset period RT may include a reset preparation period P4 and an anode control period P5.

The first scan line SL1 may be connected to the gate electrode of the first initialization transistor Ti1 and the gate electrode of the second initialization transistor Ti2. Specifically, the first scan line SL1 supplies the first scan signal SC1(n) to each of the gate electrodes of the first and second initialization transistors Ti1 and Ti2, thereby providing the first and second initialization transistor Ti1. , Ti2) each can be turned on. Here, the first scan signal SC1(n) may have a high level in the initialization period P1 and the programming/sampling period P3 of the refresh period. Therefore, the first initialization transistor Ti1 is turned on in the initialization period P1 and the programming/sampling period P3 of the refresh period to provide the initialization voltage Vinit to the second node N2. have. In addition, the second initialization transistor Ti2 is turned on in the initialization period P1 and the programming/sampling period P3 of the refresh period to supply the voltage of the third node N3 to the fourth node N4. Can provide.

The second scan line SL2 may be connected to the gate electrode of the data supply transistor Tds and the gate electrode of the reset transistor Tr. Specifically, the second scan line SL2 may turn on the data supply transistor Tds by supplying the second scan signal SC2(n) to the gate electrode of the data supply transistor Tds. The second scan line SL2 may turn on the reset transistor Tr by supplying the second scan signal SC2(n) to the gate electrode of the reset transistor Tr. Here, the second scan signal SC2(n) is the on-bias stress period P2 and the programming/sampling period P3 of the refresh period, and the anode control period P5 of the reset period RT. In can have a high level (High). Accordingly, the data supply transistor Tds is turned on in the on-bias stress period P2 and the programming/sampling period P3 during the refresh period to transmit the data voltage Vdata to the first node N1. The first reset voltage Vp1 may be provided to the first node N1 by being turned on in the anode control period P5 of the reset period RT.

The first emission control line EML1 may be connected to the gate electrode of the first emission control transistor Tec1. Specifically, the first emission control line EML1 may turn on the first emission control transistor Tec1 by supplying the first emission signal EM1 to the gate electrode of the first emission control transistor Tec1. have. Here, the first emission signal EM1 may have a high level in a plurality of light emission periods ET. Accordingly, the first light emission control transistor Tec1 is turned on in the plurality of light emission periods ET to provide the voltage of the first node N1 to the second node N2.

The second emission control line EML2 may be connected to the gate electrode of the second emission control transistor Tec2. Specifically, the second emission control line EML2 may turn on the second emission control transistor Tec2 by supplying a second emission signal EM2 to the gate electrode of the second emission control transistor Tec2. have. Here, the second emission signal EM2 may have a high level in the initialization period P1 of the refresh period and the reset preparation period P4 of the at least one reset period RT. Accordingly, the second light emission control transistor Tec2 is turned on in the reset preparation period P4 of the initialization period P1 of the refresh period and at least one reset period RT, and turns on the driving voltage VDD. It can be provided to the third node (N3).

According to an example, when the plurality of pixels P is driven at a low speed, a light emitting device (LED) is provided through at least one reset period (RT) of a hold period separately from a refresh period for updating the data voltage. By resetting the voltage of the anode electrode, the occurrence of flicker can be prevented and the visibility can be improved.

For example, when a plurality of pixels P are driven at a low speed, the length of one frame section may increase, and the length of a hold period in which the input data voltage Vdata is maintained increases. can do. Here, the pixel P may display a relatively slowly changing image (eg, current time) through low-speed driving, and a relatively fast changing image (eg, TV program, through high-speed driving). Movie). For example, when the pixel circuit PC is driven at a low speed according to the frame frequency of 1 Hz, the refresh rate at which the data voltage Vdata is updated may correspond to 1 Hz, and 1 second ( It can be refreshed at one frame per 1 sec.(1 Frame/s).

According to an example, the hold period may include a plurality of light emission periods ET and at least one reset period RT. In addition, the second node N2 that is the anode electrode of the light emitting element LED may be reset in a refresh period and at least one reset period RT. That is, when the hold period includes n-1 (n is a natural number greater than or equal to 2) reset periods (RT1 to RT(n-1)), the second node N2 is for one frame Can be reset n times. Therefore, the display device according to the present application includes n-1 reset periods (RT1 to RT(n-1)) separately from the refresh period, so that the pixel circuit PC has a frame frequency of 1 Hz. Accordingly, even when the vehicle is driven at a low speed, by resetting the second node N2 n times, flicker can be removed by preventing the decrease in luminance of the light emitting element from being perceived by the viewer's eyes. As a result, the display device according to the present application includes n-1 reset periods (RT1 to RT(n-1)) separately from the refresh period, so that the pixel circuit PC has a frame frequency of 1 Hz. ), it can have the same reset effect as in the case of high-speed driving with n refresh periods.

Each of the plurality of pixels P may initialize a voltage charged or remaining in the pixel circuit PC during a refresh period. According to an example, the refresh period may be provided in a part of the start section of the frame. Specifically, each of the plurality of pixels P may remove the influence of the data voltage Vdata and the driving voltage VDD stored in the previous frame in the refresh period. Accordingly, the plurality of pixels P may display an image corresponding to a new data voltage Vdata in a hold period (or emission period ET) of the corresponding frame.

Each of the plurality of pixels P displays an image by providing a driving current ILED corresponding to the data voltage Vdata to a light emitting device LED during a hold period, and turns on the light emitting device LED. You can keep it. Specifically, the hold period of each of the plurality of pixels P may be continued from the time when the refresh period of the corresponding frame ends to the time when the refresh of the next frame begins. have.

In addition, each of the plurality of pixels P may emit light of the light emitting device LED through the plurality of light emission periods ET during the hold period, and at least one reset period RT of the hold period Through this, the light emitting device (LED) may be temporarily turned off. Specifically, each of the plurality of pixels P may emit light emitting elements LED during the plurality of light emission periods ET based on the data voltage Vdata updated during the refresh period. The light emitting device LED may be temporarily turned off through at least one reset period RT based on the second reset voltages Vp1 and Vp2.

Here, the first reset voltage Vp1 is supplied to the first node N1 which is the source electrode of the driving transistor Tdr for at least one reset period RT, so that the light emitting element LED is in the light emission period ET. The charging time or charging delay of the second node N2, which is the anode electrode, may be reduced. For example, as the first reset voltage Vp1 increases, the voltage of the first node N1, which is the source electrode of the driving transistor Tdr, may increase, and the gate-source voltage Vgs of the driving transistor Tdr, or The drain-source voltage Vds can be reduced. At this time, the size of the drain-source current Ids passing through the driving transistor Tdr may be reduced, and the stress of the driving transistor Tdr may be reduced in the positive bias stress situation to reduce the second node ( N2) Charging delay of voltage can be eliminated. Accordingly, the magnitude of the first reset voltage Vp1 may be determined to eliminate charging delay of the second node N2 voltage of at least one reset period RT.

In addition, the second reset voltage Vp2 is supplied to the second node N2 which is the anode electrode of the light emitting element LED during at least one reset period RT, so that the second node in the at least one reset period RT (N2) The drop width of the voltage can be controlled. Here, the second reset voltage Vp2 is supplied to the second node N2 through the reset transistor Tr, thereby directly determining the drop width of the second node N2 voltage. For example, the smaller the second reset voltage Vp2, the larger the falling width of the voltage of the second node N2, and the longer the charging time of the second node N2 voltage in the light emission period ET. . Accordingly, the display device may control the charging time of the second node N2 voltage by adjusting the magnitude of the second reset voltage Vp2. According to an example, the falling width of the voltage of the second node N2 in the at least one reset period RT refreshes the charging time of the voltage of the second node N2 in the at least one reset period RT. It may be determined to set the same as the charging time of the second node N2 voltage of the period. As a result, the display device according to the present application provides the second reset voltage Vp2 to the second node N2, thereby charging and refreshing the charging time of the second node N2 voltage in at least one reset period RT. The charging time of the second node N2 voltage in the (Refresh) period may be designed to be the same, and flicker may be removed by preventing the decrease in luminance of the light emitting device from being perceived by the viewer even when driving at a low speed.

As described above, the display device according to the present application provides the first reset voltage Vp1 to the first node N1 in at least one reset period RT apart from the refresh period, thereby providing the second node N2. Charging delay of the voltage may be controlled, and a second reset voltage Vp2 may be provided to the second node N2 to control a drop width of the second node N2 voltage. . As a result, the display device according to the present application provides the first and second reset voltages Vp1 and Vp2, respectively, to the first node N1 and the second node N2, respectively, thereby providing the second node N2. The charging time and the drop width of the voltage can be independently controlled, and the voltage of the anode electrode of the light emitting device (LED) in at least one reset period (RT) of the hold period is refreshed. It can be controlled to correspond to the voltage of the anode electrode of the light emitting element (LED) of the period. In other words, in the display device according to the present application, the charging time of the second node N2 voltage in at least one reset period RT is equal to the charging time of the second node N2 voltage in the refresh period. Can be controlled. That is, in the display device according to the present application, even when driving at a low speed, the luminance reduction of the light emitting element can be prevented from being perceived by the viewer's eyes and flicker can be removed.

Accordingly, the display device according to the present application may drive a pixel at a low speed to minimize unnecessary data voltage Vdata update or frame refresh, reduce power consumption, and hold separately from a refresh period. ) By resetting the voltage of the anode electrode of the light emitting element LED through at least one reset period RT, it is possible to prevent flicker caused by low-speed driving and improve visibility.

4 is a diagram illustrating driving of a pixel circuit and a light emitting element in a refresh period in the pixels of the display device shown in FIG. 2. Specifically, FIG. 4A is a view for explaining the driving of the initialization section P1 in the refresh period, and FIG. 4B is a view for explaining the operation of the on-bias stress section P2 in the refresh period, 4C is a view for explaining the driving of the programming/sampling section P3 during the refresh period.

In FIG. 4A, the first initialization transistor Ti1 is turned on in the initialization period P1 based on the first scan signal SC1(n) to provide the initialization voltage Vini to the second node N2. Can. That is, the second node N2, which is the anode electrode of the light emitting device LED, may be initialized by receiving the initialization voltage Vini in the initialization period P1.

Then, the second light emission control transistor Tec2 is turned on in the initialization period P1 based on the second emission signal EM2 to provide the driving voltage VDD to the third node N3, The second initialization transistor Ti2 is turned on in the initialization period P1 based on the first scan signal SC1(n) to provide the voltage of the third node N3 to the fourth node N4. have. That is, the second light emission control transistor Tec2 and the second initialization transistor Ti2 may be turned on at the same time in the initialization period P1, and the driving node VDD is a fourth node that is one end of the storage capacitor Cst ( N4).

In this way, in the initialization period P1, the driving voltage VDD may be supplied to the fourth node N4 which is one end of the storage capacitor Cst, and the initialization voltage Vini is the other end of the storage capacitor Cst. It may be supplied to the second node (N2). That is, the storage capacitor Cst may store the difference voltage VDD-Vini between the driving voltage VDD and the initialization voltage Vini in the initialization period P1.

In FIG. 4B, the first and second initialization transistors Ti1 and Ti2 and the second light emission control transistor Tec2 may be turned off. Then, the data supply transistor Tds is turned on in the on-bias stress period P2 based on the second scan signal SC2(n) to provide the data voltage Vdata to the first node N1. Can. In addition, the reset transistor Tr is turned on in the on-bias stress period P2 based on the second scan signal SC2(n) to provide the second reset voltage Vp2 to the second node N2. can do. Accordingly, the first node N1, which is the source electrode of the driving transistor Tdr, can continue to receive the data voltage Vdata, and the second node N2, which is the anode electrode of the light emitting element LED, is second reset. The voltage Vp2 can be supplied.

In FIG. 4C, the data supply transistor Tds and the reset transistor Tr may also be turned on in the programming/sampling period P3 based on the second scan signal SC2(n), and the first and second initialization The transistors Ti1 and Ti2 may be turned on in the programming/sampling period P3 based on the first scan signal SC1(n). At this time, the fourth node N4, which is the gate electrode of the driving transistor Tdr, may have the driving voltage VDD stored by the storage capacitor Cst before the programming/sampling period P3, and the driving transistor Tdr ), the first node N1 as the source electrode may have a data voltage Vdata provided in the immediately preceding on-bias stress period P2. That is, the gate-source voltage Vgs of the driving transistor Tdr may correspond to the difference voltage VDD-Vdata of the driving voltage VDD and the data voltage Vdata, and the driving transistor Tdr is the gate-source. The voltage Vgs becomes greater than the threshold voltage Vth and may be turned on. Accordingly, the moment the driving transistor Tdr is first turned on in the programming/sampling period P3, the drain-source current Ids of the driving transistor Tdr is the driving voltage VDD, the data voltage Vdata, and It may be determined according to the threshold voltage Vth of the driving transistor Tdr (Ids=k*(VDD-Vdata-Vth)^2). Then, the driving transistor Tdr provides the drain-source current Ids to the first node N1 until the gate-source voltage Vgs reaches the threshold voltage Vth of the driving transistor Tdr. Can. In this way, from the moment the driving transistor Tdr is first turned on in the programming/sampling period P3, the voltage of the fourth node N4 and the drain-source current Ids of the driving transistor Tdr are The voltage of the fourth node N4 may converge to a sum voltage Vdata + Vth of the data voltage Vdata and the threshold voltage Vth of the driving transistor Tdr.

5 is a diagram illustrating driving of a pixel circuit and a light emitting element in a light emission period during a hold period in a pixel of the display device illustrated in FIG. 2.

Referring to FIG. 5, the first emission control transistor Tec1 is turned on in the emission period ET of the hold period based on the first emission signal EM1 and the voltage of the first node N1 May be provided to the second node N2, and the second emission control transistor Tec2 is turned on in the emission period ET based on the second emission signal EM2 to remove the driving voltage VDD. It can provide to 3 nodes N3. In addition, the fourth node N4, which is the gate electrode of the driving transistor Tdr, before the light emission period ET, the data voltage Vdata stored by the storage capacitor Cst and the threshold voltage Vth of the driving transistor Tdr. The sum voltage (Vdata+Vth) of the driving transistor Tdr may be turned on because the gate-source voltage Vgs is greater than the threshold voltage Vth. Therefore, the second light emission control transistor Tec2, the driving transistor Tdr, and the first light emission control transistor Tec1 are turned on in the light emission period ET, so that the driving current ILED is applied to the light emitting device LED. Can provide.

According to an example, the drain-source current Ids of the driving transistor Tdr may be provided to the light emitting device LED through the first light emission control transistor Tec1. That is, the first emission control transistor Tec1 may provide the driving current ILED to the light emitting device LED based on the drain-source current Ids of the driving transistor Tdr. Accordingly, the driving current ILED may be determined by the drain-source current Ids of the driving transistor Tdr. In addition, when the driving transistor Tdr is first turned on in the light emission period ET, the drain-source current Ids of the driving transistor Tdr may be determined by the following equation.

Ids=ILED=k*(Vgs -Vth)^2=k*(Vdata+Vth-Vini-Vth)^2=k*(Vdata-Vini)^2

Here, k corresponds to a constant. That is, the driving current ILED may be determined by the data voltage Vdata and may not be affected by the threshold voltage Vth of the driving transistor Tdr. Accordingly, the display device according to the present application internally compensates for the characteristics of the threshold voltage Vth of the driving transistor Tdr, thereby removing deviations in the electrical characteristics of the driving transistor Tdr generated between the plurality of pixels, and thus, between pixels. The luminance deviation can be eliminated. As a result, the display device according to the present application may compensate for the threshold voltage characteristic of the driving transistor Tdr, thereby uniformly maintaining the luminance of the display panel.

FIG. 6 is a diagram illustrating driving of a pixel circuit and a light emitting element in at least one reset period of a hold period in a pixel of the display device illustrated in FIG. 2. Specifically, FIG. 6A is a diagram for explaining the driving of the reset preparation section P4 of the at least one reset period RT, and FIG. 6B shows the driving of the anode control section P5 of the at least one reset period RT. It is an explanatory drawing.

In FIG. 6A, the first light emission control transistor Tec1 maintains a turn-on state in the light emission period ET in a hold period, and may be turned off before the reset preparation period P4. Then, the second light emission control transistor Tec2 maintains the turn-on state in the light emission period ET and the reset preparation period P4 in the hold period, and then turns off before the start of the anode control period P5. Can be. As described above, the plurality of pixels P may be prepared to reset the second node N2 by turning off and turning on the first and second light emission control transistors Tec1 and Tec2 before the start of the anode control period P5. have.

In FIG. 6B, the data supply transistor Tds is turned on in the anode control period P5 based on the second scan signal SC2(n) to transmit the first reset voltage Vp1 to the first node N1. Can provide. Further, the reset transistor Tr may provide the second reset voltage Vp2 to the second node N2 in the anode control period P5 based on the second scan signal SC2(n). Accordingly, the first node N1, which is the source electrode of the driving transistor Tdr, can receive the first reset voltage Vp1, and the second node N2, which is the anode electrode of the light emitting element LED, is the second node N2. The reset voltage Vp2 may be supplied. Then, the first light emission control transistor Tec1 is turned off in the anode control section P5 of at least one reset period RT based on the first emission signal EM1, so that the first node N1 is The second node N2 may be electrically separated.

7 is a diagram illustrating a process of controlling a voltage of an anode electrode of a light emitting element based on first and second reset voltages in a pixel of the display device illustrated in FIG. 2. Here, the first embodiment (Embodiment 1) of FIG. 7 represents the voltage of the anode electrode during one frame period that does not include at least one reset period when the pixel is driven at a low speed according to a frame frequency of 1 Hz. In addition, in the second embodiment (Embodiment 2), when a pixel is driven at a low speed according to a frame frequency of 1 Hz, the first and second reset voltages Vp1 and Vp2 of at least one reset period RT according to the present application It represents the voltage of the anode electrode.

Referring to FIG. 7, when the first embodiment (Embodiment 1) is driven at a low speed according to a frame frequency of 1 Hz, the data voltage may be updated through a refresh period, but does not include a separate reset period. Therefore, the length of the hold period in which the input data voltage is maintained may increase. Therefore, the voltage of the anode electrode of the first embodiment (Embodiment 1) may cause a charging delay (Delay 1) of a considerable time until the anode voltage is charged after the data voltage is updated. Accordingly, in the low-speed driving method according to the first embodiment (Embodiment 1), as the length (or frame period) of one frame section increases, the length between adjacent refresh periods increases, so that the charging delay (Delay 1) and It has a problem that flicker occurs.

In comparison, in the second embodiment (Embodiment 2), the second node is provided by providing the first reset voltage Vp1 to the first node N1 in at least one reset period RT apart from the refresh period. The charging delay (Delay 2) of the (N2) voltage may be reduced, and the second node N2 may be provided with a second reset voltage Vp2 to control the drop width of the second node N2 voltage. can do.

Specifically, the first reset voltage Vp1 is supplied to the first node N1 that is the source electrode of the driving transistor Tdr for at least one reset period RT, so that the light emitting element LED is in the light emission period ET. The charging delay (Delay 2, Delay 3) of the second node N2, which is the anode electrode, may be reduced. For example, as the first reset voltage Vp1 increases, the voltage of the first node N1, which is the source electrode of the driving transistor Tdr, may increase, and the gate-source voltage Vgs of the driving transistor Tdr, or The drain-source voltage Vds can be reduced. At this time, the size of the drain-source current Ids passing through the driving transistor Tdr may be reduced, and the stress of the driving transistor Tdr may be reduced in the positive bias stress situation to reduce the second node ( N2) The voltage charging delay (Delay 2, Delay 3) can be eliminated. Accordingly, the magnitude of the first reset voltage Vp1 may be determined to solve the charging delays Delay 2 and Delay 3 of the second node N2 voltage of at least one reset period RT.

In addition, the second reset voltage Vp2 is supplied to the second node N2 which is the anode electrode of the light emitting element LED during at least one reset period RT, so that the second node in the at least one reset period RT (N2) The drop width of the voltage can be controlled. Here, the second reset voltage Vp2 is supplied to the second node N2 through the reset transistor Tr, thereby directly determining the drop width of the second node N2 voltage. For example, the smaller the second reset voltage Vp2, the larger the falling width of the second node N2 voltage, and the time during which the second node N2 voltage is charged in the light emission period ET (Delay 3). This can be long. Accordingly, the display device may control the charging time Delay 3 of the voltage of the second node N2 by adjusting the magnitude of the second reset voltage Vp2. According to an example, the falling width of the voltage of the second node N2 in the at least one reset period RT is the charging time (Delay 3) of the voltage of the second node N2 in the at least one reset period RT. It may be determined to set the same as the charging time (Delay 2) of the second node (N2) voltage in the refresh period. As a result, the display device according to the present application provides the second reset voltage Vp2 to the second node N2, so that the charging time Delay of the second node N2 voltage in at least one reset period RT 3) and the charging time (Delay 2) of the second node N2 voltage during the refresh period can be designed to be the same, and even when driving at low speed, the luminance reduction of the light emitting device is prevented from being perceived by the viewer's eyes. Flicker can be removed.

As described above, the display device according to the present application provides the first reset voltage Vp1 to the first node N1 in at least one reset period RT apart from the refresh period, thereby providing the second node N2. Charging delay of the voltage may be controlled, and a second reset voltage Vp2 may be provided to the second node N2 to control a drop width of the second node N2 voltage. . As a result, the display device according to the present application provides the first and second reset voltages Vp1 and Vp2, respectively, to the first node N1 and the second node N2, respectively, thereby providing the second node N2. The charging time and the drop width of the voltage can be independently controlled, and the charging time of the voltage of the second node N2 in the at least one reset period RT is set to a refresh period. It can be controlled in the same manner as the charging time of the second node N2 voltage. That is, in the display device according to the present application, even when driving at a low speed, the luminance reduction of the light emitting element can be prevented from being perceived by the viewer's eyes and flicker can be removed.

Accordingly, the display device according to the present application may drive a pixel at a low speed to minimize unnecessary data voltage Vdata update or frame refresh, reduce power consumption, and hold separately from a refresh period. ) By resetting the voltage of the anode electrode of the light emitting element LED through at least one reset period RT, it is possible to prevent flicker caused by low-speed driving and improve visibility.

8 is a circuit diagram illustrating pixels in the display device according to the second embodiment.

Referring to FIG. 8, each of the plurality of pixels P may include a pixel circuit PC having a driving transistor Tdr, and a light emitting device LED connected to the pixel circuit PC.

The pixel circuit PC may drive the light emitting device LED by controlling the driving current ILED flowing through the light emitting device LED. According to an example, the pixel circuit PC includes driving transistors Tdr, first and second initialization transistors Ti1 and Ti2, data supply transistors Tds, and first and second light emission control transistors Tec1 and Tec2. , And a storage capacitor Cst.

The driving transistor Tdr may control the driving current ILED flowing through the light emitting device LED. The driving transistor Tdr may selectively connect the third node N3 and the first node N1. Specifically, the driving transistor Tdr is connected between the third node N3 and the first node N1 to provide a driving current ILED to the light emitting device LED. For example, the drain electrode of the driving transistor Tdr is connected to the third node N3, the source electrode of the driving transistor Tdr is connected to the first node N1, and the gate electrode of the driving transistor Tdr is May be connected to the fourth node N4. Accordingly, the driving transistor Tdr is turned on based on the voltage of the fourth node N4 to provide the driving current ILED provided from the third node N3 to the first node N1.

The first initialization transistor Ti1 is turned on based on the third scan signal SC3(n) to electrically connect the voltage supply line VL and the second node N2. Here, the voltage supply line VL may correspond to an initialization line that provides an initialization voltage Vini to the second node N2, and provides a second reset voltage Vp2 to the second node N2. It may correspond to a reset line. Specifically, the drain electrode of the first initialization transistor Ti1 is connected to the voltage supply line VL, the source electrode of the first initialization transistor Ti1 is connected to the second node N2, and the first initialization transistor ( The gate electrode of Ti1) may be connected to the third scan line SL3.

According to an example, the pixel circuit PC may be driven through a refresh period and a hold period, and may be driven through a plurality of light emission periods and at least one reset period during the hold period. According to an example, the drain electrode of the first initialization transistor Ti1 may receive the initialization voltage Vini in the refresh period and be supplied with the second reset voltage Vp2 in at least one reset period. Accordingly, the first initialization transistor Ti1 is turned on based on the third scan signal SC3(n) to provide the initialization voltage Vini or the second reset voltage Vp2 to the second node N2. can do.

The second initialization transistor Ti2 is turned on based on the first scan signal SC1(n) to electrically connect the third node N3 and the fourth node N4. Specifically, the drain electrode of the second initialization transistor Ti2 is connected to the third node N3, the source electrode of the second initialization transistor Ti2 is connected to the fourth node N4, and the second initialization transistor ( The gate electrode of Ti2) may be connected to the first scan line SL1. Accordingly, the second initialization transistor Ti2 may be turned on based on the first scan signal SC1(n) to provide the voltage of the third node N3 to the fourth node N4.

The data supply transistor Tds is turned on based on the second scan signal SC2(n) to electrically connect the data line DL and the first node N1. Specifically, the drain electrode of the data supply transistor Tds is connected to the data line DL, the source electrode of the data supply transistor Tds is connected to the first node N1, and the gate of the data supply transistor Tds is The electrode may be connected to the second scan line SL2.

According to an example, the pixel circuit PC may be driven through a refresh period and a hold period, and may be driven through a plurality of light emission periods and at least one reset period during the hold period. According to an example, the drain electrode of the data supply transistor Tds may receive the data voltage Vdata in the refresh period and may be supplied with the first reset voltage Vp1 in at least one reset period. Accordingly, the data supply transistor Tds is turned on based on the second scan signal SC2(n) to provide the data voltage Vdata or the first reset voltage Vp1 to the first node N1. Can.

As such, each of the data supply transistor Tds and the first initialization transistor Ti1 may be turned on independently, and the data supply transistor Tds may be turned off at a time independent of the supply time of the second reset voltage Vp2. One reset voltage Vp1 may be provided to the first node N1.

The first emission control transistor Tec1 is turned on based on the first emission signal EM1 to electrically connect the first node N1 and the second node N2. Specifically, the drain electrode of the first emission control transistor Tec1 is connected to the first node N1, the source electrode of the first emission control transistor Tec1 is connected to the second node N2, and the first emission The gate electrode of the control transistor Tec1 may be connected to the first emission control line EML1. Accordingly, the first emission control transistor Tec1 is turned on based on the first emission signal EM1 to provide the voltage of the first node N1 to the second node N2.

The second emission control transistor Tec2 is turned on based on the second emission signal EM2 to electrically connect the driving power EVDD and the third node N3. Specifically, the drain electrode of the second emission control transistor Tec2 is connected to the driving power supply EVDD, the source electrode of the second emission control transistor Tec2 is connected to the third node N3, and the second emission control The gate electrode of the transistor Tec2 may be connected to the second emission control line EML2. Therefore, the second emission control transistor Tec2 is turned on based on the second emission signal EM2 to provide the driving voltage VDD to the third node N3.

The storage capacitor Cst may be connected between the fourth node N4 and the second node N2. Specifically, the storage capacitor Cst may control the voltage of the fourth node N4 by storing the difference voltage between the fourth node N4 and the second node N2. For example, even when the second initialization transistor Ti2 is turned off, the voltage of the fourth node N4 may be kept constant by a potential difference between one end and the other end of the storage capacitor Cst. As a result, the storage capacitor Cst can control the operation of the driving transistor Tdr by maintaining the voltage of the fourth node N4 constant even when the second initialization transistor Ti2 is turned off.

9 is a waveform diagram illustrating driving of a pixel circuit and a light emitting element in a pixel of the display device illustrated in FIG. 8.

Referring to FIG. 9, each of the plurality of pixels P may be driven through a refresh period and a hold period within one frame. In addition, the refresh period may include an initialization period P1, an on-bias stress period P2, and a programming/sampling period P3. In addition, the hold period may include a plurality of light emission periods ET and at least one reset period RT. Also, at least one reset period RT may include a reset preparation period P4 and an anode control period P5.

The first scan line SL1 may be connected to the gate electrode of the second initialization transistor Ti2. Specifically, the first scan line SL1 may turn on the second initialization transistor Ti2 by supplying the first scan signal SC1(n) to the gate electrode of the second initialization transistor Ti2. Here, the first scan signal SC1(n) may have a high level in the initialization period P1 and the programming/sampling period P3 of the refresh period. Therefore, the second initialization transistor Ti2 is turned on in the initialization period P1 and the programming/sampling period P3 of the refresh period to supply the voltage of the third node N3 to the fourth node N4. Can provide.

The second scan line SL2 may be connected to the gate electrode of the data supply transistor Tds. Specifically, the second scan line SL2 may turn on the data supply transistor Tds by supplying the second scan signal SC2(n) to the gate electrode of the data supply transistor Tds. Here, the second scan signal SC2(n) is the on-bias stress period P2 and the programming/sampling period P3 of the refresh period, and the anode control period P5 of the reset period RT. In can have a high level (High). Accordingly, the data supply transistor Tds is turned on in the on-bias stress period P2 and the programming/sampling period P3 during the refresh period to transmit the data voltage Vdata to the first node N1. The first reset voltage Vp1 may be provided to the first node N1 by being turned on in the anode control period P5 of the reset period RT.

The third scan line SL3 may be connected to the gate electrode of the first initialization transistor Ti1. Specifically, the third scan line SL3 may turn on the first initialization transistor Ti1 by supplying the third scan signal SC3(n) to the gate electrode of the first initialization transistor Ti1. Here, the third scan signal SC3(n) sets a high level (High) in the initialization period P1, the on-bias stress period P2, and the programming/sampling period P3 of the refresh period. Can have Further, the third scan signal SC3(n) may be turned on at a specific time in the reset preparation period P4 or the anode control period P5 of the reset period RT, and the first emission signal EM1 It can maintain a high level (High) until it has a high level. Accordingly, the first initialization transistor Ti1 is turned on in the refresh period to provide the initialization voltage Vini to the second node N2, and is turned on in the reset period RT to generate the second initialization transistor Ti1. The reset voltage Vp2 may be provided to the second node N2.

The first emission control line EML1 may be connected to the gate electrode of the first emission control transistor Tec1. Specifically, the first emission control line EML1 may turn on the first emission control transistor Tec1 by supplying the first emission signal EM1 to the gate electrode of the first emission control transistor Tec1. have. Here, the first emission signal EM1 may have a high level in a plurality of light emission periods ET. Accordingly, the first light emission control transistor Tec1 is turned on in the plurality of light emission periods ET to provide the voltage of the first node N1 to the second node N2.

The second emission control line EML2 may be connected to the gate electrode of the second emission control transistor Tec2. Specifically, the second emission control line EML2 may turn on the second emission control transistor Tec2 by supplying a second emission signal EM2 to the gate electrode of the second emission control transistor Tec2. have. Here, the second emission signal EM2 may have a high level in the initialization period P1 of the refresh period and the reset preparation period P4 of the at least one reset period RT. Accordingly, the second light emission control transistor Tec2 is turned on in the reset preparation period P4 of the initialization period P1 of the refresh period and at least one reset period RT, and turns on the driving voltage VDD. It can be provided to the third node (N3).

According to an example, when the plurality of pixels P is driven at a low speed, a light emitting device (LED) is provided through at least one reset period (RT) of a hold period separately from a refresh period for updating the data voltage. By resetting the voltage of the anode electrode, the occurrence of flicker can be prevented and the visibility can be improved.

For example, when a plurality of pixels P are driven at a low speed, the length of one frame section may increase, and the length of a hold period in which the input data voltage Vdata is maintained increases. can do. Here, the pixel P may display a relatively slowly changing image (eg, current time) through low-speed driving, and a relatively fast changing image (eg, TV program, through high-speed driving). Movie). For example, when the pixel circuit PC is driven at a low speed according to the frame frequency of 1 Hz, the refresh rate at which the data voltage Vdata is updated may correspond to 1 Hz, and 1 second ( It can be refreshed at one frame per 1 sec.(1 Frame/s).

According to an example, the hold period may include a plurality of light emission periods ET and at least one reset period RT. In addition, the second node N2 that is the anode electrode of the light emitting element LED may be reset in a refresh period and at least one reset period RT. That is, when the hold period includes n-1 (n is a natural number greater than or equal to 2) reset periods (RT1 to RT(n-1)), the second node N2 is for one frame Can be reset n times. Therefore, the display device according to the present application includes n-1 reset periods (RT1 to RT(n-1)) separately from the refresh period, so that the pixel circuit PC has a frame frequency of 1 Hz. Accordingly, even when the vehicle is driven at a low speed, by resetting the second node N2 n times, flicker can be removed by preventing the decrease in luminance of the light emitting element from being perceived by the viewer's eyes. As a result, the display device according to the present application includes n-1 reset periods (RT1 to RT(n-1)) separately from the refresh period, so that the pixel circuit PC has a frame frequency of 1 Hz. ), it can have the same reset effect as in the case of high-speed driving with n refresh periods.

Each of the plurality of pixels P may initialize a voltage charged or remaining in the pixel circuit PC during a refresh period. According to an example, the refresh period may be provided in a part of the start section of the frame. Specifically, each of the plurality of pixels P may remove the influence of the data voltage Vdata and the driving voltage VDD stored in the previous frame in the refresh period. Accordingly, the plurality of pixels P may display an image corresponding to a new data voltage Vdata in a hold period (or emission period ET) of the corresponding frame.

Each of the plurality of pixels P displays an image by providing a driving current ILED corresponding to the data voltage Vdata to a light emitting device LED during a hold period, and turns on the light emitting device LED. You can keep it. Specifically, the hold period of each of the plurality of pixels P may be continued from the time when the refresh period of the corresponding frame ends to the time when the refresh of the next frame begins. have.

In addition, each of the plurality of pixels P may emit light of the light emitting device LED through the plurality of light emission periods ET during the hold period, and at least one reset period RT of the hold period Through this, the light emitting device (LED) may be temporarily turned off. Specifically, each of the plurality of pixels P may emit light emitting elements LED during the plurality of light emission periods ET based on the data voltage Vdata updated during the refresh period. The light emitting device LED may be temporarily turned off through at least one reset period RT based on the second reset voltages Vp1 and Vp2.

Here, the first reset voltage Vp1 is supplied to the first node N1 which is the source electrode of the driving transistor Tdr for at least one reset period RT, so that the light emitting element LED is in the light emission period ET. The charging time or charging delay of the second node N2, which is the anode electrode, may be reduced. For example, as the first reset voltage Vp1 increases, the voltage of the first node N1, which is the source electrode of the driving transistor Tdr, may increase, and the gate-source voltage Vgs of the driving transistor Tdr, or The drain-source voltage Vds can be reduced. At this time, the size of the drain-source current Ids passing through the driving transistor Tdr may be reduced, and the stress of the driving transistor Tdr may be reduced in the positive bias stress situation to reduce the second node ( N2) Charging delay of voltage can be eliminated. Accordingly, the size of the first reset voltage Vp1 may be determined to eliminate charging delay of the second node N2 voltage of at least one reset period RT.

In addition, the second reset voltage Vp2 is supplied to the second node N2 which is the anode electrode of the light emitting element LED during at least one reset period RT, so that the second node in the at least one reset period RT (N2) The drop width of the voltage can be controlled. Here, the second reset voltage Vp2 is supplied to the second node N2 through the first initialization transistor Ti1, thereby directly determining the drop width of the second node N2 voltage. For example, the smaller the second reset voltage Vp2, the larger the falling width of the voltage of the second node N2, and the longer the charging time of the second node N2 voltage in the light emission period ET. . Accordingly, the display device may control the charging time of the voltage of the second node N2 by adjusting the magnitude of the second reset voltage Vp2. According to an example, the falling width of the voltage of the second node N2 in the at least one reset period RT refreshes the charging time of the voltage of the second node N2 in the at least one reset period RT. It may be determined to set the same as the charging time of the second node N2 voltage of the period. As a result, the display device according to the present application provides the second reset voltage Vp2 to the second node N2, thereby charging and refreshing the charging time of the second node N2 voltage in at least one reset period RT. The charging time of the second node N2 voltage in the (Refresh) period may be designed to be the same, and flicker may be removed by preventing the decrease in luminance of the light emitting device from being perceived by the viewer even when driving at a low speed.

As described above, the display device according to the present application provides the first reset voltage Vp1 to the first node N1 in at least one reset period RT apart from the refresh period, thereby providing the second node N2. Charging delay of the voltage may be controlled, and a second reset voltage Vp2 may be provided to the second node N2 to control a drop width of the second node N2 voltage. . As a result, the display device according to the present application provides the first and second reset voltages Vp1 and Vp2, respectively, to the first node N1 and the second node N2, respectively, thereby providing the second node N2. The charging time and the drop width of the voltage can be independently controlled, and the voltage of the anode electrode of the light emitting device (LED) in at least one reset period (RT) of the hold period is refreshed. It can be controlled to correspond to the voltage of the anode electrode of the light emitting element (LED) of the period. In other words, in the display device according to the present application, the charging time of the second node N2 voltage in at least one reset period RT is equal to the charging time of the second node N2 voltage in the refresh period. Can be controlled. That is, in the display device according to the present application, even when driving at a low speed, the luminance reduction of the light emitting element can be prevented from being perceived by the viewer's eyes and flicker can be removed.

Accordingly, the display device according to the present application may drive a pixel at a low speed to minimize unnecessary data voltage Vdata update or frame refresh, reduce power consumption, and hold separately from a refresh period. ) By resetting the voltage of the anode electrode of the light emitting element LED through at least one reset period RT, it is possible to prevent flicker caused by low-speed driving and improve visibility.

The display device according to the exemplary embodiment of the present application may be described as follows.

The display device according to the present application includes a pixel circuit having a driving transistor, a light emitting element connected to the pixel circuit, and a pixel driven through a refresh period and a hold period, a data voltage or a first voltage applied to a first node as a source electrode of the driving transistor. A data line for selectively supplying a reset voltage, and a reset line for supplying a second reset voltage to a second node that is an anode electrode of the light emitting element, wherein the pixel circuit is configured to perform the reset through at least one reset period of the hold period. The first reset voltage may be received by one node and the second reset voltage may be received by the second node.

According to some embodiments of the present application, the pixel circuit may receive the data voltage from the data line during the refresh period.

According to some embodiments of the present application, the pixel circuit emits light emitting elements through a plurality of light emission periods of the hold period based on the data voltage, and at least one reset period of the hold period based on the first and second reset voltages Through this, the light emitting device may be temporarily turned off.

According to some embodiments of the present application, the pixel circuit includes a data supply transistor selectively connecting the data line and the first node, a reset transistor selectively connecting the reset line and the second node, and a first node and the second node. A first light emission control transistor to be selectively connected may be further included.

According to some embodiments of the present application, the data supply transistor may be turned on in the on-bias stress period and the programming/sampling period of the refresh period based on the second scan signal to provide the data voltage to the first node. .

According to some embodiments of the present application, the data supply transistor may be turned on in the anode control period of at least one reset period based on the second scan signal to provide the first reset voltage to the first node.

According to some embodiments of the present application, the reset transistor may be turned on in the anode control period of at least one reset period to provide the second reset voltage to the second node.

According to some embodiments of the present application, the first light emission control transistor is turned off in the reset preparation period and the anode control period of at least one reset period based on the first emission signal, so that the first node and the second node are turned off. It can be electrically isolated.

According to some embodiments of the present application, the first emission control transistor may be turned on in the emission period of the hold period based on the first emission signal to provide the voltage of the first node to the second node.

According to some embodiments of the present application, the pixel circuit includes a first initialization transistor that selectively provides an initialization voltage to a second node, and a second emission control transistor that selectively provides a driving voltage to a third node that is a drain electrode of the driving transistor. , A second initialization transistor selectively connecting the third node and a fourth node that is a gate electrode of the driving transistor, and a storage capacitor connected between the second node and the fourth node.

According to some embodiments of the present application, the first initialization transistor may be turned on in the initialization period and the programming/sampling period of the refresh period based on the first scan signal to provide the initialization voltage to the second node.

According to some embodiments of the present application, the second initialization transistor may be turned on in the initialization period and the programming/sampling period of the refresh period based on the first scan signal to provide the voltage of the third node to the fourth node. .

According to some embodiments of the present application, the second emission control transistor is turned on in each of the initialization period of the refresh period, the emission period of the hold period, and the reset preparation period of the at least one reset period based on the second emission signal. As a result, the driving voltage can be provided to the third node.

According to some embodiments of the present application, the pixel circuit includes a data supply transistor selectively connecting the data line and the first node, a first initialization transistor selectively connecting the reset line and the second node, and a first node and the second node. A first light emission control transistor selectively connecting the nodes may be further included.

According to some embodiments of the present application, the data supply transistor may be turned on in the anode control period of at least one reset period based on the second scan signal to provide the first reset voltage to the first node.

According to some embodiments of the present application, the first initialization transistor may be turned on in the anode control period of the at least one reset period based on the third scan signal to provide the second reset voltage to the second node.

The present application described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this application belongs that various substitutions, modifications, and changes are possible without departing from the technical details of the present application. It will be clear to those who have the knowledge of Therefore, the scope of the present application is indicated by the claims, which will be described later, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be interpreted to be included in the scope of the present application.

100: display panel 300: timing control
500: data driving circuit 700: scan driving circuit
P: Pixel PC: Pixel circuit
LED: light emitting element

Claims (16)

A pixel circuit having a driving transistor and a light emitting element connected to the pixel circuit, the pixel being driven through a refresh period and a hold period;
A data line selectively supplying a data voltage or a first reset voltage to a first node that is a source electrode of the driving transistor; And
And a reset line for supplying a second reset voltage to a second node that is an anode electrode of the light emitting element,
The pixel circuit receives the first reset voltage at the first node and the second reset voltage at the second node through at least one reset period of the hold period. According to claim 1,
And the pixel circuit receives the data voltage from the data line during the refresh period. According to claim 1,
The pixel circuit emits the light emitting elements through a plurality of light emission periods of the hold period based on the data voltage, and through the at least one reset period of the hold period based on the first and second reset voltages. A display device that temporarily turns off a light emitting element. According to claim 1,
The pixel circuit,
A data supply transistor selectively connecting the data line and the first node;
A reset transistor selectively connecting the reset line and the second node; And
And a first light emission control transistor that selectively connects the first node and the second node. The method of claim 4,
The data supply transistor is turned on in an on-bias stress period and a programming/sampling period of the refresh period based on a second scan signal to provide the data voltage to the first node. The method of claim 4,
The data supply transistor is turned on in an anode control period of the at least one reset period based on a second scan signal to provide the first reset voltage to the first node. The method of claim 4,
The reset transistor is turned on in an anode control period of the at least one reset period to provide the second reset voltage to the second node. The method of claim 4,
The first light emission control transistor is turned off in a reset preparation period and an anode control period of the at least one reset period based on a first emission signal to electrically separate the first node and the second node, Display device. The method of claim 4,
The first light emission control transistor is turned on in the light emission period of the hold period based on a first emission signal to provide a voltage of the first node to the second node. The method of claim 4,
The pixel circuit,
A first initialization transistor selectively providing an initialization voltage to the second node;
A second light emission control transistor selectively providing a driving voltage to a third node that is a drain electrode of the driving transistor;
A second initialization transistor selectively connecting the third node and a fourth node that is a gate electrode of the driving transistor; And
And a storage capacitor connected between the second node and the fourth node. The method of claim 10,
The first initialization transistor is turned on in an initialization period and a programming/sampling period of the refresh period based on a first scan signal to provide the initialization voltage to the second node. The method of claim 10,
The second initialization transistor is turned on in an initialization period and a programming/sampling period of the refresh period based on a first scan signal to provide a voltage of the third node to the fourth node. The method of claim 10,
The second light emission control transistor is turned on in each of the initialization period of the refresh period, the light emission period of the hold period, and the reset preparation period of the at least one reset period based on the second emission signal to turn on the driving voltage. A display device provided to the third node. According to claim 1,
The pixel circuit,
A data supply transistor selectively connecting the data line and the first node;
A first initialization transistor selectively connecting the reset line and the second node; And
And a first light emission control transistor that selectively connects the first node and the second node. The method of claim 14,
The data supply transistor is turned on in an anode control period of the at least one reset period based on a second scan signal to provide the first reset voltage to the first node. The method of claim 14,
The first initialization transistor is turned on in an anode control period of the at least one reset period based on a third scan signal to provide the second reset voltage to the second node.

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