KR20200081973A - Light emitting display apparatus - Google Patents

Abstract

A light emitting display device according to an embodiment of the present specification includes: a light emitting display panel having pixels including light emitting elements and pixel driving circuits; a gate driver which supplies scan signals to scan lines provided in the light emitting display panel; a data driver which supplies data voltages to data lines provided in the light emitting display panel; a control unit which controls the gate driver and gate driver, wherein the data lines are connected to a reset voltage switching unit for supplying reset voltages to reset the light emitting devices to the pixels, and the reset voltages are set differently for each color of the pixels, thereby preventing defects such as a flicker defect, a color coordinate mismatch, or a luminance mismatch.

Description

Light emitting display device {LIGHT EMITTING DISPLAY APPARATUS}

The present invention relates to a light emitting display device driven at low speed.

A light emitting display device using a light emitting element such as an organic light emitting diode can be driven by various driving frequencies.

For example, a light emitting display device driven at 60 Hz can output 60 images for 1 second.

When the screen output from the light-emitting display device by the images is a still image or a low-speed video that is changed to a low speed, the light-emitting display device outputs one image only in one frame period of a period of 1 second, that is, the remaining period, that is, In the 59 frame periods, a new image is not output, and only the already output image can be maintained. By this method, a still image or a slow motion image can be displayed through the light emitting display device.

In this case, in order to improve flicker, in the remaining frame periods in which no image is output, an anode reset method is applied in which the anode of the light emitting element is reset by a reset voltage.

However, in the conventional light emitting display device, the same reset voltage is supplied to all pixels, and thus, defects such as color coordinate misalignment or luminance misalignment are generated.

An object of the present invention proposed to solve the above-described problem is that the magnitudes of reset voltages supplied to light emitting elements in frame periods during which no image is output are set differently according to the color of pixels. Is to provide

A light emitting display device according to the present invention for achieving the above-described technical problem is to supply scan signals to a light emitting display panel provided with pixels including light emitting elements and pixel driving circuits, scan lines provided in the light emitting display panel It includes a gate driver, a data driver that supplies data voltages to data lines provided in the light emitting display panel, and a control unit that controls the gate driver and the gate driver. A reset voltage switching unit for supplying reset voltages for resetting light emitting elements to pixels is connected to the data lines, and reset voltages are set differently for each color of pixels.

According to the present invention, even if one data voltage is supplied to the pixels for a period of 1 second, flicker failure is not caused by the reset voltages.

In particular, in the present invention, reset voltages for resetting the light emitting device may be set differently for each color of pixels, and accordingly, defects such as color coordinate distortion or luminance distortion can be prevented.

1 is an exemplary view showing a configuration of a light emitting display device according to the present invention.
2 is an exemplary view showing a configuration of a pixel applied to a light emitting display device according to the present invention.
3 is an exemplary view showing a configuration of a control unit applied to a light emitting display device according to the present invention.
4 is an exemplary view showing a configuration of a gate driver applied to a light emitting display device according to the present invention.
5 is an exemplary diagram for describing a method in which the pixel illustrated in FIG. 2 is driven.
6 is an exemplary view showing a configuration of a reset voltage switching unit applied to a light emitting display device according to the present invention.
7 is a graph showing characteristics of reset voltages applied to a light emitting display device according to the present invention.
8 is another exemplary view showing a configuration of a reset voltage switching unit applied to a light emitting display device according to the present invention.
9 is another exemplary view showing a configuration of a reset voltage switching unit applied to a light emitting display device according to the present invention.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the present embodiments make the disclosure of the present invention complete, and have ordinary knowledge in the technical field to which the present invention pertains. It is provided to fully inform the person of the scope of the invention, and the invention is only defined by the scope of the claims.

It should be noted that in this specification, when adding reference numerals to components of each drawing, the same components have the same number as possible, even if they are displayed on different drawings.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. When'include','have','consist of', etc. mentioned in the specification are used, other parts may be added unless'~man' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship of two parts is described as'~top','~upper','~bottom','~side', etc.,'right' Alternatively, one or more other parts may be located between the two parts unless'direct' is used.

In the case of the description of the time relationship, for example,'after','following','~after','~before', etc., when the temporal sequential relationship is described,'right' or'direct' It may also include cases that are not continuous unless it is used.

It should be understood that the term “at least one” includes all possible combinations from one or more related items. For example, the meaning of'at least one of the first item, the second item, and the third item' means 2 of the first item, the second item, and the third item, as well as the first item, the second item, or the third item, respectively. Any combination of items that can be presented from more than one dog.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Each of the features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving may be possible, and each of the embodiments may be independently performed with respect to each other or may be implemented together in an associative relationship. It might be.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view showing a configuration of a light emitting display device according to the present invention, FIG. 2 is an exemplary view showing a configuration of a pixel applied to a light emitting display device according to the present invention, and FIG. 3 is a light emitting display device according to the present invention It is an exemplary view showing the configuration of a control unit applied to.

The light emitting display device according to the present invention, as shown in Figures 1 and 2, a light emitting display panel 100 is provided with pixels 110 including light emitting elements (ED) and pixel driving circuit (PDC), The gate driver 200 supplies scan signals to the scan lines GL provided in the light emitting display panel 100, and supplies the data voltages Vdata to the data lines DL provided in the light emitting display panel 100. The data driver 300, the gate driver 200 and the control unit 400 for controlling the gate driver 300, and the gate driver 200, the control unit 400, and a power supply for supplying power to the data driver 300 Includes.

The reset voltage switching unit 600 for supplying the reset voltages Vp for resetting the light emitting elements ED to the pixels is connected to the data lines DL, and the reset voltages are different for each color of the pixels 110. It is set differently. The reset voltage switching unit 600 may be provided in the non-display area 130 of the light emitting display panel 100, or may be provided in the data driver 300. In addition, some of the reset voltage switching unit 600 may be provided in the non-display area 130, and some of the reset voltage switching unit 600 may be provided in the data driver 300.

In the following, components are sequentially described.

First, the light emitting display panel 100 according to the present invention surrounds the display area 120 and the display area 120 in which the pixels 110 including the light emitting elements ED and the pixel driving circuits PDC are provided. The non-display area 130 is included.

As illustrated in FIG. 2, the light emitting display panel 100 includes pixels 110 including a light emitting device ED and a pixel driving circuit PDC. Further, the light emitting display panel 100 is formed with signal lines defining a pixel region in which the pixels 110 are formed and supplying driving signals to the pixel driving circuit PDC.

The light emitting element ED includes a first electrode, a light emitting layer provided on the first electrode, and a second electrode provided on the light emitting layer. The emission layer may include any one of a blue light emitting unit, a green light emitting unit, and a red light emitting unit for emitting light having a color corresponding to the color set in the pixel 110. In the light emitting layer, a white light emitting unit may be additionally disposed to increase the efficiency of the light emitting layer. The emission layer may include any one of an organic emission layer, an inorganic emission layer, and a quantum dot emission layer, or may include a stacked or mixed structure of an organic emission layer (or inorganic emission layer) and a quantum dot emission layer.

The signal lines are the first scan line GL1, the second scan line GL2, the data line DL, the first emission line EL1, the second emission line EL2, the initialization line IL, and It may include a first driving voltage line (PLA) and the second driving voltage line (PLB).

The first scan line GL1 may be formed side by side to have a constant interval along a first direction, for example, a horizontal direction, of the light emitting display panel 100. The first scan signal SCAN1 is supplied from the gate driver 200 to the pixel driving circuits PDCs through the first scan line GL1.

The second scan line GL2 may be formed alongside the first scan line GL1 along the first direction. The second scan signal SCAN2 is supplied from the gate driver 200 to the pixel driving circuit PDC through the second scan line GL2.

The data line DL intersects the first scan line GL1, the second scan line GL2, the initialization line IL, the first emission line EL1, and the second emission line EL2, The light emitting display panel 100 may be formed side by side to have a constant interval along a second direction, for example, a vertical direction. The data voltage Vdata is supplied to the data line DL.

The first driving voltage line PLA may be formed to be parallel to the data lines DL in the second direction. The first driving voltage line PLA is connected to the power supply unit and supplies the first driving voltage VDD supplied from the power supply unit to the pixel driving circuit PDC.

The second driving voltage line PLB supplies the second driving voltage VSS supplied from the power supply unit to the pixel driving circuit PDC.

The first emission line EL1 extends in the first direction. The first emission signal EM1 for controlling the light emission timing of the light emitting element ED is supplied from the gate driver 200 to the pixel driving circuit PDC through the first emission line EL.

The second emission line EL2 extends in the first direction. The second emission signal EM2 for controlling the light emission timing of the light emitting device ED is supplied from the gate driver 200 to the pixel driving circuit PDC through the second emission lines EL.

The initialization line IL may extend in the first direction or may extend in the second direction. The initialization voltage Vini is supplied from the power supply unit to the pixel driving circuit PDC through the initialization line IL.

Each of the pixels 110 is provided with a light emitting element ED and a pixel driving circuit PDC.

For example, the pixel driving circuit PDC includes a driving transistor Tdr that controls the amount of current I flowing through the light emitting element ED, and a first transistor connected between the data line DL and the driving transistor Tdr. (T1), a second transistor T2 for controlling the light emission timing of the light emitting element ED, and a storage capacitor Cst may be provided.

That is, the pixel driving circuit PDC may include a first transistor T1, a second transistor T2, a driving transistor Tdr, and a capacitor Cst, and flows through the light emitting element ED using components. The magnitude of the current I can be controlled, and according to the magnitude of the current I, the brightness of the light output from the light emitting element ED can be controlled.

In addition, transistors for external compensation or internal compensation may be further provided in the pixel driving circuit PDC provided in each of the pixels 110.

That is, the pixel driving circuit (PDC) may be changed into various structures to perform internal compensation or external compensation, and the method of driving the pixel driving circuit (PDC) may also be variously changed.

The external compensation means calculating a change in the threshold voltage or mobility of the driving transistor Tdr formed in the pixel 110 to vary the size of the data voltages Vdata supplied to the pixel according to the change amount. . Accordingly, the structure of the pixel 110 may be changed in various forms so that a change in threshold voltage or mobility of the driving transistor Tdr can be calculated.

The internal compensation means that the current transmitted to the light emitting element of the driving transistor Tdr formed in the pixel 110 is not affected by the threshold voltage of the driving transistor Tdr. To this end, in the formula for calculating the current I, the structure and driving method of the pixel can be changed in various forms so that the threshold voltage can be removed. 2 shows a pixel driving circuit (PDC) for performing internal compensation as an example of the present invention.

Second, the gate driver 200 supplies scan signals SCAN1 and SCAN2 and emission signals EM1 and EM2 to the pixel driving circuits PDC.

The gate driver 200 is provided in the non-display area 130 and may be manufactured together with the pixel driving circuits PDC when manufacturing the pixel driving circuits PDC.

That is, the gate driver 200 may be directly embedded in the non-display area 130 of the light emitting display panel 100 by using a gate in panel (GIP) method.

However, the gate driver 200 is formed to be independent of the light emitting display panel 100, so that the light emitting display panel 100 may be formed through a tape carrier package (TCP), a chip on film (COF), or a flexible printed circuit board (FPCB). Can be connected to.

The gate driver 200 includes stages connected to a scan line GL provided in the light emitting display panel 100.

The gate driver 200 supplies the scan-on signal to the scan lines GL provided in the light emitting display panel 100 using the gate control signals GCS transmitted from the control unit 400. To this end, the gate control signals GCS may include a plurality of gate clocks.

Here, the scan-on signal means a signal that can turn on the second scan line GL2 (or the first transistor T1 (or the third transistor T3) connected to the first scan lines GL1). The signal capable of turning off the first transistor T1 (or the third transistor T3) is referred to as a scan-off signal, collectively referred to as a scan signal SCAN.

The gate driver 200 supplies an emission-on signal to the emission lines EL1 and EL2 provided in the light emitting display panel 100 by using the gate control signals GCS transmitted from the control unit 400. . To this end, the gate control signals GCS may include a plurality of emission clocks.

Here, the emission on signal may turn on the second transistor T2 (or the fourth transistor T4) connected to the first emission line EL1 (or the second emission line EL2). It means a signal. The signal capable of turning off the second transistor T2 (or the fourth transistor T4) is called an emission off signal. The emission on signal and the emission off signal are collectively referred to as an emission signal EM.

The configuration and function of the gate driver 200 will be described in detail below with reference to FIG. 4.

Third, the power supply unit supplies power to the gate driver 200, the data driver 300, the reset voltage switching unit 600, and the control unit 400.

Fourth, the data driver 300 converts the image data Data transmitted from the control unit 400 into data voltages Vdata and supplies the data voltages Vdata to the data lines DL.

Fifth, the control unit 400 controls the driving of the gate control signal GCS and the data driver 300 to control the driving of the gate driver 200 by using the timing synchronization signal TSS input from an external system. Data control signals (DCS) for each are generated.

In addition, the control unit 400 converts input image data Ri, Gi, Bi input from an external system into image data, and transmits the image data to the data driver 300.

In order to perform the above-described function, the control unit 400, as shown in FIG. 3, uses the timing synchronization signal (TSS) transmitted from the external system, input image data (Ri) transmitted from the external system , Gi, Bi) by rearranging the data alignment unit 430 for supplying the rearranged image data to the data driver 300, the gate control signal GCS and the data control signal DCS using the timing synchronization signal TSS. ) To generate a control signal generator 420, a timing synchronization signal (TSS) transmitted from an external system and input image data (Ri, Gi, Bi), a data aligner 430 and a control signal generator 420 ) To output the image data generated by the input unit 410 and the data alignment unit and the control signals DCS and GCS generated by the control signal generation unit to the data driver 300 or the gate driver 200. It may include an output unit 440 for.

In addition, the control unit 400 may further include a storage unit 450 for storing at least one of information necessary for generating control signals, information necessary for generating image data, and information necessary for compensation. have. However, the storage unit 450 may be configured independently of the control unit 400.

In particular, the control signal generation unit 420 may generate a switching unit control signal (SCS) for controlling the reset voltage switching unit 600.

The gate driver 200 may be controlled by a gate control signal GCS generated by the control signal generator 420. To this end, the gate control signal GCS may include gate clocks, gate start signals, emission clocks, and emission start signals.

The data driver 300 may be controlled by a data control signal (DCS) generated by the control signal generator 420. The data control signal DCS may include various types of signals for controlling the timing at which data voltages Vdata are output to the data lines DL.

If the control unit 400 does not transmit the image data Data to the data driver 300, data voltages are not output to the data lines DL. Accordingly, the data driver 300 may be controlled by image data.

In the following description, the frame period means a period in which one image is output. That is, one image is output through the light emitting display panel 100 during one frame period (one frame period). During a plurality of frame periods, different images are output through the light emitting display panel 100, so that a video can be expressed. When the same images are output through the light emitting display panel 100 in a plurality of frame periods, a still image may be expressed.

The image refers to an image output through all pixels of the light emitting display panel 100 in one frame period. That is, in one frame period, one light is output from each pixel 110 and the light output from the pixels 110 of the light emitting display panel 100 gather to form one image.

In the following description, when the order of the frame periods is required, the first frame period and the second frame period are used, and when the number of frame periods is required, one frame period and two frame periods, 60 frame periods, etc. Is used.

The present invention uses a variable refresh rate (VRR) mode (hereinafter simply referred to as VRR) mode. The VRR mode means, for example, a mode in which an image is output only in the first frame period among the preset frame periods, and a new image is not output during the remaining frame periods.

More specifically, when the light emitting display device is driven at 60 Hz, generally, 1 second includes 60 frame periods, and the light emitting display device displays 60 images for 1 second through the light emitting display panel 100. Output.

However, in the light emitting display device using the VRR mode, only one image is output through the light emitting display panel 100 in the first frame period for 1 second, and in the remaining 59 frame periods, the light emitting display panel 100 is displayed. New images are not output through. That is, in 59 frame periods, the image output in the first frame period is continuously output, and a new image is not output.

The light emitting display device using the VRR mode may be used, for example, in an electronic watch combined with a smart phone and a watch, or an advertising monitor that continuously outputs the same advertising phrase. That is, the light emitting display device according to the present invention can be applied to various types of electronic devices, for example, electronic watches and advertising monitors.

In particular, the electronic clock expresses the change of time in numbers in 1 second increments. Therefore, the electronic clock can achieve its purpose with only one image output in the first frame period for one second.

However, in the conventional light emitting display device using the VRR mode, since only one image is output per second, defects such as flicker may occur.

To solve this, in a conventional light emitting display device, a reset voltage Vp is supplied to the anode of the light emitting elements in 59 frame periods during which no new image is output during a period of 1 second.

However, in the conventional light emitting display device, reset voltages Vp of the same level are supplied to all pixels provided in the light emitting display panel, and in this case, defects such as color coordinate distortion or luminance distortion are generated.

To solve this problem, in the light emitting display device according to the present invention, the sizes of the reset voltages supplied to the light emitting element in frame periods during which no image is output are set differently according to the color of pixels.

An electronic device to which the light emitting display device according to the present invention described below is applied may be an electronic watch.

In this case, the system for controlling the function of the electronic clock is hereinafter referred to as an external system, and the light emitting display device receives input image data and timing signals from the external system.

However, the present invention described below can be applied to various electronic devices using the VRR mode in addition to the electronic clock, as described above.

In addition, hereinafter, a preset period is set to 1 second, and a light emitting display device that outputs 60 images for 1 second is described as an example of the present invention. That is, in the light emitting display device described below, 1 second may be divided into 60 frame periods.

In addition, hereinafter, the data voltage is supplied to the pixels during the first frame period among the n frame periods included in the preset period (eg, 1 second) to emit the pixels, and the reset voltage is applied to the remaining frame periods. A light emitting display device that supplies them to pixels is described as an example of the present invention. However, in the present invention, the reset voltage may be supplied to the pixels in at least one of the remaining frame periods.

4 is an exemplary view showing a configuration of a gate driver applied to a light emitting display device according to the present invention.

The gate driver 200 applied to the light emitting display device according to the present invention includes stages 210 connected to scan lines GL provided in the light emitting display panel 100.

Each of the stages 210 supplies a scan signal SCAN to a scan line GL connected to itself, and an emission signal EM to an emission line ML.

As described above, the scan signal SCAN is configured to turn on the first transistor T1 (or the third transistor T3) connected to the second scan line GL2 (or the first scan line GL1). It includes a scan-on signal and a scan-off signal that turns off the first transistor T1 (or the third transistor T3).

That is, the gate driver 200 sequentially supplies scan-on signals to the scan lines GL by using the gate control signals GCS transmitted from the control unit 400.

The order in which scan-on signals are output to the scan lines may be variously changed.

The gate driver 200 may be driven by a gate start signal included in the gate control signal GCS.

For example, the first stage ST1 among the stages 210 illustrated in FIG. 4 may start driving by a gate start signal transmitted from the control unit 400 and output a first scan-on signal.

The first scan-on signal may be used as a gate start signal of the second stage ST2 shown in FIG. 4 in the next stage, or may be used as a gate start signal of the m-th stage.

Here, m may be a natural number greater than 2 or an integer less than 1.

For example, the first scan-on signal output from the first stage ST1 is supplied to the third stage, the fourth stage, the fifth stage, and the like, and may be used as a gate start signal of any one of the stages.

In addition, the scan-on signal output from any one stage is supplied to any one of the stages provided at the front end of the stage, and may be used as a gate start signal of any one of the stages.

That is, the scan-on signal output from any one of the stages 210 may be input to at least one of the stages provided at the front end or the rear end of any one of the stages 210 and used as a gate start signal.

Each of the stages 210 may generate a scan-on signal using at least one of the gate clocks included in the gate control signal GCS transmitted from the control unit 400.

For example, when four gate clocks are supplied from the control unit 400, each of the stages 210 may generate a scan-on signal using at least one gate clock.

However, the number of gate clocks supplied to the gate driver 200, the number of gate clocks supplied to the stages 210, the level of the gate clocks, etc., depends on the configuration of the gate driver 200 and the configuration of the stages 210. Accordingly, it can be variously changed.

The method in which each of the stages 210 supplies a scan signal SCAN to pixels has been described above.

The stages 210 may supply the emission signals EM to the pixels using a method similar to the method of supplying the scan signals SCAN to the pixels. Accordingly, a detailed description of how emission signals EM are generated is omitted.

To perform the functions as described above, each of the stages 210 may include a scan signal generator for generating a scan signal SCAN and an emission signal generator for generating an emission signal EM.

5 is an exemplary view for explaining a method of driving the pixel illustrated in FIG. 2, and FIG. 6 is an exemplary view showing a configuration of a reset voltage switching unit applied to the light emitting display device according to the present invention. In particular, FIG. 5A shows a method in which the data voltage Vdata and the reset voltage Vp are output. In FIG. 5(a), the solid line represents a frame period in which the data voltage Vdata is output, and the dotted line represents a frame period in which the reset voltage Vp is output. 5B is an exemplary view showing waveforms of signals applied in a first frame period in which the data voltage Vdata is output, and FIG. 5C is applied in a frame period in which the reset voltage Vdata is output It is an exemplary diagram showing the waveforms of the signals.

In the light emitting display device according to the present invention, as shown in FIG. 6, in the data lines DL, a reset voltage switching unit for supplying reset voltages Vp for resetting the light emitting elements ED to pixels. 600 is connected, and the reset voltages Vp_R, Vp_G, and Vp_B are set differently for each color of pixels.

In this case, the reset voltage switching unit 600 may be provided in the non-display area 130 of the light emitting display panel 100 or may be provided in the data driver 300. In addition, some of the reset voltage switching unit 600 may be provided in the non-display area 130, and some of the reset voltage switching unit 600 may be provided in the data driver 300.

Hereinafter, first, a basic driving method of the light emitting display device according to the present invention will be described with reference to FIGS. 5 and 6, and next, a configuration of the reset voltage switching unit 600 will be described in detail with reference to FIG. 6. .

In the following description, a light emitting display device in which 60 frame periods are present in one second period is described as an example of the present invention.

Particularly, hereinafter, as shown in FIG. 5(a), pixels are generated during the first frame period among n frame periods (60 frame periods) included in a preset period (eg, 1 second). A light emitting display device that supplies the data voltages Vdata to the 110s to emit the pixels 110 and the rest of the frame periods to provide reset voltages Vp_R, Vp_G, Vp_B to the pixels 110 is seen. It is described as an example of the invention.

In this case, in the first frame period, signals as shown in FIG. 5B are supplied to the pixel driving circuit PDC.

First, for example, during the first frame period, in the first period A1 shown in FIG. 5B, the high level first scan signal SCAN1 and the low level second scan signal SCAN2. , The low-level first emission signal EM1 and the high-level second emission signal EM2 are supplied to the pixel driving circuit PDC.

Accordingly, the third transistor T3 and the fifth transistor T5 are turned on, the first transistor T1 is turned off, the second transistor T2 is turned off, and the fourth transistor T4 is turned on. do.

Therefore, the gate of the storage capacitor Cst and the driving transistor Tdr may be initialized by the initialization voltage Vini.

In this case, each of the first period A and the second to tenth periods A2 to A10 described below, for example, is one horizontal where the data voltage Vdata is output to the data lines DL. It may be a period corresponding to the period.

Next, in the second period A2 to the fourth period A4, the low level first scan signal SCAN1, the high level second scan signal SCAN2, and the low level first emission signal EM1. And a low-level second emission signal EM2 is supplied to the pixel driving circuit PDC.

Accordingly, the third transistor T3 and the fifth transistor T5 are turned off, the first transistor T1 is turned on, the second transistor T2 is turned off, and the fourth transistor T4 is turned off. Is off.

In this case, the second period (A2) to the fourth period (A4) is a period in which three horizontal periods are combined, that is, three horizontal periods.

In the present invention, as shown in FIG. 6, three pixels are connected to one data line DL, and data voltages Vdata are sequentially applied to at least three pixels constituting one unit pixel 140. ) Are supplied. The unit pixel 140 includes at least three pixels 110 that output different colors. 6 illustrates a light emitting display panel 100 including a unit pixel 140 composed of a red pixel (R), a green pixel (G), and a blue pixel (B), as an example of the present invention.

In this case, during one horizontal period among three horizontal periods corresponding to the second period A2 to the fourth period A4, the data voltage is applied only to pixels connected to one of the three unit pixels 140. Vdata) are supplied, and data voltages Vdata are supplied only to pixels connected to another unit pixel in another 1 horizontal period, and data voltages Vdata are supplied only to pixels connected to the remaining unit pixels in the other 1 horizontal period. do.

The operation as described above may be performed on all pixels provided in one horizontal line.

Accordingly, during three horizontal periods, data voltages Vdata may be supplied to all pixels provided in one horizontal line. The horizontal line means a virtual line parallel to the scan line GL. In the horizontal line, pixels 110 provided in a line along the scan line GL are provided.

In detail, in the second period A2 to the fourth period A4 illustrated in FIG. 5B, the first transistor T1 provided in the pixels 110 provided in one horizontal line. Through them, the data voltages Vdata are supplied to the pixels 110 provided in one horizontal line.

Next, in the fifth period A5, the high level first scan signal SCAN1, the high level second scan signal SCAN2, the low level first emission signal EM1, and the low level second emission The Sean signal EM2 is supplied to the pixel driving circuit PDC.

Accordingly, the third transistor T3 and the fifth transistor T5 are turned on, the first transistor T1 is turned on, the second transistor T2 is turned off, and the fourth transistor T4 is turned off. do.

In the fifth period A5, the data voltages Vdata supplied through the first transistors T1 in the second period A2 to the fourth period A4 may be charged in the storage capacitors Cst.

For example, the data voltage Vdata supplied to the first node N1 through the first transistor T1 in the second period A2 to the fourth period A4 is driven in the fifth period A5. It is supplied to the second node N2 through the transistor Tdr and the third transistor T3 to be charged in the storage capacitor Cst.

In this case, threshold voltages of the driving transistors Tdr may also be charged in the storage capacitors Cst.

Next, in the sixth period A6 and the seventh period A7, the low level first scan signal SCAN1, the low level second scan signal SCAN2, and the low level first emission signal EM1. And a low-level second emission signal EM2 is supplied to the pixel driving circuit PDC.

Accordingly, the third transistor T3 and the fifth transistor T5 are turned off, the first transistor T1 is turned off, the second transistor T2 is turned off, and the fourth transistor T4 is Turn off.

In this case, the voltages of the storage capacitors Cst are maintained as the data voltages Vdata and threshold voltages charged in the fifth period A5.

Next, in the eighth period A8 and the ninth period A9, the low level first scan signal SCAN1, the low level second scan signal SCAN2, and the high level first emission signal EM1. And a low-level second emission signal EM2 is supplied to the pixel driving circuit PDC.

Accordingly, the third transistor T3 and the fifth transistor T5 are turned off, the first transistor T1 is turned off, the second transistor T2 is turned on, and the fourth transistor T4 is turned off. Is off.

In this case, the voltages of the storage capacitors Cst are maintained as the data voltages Vdata and threshold voltages charged in the fifth period A5.

Finally, in the tenth period A10, the low level first scan signal SCAN1, the low level second scan signal SCAN2, the high level first emission signal EM1, and the high level second The emission signal EM2 is supplied to the pixel driving circuit PDC.

Accordingly, the third transistor T3 and the fifth transistor T5 are turned off, the first transistor T1 is turned off, the second transistor T2 is turned on, and the fourth transistor T4 is turned on. do.

In this case, since the voltage charged in the storage capacitor Cst, that is, the data voltage Vdata and the threshold voltage of the driving transistor Tdr are supplied to the gate of the driving transistor Tdr, the driving transistor Tdr is also turned on. do.

Accordingly, the current I can be supplied to the light emitting device ED through the fourth transistor T4, the driving transistor Tdr, and the second transistor T2, and the light emitting device ED is the current I It can output the light of the luminance corresponding to.

In this case, the voltage (gate voltage) applied to the gate of the driving transistor Tdr is the sum (= Vdata + Vth) of the data voltage Vdata and the threshold voltage Vth of the driving transistor Tdr, and the driving transistor Tdr ) The current I passing through is proportional to the square of the voltage obtained by subtracting the threshold voltage Vth of the driving transistor Tdr from the difference between the gate voltage of the driving transistor Tdr and the source voltage.

That is, in the tenth period A10, the current I supplied to the light emitting element ED through the driving transistor Tdr may be expressed by Equation 1 below.

In [Equation 1], k is a proportionality constant determined by various factors.

That is, in the tenth period A10, in the equation for calculating the current I supplied to the light emitting element ED through the driving transistor Tdr, the threshold voltage Vth may be removed.

Therefore, the current I supplied to the light emitting element ED through the driving transistor Tdr in the tenth period A10 is determined by the data voltage Vdata, and the threshold voltage Vth of the driving transistor Tdr. It is not determined by.

In general, as the light emitting display device is used for a long time, the driving transistor Tdr may deteriorate, and accordingly, the threshold voltage Vth of the driving transistor Tdr may be changed.

In addition, the degree of deterioration of the driving transistor Tdr provided in the pixel 110 formed in the organic light emitting display panel 100 may be different from each other due to various causes.

When the deterioration degrees of the driving transistors Tdr are changed, threshold voltages of the driving transistors Tdr are also different from each other.

When the threshold voltages of the driving transistors Tdr are changed, even if the same data voltages Vdata are supplied to the driving transistors Tdr, the sizes of currents supplied to the light emitting devices ED through the driving transistors Tdr may be different. have. Therefore, the light emitting elements ED provided in the pixels supplied with the same data voltage Vdata can output light having different brightness.

In order to solve the above-described problem, the present invention is configured such that the current I flowing through the driving transistor Tdr is not affected by the threshold voltage Vth of the driving transistor Tdr.

That is, in the present invention, the size of the current I passing through the driving transistor Tdr is driven by the structure of the pixel as shown in FIG. 2 and the driving method described with reference to FIG. 5B. It is not affected by the threshold voltage Vth of the transistor Tdr.

Therefore, according to the present invention, even if the driving transistors Tdr are deteriorated, a normal current corresponding to the data voltage Vdata may be supplied to the light emitting device ED in each pixel, and accordingly, the light emitting device ED may A light having a brightness proportional to the data voltage Vdata can be output.

In the present invention, during the period of 1 second, only in the first frame period, data voltages Vdata are charged to the storage capacitor Cst by signals as shown in FIG. 5B, and the data voltage Vdata The light emitting elements ED output light by the fields, and accordingly, one image may be output through the light emitting display panel 110.

In the second to 60th frame periods, other data voltages Vdata are not charged in the storage capacitor Cst. However, the data voltages Vdata charged in the storage capacitors Cst may be continuously maintained in the second to 60th frame periods, and the first emission signal EM1 and the second emission signal ( Since the second transistor T2 and the fourth transistor T4 are continuously turned on by EM2, the light emitting elements ED continuously correspond to the data voltages Vdata during the second to 60th frame periods. Can output the light.

Accordingly, during the first to 60th frame periods, one image corresponding to the data voltages Vdata may be continuously output.

For example, when the light emitting display device according to the present invention is applied to an electronic watch, the light emitting display device may continuously output the number '1' displayed in the first frame period for 1 second, and thus, through the electronic watch. 1 second may be displayed.

When 1 second has elapsed and another 1 second starts, the number '2' output in the first frame period constituting another 1 second may last for another 1 second, and thus, 2 seconds may be displayed through the clock. .

In this case, as described above, if the image output through the light emitting display device changes every 1 second, a defect such as flicker may occur.

In order to prevent this, in the present invention, reset voltages Vp are supplied to the light emitting elements ED in at least one frame period from the second frame period to the 60th frame period, thereby preventing defects such as flicker. Can be.

To this end, in at least one frame period of the second to 60th frame periods excluding the first frame period, signals are supplied to the pixel driving circuit (PDC) as shown in FIG. , The light emitting elements ED may be reset.

First, for example, during the second frame period, in the first period B1 illustrated in FIG. 5C, the low level first scan signal SCAN1 and the low level second scan signal SCAN2. , The high level first emission signal EM1 and the high level second emission signal EM2 are supplied to the pixel driving circuit PDC.

Accordingly, the third transistor T3 and the fifth transistor T5 are turned off, the first transistor T1 is turned off, the second transistor T2 is turned on, and the fourth transistor T4 is turned on. do.

The waveforms of the signals applied in the first period B1 in the second frame period are the same as the waveforms of the signals applied in the tenth period A10 in the first frame period.

Accordingly, in the first period B1 of the second frame period, the image output in the tenth period A10 of the first frame period is continuously output through the light emitting display panel 100.

Next, during the second frame period, in the second period (B2) to the fifth period (B5), the low level first scan signal SCAN1, the high level second scan signal SCAN2, and the high level first The emission signal EM1 and the low-level second emission signal EM2 are supplied to the pixel driving circuit PDC.

Accordingly, the third transistor T3 and the fifth transistor T5 are turned off, the first transistor T1 is turned on, the second transistor T2 is turned on, and the fourth transistor T4 is turned off. do.

Therefore, in the second period B2 to the fifth period B5, the reset voltage Vp is applied to the light emitting element ED through the data line DL, the first transistor T1, and the second transistor T2. Is supplied.

Accordingly, the light emitting element ED may be reset.

In this case, in the second period (B2) to the fifth period (B5) of the second frame period, by a method similar to the method described in the second period (A2) to the fifth period (A5) of the first frame period , Reset voltages Vp may be supplied to all pixels provided in one horizontal line.

In particular, in the present invention, the level of the reset voltages Vp is set differently for each color of the pixels 110.

A specific structure of the reset voltage switching unit 600 for supplying reset voltages Vp of different levels to all pixels provided in one horizontal line in the second period B2 to the fifth period B5, and The function is described in detail below with reference to FIG. 6.

Next, in the second frame period, in the sixth period (B6) to the ninth period (B9), the low level first scan signal SCAN1, the low level second scan signal SCAN2, and the high level first The emission signal EM1 and the low-level second emission signal EM2 are supplied to the pixel driving circuit PDC.

Accordingly, the third transistor T3 and the fifth transistor T5 are turned off, the first transistor T1 is turned off, the second transistor T2 is turned on, and the fourth transistor T4 is turned off. Is off.

Therefore, in the sixth period (B6) to the ninth period (B9), the process of resetting the light emitting element ED may continue.

Finally, during the second frame period, after the tenth period B10, the low level first scan signal SCAN1, the low level second scan signal SCAN2, and the high level first emission signal EM1 ) And a high-level second emission signal EM2 are supplied to the pixel driving circuit PDC.

Accordingly, the third transistor T3 and the fifth transistor T5 are turned off, the first transistor T1 is turned off, the second transistor T2 is turned on, and the fourth transistor T4 is turned on. do.

The waveforms of signals applied to the tenth period B10 in the second frame period are the same as those of the signals applied to the tenth period A10 in the first frame period.

Accordingly, in the tenth period B10 of the second frame period and subsequent periods, the image output in the tenth period A10 of the first frame period is continuously output through the light emitting display panel 100.

In detail, the storage capacitor Cst may be stored in the storage capacitors Cst through the second period A2 to the fifth period A5 of the first frame period while the second frame period to the 60th frame period have elapsed. The data voltages Vdata stored in) are continuously charged.

The data voltages Vdata charged in the storage capacitors Cst do not change while the light emitting elements ED are reset in the second period B2 to the ninth period B9 of the second frame period.

Therefore, in each of the second frame period to the 60th frame period, after the tenth period B10, the light emitting display panel in the first frame period by the data voltages Vdata charged in the storage capacitors Cst. Images identical to the image output through the 100 may be continuously output through the light emitting display panel 100.

Hereinafter, the reset voltages Vp that are set differently according to the color of the pixels in the frame periods in which no image is output, for example, in the second frame period to the 60th frame period, the light emitting elements ED. A configuration and an operation method of the reset voltage switching unit 600 for supplying to are described with reference to FIG. In this case, contents identical or similar to those described above are omitted or simply described.

In the light emitting display device according to the present invention, the reset voltage switching unit 600 for supplying reset voltages Vp for resetting the light emitting elements ED to pixels is connected to the data lines DL, and the reset voltage (Vp) are set differently for each color of pixels.

In the first frame period of the n frame periods (for example, 60 frame periods) included in the preset period (for example, 1 second), the control unit 400 may include (a) of FIG. 5 and Using the methods described with reference to (b), the data voltage is supplied to the pixels 110 to emit the pixels, and in at least one frame period among the remaining frame periods, FIGS. 5A and 5C ), the reset voltages Vp are supplied to the pixels 110 using the methods described with reference to FIG.

In order to perform the above-described function, the reset voltage switching unit 600 switches the reset voltages Vp_R, Vp_G, Vp_B to supply them to the data lines DL, as shown in FIG. 6. It includes a first switching unit 610 and a second switching unit 620 sequentially connecting one data line (DL) to at least three pixels (110).

In this case, the light emitting display panel 100 is divided into a display area 120 and a non-display area 130 surrounding the display area 120, and the first switching unit 610 and the second switching unit 620 At least one of them may be provided in the non-display area 130.

Also, at least one of the first switching unit 610 and the second switching unit 620 may be provided in the data driver 300.

For example, the second switching unit 620 may be provided in the non-display area 130, and the first switching unit 610 may be provided in the data driver 300. Also, both the second switching unit 620 and the first switching unit 610 may be provided in the non-display area 130. In addition, both the second switching unit 620 and the first switching unit 610 may be provided in the data driver 300.

In the present invention, one unit pixel 140 may be composed of at least three pixels having different colors. However, in the following description, for convenience of description, as illustrated in FIG. 6, a light emitting display device in which one unit pixel is composed of a red pixel (R), a green pixel (G), and a blue pixel (B) is an example of the present invention. It is described as.

In this case, the reset voltage switching unit 600 branches from the first switching unit 610 and one data line DL including reset switches 611 to 613 connected to each of the data lines DL. And a second switching unit 620 including three branch data lines DDL connected to the same color pixels 110 provided in the three unit pixels 140.

For example, in FIG. 6, a first reset switch 611 for supplying the first reset voltage Vp_R to the first data line DL1 is connected to the first data line DL1 and the second data The second reset switch 612 for supplying the second reset voltage Vp_G to the second data line DL2 is connected to the line DL2, and the third reset voltage Vp_B to the third data line DL3. ), the third reset switch 613 for supplying to the third data line DL3 is connected.

The first reset voltage Vp_R may be the reset voltage Vp supplied to the red pixel R among the pixels 110, and the second reset voltage Vp_G may be the green pixel G of the pixels 110. ) May be a reset voltage Vp, and the third reset voltage Vp_B may be a reset voltage Vp supplied to the blue pixel B of the pixels 110.

However, the color of the pixels 110 may be variously changed.

Three branch data lines DDL are connected to one data line DL. Each of the three branch data lines DDL is connected to one of the three unit pixels 140, and each of the three branch data lines DDL is connected to a pixel 110 of the same color. .

For example, in FIG. 6, one of the three branch data lines DDL branched from the first data line DL1 is connected to a first unit pixel provided on the left side of the display area 120. , The other is connected to the second unit pixel, and the other is connected to the third unit pixel.

In this case, in the second switching unit 620, three branch data lines DDL branched from one data line DL are pixels 110 of the same color provided in three unit pixels 140. And is connected.

For example, in FIG. 6, one of the three branch data lines DDL branched from the first data line DL1 is connected to the red pixel R provided in the first unit pixel, and the other Is connected to the red pixel R provided in the second unit pixel, and the other is connected to the red pixel R provided in the third unit pixel.

In addition, one of the three branch data lines DDL branched from the second data line DL2 is connected to the green pixel G provided in the first unit pixel, and the other to the second unit pixel. It is connected to the green pixel G provided, and the other is connected to the green pixel G provided in the third unit pixel.

In addition, one of the three branch data lines DDL branched from the third data line DL3 is connected to the blue pixel B provided in the first unit pixel, and the other is connected to the second unit pixel. It is connected to the provided blue pixel B, and the other is connected to the blue pixel B provided in the third unit pixel.

In this case, a mux switch is connected to each of the branch data lines DDL.

For example, in FIG. 6, one mux switch is connected to each of the nine branch data lines DDL. Accordingly, nine MUX switches 621 to 629 are connected to the nine branch data lines DDL connected to the first to third data lines DL1 to DL3 shown in FIG. 6.

The MUX switches 621 to 629 may be divided into at least three MUX groups.

For example, three MUX switches 621, 622, and 623 connected to the first unit pixel form a first MUX group, and three MUX switches 624, 625, and 626 connected to the second unit pixel are The second MUX group is formed, and the three MUX switches 627, 628, and 629 connected to the third unit pixel form the third MUX group.

In this case, at least three mux switches constituting one mux group are connected to different data lines, and are connected to pixels of different colors provided in one unit pixel.

For example, the first mux switch 621 among the three mux switches 621, 622, and 623 constituting the first mux group is connected to the first data line DL1, and the second mux switch 622 ) Is connected to the second data line DL2, and the third mux switch 623 is connected to the third data line DL3.

In addition, the first MUX switch 621 is connected to the red pixel R provided in the first unit pixel, and the second MUX switch 622 is connected to the green pixel G provided in the first unit pixel. The third MUX switch 623 is connected to the blue pixel B provided in the first unit pixel.

Of the three mux switches 624, 625, and 626 constituting the second mux group, the fourth mux switch 624 is connected to the first data line DL1, and the fifth mux switch 625 is the second. It is connected to the data line DL2, and the sixth mux switch 626 is connected to the third data line DL3.

In addition, the fourth MUX switch 624 is connected to the red pixel R provided in the second unit pixel, and the fifth MUX switch 625 is connected to the green pixel G provided in the second unit pixel. The sixth MUX switch 626 is connected to the blue pixel B provided in the second unit pixel.

The seventh mux switch 627 among the three mux switches 627, 628, and 629 constituting the third mux group is connected to the first data line DL1, and the eighth mux switch 628 is the second. It is connected to the data line DL2, and the ninth mux switch 629 is connected to the third data line DL3.

Further, the seventh MUX switch 727 is connected to the red pixel R provided in the third unit pixel, and the eighth MUX switch 628 is connected to the green pixel G provided in the third unit pixel. The ninth MUX switch 629 is connected to the blue pixel B provided in the third unit pixel.

The reset switches 611, 612, 613 and mux switches 621 to 629 may be composed of transistors.

The first to third mux switches 621, 622, and 623 constituting the first mux group are turned on or off according to the first mux control signal MUX_1, and the fourth to fourth constituting the second mux group. The six mux switches 624, 625, and 626 are turned on or off according to the second mux control signal MUX_2, and the seventh to ninth mux switches 627, 628, and 629 constituting the third mux group. Is turned on or off according to the third MUX control signal MUX_3.

For example, among the periods described with reference to FIG. 5, in the second period (A2) to the fourth period (A4) of the first frame, the first to third MUX control signals (MUX_1 to MUX_3) are sequentially , Turn on the first to third mux groups.

For example, in the second period A2, the first to third mux switches 621, 622, and 623 constituting the first mux group may be turned on by the first mux control signal MUX_1. Accordingly, the data voltages Vdata transmitted from the first to third data lines DL1 to DL3 are charged to the three pixels R, G, and B connected to the first unit pixel.

In the third period A3, the fourth to sixth mux switches 624, 625, and 626 constituting the second mux group may be turned on by the second mux control signal MUX_2, and accordingly, the second mux control signal MUX_2 may be turned on. The data voltages Vdata transmitted from the first to third data lines DL1 to DL3 are charged in the three pixels R, G, and B connected to the unit pixel.

In the fourth period A4, the seventh to ninth mux switches 627, 628, and 629 constituting the third mux group may be turned on by the third mux control signal MUX_3, and accordingly, the third mux control signal MUX_3 may be turned on. The data voltages Vdata transmitted from the first to third data lines DL1 to DL3 are charged in the three pixels R, G, and B connected to the unit pixel.

In this case, in the second period A2 to the fourth period A4, the first to third reset switches 611, 612, and 613, the first to third reset control signals Vp_CTRL_R, Vp_CTRL_G, Vp_CTRL_B All of them are turned off. Accordingly, as described above, the data voltages Vdata transmitted from the data lines DL may be supplied to the pixels.

In addition, among the periods described with reference to FIG. 5, in the second period (B2) to the fourth period (B4) of the second frame period, the first to third MUX control signals (MUX_1 to MUX_3) are sequentially, The first to third mux groups are turned on by the method as described above.

In the second period (B2) to the fourth period (B4) of the second frame period, the first to third reset switches 611, 612, and 613, the first to third reset control signals (Vp_CTRL_R, Vp_CTRL_G) , Vp_CTRL_B), and accordingly, reset voltages Vp_R, Vp_G, and Vp_B are supplied to the data lines DL. In this case, the data voltages Vdata are not supplied to the data lines DL.

For example, in the second period B2 of the second frame period, the first reset voltage Vp_R is supplied to the first data line DL1 by the first reset control signal Vp_CTRL_R, and the second reset control signal The second reset voltage Vp_G is supplied to the second data line DL1 by (Vp_CTRL_G), and the third reset voltage Vp_B is transferred to the third data line DL1 by the third reset control signal Vp_CTRL_B. Is supplied.

In the second period B2 of the second frame period, the first to third mux switches 621, 622, and 623 constituting the first mux group are turned on.

Accordingly, in the second period B2, the red pixel R, the green pixel G, and the blue pixel B provided in the first unit pixel are the first reset voltage Vp_R and the second reset voltage Vp_G. ) And the third reset voltage Vp_B are simultaneously supplied.

In the third period B3 of the second frame period, the first reset voltage Vp_R is supplied to the first data line DL1 by the first reset control signal Vp_CTRL_R, and is supplied to the second reset control signal Vp_CTRL_G. The second reset voltage Vp_G is supplied to the second data line DL1, and the third reset voltage Vp_B is supplied to the third data line DL1 by the third reset control signal Vp_CTRL_B.

In the third period B3 of the second frame period, the fourth to sixth mux switches 624, 625, and 626 constituting the second mux group are turned on.

Accordingly, in the third period B3, the red pixel R, the green pixel G, and the blue pixel B provided in the second unit pixel are the first reset voltage Vp_R and the second reset voltage Vp_G. ) And the third reset voltage Vp_B are simultaneously supplied.

In the fourth period B4 of the second frame period, the first reset voltage Vp_R is supplied to the first data line DL1 by the first reset control signal Vp_CTRL_R, and is supplied to the second reset control signal Vp_CTRL_G. The second reset voltage Vp_G is supplied to the second data line DL1, and the third reset voltage Vp_B is supplied to the third data line DL1 by the third reset control signal Vp_CTRL_B.

In the fourth period B4, the seventh to ninth mux switches 627, 628, and 629 constituting the third mux group are turned on.

Accordingly, in the fourth period B4, the red pixel R, the green pixel G, and the blue pixel B provided in the third unit pixel are the first reset voltage Vp_R and the second reset voltage Vp_G. ) And the third reset voltage Vp_B are simultaneously supplied.

That is, the reset voltage switching unit 600 as illustrated in FIG. 6 includes three data lines DL1 to DL3 in the second to fourth periods A2, A3, and A4 of the first frame period. The three data voltages Vdata supplied are sequentially supplied to each of the three unit pixels.

In addition, the reset voltage switching unit 600 is supplied from three data lines DL1 to DL3 in the second to fourth periods B2, B3, and B4 of the remaining frame periods except the first frame period. The three reset voltages Vp_R, Vp_G, and Vp_B are sequentially supplied to each of the three unit pixels.

Accordingly, in each of the remaining frame periods except the first frame period, the pixels 110 may be reset by three reset voltages Vp_R, Vp_G, and Vp_B.

In this case, the structure and driving method of the three data lines DL1 to DL3, the three reset switches 611, 612, and 613 and the nine mux switches 621 to 629 shown in FIG. The same may be applied to other data lines provided in the display panel 100.

7 is a graph showing characteristics of reset voltages applied to a light emitting display device according to the present invention.

As described with reference to FIGS. 5 and 6, the reset voltage switching unit 600 includes three data lines DL1 in the second to fourth periods A2, A3, and A4 of the first frame period. to DL3), the three data voltages Vdata are sequentially supplied to each of the three unit pixels.

In addition, the reset voltage switching unit 600 is supplied from three data lines DL1 to DL3 in the second to fourth periods B2, B3, and B4 of the remaining frame periods except the first frame period. The three reset voltages Vp_R, Vp_G, and Vp_B are sequentially supplied to each of the three unit pixels.

In this case, the levels of the three reset voltages Vp_R, Vp_G, Vp_B may be set differently.

That is, the inventors of the present invention, as shown in FIG. 7, confirmed that the level of the reset voltage that does not change the luminance of the light emitting element ED varies for each color.

For example, the graph illustrated in FIG. 7 shows a change in luminance of the light emitting element ED when the reset voltage Vp is changed for each color.

In other words, even if the level of the reset voltage Vp supplied to the blue pixels B is changed, the luminances of the light emitting elements provided in the blue pixels B do not change significantly.

However, between the luminance when the reset voltage Vp of about 0.6V is supplied to the green pixel G and the luminance when the reset voltage Vp of about 0.8V is supplied to the green pixel G, A difference of approximately 20% occurs.

Further, between the luminance when the reset voltage Vp of about 0.6V is supplied to the red pixel R and the luminance when the reset voltage Vp of about 0.7V is supplied to the red pixel R, A difference of approximately 20% occurs.

In other words, the inventors of the present invention have the same reset voltage Vp due to differences in capacitances of the light emitting elements of the red pixel R, the light emitting elements of the green pixel G, and the light emitting elements of the blue pixel B. After being supplied to the red pixel (R), the green pixel (G), and the blue pixel (B), a difference may occur in the timing at which the light emitting elements emit light again. Accordingly, the red pixel (R), the green pixel ( It was confirmed that a luminance difference may occur in the G) and the blue pixel (B).

Therefore, in the light emitting display device according to the present invention, as described above, the reset voltages Vp are set differently for each color of the pixel.

8 is another exemplary view showing a configuration of a reset voltage switching unit applied to a light emitting display device according to the present invention. In the following description, contents identical or similar to those described with reference to FIGS. 1 to 7 are omitted or briefly described.

In the light emitting display device according to the present invention, the reset voltage switching unit 600 for supplying reset voltages Vp for resetting the light emitting elements ED to pixels is connected to the data lines DL, and the reset voltage (Vp) are set differently for each color of pixels.

In the first frame period of the n frame periods (for example, 60 frame periods) included in the preset period (for example, 1 second), the control unit 400 may include (a) of FIG. 5 and Using the methods described with reference to (b), the data voltage is supplied to the pixels 110 to emit the pixels, and in at least one frame period among the remaining frame periods, FIGS. 5A and 5C ), the reset voltages Vp are supplied to the pixels 110 using the methods described with reference to FIG.

In order to perform the above-described function, the reset voltage switching unit 600 switches the reset voltages Vp_R, Vp_G, Vp_B to supply them to the data lines DL, as shown in FIG. 8. It includes a first switching unit 610 and a second switching unit 620 for sequentially connecting one data line (DL) to at least three pixels (110).

At least one of the first switching unit 610 and the second switching unit 620 may be provided in the non-display area 130, and at least one of the first switching unit 610 and the second switching unit 620 One may be provided in the data driver 300.

In the present invention, one unit pixel 140 may be composed of at least three pixels having different colors.

In this case, the reset voltage switching unit 600 is connected to each of the data lines DL, and includes reset switches 611a, 612a, and 613a connected to one reset control signal line RCL. At least three branch data lines DDL branched from the first switching unit 610 and one data line DL to be connected to the three pixels R, G, and B provided in one unit pixel 140 It includes a second switching unit 620, including.

For example, as illustrated in FIG. 8, each of the three reset switches 611a, 612a, and 613a is connected to one data line DL, and the three reset switches 611a, 612a, and 613a One reset control signal line RCL is connected to.

Further, at least three branch data lines DDL branched from one data line DL are connected to three pixels R, G, and B provided in one unit pixel 140.

For example, in FIG. 8, three branch data lines DDL branched from the first data line DL1 are connected to a first unit pixel provided on the left side of the display area 120, and the second data line ( The three branch data lines DDL branched from DL2) are connected to the second unit pixel, and the three branch data lines DDL branched from the third data line DL1 are connected to the third unit pixel. .

In addition, a mux switch is connected to each of the three branch data lines DDL branched from one data line DL.

Accordingly, in the second switching unit 620 illustrated in FIG. 8, the first to ninth mux switches are included in the nine branch data lines DDL connected to the first to third data lines DL1 to DL3. (621a to 629a) are connected.

The MUX switches 621a to 629a may be divided into three MUX groups.

For example, three mux switches 621a, 622a, and 623a connected to the first unit pixel form a first mux group, and three mux switches 624a, 625a, 626a connected to the second unit pixel are formed. The second MUX group is formed, and the three MUX switches 627a, 628a, and 629a connected to the third unit pixel form the third MUX group.

In this case, three MUX switches constituting one MUX group are connected to one data line, and are connected to pixels of different colors provided in one unit pixel.

The reset switches 611a, 612a, 613a and mux switches 621a to 629a may be composed of transistors.

The mux switches connected to pixels of the same color among the three unit pixels may be turned on or off by one mux control signal.

For example, the first mux switch 621a constituting the first mux group, the fourth mux switch 624a constituting the second mux group, and the seventh mux switch 627a constituting the third mux group are red. Turned on or off by the MUX control signal (MUX_R).

The second mux switch 622a constituting the first mux group, the fifth mux switch 625a constituting the second mux group, and the eighth mux switch 628a constituting the third mux group have a green mux control signal ( MUX_G) to turn on or off.

The third mux switch 623a constituting the first mux group, the sixth mux switch 626a constituting the second mux group, and the ninth mux switch 629a constituting the third mux group include a blue mux control signal ( It is turned on or off by MUX_R).

For example, among the periods described with reference to FIG. 5, in the second period (A2) to the fourth period (A4) of the first frame, the red, green and blue mux control signals (MUX_R, MUX_G, MUX_B) are Subsequently, the MUX switches 621a to 629a are turned on.

For example, the first, fourth and seventh mux switches 621a, 624a, and 627a are turned on by the red mux control signal MUX_R in the second period A2, and green in the third period A3. The second, fifth and eighth MUX switches 622a, 625a, and 628a are turned on by the MUX control signal MUX_G, and the third and third by the blue MUX control signal MUX_B in the fourth period A4. The sixth and ninth mux switches 623a, 626a, and 629a are turned on.

Accordingly, the data voltages Vdata are supplied to the red pixels R in the second period A2, and the data voltages Vdata are supplied to the green pixels G in the third period A3. The data voltages Vdata are supplied to the blue pixels B in the fourth period A4, and the data voltages Vdata are charged to the storage capacitors Cst in the fifth period A5.

In this case, in the second period A2 to the fifth period A5, the first to third reset switches 611a, 612a, and 613a are all turned off by the reset control signal Vp_CTRL. Accordingly, as described above, the data voltages Vdata transmitted from the data lines DL may be supplied to the pixels.

In addition, among the periods described with reference to FIG. 5, red, green, and blue mux control signals MUX_R, MUX_G, and MUX_B are also described in the second period (B2) to the fourth period (B4) of the second frame period. By one method, sequentially, the MUX switches 621a to 629a are turned on.

In the second period (B2) to the fourth period (B4) of the second frame period, the first to third reset switches 611a, 612a, and 613a are simultaneously turned on by the reset control signal Vp_CTRL. Accordingly, the first to third reset voltages Vp_R, Vp_G, Vp_B are sequentially supplied. In this case, the data voltages Vdata are not supplied to the data lines DL.

For example, in the second period B2 of the second frame period, the first reset voltage Vp_R is supplied to the first to third data lines DL1 to DL3 by the reset control signal Vp_CTRL. In the third period B3, the second reset voltage Vp_G is supplied to the first to third data lines DL1 to DL3 by the reset control signal Vp_CTRL, and in the fourth period B4, the reset control signal ( The third reset voltage Vp_B is supplied to the first to third data lines DL1 to DL3 by Vp_CTRL).

That is, the reset voltage switching unit 600 as illustrated in FIG. 8 is configured from three data lines DL1 to DL3 in the second to fourth periods A2, A3, and A4 of the first frame period. The three data voltages Vdata supplied are sequentially supplied to each of the three unit pixels.

In addition, the reset voltage switching unit 600 is supplied from three data lines DL1 to DL3 in the second to fourth periods B2, B3, and B4 of the remaining frame periods except the first frame period. The three reset voltages Vp_R, Vp_G, and Vp_B are sequentially supplied to each of the three unit pixels.

Accordingly, in each of the remaining frame periods except the first frame period, the pixels 110 may be reset by three reset voltages Vp_R, Vp_G, and Vp_B.

In this case, the structure and driving method of the three data lines DL1 to DL3, the three reset switches 611, 612, and 613 and the nine mux switches 621a to 629a shown in FIG. 8 emit light. The same may be applied to other data lines provided in the display panel 100.

9 is another exemplary view showing a configuration of a reset voltage switching unit applied to a light emitting display device according to the present invention. In the following description, contents identical or similar to those described with reference to FIGS. 1 to 8 are omitted or briefly described.

In the light emitting display device according to the present invention, the reset voltage switching unit 600 for supplying reset voltages Vp for resetting the light emitting elements ED to pixels is connected to the data lines DL, and the reset voltage (Vp) are set differently for each color of pixels.

In the first frame period of the n frame periods (for example, 60 frame periods) included in the preset period (for example, 1 second), the control unit 400 may include (a) of FIG. 5 and Using the methods described with reference to (b), the data voltage is supplied to the pixels 110 to emit the pixels, and in at least one frame period among the remaining frame periods, FIGS. 5A and 5C ), the reset voltages Vp are supplied to the pixels 110 using the methods described with reference to FIG.

In order to perform the above-described function, the reset voltage switching unit 600 switches the reset voltages Vp_R, Vp_G, Vp_B to supply them to the data lines DL, as shown in FIG. 9. It includes a first switching unit 610 and a second switching unit 620 for sequentially connecting one data line (DL) to at least three pixels (110).

At least one of the first switching unit 610 and the second switching unit 620 may be provided in the non-display area 130, and at least one of the first switching unit 610 and the second switching unit 620 One may be provided in the data driver 300.

In the present invention, one unit pixel 140 may be composed of at least three pixels having different colors.

In this case, the reset voltage switching unit 600 is branched from the first switching unit 610 and one data line including reset switches connected to each of the data lines at least three times, and provided in one unit pixel. It includes a second switching unit 620 including three branch data lines (DDL) connected to the three pixels (110).

In addition, a mux switch is connected to each of the branch data lines branched from one data line DL.

In this case, the configuration of the second switching unit 620 illustrated in FIG. 9 is the same as the configuration of the second switching unit 620 illustrated in FIG. 8. Therefore, detailed description thereof is omitted.

Therefore, in the second switching unit 620 illustrated in FIG. 9, the first to ninth mux switches are included in the nine branch data lines DDL connected to the first to third data lines DL1 to DL3. (621a to 629a) are connected.

As described above, the first switching unit 610 includes reset switches connected to at least three of each of the data lines.

For example, first to third reset switches 611b, 612b, and 613b are connected to the first data line DL1, and fourth to sixth reset switches 614b to the second data line DL2. 615b and 616b are connected, and seventh to ninth reset switches 617b, 618b, and 619b may be connected to the third data line DL3.

The reset switches 611b to 619b and mux switches 621a to 629a may be composed of transistors.

The first, fourth and seventh reset switches 611b, 614b, and 617b may be turned on by the red reset control signal Vp_CTRL_R, and the second, fifth and eighth reset switches 612b, 615b, 618b ) May be turned on by the green reset control signal Vp_CTRL_G, and the third, sixth, and ninth reset switches 613b, 616b, and 619b may be turned on by the blue reset control signal Vp_CTRL_B.

In this case, the driving method of the second switching unit 620 illustrated in FIG. 9 is the same as the driving method of the second switching unit 620 illustrated in FIG. 8. Therefore, detailed description thereof is omitted.

That is, as described above, data voltages Vdata are supplied to the red pixels R in the second period A2 during the first frame period, and data to the green pixels G in the third period A3. Voltages Vdata are supplied, data voltages Vdata are supplied to blue pixels B in the fourth period A4, and data voltages Vdata are storage capacitors Cst in the fifth period A5. Is charged in.

In this case, in the second period A2 to the fifth period A5, the first to ninth reset switches 611b to 619b include a red reset control signal Vp_CTRL_R, a green reset control signal Vp_CTRL_G, and a blue reset. All are turned off by the control signal Vp_CTRL_B. Accordingly, as described above, the data voltages Vdata transmitted from the data lines DL may be supplied to the pixels.

In addition, among the periods described with reference to FIG. 5, red, green, and blue mux control signals MUX_R, MUX_G, and MUX_B are sequentially also in the second period (B2) to the fourth period (B4) of the second frame period. In turn, the MUX switches 621a to 629a are turned on.

In the second period (B2) to the fourth period (B4) of the second frame period, the first to ninth reset switches 611b to 619b are sequentially controlled by the reset control signals (Vp_CTRL_R, Vp_CTRL_G, Vp_CTRL_B) Turned on, accordingly, the reset control signals Vp_R, Vp_G, Vp_B are sequentially supplied to the data lines DL, and the data voltages Vdata are not supplied to the data lines DL.

For example, in the second period B2, the first reset voltage Vp_R is supplied to the first to third data lines DL1 to DL3 by the red reset control signal Vp_CTRL_R, and the third period B3. ), the second reset voltage Vp_G is supplied to the first to third data lines DL1 to DL3 by the reset control signal Vp_CTRL, and in the fourth period B4 by the reset control signal Vp_CTRL. The third reset voltage Vp_B is supplied to the first to third data lines DL1 to DL3.

Accordingly, the red reset voltage Vp_R is supplied to the red pixels in the second period B2, the second reset voltage Vp_G is supplied to the green pixels in the third period B3, and the fourth period ( The third reset voltage Vp_B is supplied to B4) as blue pixels.

That is, the reset voltage switching unit 600 as illustrated in FIG. 9 is configured from three data lines DL1 to DL3 in the second to fourth periods A2, A3, and A4 of the first frame period. The three data voltages Vdata supplied are sequentially supplied to each of the three unit pixels.

In addition, the reset voltage switching unit 600 is supplied from three data lines DL1 to DL3 in the second to fourth periods B2, B3, and B4 of the remaining frame periods except the first frame period. The three reset voltages Vp_R, Vp_G, and Vp_B are sequentially supplied to each of the three unit pixels.

Accordingly, in each of the remaining frame periods except the first frame period, the pixels 110 may be reset by three reset voltages Vp_R, Vp_G, and Vp_B.

In this case, the structure and driving method of the three data lines DL1 to DL3, the nine reset switches 611b to 619b, and the nine mux switches 621a to 629a shown in FIG. 9 include a light emitting display panel. The same may be applied to other data lines provided in (100).

According to the present invention as described above, reset voltages for resetting the light emitting device may be set differently for each color of pixels, and accordingly, defects such as color coordinate distortion or luminance distortion can be prevented.

The light emitting display device according to the exemplary embodiment of the present specification includes a light emitting display panel provided with pixels including light emitting elements and pixel driving circuits, a gate driver supplying scan signals to scan lines provided in the light emitting display panel, and a light emitting display panel It includes a data driver for supplying data voltages to the data lines provided in, a gate driver and a control unit for controlling the gate driver, and the data lines include reset voltage switching for supplying reset voltages for resetting light emitting elements to pixels. An additional connection is made, and the reset voltages are set differently for each color of pixels.

According to an exemplary embodiment of the present specification, the controller supplies data voltages to pixels in a first frame period among n frame periods included in a preset period to emit pixels, and at least one frame of the remaining frame periods In the period, reset voltages are supplied to the pixels.

According to the exemplary embodiment of the present specification, the reset voltage switching unit includes a first switching unit that switches reset voltages and supplies them to data lines, and a second switching unit that sequentially connects one data line to at least three pixels. .

According to the exemplary embodiment of the present specification, the light emitting display panel is divided into a display area and a non-display area surrounding the display area, and at least one of the first switching unit and the second switching unit is provided in the non-display area.

According to an embodiment of the present disclosure, at least one of the first switching unit and the second switching unit is provided in the data driver

According to an exemplary embodiment of the present specification, at least three pixels displaying different colors constitute one unit pixel, and the reset voltage switching unit includes a first switching unit including reset switches connected to each of the data lines, one And a second switching unit including at least three branch data lines that are branched from the data line and connected to pixels of the same color provided in at least three unit pixels, and at least three branch data branched from one data line. The lines are connected to pixels of the same color provided in at least three unit pixels, and a mux switch is connected to each of the branch data lines.

According to the exemplary embodiment of the present specification, the MUX switches are divided into at least three MUX groups, and at least three MUX switches constituting one MUX group are connected to different data lines and provided in one unit pixel. It is connected to pixels of different colors.

According to the exemplary embodiment of the present specification, at least three pixels displaying different colors constitute one unit pixel, and the reset voltage switching unit is connected to each of the data lines, and is connected to one reset control signal line. A first switching unit including reset switches; And a second switching unit that includes at least three branch data lines branched from one data line and connected to at least three pixels provided in one unit pixel, and at least three branch data branched from one data line. A mux switch is connected to each of the lines.

According to the exemplary embodiment of the present specification, the MUX switches connected to each of at least three branch data lines branched from one data line are sequentially turned on.

According to an exemplary embodiment of the present specification, at least three pixels displaying different colors constitute one unit pixel, and the reset voltage switching unit includes a first switch including reset switches connected to each of the data lines at least three times. Switching unit; And a second switching unit that includes at least three branch data lines branched from one data line and connected to at least three pixels provided in one unit pixel, and at least three branch data branched from one data line. A mux switch is connected to each of the lines.

According to an embodiment of the present disclosure, a first reset switch, a second reset switch, and a third reset switch are connected to one data line, and the first reset switches connected to different data lines are one first reset control signal The second reset switches connected to the line and connected to different data lines are connected to one second reset control signal line, and the third reset switches connected to different data lines are connected to one third reset control signal line. Connected.

Those skilled in the art to which the present invention pertains will appreciate that the present invention may be implemented in other specific forms without changing its technical spirit or essential characteristics. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be interpreted to be included in the scope of the present invention. .

100: light emitting display panel 200: gate driver
300: data driver 400: control unit
600: reset voltage switching unit

Claims (11)

A light emitting display panel including pixels including light emitting elements and pixel driving circuits;
A gate driver supplying scan signals to scan lines provided on the light emitting display panel;
A data driver supplying data voltages to data lines provided on the light emitting display panel; And
The gate driver and a control unit for controlling the gate driver,
A reset voltage switching unit for supplying reset voltages for resetting the light emitting elements to the pixels is connected to the data lines,
The reset voltages are set differently for each color of the pixels. According to claim 1,
The control unit,
In the first frame period among the n frame periods included in the preset period, the data voltage is supplied to the pixels to emit the pixels,
The light emitting display device supplies the reset voltages to the pixels in at least one of the remaining frame periods. According to claim 1,
The reset voltage switching unit,
A first switching unit switching the reset voltages and supplying them to the data lines; And
And a second switching unit sequentially connecting one data line to at least three pixels. The method of claim 3,
The light emitting display panel is divided into a display area and a non-display area surrounding the display area, and at least one of the first switching unit and the second switching unit is provided in the non-display area. The method of claim 3,
At least one of the first switching unit and the second switching unit is a light emitting display device provided in the data driver. According to claim 1,
At least three pixels displaying different colors constitute one unit pixel,
The reset voltage switching unit,
A first switching unit including reset switches connected to each of the data lines; And
And a second switching unit that includes at least three branch data lines that are branched from one data line and connected to pixels of the same color provided in at least three unit pixels,
The at least three branch data lines branched from one data line are connected to pixels of the same color provided in at least three unit pixels,
A light-emitting display device having a MUX switch connected to each of the branch data lines. The method of claim 6,
The MUX switches are divided into at least three MUX groups,
At least three MUX switches constituting one MUX group are connected to different data lines, and are connected to pixels of different colors provided in one unit pixel. According to claim 1,
At least three pixels displaying different colors constitute one unit pixel,
The reset voltage switching unit,
A first switching unit connected to each of the data lines and including reset switches connected to one reset control signal line; And
And a second switching unit that includes at least three branch data lines branched from one data line and connected to at least three pixels provided in one unit pixel,
A light emitting display device having a MUX switch connected to each of the at least three branch data lines branched from one data line. The method of claim 8,
The MUX switches connected to each of the at least three branch data lines branched from one data line are sequentially turned on. According to claim 1,
At least three pixels displaying different colors constitute one unit pixel,
The reset voltage switching unit,
A first switching unit including reset switches connected to at least three data lines respectively; And
And a second switching unit that includes at least three branch data lines branched from one data line and connected to at least three pixels provided in one unit pixel,
A light emitting display device having a MUX switch connected to each of the at least three branch data lines branched from one data line. The method of claim 10,
A first reset switch, a second reset switch, and a third reset switch are connected to one data line,
The first reset switches connected to different data lines are connected to one first reset control signal line,
The second reset switches connected to different data lines are connected to one second reset control signal line,
The third reset switches connected to different data lines are connected to one third reset control signal line.

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