KR20200069805A - Display device - Google Patents

Abstract

The present invention provides a display device capable of reducing power consumption. According to an embodiment of the present invention, the display device comprises: a substrate having a first sub-pixel and a second sub-pixel; a first light emission layer provided on the substrate to emit light of a first color; a second light emission layer provided on the first light emission layer to emit light of a second color; a first electrode provided between the substrate and the first light emission layer in the first sub-pixel; a second electrode provided between the first light emission layer and the second light emission layer in each of the first sub-pixel and the second sub-pixel; and a third electrode provided on the second light emission layer. The second electrode of the first sub-pixel is electrically connected to the third electrode.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device for displaying an image.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, recently, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been used.

Recently, a head mounted display (HMD) including such a display device has been developed. A head-mounted display (HMD) is a virtual reality (VR) or augmented reality (Augmented Reality) eyeglass-type monitor device in which focus is formed at a distance close to the user's eyes by wearing glasses or a helmet.

Such a head-mounted display has difficulty in precisely patterning light emitting layers of different colors for each sub-pixel due to high-resolution and dense pixel spacing. To solve this, the head-mounted display may implement a different color by forming a white light-emitting layer composed of a plurality of stacks emitting light of different colors as a common layer, and arranging color filters for each sub-pixel. In this case, the head-mounted display has an advantage in that a precise mask fabrication process or a precise mask alignment process is not required, but there is a problem that power is consumed by a plurality of stacks.

The present invention provides a display device capable of reducing power consumption.

A display device according to an exemplary embodiment of the present invention includes a substrate having a first sub-pixel and a second sub-pixel, a first light-emitting layer provided on the substrate to emit light of a first color, and a first light-emitting layer provided on the substrate. A second emission layer that emits light of two colors, a first electrode provided between the substrate and the first emission layer in the first sub-pixel, and a first emission layer and a second emission layer in each of the first sub-pixel and the second sub-pixel, respectively. It includes a second electrode, and a third electrode provided on the second light emitting layer. The second electrode of the first sub-pixel is electrically connected to the third electrode.

According to the present invention, by forming the first emission layer and the second emission layer on the entire surface of the sub-pixels without a mask, it is possible to solve the problem of forming different emission layers for each sub-pixel by using a mask. That is, the present invention does not require a precise mask fabrication or precise mask alignment process, and can be applied to a high-resolution display device having a dense pixel spacing.

In addition, although the first light emitting layer and the second light emitting layer are formed on the entire surface of the present invention, only one of the first light emitting layer and the second light emitting layer can be emitted from each of the sub pixels. Accordingly, the present invention can significantly reduce power consumption as compared to emitting both the first light emitting layer and the second light emitting layer.

In addition, according to the present invention, the second electrode is disconnected between the sub-pixels using the occlusion pattern, and the second electrode of each of the sub-pixels is connected to any one of the first power line, the second power line, and the second connection electrode. Can be. In the present invention, there is no need to manufacture a separate mask, and a separate process is not added by forming a masking pattern simultaneously with the first electrode.

In addition, the present invention does not form the first electrode in some sub-pixels. Accordingly, the present invention can improve the transmittance in the sub-pixel without the first electrode, and in particular, when the display device is made of the lower emission method, the light emitted from the emission layer does not have to pass through the first electrode. Light efficiency can be improved.

Further, the present invention does not form banks in some sub-pixels. Accordingly, the present invention can have a large emission area in a sub-pixel without a bank, and maximize the aperture ratio.

The effects obtainable in the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description. .

1 is a perspective view showing a display device according to an exemplary embodiment of the present invention.
FIG. 2 is a plan view showing the first substrate of FIG. 1, a source drive IC, a flexible film, a circuit board, and a timing control unit.
3 is a plan view schematically showing a first substrate according to a first embodiment of the present invention.
4 is a cross-sectional view showing an example of II of FIG. 3.
5 is a cross-sectional view showing an example of II-II of FIG. 3.
6 is a plan view schematically showing an example of a first sub-pixel and a second sub-pixel.
7 is a plan view showing a modified example of FIG. 6.
8 is a plan view schematically showing an example of a third sub-pixel.
9 is an enlarged view showing an example of area A of FIG. 4.
10 is a cross-sectional view showing an example of III-III of FIG. 3.
11 is a cross-sectional view showing an example of IV-IV of FIG. 3.
12 is a cross-sectional view showing a modified embodiment of FIG. 4.
13 is a cross-sectional view showing another modified embodiment of FIG. 4.
14 is a plan view schematically illustrating a first substrate of a display panel according to a second exemplary embodiment of the present invention.
15 is a cross-sectional view showing an example of V-V of FIG. 14.
16 is a plan view schematically showing an example of a first sub-pixel and a second sub-pixel.
17 is a flowchart illustrating a method of manufacturing a display device according to a first embodiment of the present invention.
18A to 18J are cross-sectional views illustrating a method of manufacturing a display device according to a first embodiment of the present invention.
19A to 19C relate to a display device according to another exemplary embodiment of the present invention, which relates to a head mounted display (HMD) device.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and have ordinary knowledge in the art to which the present invention pertains. It is provided to fully inform the person of the scope of the invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

When'include','have','consist of' and the like mentioned in this specification are used, other parts may be added unless'~man' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship of two parts is described as'~top','~upper','~bottom','~side', etc.,'right' Alternatively, one or more other parts may be located between the two parts unless'direct' is used.

In the case of a description of a time relationship, for example,'after','following','~after','~before', etc. When a temporal sequential relationship is described,'right' or'direct' It may also include cases that are not continuous unless it is used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

"X-axis direction", "Y-axis direction" and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is vertical, and is wider within a range in which the configuration of the present invention can function functionally. It can mean having directionality.

It should be understood that the term “at least one” includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item, and the third item" means 2 of the first item, the second item, or the third item, as well as the first item, the second item, and the third item, respectively. It can mean any combination of items that can be presented from more than one dog.

Each of the features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving may be possible, and each of the embodiments may be independently implemented with respect to each other or may be implemented together in an association relationship. It might be.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view showing a display device according to an exemplary embodiment of the present invention. FIG. 2 is a plan view showing the first substrate of FIG. 1, a source drive IC, a flexible film, a circuit board, and a timing control unit.

1 and 2, the display device 100 according to an exemplary embodiment of the present invention includes a display panel 110, a source drive integrated circuit (hereinafter referred to as “IC”) 140, and a flexible film 150, a circuit board 160, and a timing control unit 170.

The display panel 110 includes a first substrate 111 and a second substrate 112. The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film.

Gate lines, data lines, and sub-pixels are formed on one surface of the first substrate 111 facing the second substrate 112. The sub-pixels are provided in an area defined by an intersection structure of gate lines and data lines.

Each of the sub-pixels may include a thin film transistor, a light emitting device having an anode electrode, a light emitting layer, and a cathode electrode. Each of the sub-pixels supplies a predetermined current to the light emitting device according to the data voltage of the data line when a gate signal is input from the gate line using a thin film transistor. Accordingly, when a high potential voltage is applied to the anode electrode and a low potential voltage is applied to the cathode electrode, each of the sub-pixels may emit light with a predetermined brightness according to a predetermined current.

The display panel 110 may be divided into a display area DA displaying an image by forming sub-pixels and a non-display area NDA displaying an image. Gate lines, data lines, and sub-pixels may be formed in the display area DA. Gate drivers and pads may be formed in the non-display area NDA.

The gate driver supplies gate signals to gate lines according to the gate control signal input from the timing controller 170. The gate driver may be formed in a non-display area DA on one side or both sides of the display area DA of the display panel 110 by a gate driver in panel (GIP) method. Alternatively, the gate driver is made of a driving chip, mounted on a flexible film, and attached to a non-display area DA on one side or both sides of the display area DA of the display panel 110 by a tape automated bonding (TAB) method. It might be.

The source drive IC 140 receives digital video data and a source control signal from the timing controller 170. The source drive IC 140 converts digital video data into analog data voltages according to the source control signal and supplies the data to the data lines. When the source drive IC 140 is manufactured as a driving chip, it may be mounted on the flexible film 150 in a chip on film (COF) or chip on plastic (COP) method.

Pads such as data pads may be formed in the non-display area NDA of the display panel 110. Wires connecting the pads and the source drive IC 140 may be formed on the flexible film 150, and wirings connecting the pads and the wirings of the circuit board 160 may be formed. The flexible film 150 is attached on the pads using an anisotropic conducting film, and thereby the pads and wirings of the flexible film 150 can be connected.

The circuit board 160 may be attached to the flexible films 150. The circuit board 160 may be mounted with a plurality of circuits implemented with driving chips. For example, the timing control unit 170 may be mounted on the circuit board 160. The circuit board 160 may be a printed circuit board or a flexible printed circuit board.

The timing controller 170 receives digital video data and timing signals from an external system board through a cable of the circuit board 160. The timing controller 170 generates a gate control signal for controlling the operation timing of the gate driver and a source control signal for controlling the source drive ICs 140 based on the timing signal. The timing controller 170 supplies the gate control signal to the gate driver, and supplies the source control signal to the source drive ICs 140.

Example 1

3 is a plan view schematically showing a first substrate of a display panel according to a first embodiment of the present invention, FIG. 4 is a cross-sectional view showing an example of II of FIG. 3, and FIG. 5 is a view of II-II of FIG. 3 It is a cross-sectional view showing an example. 6 is a plan view schematically showing an example of a first sub-pixel and a second sub-pixel, FIG. 7 is a plan view showing a modified example of FIG. 6, and FIG. 8 is a schematic view showing an example of a third sub-pixel It is a top view. 9 is an enlarged view showing an example of area A of FIG. 4. 10 is a cross-sectional view showing an example of III-III of FIG. 3, and FIG. 11 is a cross-sectional view showing an example of IV-IV of FIG. 3. FIG. 12 is a cross-sectional view showing a modified embodiment of FIG. 4, and FIG. 13 is a cross-sectional view showing another modified embodiment of FIG. 4.

3 to 13, the display panel 110 according to the first exemplary embodiment of the present invention includes a first substrate 111, a light blocking layer 210, a first insulating layer 220, a thin film transistor 230, The first connection electrode 241, 242, 360, the second connection electrode 250, the second insulating film 260, the planarization film 270, the obscuring patterns 281, 282, 283, the first electrodes 311, 312 ), the bank 315, the first emission layers 321, 322, and 323, the second electrodes 331, 332, and 333, the second emission layer 340, and the third electrode 350.

The first substrate 111 may be made of glass or plastic, but is not limited thereto, and may be made of a semiconductor material such as a silicon wafer. The first substrate 111 may be made of a transparent material or an opaque material.

The first substrate 111 is divided into a display area DA and a non-display area NDA. A first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 may be provided in the display area DA of the first substrate 111. The first sub-pixel P1 emits red light, the second sub-pixel P2 emits green light, and the third sub-pixel P3 may be provided to emit blue light, but is not limited thereto. It is not. A fourth sub-pixel emitting light of white (W) may be further provided in the display area DA of the substrate 111. In addition, the arrangement order of each sub-pixel P1, P2, P3 may be variously changed.

The display device according to the first exemplary embodiment of the present invention may be formed in a so-called bottom emission method in which emitted light is emitted downward, but is not limited thereto. When the display device according to the first embodiment of the present invention is made of a lower emission method, a transparent material may be used for the first substrate 111. On the other hand, when the display device according to the first embodiment of the present invention is made of a top emission method in which emitted light is emitted upward, the first substrate 111 may be made of an opaque material as well as a transparent material. It might be.

On the first substrate 111, circuit elements including various signal lines, a thin film transistor 230, and a capacitor are provided for each sub-pixel P1, P2, and P3. The signal lines may include gate lines, data lines, power lines, and reference lines.

The thin film transistor 230 is provided for each of the sub-pixels P1, P2, and P3. One first thin film transistor 232 is provided in the first sub-pixel P1, the second second thin film transistor 234 is provided in the second sub-pixel P2, and the third sub-pixel P3 is provided. Another third thin film transistor may be provided.

When the gate signal is input to the gate line, the thin film transistor 230 supplies a predetermined voltage to the first electrodes 311 and 312 according to the data voltage of the data line. The thin film transistor 230 includes an active layer, a gate electrode, a source electrode, and a drain electrode.

An active layer is formed on the first substrate 111. The active layer may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. A light blocking layer 210 for blocking external light incident on the active layer may be formed between the first substrate 111 and the active layer as illustrated in FIG. 4. When the light blocking layer 210 is formed of a metal material, the first insulating layer 220 may be formed between the active layer and the light blocking layer 210.

A gate insulating film may be formed on the active layer. The gate insulating film may be formed of an inorganic film, for example, a silicon oxide film, a silicon nitride film, or multiple films thereof.

A gate electrode may be formed on the gate insulating layer. The gate electrode may be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), or alloys thereof. It may be made of a single layer or multiple layers, but is not limited thereto.

An interlayer insulating film may be formed on the gate electrode. The interlayer insulating film may be formed of an inorganic film, for example, a silicon oxide film, a silicon nitride film, or multiple films thereof.

A source electrode and a drain electrode may be formed on the interlayer insulating film. Each of the source electrode and the drain electrode may be connected to the active layer through a contact hole passing through the gate insulating layer and the interlayer insulating layer. Each of the source electrode and the drain electrode is one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), or It may be a single layer or multiple layers made of these alloys, but is not limited thereto.

The first connection electrodes 241, 242 and 360 and the second connection electrodes 250 are formed on the first substrate 111.

The first connection electrodes 241, 242, and 360 electrically connect the second electrodes 331, 332 and the third electrode 350 of the first sub-pixel P1 and the second sub-pixel P2, respectively. More specifically, the first connection electrodes 241, 242, and 360 may include a first power line 241, a second power line 242, and an auxiliary power line 360.

The auxiliary power line 360 is formed to extend in the first direction (X-axis direction) in the non-display area NDA. The auxiliary power line 360 is partially exposed without being covered by the first insulating layer 220, the second insulating layer 260, and the planarization layer 270, as shown in FIGS. 10 and 11, and in the exposed region The third electrode 350 can be connected.

The auxiliary power line 360 may be formed of the same material in the same layer as the light blocking layer 210, but is not limited thereto. The auxiliary power line 360 may be formed of the same material in the same layer as any one of the active layer, gate electrode, source electrode, and drain electrode of the thin film transistor 230.

The first power line 241 is disposed on one side of the first sub-pixel P1 in the display area DA, and is connected to the second electrode 331 of the first sub-pixel P1. 4 to 7, the first power line 241 is illustrated as being disposed between the first sub-pixel P1 and the third sub-pixel P3, but is not limited thereto. The first power line 241 may be disposed between the first sub-pixel P1 and the second sub-pixel P2.

The first power line 241 may extend in the second direction (Y-axis direction) in the display area DA. The plurality of first sub-pixels P1 may be arranged along the second direction in parallel with the first power line 241. In this case, the first power line 241 is connected to the second electrode 331 of all of the plurality of first sub-pixels P1 arranged side by side, or some of the plurality of first sub-pixels P1. The second electrode 331 can be connected.

Meanwhile, the plurality of first sub-pixels P1 may be alternately arranged with the plurality of second sub-pixels P2 along the second direction. In this case, the first power line 241 is connected to the second electrode 331 of all of the plurality of first sub-pixels P1, or the second electrode of some of the plurality of first sub-pixels P1 ( 331). Alternatively, the first power line 241 is connected to the second electrodes 331 and 332 of both the plurality of first sub-pixels P1 and the plurality of second pixels P2, or the plurality of first sub-pixels ( The second electrodes 331 and 332 of P1) and some of the plurality of second pixels P2 may be connected.

One end of the first power line 241 is connected to the auxiliary power line 360. The first power line 241 may be connected to the auxiliary power line 360 through a contact hole as illustrated in FIG. 10, but is not limited thereto.

The first power line 241 may be formed of the same material in the same layer as any one of the active layer, gate electrode, source electrode, and drain electrode of the first thin film transistor 232.

As described above, in the first sub-pixel P1, the second electrode 331 and the third electrode 350 are electrically connected through the first power line 241 and the auxiliary power line 360. That is, when a low potential voltage is applied to the third electrode 350, the second electrode 331 of the first sub-pixel P1 is applied with the same low potential voltage as the third electrode 350.

The second power line 242 is disposed on one side of the second sub-pixel P2 in the display area DA, and is connected to the second electrode 332 of the second sub-pixel P2. 4 to 7, the second power line 242 is illustrated as being disposed between the first sub-pixel P1 and the second sub-pixel P2, but is not limited thereto. The second power line 242 may be disposed between the second sub-pixel P2 and the third sub-pixel P3.

The second power line 242 is disposed in the display area DA and may be formed to extend in the second direction (Y-axis direction). The plurality of second sub-pixels P2 may be arranged along the second direction in parallel with the second power line 242. In this case, the second power line 242 is connected to the second electrode 332 of all of the plurality of second sub-pixels P2 arranged side by side, or some of the plurality of second sub-pixels P2 It can be connected to the second electrode 332.

Meanwhile, the plurality of second sub-pixels P2 may be alternately arranged with the plurality of first sub-pixels P1 along the second direction. In this case, the second power line 242 is connected to the second electrode 332 of all of the plurality of second sub-pixels P2, or the second electrode of some of the plurality of second sub-pixels P2 ( 332). Alternatively, the second power line 242 is connected to the second electrodes 331 and 332 of both the plurality of first sub-pixels P1 and the plurality of second pixels P2, or the plurality of first sub-pixels ( The second electrodes 331 and 332 of P1) and some of the plurality of second pixels P2 may be connected.

One end of the second power line 242 is connected to the auxiliary power line 360. The second power line 242 may be connected to the auxiliary power line 360 through a contact hole as illustrated in FIG. 11, but is not limited thereto.

The second power line 242 may be formed of the same material in the same layer as any one of the active layer, gate electrode, source electrode, and drain electrode of the second thin film transistor 234.

As described above, the second sub-pixel P2 is electrically connected to the second electrode 332 and the third electrode 350 through the second power line 242 and the auxiliary power line 360. That is, when a low potential voltage is applied to the third electrode 350, the second electrode 332 of the second sub-pixel P2 is applied with the same low potential voltage as the third electrode 350.

The second connection electrode 250 is electrically connected to the second electrode 333 of the third sub-pixel P3.

The second connection electrode 250 is disposed on one side of the third sub-pixel P3 in the display area DA, and is connected to the second electrode 333 of the third sub-pixel P3.

4, 5, and 8, the second connection electrode 250 is illustrated as being disposed between the second sub-pixel P2 and the third sub-pixel P3, but is not limited thereto. The second connection electrode 250 may be disposed between the third sub-pixel P3 and the first sub-pixel P1.

The second connection electrode 250 may be patterned to correspond to each of the plurality of third sub-pixels P3. At this time, the second connection electrodes 250 formed to correspond to each of the plurality of third sub-pixels P3 are spaced apart as illustrated in FIG. 3 so as not to be electrically connected to each other. One third sub-pixel P3 may be connected to one second connection electrode 251, and the other third sub-pixel P3 may be connected to another second connection electrode 252. In this case, one second connection electrode 251 and the other second connection electrode 252 may be patterned and spaced apart so as not to be electrically connected to each other.

The second connection electrode 250 may be any one of a source electrode and a drain electrode of the third thin film transistor.

The second insulating layer 260 is formed on the first and second thin film transistors 232 and 234, the first connecting electrodes 241, 242 and 360 and the second connecting electrode 250. The second insulating layer 260 covers and protects the first and second thin film transistors 232 and 234 while exposing a portion of the first connecting electrodes 241, 242 and 360 and the second connecting electrode 250.

More specifically, the second insulating layer 260 includes opening regions OA1, OA2, OA3, and OA4 exposing portions of the first connection electrodes 241, 242, and 360.

The second insulating layer 260 may include a first opening region OA1 exposing a portion of the first power line 241 as illustrated in FIGS. 4 and 5. The first opening area OA1 may be formed along the first power line 241. At this time, the first opening area OA1 may be formed in one or a plurality of patterns having a predetermined length in the second direction (Y-axis direction) on one first power line 241.

In addition, the second insulating layer 260 may include a second opening area OA2 exposing a portion of the second power line 242 as illustrated in FIGS. 4 and 5. The second opening area OA2 may be formed along the second power line 242. At this time, the second opening area OA2 may be formed in one or a plurality of patterns having a predetermined length in a second direction (Y-axis direction) on one second power line 242.

Also, the second insulating layer 260 may include a third opening region OA3 exposing a portion of the second connection electrode 250 as illustrated in FIGS. 4 and 5. The third opening area OA3 may be formed to surround the third sub-pixel P3. Accordingly, the third opening region OA3 exposes a portion of the second connection electrode 250 in the region where the second connection electrode 250 is formed, and the first in the region where the second connection electrode 250 is not formed. The insulating film 220 is exposed.

In addition, the second insulating layer 260 may include a fourth opening area OA4 exposing a portion of the auxiliary power line 360 as illustrated in FIGS. 10 and 11. The auxiliary power line 360 is partially exposed by the first insulating layer 220, and the fourth opening area OA4 may be formed on the exposed auxiliary power line 360.

The second insulating film 260 may be formed of an inorganic film, for example, a silicon oxide film, a silicon nitride film, or multiple films thereof.

The planarization layer 270 is formed on the second insulating layer 260 to planarize the step due to the thin film transistor 230. At this time, the planarization film 270 is not formed in the opening regions OA1, OA2, OA3, and OA4 of the second insulating film 260. Accordingly, a portion of the first connection electrodes 241, 242 and 360 and the second connection electrodes 250 may still be exposed.

The planarization layer 270 may have a smaller formation area than the second insulating layer 260. Accordingly, the planarization layer 270 may expose a portion of the second insulating layer 260. At this time, the second insulating layer 260 may be exposed without being covered by the planarization layer 270 in an area adjacent to the opening regions OA1, OA2, OA3, and OA4.

The planarization film 270 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. Can be.

The first electrodes 311 and 312 are patterned on each of the first sub-pixel P1 and the second sub-pixel P2 on the planarization layer 270. One first electrode 311 is formed in the first sub-pixel P1, and another first electrode 312 is formed in the second sub-pixel P2.

The display device 100 according to the first embodiment of the present invention is characterized in that the first electrodes 311 and 312 are not formed in the third sub-pixel P3. Accordingly, the display device 100 according to the first embodiment of the present invention can improve transmittance in the third sub-pixel P3. Particularly, when the display device 100 is made of a lower emission method, since the light emitted from the second emission layer 340 does not need to pass through the first electrodes 311 and 312 in the third sub-pixel P3, the light efficiency is improved. Improve it.

The first electrodes 311 and 312 may be source electrodes of the first and second thin film transistors 232 and 234 through the contact holes CH1 and CH2 passing through the second insulating layer 260 and the planarization layer 270, or It is connected to the drain electrode. The first electrode 311 of the first sub-pixel P1 is connected to the source electrode or the drain electrode of the first thin film transistor 232 through the contact hole CH1, and a first high potential voltage is applied. The first electrode 312 of the second sub-pixel P2 is connected to the source electrode or the drain electrode of the second thin film transistor 234 through the contact hole CH2, and a second high potential voltage is applied.

The first electrodes 311 and 312 may be made of a transparent metal material, a semi-transmissive metal material, or a metal material having high reflectance. When the display device 100 is made of a lower emission method, the first electrodes 311 and 312 are transparent metal materials such as ITO and IZO that can transmit light (TCO, Transparent Conductive Material), or magnesium (Mg), It may be formed of a semi-transmissive conductive material such as silver (Ag) or an alloy of magnesium (Mg) and silver (Ag). When the display device 100 is made of an upper emission method, the first electrodes 311 and 312 are a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), Ag alloy, and Ag alloy and ITO laminated structure (ITO / Ag alloy / ITO) can be formed of a high reflectivity metal material. The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). The first electrodes 311 and 312 may be anode electrodes.

The obstruction patterns 281, 282, and 283 are formed to cover a part of the opening regions OA1, OA2, and OA3 of the second insulating layer 260 on the second insulating layer 260. The occlusion patterns 281, 282, and 283 include a first occlusion pattern 281, a second occlusion pattern 282, and a third occlusion pattern 283.

The first obstruction pattern 281 is formed on the second insulating layer 260 exposed without being covered by the planarization layer 270, and the first opening region OA1 exposing a portion of the first power line 241 is exposed. It includes a protrusion 281a protruding to cover a part. At this time, the protrusion 281a of the first obstruction pattern 281 is spaced apart from the first power line 241 to form a space between the first power line 241.

The first occlusion pattern 281 is formed close to the sub-pixel disposed adjacent to the first sub-pixel P1 with the first opening area OA1 therebetween. The first opening area OA1 exposing the first power line 241 may be disposed between the first sub-pixel P1 and the third sub-pixel P3, but is not limited thereto.

When the first opening region OA1 of the second insulating layer 260 is disposed between the third sub-pixel P3 and the first sub-pixel P1, the first obstruction pattern 281 has a protrusion 281a. The third sub-pixel P3 may protrude in a direction toward the first opening area OA1. Accordingly, a portion of the first opening area OA1 adjacent to the third sub-pixel P3 is covered by the first blocking pattern 281, and the first power line 241 is also the first blocking pattern 281. It is covered. The remaining area of the first opening area OA1 adjacent to the first sub-pixel P1 still exposes the first power line 241.

The first obstruction pattern 281 may be formed along the first power line 241 like the first opening area OA1. At this time, the first cover pattern 281 may be formed of a plurality of patterns having a predetermined length in the second direction (Y-axis direction) on one first power line 241, as shown in FIG. 6, It is not necessarily limited to this. The first obstruction pattern 281 may be formed as one line pattern extending in the second direction (Y-axis direction) on one first power supply line 241 as illustrated in FIG. 7.

Meanwhile, the first covering pattern 281 may be formed of the same material in the same layer as the first electrodes 311 and 312, but is not limited thereto.

The first obstruction pattern 281 may be formed of the same material in the same layer as the first electrodes 311 and 312 as illustrated in FIGS. 4 and 5. In this case, the first obstruction pattern 281 may be formed to be spaced apart from the first electrodes 311 and 312.

In this case, the display device is formed of the same material in the same layer as the first electrodes 311 and 312 by forming the first cover pattern 281, so that the first cover pattern 281 is formed without adding a separate process. .

However, the present invention is not limited thereto, and the first obstruction pattern 281 may be formed on a different layer from the first electrodes 311 and 312. The first obstruction pattern 281 may be formed between the second insulating layer 260 and the planarization layer 270.

The second obstruction pattern 282 is formed on the exposed second insulating layer 260 without being covered by the planarization layer 270, and the second opening pattern OA2 exposes a portion of the second power line 242. It includes a protrusion 282a protruding to cover a part. At this time, the protrusion 282a of the second obstruction pattern 282 is spaced apart from the second power line 242 to form a space between the second power line 242.

The second occlusion pattern 282 is formed close to the sub-pixel disposed adjacent to the second sub-pixel P2 with the second opening area OA2 therebetween. The second opening area OA2 exposing the second power line 242 may be disposed between the first sub-pixel P1 and the second sub-pixel P2, but is not limited thereto.

When the second opening region OA2 of the second insulating layer 260 is disposed between the first sub-pixel P1 and the second sub-pixel P2, the second obstruction pattern 282 has a protrusion 282a. A sub-pixel P1 may protrude in a direction toward the second opening area OA2. Accordingly, a portion of the second opening area OA2 adjacent to the first sub-pixel P1 is covered by the second blocking pattern 282, and the second power line 242 is also the second blocking pattern 282. It is covered. The remaining area adjacent to the second sub-pixel P12 of the second opening area OA2 still exposes the second power line 242.

The second obstruction pattern 282 may be formed along the second power line 242 like the second opening area OA2. At this time, the second obstruction pattern 282 may be formed as a plurality of patterns having a predetermined length in the second direction (Y-axis direction) on one second power line 242 as shown in FIG. 6, It is not necessarily limited to this. The second obstruction pattern 282 may be formed as one line pattern extending in the second direction (Y-axis direction) on one second power supply line 242 as illustrated in FIG. 7.

Meanwhile, the second covering pattern 282 may be formed of the same material in the same layer as the first electrodes 311 and 312, but is not limited thereto.

The second obstruction pattern 282 may be formed of the same material in the same layer as the first electrodes 311 and 312 as illustrated in FIGS. 4 and 5. In this case, the second obstruction pattern 282 may be formed to be spaced apart from the first electrodes 311 and 312.

When the second opening area OA2 of the second insulating layer 260 is disposed between the first sub-pixel P1 and the second sub-pixel P2, the second occlusion pattern 282 is the first sub-pixel P1 ) Are spaced apart from the first electrode 311 so that the first electrode 311 of the first sub-pixel P1 is not electrically connected to each other. The second obstruction pattern 282 may be formed on the planarization layer 270 as well as the second insulating layer 260 exposed without being covered by the planarization layer 270.

In this case, the display device forms the second masking pattern 282 with the same material in the same layer as the first electrodes 311 and 312, thereby forming a second masking pattern 282 without adding a separate process. .

However, the present invention is not limited thereto, and the second obstruction pattern 282 may be formed on a different layer from the first electrodes 311 and 312. The second obstruction pattern 282 may be formed between the second insulating layer 260 and the planarization layer 270.

The third obstruction pattern 283 is formed on the exposed second insulating layer 260 without being covered by the planarization layer 270, and the third opening region OA3 exposing a portion of the second connection electrode 250 is exposed. It includes a protrusion 283a protruding to cover a part. At this time, the protrusion 283a of the third obstruction pattern 283 is spaced apart from the second connection electrode 250 to form a space between the second connection electrode 250.

The third occlusion pattern 283 is formed close to the sub-pixel disposed adjacent to the third sub-pixel P3 with the third opening area OA3 therebetween. The third opening area OA3 exposing the second connection electrode 250 is between the first sub-pixel P1 and the third sub-pixel P3 and the second sub-pixel P2 and the third sub-pixel P3. It may be disposed between, but is not necessarily limited to this.

When the third opening region OA3 of the second insulating layer 260 is disposed between the first sub-pixel P1 and the third sub-pixel P3, the third obstruction pattern 283 has a protrusion 283a. A sub-pixel P1 may protrude in a direction toward the third opening area OA3. Accordingly, a portion of the third opening area OA3 adjacent to the first sub-pixel P1 is covered by the third blocking pattern 283, and the second connection electrode 250 or the first insulating layer 220 is also It is obscured by the third obscuring pattern 283. The remaining area adjacent to the third sub-pixel P3 of the third opening area OA2 still exposes the second connection electrode 250 or the first insulating layer 220.

In addition, when the third opening region OA3 of the second insulating layer 260 is disposed between the second sub-pixel P2 and the third sub-pixel P3, the third obstruction pattern 283 is a protrusion 283a. May protrude in the direction from the second sub-pixel P2 toward the third opening area OA3. Accordingly, a part of the third opening area OA3 adjacent to the second sub-pixel P2 is covered by the third blocking pattern 283, and the second connection electrode 250 or the first insulating layer 220 is also It is obscured by the third obscuring pattern 283. The remaining area adjacent to the third sub-pixel P3 of the third opening area OA2 still exposes the second connection electrode 250 or the first insulating layer 220.

As illustrated in FIG. 8, the third occlusion pattern 283 may be formed to surround the third sub-pixel P3 as in the third opening area OA3. The second electrode 333 of the third sub-pixel P3 is the second electrode 331 of the first sub-pixel P1 and the second electrode of the second sub-pixel P2 by the third occlusion pattern 283. (332). In the display device according to the first exemplary embodiment of the present invention, the third blocking pattern 283 is formed to surround the third sub-pixel P3, so that the second electrode 333 of the third sub-pixel P3 is the first sub The second electrode 331 of the pixel P1 and the second electrode 332 of the second sub-pixel P2 are not electrically connected to each other.

Meanwhile, the third masking pattern 283 may be formed of the same material in the same layer as the first electrodes 311 and 312, but is not limited thereto.

The third obstruction pattern 283 may be formed of the same material in the same layer as the first electrodes 311 and 312 as illustrated in FIGS. 4 and 5. In this case, the third obstruction pattern 283 may be formed to be spaced apart from the first electrodes 311 and 312.

When the third opening area OA3 of the second insulating layer 260 is disposed between the first sub-pixel P1 and the third sub-pixel P3, the third occlusion pattern 283 is the first sub-pixel P1 ) Are spaced apart from the first electrode 311 so that the first electrode 311 of the first sub-pixel P1 is not electrically connected to each other. The third obstruction pattern 283 may be formed on the planarization layer 270 as well as the second insulating layer 260 exposed without being covered by the planarization layer 270.

In addition, when the third opening area OA3 of the second insulating layer 260 is disposed between the second sub-pixel P2 and the third sub-pixel P3, the third occlusion pattern 283 is the second sub-pixel The second electrode 312 of (P2) is spaced apart from each other so that the second electrode 312 of the second sub-pixel (P2) is not electrically connected to each other. The third obstruction pattern 283 may be formed on the planarization layer 270 as well as the second insulating layer 260 exposed without being covered by the planarization layer 270.

In this case, the display device is formed of the same material in the same layer as the first electrodes 311 and 312 by forming the third masking pattern 283, so that the third masking pattern 283 is formed without adding a separate process. .

However, the present invention is not limited thereto, and the third obstruction pattern 283 may be formed on a different layer from the first electrodes 311 and 312. The third obstruction pattern 283 may be formed between the second insulating layer 260 and the planarization layer 270.

The bank 315 may be formed on the planarization layer 270 to cover the ends of the first electrodes 311 and 312. Accordingly, a problem in which the light emission efficiency is lowered due to the concentration of current at the ends of the first electrodes 311 and 312 can be prevented.

Meanwhile, the bank 315 is not formed in the opening regions OA1, OA2, OA3, and OA4 of the second insulating layer 260. Accordingly, a portion of the first connection electrodes 241, 242 and 360 and the second connection electrodes 250 may still be exposed.

Further, the bank 315 may also be formed on the obstruction patterns 281, 282, and 283. At this time, the bank 315 may be formed so that the protrusions 281a, 282a, and 283a of the obstruction patterns 281, 282, and 283 are exposed without being covered.

When the bank 315 is formed to cover the protrusions 281a, 282a, and 283a of each of the obstruction patterns 281, 282, and 283a, the first light emitting layer 321 of each of the sub-pixels P1, P2, P3, 322, 323) can be connected to each other without being disconnected. Also, the second electrodes 331, 332, and 333 of each of the sub-pixels P1, P2, and P3 may be connected to each other without being disconnected. Accordingly, the second electrode 331 of the first sub-pixel P1 is not connected to the first power line 241, and the second electrode 332 of the second sub-pixel P2 is connected to the second power line ( 242, the second electrode 333 of the third sub-pixel P3 cannot be connected to the second connection electrode 250.

In the display device according to the first exemplary embodiment of the present invention, the bank 315 is formed so as not to cover the protruding portions 281a, 282a, and 283a of the covering patterns 281, 282, and 283a so as not to cause this problem. Should be.

The bank 315 defines light emitting regions EA1 and EA2 in each of the first sub-pixel P1 and the second sub-pixel P2. That is, the exposed areas of the first electrodes 311 and 312 exposed without the bank 315 formed in each of the first sub-pixel P1 and the second sub-pixel P2 become light-emitting areas EA1 and EA2. .

Meanwhile, the display device 100 according to the first embodiment of the present invention is characterized in that the bank 315 is not formed in the third sub-pixel P1. Since the first electrode 310 is not formed in the third sub-pixel P1, the bank 315 covering the end of the first electrode 310 may also not be formed. Accordingly, in the display device 100 according to the first embodiment of the present invention, the emission area EA3 of the third sub-pixel P3 includes the emission area EA1 and the second sub-pixel of the first sub-pixel P1. It is larger than the light emission area EA2 of (P2). That is, the third sub-pixel P3 may have a larger emission area and aperture ratio than the first sub-pixel P1 and the second sub-pixel P2.

In the third sub-pixel P3, the emission area EA3 may be defined by the third occlusion pattern 283 disposed adjacent to the third sub-pixel P3. In the third sub-pixel P3, the exposed area of the second electrode 333 exposed by the third occlusion pattern 283 may be the emission area EA3.

The bank 315 may be made of an inorganic insulating film having a relatively thin thickness, but may also be made of an organic insulating film having a relatively thick thickness.

The first emission layer 320 is formed on the first electrode 310. More specifically, the first light emitting layers 321 and 322 are formed on the first electrodes 311 and 312 in the first and second sub pixels P1 and P2. The first light emitting layers 321 and 322 may also be formed on the bank 315. In addition, the first emission layer 323 is formed on the planarization layer 270 in the third sub-pixel P3.

The first light emitting layers 321, 322, and 323 may include a hole transporting layer, a light emitting layer, and an electron transporting layer. In this case, holes and electrons in the first light emitting layers 321, 322, and 323 are moved to the light emitting layer through the hole transport layer and the electron transport layer, respectively, and are combined with each other in the light emitting layer to emit light in a predetermined color.

The first emission layers 321, 322, and 323 may be any one of a red emission layer that emits red light, a green emission layer that emits green light, a blue emission layer that emits blue light, and a yellow emission layer that emits yellow light. It is not limited to this.

The first light emitting layers 321, 322, and 323 are disconnected between the first subpixel P1, the second subpixel P2, and the third subpixel P3. The obstruction patterns 281, 282, and 283 are provided between the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3. The first light emitting layers 321, 322, and 323 may be cut off from each other by the blocking patterns 281, 282, 283.

More specifically, the first emission layers 321, 322, and 323 may be cut off between the first sub-pixel P1 and the second sub-pixel P2 by the second occlusion pattern 282. When the first emission layers 321, 322, and 323 are entirely deposited without a mask, the first emission layer 321 deposited on the first sub-pixel P1 may have a second occlusion pattern (as illustrated in FIGS. 4 and 9). Due to the step between the protrusion 282a of the 282 and the second power line 242, it may be cut on the protrusion 282a of the second obscuring pattern 282. The first emission layer 322 deposited on the second sub-pixel P2 is a space between the protrusion 282a of the second obstruction pattern 282 and the second power line 242 as illustrated in FIGS. 4 and 9. It is introduced into the, may be formed under the protrusion 282a of the second cover pattern 282.

In the display device according to the first exemplary embodiment of the present invention, it is preferable that the first emission layer 321 of the first sub-pixel P1 and the first emission layer 322 of the second sub-pixel P2 are disconnected from each other. Do. Accordingly, when the second electrodes 331, 332, and 333 are entirely deposited on the first light emitting layers 321, 322, and 323, the second electrode 332 deposited on the second sub-pixel P2 is second. A space that can be introduced between the protrusion 282a of the obstruction pattern 282 and the first emission layer 322 of the second sub-pixel P2 may be secured.

Also, the first emission layers 321, 322, and 323 may be cut between the second sub-pixel P2 and the third sub-pixel P3 by the third occlusion pattern 283. When the first emission layers 321, 322, and 323 are entirely deposited without a mask, the first emission layer 322 deposited on the second sub-pixel P2 may have a third occlusion pattern (as shown in FIGS. 4 and 9). Due to the step between the protrusion 283a of the 283 and the second connection electrode 250, it may be cut on the protrusion 283a of the third occlusion pattern 283. The first emission layer 323 deposited on the third sub-pixel P3 is a space between the protrusion 283a and the second connection electrode 250 of the third obstruction pattern 283 as illustrated in FIGS. 4 and 9. It is introduced into the, may be formed under the protrusion 283a of the third cover pattern 283.

In the display device according to the first embodiment of the present invention, it is preferable that the first emission layer 322 of the second sub-pixel P2 and the first emission layer 323 of the third sub-pixel P3 are disconnected from each other. Do. Accordingly, when the second electrodes 331, 332, and 333 are entirely deposited on the first light emitting layers 321, 322, and 323, the second electrode 333 deposited on the third sub-pixel P3 is third. A space that can be introduced between the protrusion 283a of the obstruction pattern 283 and the first emission layer 323 of the third sub-pixel P3 may be secured.

Also, the first emission layers 321, 322, and 323 may be disconnected between the first sub-pixel P1 and the third sub-pixel P3 by the third occlusion pattern 283 and the first occlusion pattern 281. have. As illustrated in FIG. 5, a third occlusion pattern 283 and a first occlusion pattern 281 may be formed between the first sub-pixel P1 and the third sub-pixel P3. In this case, the first obstruction pattern 281 includes a protrusion 281a protruding from the third sub-pixel P3 in the direction of the first sub-pixel P1 to cover a part of the first opening area OA1. The third obstruction pattern 283 includes a protrusion 283a protruding from the first sub-pixel P1 toward the third sub-pixel P3 and covering a part of the third opening area OA3.

When the first emission layers 321, 322, and 323 are entirely deposited without a mask, the first emission layer 323 deposited on the third sub-pixel P3 may have a third masking pattern (as shown in FIGS. 5 and 9). 283) may be introduced into the space between the protrusion 283a and the first insulating layer 220, and be formed under the protrusion 283a of the third obscuring pattern 283. The first emission layer 321 deposited on the first sub-pixel P1 is a space between the protrusion 281a of the first obstruction pattern 281 and the first power line 241 as illustrated in FIGS. 5 and 9. It is introduced into the, may be formed under the protrusion 281a of the first cover pattern 281.

The second electrodes 331, 332, and 333 are formed on the first light emitting layers 321, 322, and 323. The second electrodes 331, 332, and 333 are disconnected between the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3. The obstruction patterns 281, 282, and 283 are provided between the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3. The first light emitting layers 321, 322, and 323 may be cut off from each other by the blocking patterns 281, 282, 283.

More specifically, the second electrodes 331, 332, and 333 may be disconnected between the first sub-pixel P1 and the second sub-pixel P2 by the second occlusion pattern 282. When the second electrodes 331, 332, and 333 are deposited on the entire surface, the second electrode 331 deposited on the first sub-pixel P1 has a second masking pattern 282 as shown in FIGS. 4 and 9. Due to the step between the protrusion 282a of the second power line 242, the second shielding pattern 282 may be cut off on the protrusion 282a.

The second electrode 332 deposited on the second sub-pixel P2 is a space between the protrusions 282a and the first light emitting layer 322 of the second obstruction pattern 282 as illustrated in FIGS. 4 and 9. Inflow, it may be formed under the protrusion 282a of the second cover pattern 282. In this case, the second electrode 332 of the second sub-pixel P2 may be deposited under a protrusion 282a of the second obstruction pattern 282 with a larger area than the first emission layer 322. Accordingly, the second electrode 332 of the second sub-pixel P2 may be connected to the second power line 242.

In the second sub-pixel P2, since the second electrode 332 is connected to the second power line 242, the second electrode 332 and the second power line 242 and the second power line 360 are connected to the second sub-pixel P332. The three electrodes 350 may be electrically connected. Accordingly, when a low potential voltage is applied to the third electrode 350, the second electrode 332 of the second sub-pixel P2 may be applied with the same low potential voltage as the third electrode 350. In this case, the second electrode 332 of the second sub-pixel P2 may be a cathode electrode.

4 and 9 illustrate that the second electrode 331 of the first sub-pixel P1 and the second electrode 332 of the second sub-pixel P2 are disconnected without contacting each other, but are necessarily limited to this. Does not work. The second electrodes 331 and 332 of each of the first sub-pixel P1 and the second sub-pixel P2 are both cathode electrodes, and a common voltage may be applied. The second electrodes 331 and 332 of each of the first sub-pixel P1 and the second sub-pixel P2 are formed to be in contact with each other and can be electrically connected to each other.

Also, the second electrodes 331, 332, and 333 may be disconnected between the second sub-pixel P2 and the third sub-pixel P3 by the third occlusion pattern 283. When the second electrodes 331, 332, and 333 are entirely deposited, the second electrode 332 deposited on the second sub-pixel P2 is a third masking pattern 283 as illustrated in FIGS. 4 and 9. Due to the step between the protrusion 283a and the first light emitting layer 323, the third cover pattern 283 may be cut off on the protrusion 283a.

The second electrode 333 deposited on the third sub-pixel P3 is a space between the protrusion 283a and the first light emitting layer 323 of the third obstruction pattern 283 as illustrated in FIGS. 4 and 9. Inflow, it may be formed under the protrusion 283a of the third cover pattern 283. At this time, the second electrode 333 of the third sub-pixel P3 may be deposited with a larger area than the first emission layer 323 under the protrusion 283a of the third occlusion pattern 283. Accordingly, the second electrode 333 of the third sub-pixel P3 may be connected to the second connection electrode 250.

In the third sub-pixel P3, the second electrode 333 is connected to the second connection electrode 250. The second connection electrode 250 may be a source electrode or a drain electrode of the third thin film transistor. In this case, the second electrode 333 of the third sub-pixel P3 is directly connected to the second connection electrode 250, and a third high potential voltage is applied. In this case, the second electrode 333 of the third sub-pixel P3 may be an anode electrode.

In the display device 100 according to the first exemplary embodiment of the present invention, the second electrode 332 of the second sub-pixel P2 and the second electrode 333 of the third sub-pixel P3 do not contact each other and are disconnected. It is desirable to be. As described above, in the second sub-pixel P2, the second electrode 332 may be a cathode electrode, and in the third sub-pixel P3, the second electrode 333 may be an anode electrode. In this case, when the second electrode 332 of the second sub-pixel P2 and the second electrode 333 of the third sub-pixel P3 come into contact, the second electrode 332 of the second sub-pixel P2 A short circuit occurs between the second electrode 333 of the third sub-pixel P3 and the display device 100 cannot be driven normally.

In addition, the second electrodes 331, 332, and 333 may be disconnected between the first sub-pixel P1 and the third sub-pixel P3 by the third occlusion pattern 283 and the first occlusion pattern 281. have.

When the second electrodes 331, 332, and 333 are deposited on the entire surface, the second electrode 333 deposited on the third sub-pixel P3 is a third masking pattern 283 as shown in FIGS. 5 and 9. May be introduced into the space between the protrusion 283a and the first emission layer 323, and be formed under the protrusion 283a of the third obscuring pattern 283.

At this time, the second electrode 333 of the third sub-pixel P3 may be deposited with a larger area than the first emission layer 323 under the protrusion 283a of the third occlusion pattern 283. The second electrode 331 deposited on the first sub-pixel P1 is a space between the protrusions 281a and the first light emitting layer 321 of the first obstruction pattern 281 as shown in FIGS. 5 and 10. Inflow, it may be formed under the protrusion 281a of the first cover pattern 281.

At this time, the second electrode 331 of the first sub-pixel P1 may be deposited with a larger area than the first light-emitting layer 321 under the protrusion 281a of the first obstruction pattern 281. Accordingly, the second electrode 331 of the first sub-pixel P1 may be connected to the first power line 241.

In the first sub-pixel P1, since the second electrode 331 is connected to the first power line 241, the second electrode 331 and the second electrode 331 are formed through the first power line 241 and the auxiliary power line 360. The three electrodes 350 may be electrically connected. Accordingly, when a low potential voltage is applied to the third electrode 350, the second electrode 331 of the first sub-pixel P1 may be applied with the same low potential voltage as the third electrode 350. In this case, the second electrode 331 of the first sub-pixel P1 may be a cathode electrode.

The second electrode (331, 332, 333) is a transparent metal material (TCO, Transparent Conductive Material), such as ITO, IZO that can transmit light, or magnesium (Mg), silver (Ag), or magnesium (Mg) and It may be formed of a semi-transmissive conductive material, such as an alloy of silver (Ag).

The second emission layer 340 is formed on the second electrodes 331, 332, and 333. The second emission layer 340 may include a hole transporting layer, a light emitting layer, and an electron transporting layer. In this case, in the second light emitting layer 340, holes and electrons move to the light emitting layer through the hole transport layer and the electron transport layer, respectively, and are combined with each other in the light emitting layer to emit light in a predetermined color.

The second emission layer 340 may be any one of a red emission layer that emits red light, a green emission layer that emits green light, a blue emission layer that emits blue light, and a yellow emission layer that emits yellow light, but is not limited thereto. .

However, the second emission layer 340 may emit light having a different color from the first emission layers 321, 322, and 323. When the first light emitting layers 321, 322, and 323 are light emitting layers that emit light of a first color, the second light emitting layer 340 may be light emitting layers that emit light of a second color different from the first color. For example, the first emission layers 321, 322, and 323 may be yellow emission layers that emit yellow light, and the second emission layers 340 may be blue emission layers that emit blue light.

Unlike the first emission layers 321, 322, and 323, the second emission layer 340 is connected to each other between the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3. The second emission layer 340 may be formed while partially filling the space between the occlusion patterns 281, 282, and 283 and the second electrodes 331, 332, and 333. At this time, an air gap AG may be formed in a space where the second emission layer 340 is not filled between the occlusion patterns 281, 282, 283 and the second electrodes 331, 332, 333.

The third electrode 350 is formed on the second emission layer 340. The third electrode 350 may be made of a transparent metal material, a semi-transmissive metal material, or a metal material having high reflectance. When the display device 100 is made of a lower emission method, the third electrode 350 is a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), and an Ag alloy. And, it may be formed of a metal material having a high reflectance, such as a laminated structure of ITO and Ag alloy (ITO / Ag alloy / ITO). The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). When the display device 100 is made of an upper emission method, the third electrode 350 is a transparent conductive material (TCO, transparent conductive material) such as ITO, IZO, or magnesium (Mg), silver ( Ag), or a semi-transmissive conductive material, such as an alloy of magnesium (Mg) and silver (Ag). The third electrode 350 may be a cathode electrode.

The display device 100 according to the first exemplary embodiment of the present invention is characterized in that only one of the first light emitting layers 321, 322, and 323 and the second light emitting layer 340 is emitted from each of the sub pixels P1, P2, and P3. do.

More specifically, the first light emitting layer 321 emits light in the first sub-pixel P1. In the first sub-pixel P1, since the second electrode 331 is connected to the first power line 241, the second electrode 331 and the second electrode 331 are formed through the first power line 241 and the auxiliary power line 360. The three electrodes 350 are electrically connected. When a low potential voltage is applied to the third electrode 350, the second electrode 331 of the first sub-pixel P1 is applied with the same low potential voltage as the third electrode 350. Accordingly, in the first sub-pixel P1, the second emission layer 340 provided between the second electrode 331 and the third electrode 350 does not emit light.

Meanwhile, when the first high potential voltage is applied to the first electrode 311 and the low potential voltage is applied to the second electrode 331 of the first sub-pixel P1, the first electrode 311 and the second electrode The first light emitting layer 321 provided between 331 emits light at a predetermined brightness according to a predetermined current.

The first emission layer 322 emits light in the second sub-pixel P2. In the second sub-pixel P2, since the second electrode 332 is connected to the second power line 242, the second electrode 332 and the second power line 242 and the second power line 360 are connected to the second sub-pixel P332. The three electrodes 350 are electrically connected. When a low potential voltage is applied to the third electrode 350, the second electrode 332 of the second sub-pixel P2 is applied with the same low potential voltage as the third electrode 350. Accordingly, in the second sub-pixel P2, the second emission layer 340 provided between the second electrode 332 and the third electrode 350 does not emit light.

Meanwhile, when the second high potential voltage is applied to the first electrode 312 and the low potential voltage is applied to the second electrode 332 of the second sub-pixel P2, the first electrode 312 and the second electrode The first light emitting layer 322 provided between 332 emits light at a predetermined brightness according to a predetermined current.

That is, both of the first sub-pixel P1 and the second sub-pixel P2 emit light of the same color in the first emission layers 321 and 322. The display device according to the first exemplary embodiment of the present invention may further include a color filter (not shown) to emit light of different colors from the first sub-pixel P1 and the second sub-pixel P2. .

The color filter (not shown) may include a first color filter disposed to correspond to the first sub-pixel P1 and a second color filter disposed to correspond to the second sub-pixel P2. The first color filter and the second color filter can transmit light of different colors.

For example, the first emission layers 321, 322, and 323 may be yellow emission layers that emit yellow light. The first color filter may be a red color filter that transmits red light, and the second color filter may be a green color filter that transmits green light. Accordingly, the first sub-pixel P1 may emit red light, and the second sub-pixel P2 may emit green light.

The color filter may be disposed under the first electrodes 311 and 312 or on the third electrode 350 according to the light emission method of the display device 100. When the display device 100 is a lower emission type, a color filter may be provided under the first electrodes 311 and 312. When the display device 100 is an upper emission type, a color filter may be provided on the third electrode 350.

The second emission layer 340 emits light in the third sub-pixel P3. Since the first electrode 310 is not formed in the third sub-pixel P3, the first emission layer 323 does not emit light.

Meanwhile, in the third sub-pixel P3, the second electrode 333 is connected to the second connection electrode 250 to receive a third high potential voltage. When a low potential voltage is applied to the third electrode 350, the second light emitting layer 340 provided between the second electrode 333 and the third electrode 350 emits light at a predetermined brightness according to a predetermined current.

For example, the third sub-pixel P3 may be a blue light emitting layer that emits blue light. In this case, the display device 100 may implement a blue sub-pixel without having a separate color filter at a position corresponding to the third sub-pixel P3.

As described above, the display device 100 according to the first embodiment of the present invention emits only the first emission layers 321, 322, and 323 from the first sub-pixel P1 and the second sub-pixel P2, Only the second emission layer 340 may emit light in the third sub-pixel P3. For this reason, the display device 100 according to the first embodiment of the present invention significantly reduces power consumption compared to emitting all of the first emission layers 321, 322 and 323 and the second emission layers 340 in all sub-pixels. Can be reduced.

In addition, the display device 100 according to the first embodiment of the present invention, the first light emitting layer (321, 322, 323) and the second light emitting layer 340 on the sub-pixels (P1, P2, P3) on the front without a mask To form. Accordingly, the display device 100 according to the first embodiment of the present invention can solve a problem of forming different emission layers for each sub-pixel P1, P2, P3 by using a mask.

In addition, in the display device 100 according to the first embodiment of the present invention, the second electrodes 331, 332, and 333 include sub-pixels P1, P2, and P3 using occlusion patterns 281, 282, and 283. It can be cut off between. The display device 100 according to the first embodiment of the present invention forms the occlusion patterns 281, 282, 283, and the first emission layer on the first substrate 111 on which the occlusion patterns 281, 282, 283 are formed. (321, 322, 323) and the second electrode (331, 332, 333) is formed on the front surface without a mask. The first emission layers 321, 322, and 323 and the second electrodes 331, 332, and 333 are cut off between the sub-pixels P1, P2, and P3 by the blocking patterns 281, 282, 283. Particularly, the second electrodes 331, 332, and 333 have a first power line 241, a second power line 242, and a second under the protrusions 281a, 282a, and 283a of the obstruction patterns 281, 282, and 283a. 2 It is connected to any one of the connection electrodes 250.

Referring to FIG. 9, in the display device 100 according to the first exemplary embodiment of the present invention, the second electrodes 331, 332, and 333 are disconnected between the sub-pixels P1, P2, and P3, and the second emission layer The thickness T1 of the second insulating layer 260 may be designed so that the 340 can be connected without being disconnected between the sub-pixels P1, P2, and P3. At this time, the thickness T1 of the second insulating layer 260 includes the protrusions 281a, 282a, and 283a of the obstruction patterns 281, 282, and 283, the first power line 241, the second power line 242, and the second 2 may correspond to a separation distance from any one of the connection electrodes 250.

The thickness T1 of the second insulating layer 260 may be designed to be larger than the thickness T3 of the first light emitting layers 321, 322, and 323 and the thickness T2 of the second electrodes 331, 332, 333. Can be. Accordingly, the display device 100 according to the first embodiment of the present invention can prevent the second electrodes 331, 332, and 333 from being connected to each other between the sub-pixels P1, P2, and P3.

The thickness T1 of the second insulating layer 260 is the thickness T3 of the first light emitting layers 321, 322, and 323, the thickness T2 of the second electrodes 331, 332, 333, and the second light emitting layer 340 ) Can be designed to be smaller than the combined thickness (T4). Accordingly, the display device 100 according to the first embodiment of the present invention can prevent the second light emitting layer 340 from being disconnected between the sub-pixels P1, P2, and P3.

Meanwhile, in the display device 100 according to the first embodiment of the present invention, the length L1 of the protrusions 281a, 282a, and 283a of the obstruction patterns 281, 282, and 283a may be appropriately designed. If the length L1 of the protrusions 281a, 282a, and 283a of the obstruction patterns 281, 282, 283 is too long, it may be struck down due to the weight. In this case, a space sufficient to form the first light emitting layers 321, 322, 323 and the second electrodes 331, 332, 333 under the protrusions 281a, 282a, 283a of the obstruction patterns 281, 282, 283. This may not be secured.

On the other hand, if the length L1 of the protrusions 281a, 282a, 283a of the obstruction patterns 281, 282, 283 is too short, the second electrodes 331, 332, 333, the first power line 241, the first The contact area with any one of the 2 power lines 242 and the second connection electrode 250 may be reduced. In this case, a resistance may increase between any one of the second electrodes 331, 332, and 333 and the first power line 241, the second power line 242, and the second connection electrode 250.

Also, the display device 100 according to the first embodiment of the present invention does not form the first electrode 310 in the third sub-pixel P3. Accordingly, the display device 100 according to the first embodiment of the present invention can improve transmittance in the third sub-pixel P3. Particularly, when the display device 100 is made of a lower emission method, since the light emitted from the second emission layer 340 does not need to pass through the first electrodes 311 and 312 in the third sub-pixel P3, the light efficiency is improved. Improve it.

Meanwhile, FIG. 4 illustrates that the planarization layer 270 is formed on all of the first to third sub-pixels P1, P2, and P3, but is not limited thereto. In another embodiment, the planarization layer 270 may be formed only on the first and second sub-pixels P1 and P2 as illustrated in FIG. 12. That is, the display device 100 according to the modified embodiment of the present invention may not form the planarization layer 270 in the third sub-pixel P3. Accordingly, the display device 100 according to the modified embodiment of the present invention can further improve the transmittance in the third sub-pixel P3. Particularly, when the display device 100 is formed in a lower emission method, light emitted from the second emission layer 340 passes through the first electrodes 311 and 312 and the planarization layer 270 in the third sub-pixel P3. Since it is not necessary, light loss can be reduced and light efficiency can be further improved.

Furthermore, in FIG. 4, the second insulating layer 260 is formed on all of the first to third sub-pixels P1, P2, and P3, but is not limited thereto. In another embodiment, the insulating layer 260 and the planarization layer 270 may be formed only in the first and second sub-pixels P1 and P2 as illustrated in FIG. 13. That is, the display device 100 according to another modified embodiment of the present invention may not form the insulating layer 260 and the planarization layer 270 in the third sub-pixel P3. Accordingly, the display device 100 according to another modified embodiment of the present invention may maximize transmittance in the third sub-pixel P3. When the display device 100 is made of a lower emission method, the light emitted from the second emission layer 340 may include first electrodes 311 and 312, an insulating layer 260, and a planarization layer 270 in the third sub-pixel P3. ), it is possible to minimize light loss and maximize light efficiency.

In addition, the display device 100 according to the first embodiment of the present invention does not form the bank 315 in the third sub-pixel P3. Since the first electrode 310 is not formed in the third sub-pixel P1, the bank 315 covering the end of the first electrode 310 may also not be formed. Accordingly, the display device 100 according to the first exemplary embodiment of the present invention has a light emission area EA larger than the first sub-pixel P1 and the second sub-pixel P2 in the third sub-pixel P3. Can be. That is, the third sub-pixel P3 may have a larger emission area and aperture ratio than the first sub-pixel P1 and the second sub-pixel P2.

Example 2

14 is a plan view schematically showing a first substrate of a display panel according to a second embodiment of the present invention, FIG. 15 is a cross-sectional view showing an example of V-V of FIG. 14, FIG. 16 is a first sub-pixel, and This is a plan view schematically showing an example of the second sub-pixel.

14 to 16, the display panel 110 according to the second exemplary embodiment of the present invention includes a first substrate 111, a light blocking layer 210, a first insulating layer 220, a thin film transistor 230, The first connection electrode 241, 242, 360, the second connection electrode 250, the second insulating film 260, the planarization film 270, the obscuring patterns 281, 282, 283, the first electrodes 311, 312 ), the bank 315, the first emission layers 321, 322, and 323, the second electrodes 331, 332, and 333, the second emission layer 340, and the third electrode 350.

The display panel 110 according to the second embodiment of the present invention is illustrated in FIGS. 3 to 11 in that the first power line 241 and the second power line 242 of the first connection electrode are integrally formed. There is a difference from the display panel 110 according to the first embodiment of the present invention. Accordingly, the display panel 110 according to the second embodiment of the present invention is shown in FIGS. 3 to 11 except for the first connection electrodes 241, 242 and 360 and the occlusion patterns 281, 282 and 283. It is substantially the same as the components of the display panel 110 according to the first embodiment of the present invention. Hereinafter, the first substrate 111, the light blocking layer 210, the first insulating film 220, the thin film transistor 230, the second insulating film 260 of the display panel 110 according to the second embodiment of the present invention, Planarization film 270, second connection electrode 250, first electrodes 311, 312, bank 315, first light emitting layers 321, 322, 323, second electrodes 331, 332, 333, A detailed description of the second light emitting layer 340 and the third electrode 350 will be omitted.

The first connection electrodes 241, 242, and 360 are formed on the first substrate 111.

The first connection electrodes 241, 242, and 360 electrically connect the second electrodes 331, 332 and the third electrode 350 in each of the first sub-pixel P1 and the second sub-pixel P2. More specifically, the first connection electrodes 241, 242, and 360 may include a first power line 241, a second power line 242, and an auxiliary power line 360.

The auxiliary power line 360 is formed to extend in the first direction (X-axis direction) in the non-display area NDA. A portion of the auxiliary power line 360 is exposed without being covered by the first insulating layer 220, the second insulating layer 260, and the planarization layer 270, and may be connected to the third electrode 350 in the exposed region. .

The first power line 241 is disposed between the first sub-pixel P1 and the second sub-pixel P2 in the display area DA, and is connected to the second electrode 331 of the first sub-pixel P1. do. The second power line 242 is disposed between the first sub-pixel P1 and the second sub-pixel P2 in the display area DA, and is connected to the second electrode 332 of the second sub-pixel P2. do. In this case, the display device 100 according to the second embodiment of the present invention is characterized in that the first power line 241 and the second power line 242 are integrally formed.

The first power line 241 and the second power line 242 may be formed to extend in the second direction (Y-axis direction) in the display area DA. One end of the first power line 241 and the second power line 242 is connected to the auxiliary power line 360. In this case, the first power line 241 and the second power line 242 may be connected to the auxiliary power line 360 through a contact hole, but are not limited thereto.

The first power line 241 and the second power line 242 may be formed of the same material in the same layer as any one of the active layer, gate electrode, source electrode, and drain electrode of the thin film transistor 230.

As described above, the first sub-pixel P1 includes the second electrode 331 and the third electrode 350 through the first power line 241, the second power line 242, and the auxiliary power line 360. It is electrically connected. That is, when a low potential voltage is applied to the third electrode 350, the second electrode 331 of the first sub-pixel P1 is applied with the same low potential voltage as the third electrode 350.

The second sub-pixel P2 is electrically connected to the second electrode 332 and the third electrode 350 through the first power line 241, the second power line 242, and the auxiliary power line 360. . That is, when a low potential voltage is applied to the third electrode 350, the second electrode 332 of the second sub-pixel P2 is applied with the same low potential voltage as the third electrode 350.

The obstruction patterns 281, 282, and 283 are formed to cover a part of the opening regions OA1, OA2, and OA3 of the second insulating layer 260 on the second insulating layer 260. The occlusion patterns 281, 282, and 283 include a first occlusion pattern 281, a second occlusion pattern 282, and a third occlusion pattern 283. Since the third obstruction pattern 283 is substantially the same as the third obstruction pattern 283 of the display panel 110 according to the first embodiment of the present invention illustrated in FIGS. 3 to 11, a detailed description thereof will be omitted. .

The first occlusion pattern 281 is provided between the first sub-pixel P1 and the second sub-pixel P2. In particular, the first obstruction pattern 281 is between the first opening area OA1 exposing a portion of the first power line 241 and the second opening area OA2 exposing a portion of the second power line 242. It is formed on the second insulating film 260 formed in.

The first obstruction pattern 281 includes a protrusion 281a protruding to cover a part of the first opening area OA1. At this time, the protrusion 281a of the first obstruction pattern 281 is spaced apart from the first power line 241 to form a space between the first power line 241.

In the first obstruction pattern 281, the protrusion 281a may protrude in a direction from the second sub-pixel P2 toward the first sub-pixel P1. Accordingly, a portion of the first opening area OA1 adjacent to the second sub-pixel P2 is covered by the first blocking pattern 281, and the first power line 241 is also the first blocking pattern 281. It is covered. The remaining area of the first opening area OA1 adjacent to the first sub-pixel P1 still exposes the first power line 241.

The first obstruction pattern 281 may be formed along the first power line 241 like the first opening area OA1. In this case, the first obstruction pattern 281 may be formed as a plurality of patterns having a predetermined length in the second direction (Y-axis direction) on the first power line 241, but is not limited thereto. The first obstruction pattern 281 may be formed as one line pattern extending in the second direction (Y-axis direction) on one first power line 241.

Meanwhile, the first covering pattern 281 may be formed of the same material in the same layer as the first electrodes 311 and 312, but is not limited thereto.

The second occlusion pattern 282 is provided between the first sub-pixel P1 and the second sub-pixel P2. In particular, the second obstruction pattern 282 is between the first opening area OA1 exposing a portion of the first power line 241 and the second opening area OA2 exposing a portion of the second power line 242. It is formed on the second insulating film 260 formed in. In this case, in the display device 100 according to the second embodiment of the present invention, the first obstruction pattern 281 and the second obstruction pattern 282 may be integrally formed.

The second obstruction pattern 282 includes a protrusion 282a protruding to cover a portion of the second opening area OA2. At this time, the protrusion 282a of the second obstruction pattern 282 is spaced apart from the second power line 242 to form a space between the second power line 242.

The second obstruction pattern 282 may protrude in a direction in which the protrusion 282a is directed from the first sub-pixel P1 to the second sub-pixel P2. Accordingly, a portion of the second opening area OA2 adjacent to the first sub-pixel P1 is covered by the second blocking pattern 282, and the second power line 242 is also the second blocking pattern 282. It is covered. The remaining area of the second opening area OA2 adjacent to the second sub-pixel P2 still exposes the second power line 242.

The second obstruction pattern 282 may be formed along the second power line 242 like the second opening area OA2. At this time, the second obstruction pattern 282 may be formed as a plurality of patterns having a predetermined length in the second direction (Y-axis direction) on the second power line 242, but is not limited thereto. The second obstruction pattern 282 may be formed as one line pattern extending in the second direction (Y-axis direction) on one second power line 242.

Meanwhile, the second covering pattern 282 may be formed of the same material in the same layer as the first electrodes 311 and 312, but is not limited thereto.

17 is a flowchart illustrating a method of manufacturing a display device according to a first embodiment of the present invention, and FIGS. 18A to 18J are cross-sectional views illustrating a method of manufacturing a display device according to a first embodiment of the present invention. .

First, as shown in FIG. 18A, first to third thin film transistors 230, first connection electrodes 241, 242 and 360 and second connection electrodes 250 are formed on the first substrate 111 (S1701 ). .

More specifically, the light blocking layer 210 is formed on the first substrate 111. The light blocking layer 210 is for blocking external light incident on the active layers of the first to third thin film transistors 230 corresponding to the first to third sub pixels P1, P2, and P3, respectively. The third to third thin film transistors 230 are formed at positions corresponding to the active layers. The light blocking layer 210 may be formed of a metal material. When the light blocking layer 210 is formed of a metal material, the auxiliary power line 360 may be formed of the same material on the same layer as the light blocking layer 210 on the first substrate 111.

Then, the first insulating film 220 is formed on the light blocking layer 210. The first insulating film 220 may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or multiple films thereof.

Then, the first to third thin film transistors 230, the first power line 241, the second power line 242, and the second connection electrode 250 are formed on the first insulating layer 220.

An active layer is formed on the first insulating layer 220. The active layer may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material.

A gate insulating film may be formed on the active layer. The gate insulating film may be formed of an inorganic film, for example, a silicon oxide film, a silicon nitride film, or multiple films thereof.

A gate electrode may be formed on the gate insulating layer. The gate electrode may be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), or alloys thereof. It may be made of a single layer or multiple layers, but is not limited thereto.

An interlayer insulating film may be formed on the gate electrode. The interlayer insulating film may be formed of an inorganic film, for example, a silicon oxide film, a silicon nitride film, or multiple films thereof.

A source electrode and a drain electrode may be formed on the interlayer insulating film. Each of the source electrode and the drain electrode may be connected to the active layer through a contact hole passing through the gate insulating layer and the interlayer insulating layer. Each of the source electrode and the drain electrode is one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), or It may be a single layer or multiple layers made of these alloys, but is not limited thereto.

Meanwhile, the first power line 241 and the second power line 242 may be formed of the same material on the same layer as the source electrode and the drain electrode.

Also, the second connection electrode 250 may be a source electrode or a drain electrode of the third thin film transistor 230.

Next, a second insulating layer 260 is formed as shown in FIG. 18B (S1702).

More specifically, the second insulating layer 260 is formed on the first to third thin film transistors 230, the first connection electrodes 241, 242 and 360 and the second connection electrodes 250.

The second insulating layer 260 may be formed with a contact hole exposing a portion of the source electrode or the drain electrode of the first and second thin film transistors 230, but is not limited thereto. The contact hole may be formed through a subsequent process.

The second insulating film 260 may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or multiple films thereof, but is not limited thereto.

Next, a planarization film 270 is formed as shown in FIG. 18C (S1703).

More specifically, a planarization layer 270 is formed on the second insulating layer 260. The planarization layer 270 is formed on the second insulating layer 260 to planarize the step due to the first to third thin film transistors 230. The planarization layer 270 is patterned so that a portion of the second insulating layer 260 disposed in the region where the first power line 241, the second power line 242 and the second connection electrode 250 are formed is exposed. Can be.

The planarization layer 270 may be formed with a contact hole exposing a portion of the source electrode or the drain electrode of the first and second thin film transistors 230, but is not limited thereto. The contact hole may be formed through a subsequent process.

The planarization film 270 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. have.

Next, as illustrated in FIG. 18D, first electrodes 311 and 312 and occlusion patterns 281, 282 and 283 are formed (S1704 ).

More specifically, the first electrodes 311 and 312 are formed on each of the first sub-pixel P1 and the second sub-pixel P2 on the planarization layer 270. The first electrodes 311 and 312 are connected to the source electrode or the drain electrode of the first and second thin film transistors 230 through contact holes.

The first electrodes 311 and 312 may be made of a transparent metal material, a semi-transmissive metal material, or a metal material having high reflectance. When the display device 100 is made of a lower emission method, the first electrodes 311 and 312 are transparent metal materials such as ITO and IZO that can transmit light (TCO, Transparent Conductive Material), or magnesium (Mg), It may be formed of a semi-transmissive conductive material such as silver (Ag) or an alloy of magnesium (Mg) and silver (Ag). When the display device 100 is made of an upper emission method, the first electrodes 311 and 312 are a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), Ag alloy, and Ag alloy and ITO laminated structure (ITO / Ag alloy / ITO) can be formed of a high reflectivity metal material. The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). The first electrodes 311 and 312 may be anode electrodes.

The obstruction patterns 281, 282 and 283 are formed on the planarization layer 270 to be spaced apart from the first electrodes 311 and 312. The obstruction patterns 281, 282, and 283 are also formed on a portion of the second insulating layer 260 exposed without being covered by the planarization layer 270.

The obstruction patterns 281, 282, and 283 may be simultaneously formed of the same material as the first electrodes 311 and 312.

Next, a bank 315 is formed as shown in FIG. 18E (S1705).

More specifically, the banks 315 are formed to cover the ends of each of the first electrodes 311 and 312. The bank 315 includes the second insulating layer 260 and the covering patterns 281, 282, and 283 disposed in the region where the first power line 241, the second power line 242, and the second connection electrode 250 are formed. A pattern may be formed so that a portion of the can be exposed. Further, the bank 315 is not formed in the third sub-pixel P3.

Next, as shown in FIG. 18F, opening regions OA1, OA2, and OA3 are formed in the second insulating layer 260 (S1706).

More specifically, the etching regions are performed to form the opening regions OA1, OA2, and OA3 in the second insulating layer 260. At this time, the etching process may be a wet etch process, and the second insulating layer 260 may be etched, but an etchant that may not etch the masking patterns 281, 282, and 283 may be used. Accordingly, the undercut structure may be formed while the cover patterns 281, 282, and 283 are not etched, but only the exposed second insulating layer 260 is etched.

The second insulating layer 260 includes a first opening region OA1 exposing a portion of the first power line 241 through an etching process, and a second opening region OA2 exposing a portion of the second power line 242. , And a third opening area OA3 exposing a portion of the second connection electrode 250 may be formed.

Next, as shown in 18g, the first light emitting layers 321, 322, and 323 are formed (S1707).

More specifically, the first light emitting layers 321, 322, and 323 are formed on the first electrodes 311, 312 and the blocking patterns 281, 282, 283. The first light emitting layers 321, 322, and 323 may be formed by a deposition process or a solution process. When the first emission layers 321, 322, and 323 are formed by a deposition process, they may be formed using evaporation.

The first emission layers 321, 322, and 323 are cut off between the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 by the occlusion patterns 281, 282, 283. . The first light emitting layers 321, 322, and 323 may be cut off on the blocking patterns 281, 282, 283. Also, the first light emitting layers 321, 322, and 323 may be introduced into the space formed under the obstruction patterns 281, 282, 283 and be formed under the obstruction patterns 281, 282, 283.

The first emission layers 321, 322, and 323 may be any one of a red emission layer that emits red light, a green emission layer that emits green light, a blue emission layer that emits blue light, and a yellow emission layer that emits yellow light. It is not limited to this.

Next, as shown in FIG. 18H, second electrodes 331, 332, and 333 are formed (S1708).

More specifically, the second electrodes 331, 332, and 333 are formed on the first light emitting layers 321, 322, and 323. The second electrodes 331, 332, and 333 are disconnected between the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 by the occlusion patterns 281, 282, 283. . The second electrodes 331, 332, and 333 may be cut off on the obstruction patterns 281, 282, and 283. Also, the second electrodes 331, 332, and 333 may be introduced into the space formed under the obstruction patterns 281, 282, and 283 to be formed under the obstruction patterns 281, 282, and 283.

The second electrodes 331, 332, and 333 may be formed by physical vapor deposition, such as sputtering. A film formed by a physical vapor deposition method such as sputtering has excellent step coverage characteristics. Therefore, the second electrodes 331, 332, and 333 may be formed with a larger area than the first light emitting layers 321, 322, and 323 formed by using evaporation. Accordingly, the second electrodes 331, 332, and 333 may have any one of the first power line 241, the second power line 242, and the second connection electrode 250 under the obstruction patterns 281, 282, and 283. It can be connected to one.

The second electrode (331, 332, 333) is a transparent metal material (TCO, Transparent Conductive Material), such as ITO, IZO that can transmit light, or magnesium (Mg), silver (Ag), or magnesium (Mg) and It may be formed of a semi-transmissive conductive material, such as an alloy of silver (Ag).

Next, as shown in Figure 18i, to form a second light emitting layer 340 (S1709).

More specifically, the second light emitting layer 340 is formed on the second electrodes 331, 332, and 333. The second emission layer 340 may be formed by a deposition process or a solution process. When the second emission layer 340 is formed by a deposition process, it may be formed using an evaporation method.

The second emission layer 340 is connected to each other between the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3. The second emission layer 340 may be formed while partially filling the space between the occlusion patterns 281, 282, and 283 and the second electrodes 331, 332, and 333. At this time, an air gap AG may be formed in a space where the second emission layer 340 is not filled between the occlusion patterns 281, 282, 283 and the second electrodes 331, 332, 333.

The second emission layer 340 may be any one of a red emission layer that emits red light, a green emission layer that emits green light, a blue emission layer that emits blue light, and a yellow emission layer that emits yellow light, but is not limited thereto. .

However, the second emission layer 340 may emit light having a different color from the first emission layers 321, 322, and 323. When the first light emitting layers 321, 322, and 323 are light emitting layers that emit light of a first color, the second light emitting layer 340 may be light emitting layers that emit light of a second color different from the first color. For example, the first emission layers 321, 322, and 323 may be yellow emission layers that emit yellow light, and the second emission layers 340 may be blue emission layers that emit blue light.

Next, a third electrode 350 is formed as shown in FIG. 18J (S1710).

More specifically, the third electrode 350 is formed on the second emission layer 340. The third electrode 350 may be formed by physical vapor deposition, such as sputtering. Alternatively, the third electrode 350 may be formed using evaporation.

The third electrode 350 may be made of a transparent metal material, a semi-transmissive metal material, or a metal material having high reflectance. When the display device 100 is made of a lower emission method, the third electrode 350 is a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), and an Ag alloy. And, it may be formed of a metal material having a high reflectance, such as a laminated structure of ITO and Ag alloy (ITO / Ag alloy / ITO). The Ag alloy may be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). When the display device 100 is made of an upper emission method, the third electrode 350 is a transparent conductive material (TCO, transparent conductive material) such as ITO, IZO, or magnesium (Mg), silver ( Ag), or a semi-transmissive conductive material, such as an alloy of magnesium (Mg) and silver (Ag). The third electrode 350 may be a cathode electrode.

19A to 19C relate to a display device according to another exemplary embodiment of the present invention, which relates to a head mounted display (HMD) device. 19A is a schematic perspective view, FIG. 19B is a schematic plan view of a VR (Virtual Reality) structure, and FIG. 19C is a schematic cross-sectional view of an Augmented Reality (AR) structure.

19A, the head mounted display device according to the present invention includes a storage case 10 and a head mounting band 30.

The storage case 10 houses components such as a display device, a lens array, and an eyepiece therein.

The head mounting band 30 is fixed to the storage case 10. The head mounting band 30 is illustrated to be formed so as to surround the top and both sides of the user's head, but is not limited thereto. The head mounting band 30 is for fixing the head mounted display to the user's head, and may be replaced with a frame or a helmet-shaped structure.

As can be seen in FIG. 19B, a head mounted display device having a VR (Virtual Reality) structure according to the present invention includes a left eye display 12 and a right eye display 11, a lens array 13, and a left eye eyepiece ( 20a) and the right-eye eyepiece 20b.

The left-eye display device 12, the right-eye display device 11, the lens array 13, and the left-eye eyepiece 20a and the right-eye eyepiece 20b are housed in the aforementioned storage case 10.

The display device 12 for the left eye and the display device 11 for the right eye can display the same image, in which case the user can watch the 2D image. Alternatively, the left-eye display device 12 may display a left-eye image and the right-eye display device 11 may display a right-eye image, in which case the user can view a stereoscopic image. Each of the display device 12 for the left eye and the display device 11 for the right eye may be formed of the display devices according to FIGS. 1 to 16 described above. At this time, in FIG. 1 to FIG. 16, an upper portion corresponding to a surface on which an image is displayed, for example, a color filter layer (not shown) faces the lens array 13.

The lens array 13 may be provided between the left eyepiece lens 20a and the left eye display device 12 while being spaced apart from each of the left eyepiece lens 20a and the left eye display device 12. That is, the lens array 13 may be positioned in front of the left eyepiece lens 20a and behind the left eye display device 12. Further, the lens array 13 may be provided between the right-eye eye lens 20b and the right-eye display device 11 while being spaced apart from each of the right-eye eye lens 20b and the right-eye display device 11. That is, the lens array 13 may be positioned in front of the right-eye eyepiece lens 20b and behind the right-eye display device 11.

The lens array 13 may be a micro lens array. The lens array 13 may be replaced with a pin hole array. The image displayed on the display device 12 for the left eye or the display device 11 for the right eye due to the lens array 13 may be enlarged to the user.

The left eye LE of the user may be located in the left eyepiece 20a, and the right eye RE of the user may be located in the right eyepiece 20b.

As can be seen in FIG. 19C, the head mounted display device of the AR (Augmented Reality) structure according to the present invention includes a left eye display device 12, a lens array 13, a left eye lens 20a, and a transmissive reflector 14 , And a transmission window (15). For convenience, only the left eye configuration is illustrated in FIG. 19C, and the right eye configuration is the same as the left eye configuration.

The left-eye display device 12, the lens array 13, the left-eye eyepiece 20a, the transmissive reflecting portion 14, and the transmissive window 15 are housed in the aforementioned storage case 10.

The display device 12 for the left eye may be disposed on one side, for example, the upper side of the transmissive reflector 14 without covering the transmissive window 15. Accordingly, the left eye display device 12 may provide an image to the transmissive reflector 14 without obscuring the external background seen through the transmissive window 15.

The left eye display device 12 may be formed of the display devices according to FIGS. 1 to 16 described above. At this time, in FIG. 1 to FIG. 16, an upper portion corresponding to a surface on which an image is displayed, for example, a color filter (not shown) faces the transmissive reflector 14.

The lens array 13 may be provided between the left eyepiece lens 20a and the transmissive reflector 14.

The left eye of the user is located in the left eye eyepiece 20a.

The transmissive reflector 14 is disposed between the lens array 13 and the transmissive window 15. The transmissive reflector 14 may include a reflective surface 14a that transmits a portion of light and reflects another portion of light. The reflective surface 14a is formed such that an image displayed on the left eye display device 12 proceeds to the lens array 13. Accordingly, the user can view both the external background and the image displayed by the left eye display device 12 through the transparent layer 15. That is, since the user can view the virtual image and the background of the reality as a single image, augmented reality (AR) can be implemented.

The transmissive layer 15 is disposed in front of the transmissive reflector 14.

The embodiments of the present invention have been described in more detail with reference to the accompanying drawings, but the present invention is not necessarily limited to these embodiments, and may be variously modified without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of protection of the present invention should be interpreted by the claims, and all technical spirits within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

100: display device 110: display panel
111: first substrate 112: second substrate
140: source drive IC 150: flexible film
160: circuit board 170: timing control
210: light shielding layer 220: first insulating film
230: thin film transistor 241: first power line
242: second power line 250: second connection electrode
260: second insulating film 270: planarization film
281, 282, 283: occlusion pattern 311, 312, 313: first electrode
321, 322, 323: first light emitting layer 331, 332, 333: second electrode
340: second light emitting layer 350: third electrode

Claims (32)

A substrate having a first sub-pixel and a second sub-pixel;
A first emission layer provided on the substrate to emit light of a first color;
A second emission layer provided on the first emission layer to emit light of a second color;
A first electrode provided between the substrate and the first emission layer in the first sub-pixel;
A second electrode provided between the first emission layer and the second emission layer in each of the first sub-pixel and the second sub-pixel; And
It includes a third electrode provided on the second light emitting layer,
The second electrode of the first sub-pixel is a display device that is electrically connected to the third electrode. According to claim 1,
The second electrode is a display device that is disconnected between the first sub-pixel and the second sub-pixel. According to claim 1,
In the first sub-pixel, the first light-emitting layer provided between the first electrode and the second electrode emits light, and in the second sub-pixel, a second light-emitting layer provided between the second electrode and the third electrode is provided. A light emitting display device. According to claim 3,
The second emission layer is a display device that emits blue light. According to claim 1,
A first thin film transistor provided in the first sub-pixel on the substrate; And
Further comprising a second thin film transistor provided on the second sub-pixel on the substrate,
The first electrode provided in the first sub-pixel is connected to the first thin film transistor to receive a first voltage,
A second electrode provided in the second sub-pixel is connected to the second thin film transistor to receive a second voltage. According to claim 1,
The first electrode is a display device formed only on the first sub-pixel among the first sub-pixel and the second sub-pixel. According to claim 1,
A display device provided only on the first sub-pixel among the first sub-pixel and the second sub-pixel, and further comprising a patterned bank covering an end of the first electrode. According to claim 1,
The first light emitting layer is a display device that is disconnected between the first sub-pixel and the second sub-pixel. According to claim 1,
The second emission layer is a display device connected between the first sub-pixel and the second sub-pixel. According to claim 1,
The third electrode is a display device connected between the first sub-pixel and the second sub-pixel. According to claim 1,
And a first connection electrode electrically connecting the second electrode of the first sub-pixel and the third electrode of the first sub-pixel. The method of claim 11, wherein the first connection electrode,
A first power line connected to a second electrode of the first sub-pixel; And
And an auxiliary power line connected to each of the first power line and the third electrode of the first sub-pixel. The method of claim 12,
The substrate includes a display area in which the first sub-pixel and the second sub-pixel are disposed and a non-display area surrounding the display area,
The auxiliary power line is disposed in the non-display area,
The first power line is disposed in the display area to connect to the second electrode of the first sub-pixel, and extends from the display area to the auxiliary power line disposed in the non-display area, one end of which is connected to the auxiliary power line. Display device to be connected. The method of claim 13,
An active layer, a gate electrode, a source electrode and a drain electrode, and further comprising a first thin film transistor that supplies a first voltage to the first sub-pixel,
The first power line is a display device formed apart from the same layer as one of the active layer, the gate electrode, the source electrode, and the drain electrode constituting the first thin film transistor. The method of claim 14,
The first thin film transistor and a first insulating layer provided on the first power line, and further including a first opening region exposing a portion of the first power line, are further included,
The second electrode of the first sub-pixel is connected to the first power line in the first opening area. The method of claim 15,
The display device further includes a first masking pattern provided on the first insulating layer and having a protrusion formed to cover a portion of the first opening region. The method of claim 16,
The first obscuration pattern is a display device formed of the same material as the first electrode at the same time. The method of claim 17,
The first obstruction pattern is a display device spaced apart from the first electrode. The method of claim 16,
The first obstruction pattern is a display device formed along the first power line in the display area. The method of claim 16,
A display device that connects the second electrode of the first sub-pixel to the first power line under the first occlusion pattern. According to claim 1,
And a second connection electrode electrically connected to the second electrode of the second sub-pixel. The method of claim 21,
The second connection electrode is a display device provided between the first sub-pixel and the second sub-pixel. The method of claim 21,
An active layer, a gate electrode, a source electrode and a drain electrode, and further comprising a second thin film transistor that supplies a second voltage to the second sub-pixel,
The second connection electrode is any one of the source electrode and the drain electrode of the second thin film transistor. The method of claim 23,
The first insulating film is provided on the second connection electrode and has a second opening region exposing a part of the second connection electrode.
A display device that connects the second electrode of the second sub-pixel to the second connection electrode in the second opening area. The method of claim 24,
The display device further includes a second cover pattern provided on the first insulating layer and having a protruding portion formed to cover a portion of the second opening region. The method of claim 25,
The second obscuration pattern is formed of the same material as the first electrode at the same time. The method of claim 25,
The second obscuration pattern is formed to surround the second sub-pixel. The method of claim 25,
The first emission layer is a display device that is disconnected between the first sub-pixel and the second sub-pixel by the second occlusion pattern. The method of claim 25,
The second electrode is a display device that is disconnected between the first sub-pixel and the second sub-pixel by the second occlusion pattern. The method of claim 29,
A display device that connects the second electrode of the second sub-pixel to the second connection electrode under the second occlusion pattern. According to claim 1,
The first sub-pixel and the second sub-pixel have different display areas. The method of claim 31,
A display device in which the second sub-pixel has a larger emission area than the first sub-pixel.

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