KR20200052487A - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of manufacturing a semiconductor device, comprising the following steps of: designing a layout; manufacturing a photomask based on the designed layout; correcting light transmittance of the photomask; and performing a photolithography process by using the photomask to form a pattern on a substrate. The step of correcting light transmittance of the photomask includes the following steps of: generating a light intensity map by photographing light which has passed through the photomask; generating a virtual light intensity map by simulating the layout; and correcting light transmittance of a mask substrate of the photomask by comparing the light intensity map with the virtual light intensity map.

Description

Method for manufacturing a semiconductor device {Method for manufacturing semiconductor device}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a method for correcting light transmittance of a photomask.

Semiconductor devices have been spotlighted as important elements in the electronics industry due to characteristics such as miniaturization, multi-function, and / or low manufacturing cost. The semiconductor elements may be divided into a semiconductor memory element for storing logic data, a semiconductor logic element for processing and processing logic data, and a hybrid semiconductor element including memory elements and logic elements. As the electronics industry is highly developed, the demand for characteristics of semiconductor devices is increasing. For example, there is an increasing demand for high reliability, high speed, and / or multifunctionality for semiconductor devices. In order to meet these requirements, structures in semiconductor devices are becoming more and more complex, and semiconductor devices are becoming more and more highly integrated.

The problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device capable of effectively correcting the light transmittance of a photomask.

A method for manufacturing a semiconductor device according to the concept of the present invention includes designing a layout; Manufacturing a photomask based on the designed layout; Correcting the light transmittance of the photomask; And performing a photolithography process using the photomask, thereby forming a pattern on the substrate. Correcting the light transmittance of the photomask includes: generating a light intensity map by photographing light passing through the photomask; Generating a virtual light intensity map by simulating the layout; And comparing the light intensity map and the virtual light intensity map to correct light transmittance of the mask substrate of the photomask.

According to another concept of the present invention, a method of manufacturing a semiconductor device includes designing a layout; Manufacturing a photomask based on the designed layout; Correcting the light transmittance of the photomask; And performing a photolithography process using the photomask, thereby forming a pattern on the substrate. Correcting the light transmittance of the photomask includes: dividing the layout into a plurality of grid regions; Calculating a light intensity value of each of the lattice regions; And generating a virtual light intensity map based on the light intensity value.

According to another concept of the present invention, a method of manufacturing a semiconductor device includes designing a layout including first and second regions having different pattern densities from each other; Manufacturing a photomask based on the designed layout, the photomask comprising a first portion made based on the first region and a second portion made based on the second region; Photographing light passing through the first portion and the second portion of the photomask, thereby generating a first pixel and a second pixel, respectively; Simulating the first area and the second area of the layout to generate a first virtual pixel and a second virtual pixel, respectively; Comparing the first pixel and the first virtual pixel, and comparing the second pixel and the second virtual pixel to correct light transmittance of the mask substrate of the photomask; And performing a photolithography process using the photomask, thereby forming a pattern on the substrate.

In the method for manufacturing a semiconductor device according to the present invention, a process defect that may occur in a photolithography process can be prevented by using a method of correcting light transmittance of a photomask. In the method of correcting the light transmittance of the photomask, the mask substrate may be corrected in consideration of only factors that cause a difference in light transmittance by the mask substrate.

1 is a flowchart illustrating a method of designing and manufacturing a semiconductor device according to embodiments of the present invention.
2 is a conceptual diagram showing a photolithography system using a photomask manufactured according to embodiments of the present invention.
3 is a plan view illustrating a reticle including a photomask according to embodiments of the present invention.
4 is a cross-sectional view taken along line I-I 'of FIG. 3.
5 is a flowchart illustrating a method of correcting light transmittance of a photomask according to embodiments of the present invention.
6A is a plan view showing one of the mask pattern regions of the photomasks of FIGS. 3 and 4.
6B is a cross-sectional view taken along line I-I 'in FIG. 6A. 7 is a schematic diagram for explaining generating a light intensity map of a photomask.
FIG. 8 shows a light intensity map of the mask pattern region of FIG. 6A.
FIG. 9 is a flowchart for specifically describing the steps of generating the virtual light intensity map of FIG. 5.
10 is a view schematically showing the layout of the mask pattern area of FIG. 6A.
11A, 12A, 13A, and 14A are enlarged views of the first area of FIG. 10.
11B, 12B, 13B, and 14B are enlarged views of the second area of FIG. 10.
15 is a view showing a virtual light intensity map corresponding to the light intensity map of FIG. 8.
16 is a schematic view for explaining correction of light transmittance of a mask substrate of a photomask.

1 is a flowchart illustrating a method of designing and manufacturing a semiconductor device according to embodiments of the present invention.

Referring to FIG. 1, a layout design for implementing a semiconductor integrated circuit on a silicon substrate may be performed (first step, S10). The layout design may include a routing procedure to place and connect various standard cells provided in a cell library according to a prescribed design rule.

The cell library for layout design can also include information about the operation, speed, and power consumption of standard cells. A cell library for expressing a specific gate level circuit as a layout is defined in most layout design tools. The layout design may be a procedure for defining a shape or size of a pattern for configuring transistors and metal wires to be actually formed on a silicon substrate. For example, in order to actually form the inverter circuit on the silicon substrate, layout patterns such as PMOS, NMOS, N-WELL, gate electrode, and metal wirings to be disposed thereon can be appropriately disposed. For this, first, a suitable one can be selected from among inverters already defined in the cell library.

Routing for deployed standard cells can be performed. Specifically, routing with upper wirings may be performed on the standard cells arranged. Standard cells can be connected to each other according to the design through a routing procedure. Most of these series of processes can be performed automatically or manually by the layout design tool. Furthermore, the placement and routing of standard cells may be performed automatically using a separate Place & Routing tool.

After routing, layout verification may be performed to determine whether there is a part that violates the design rule. Items to verify include: Design Rule Check (DRC), which verifies that the layout is properly in accordance with the design rules, Electronic Rule Check (ERC), which verifies that the layout is properly performed without interruption, and whether the layout matches the gate-level netlist. And LVS (Layout vs Schematic).

An optical proximity correction (OPC) procedure may be performed (second step, S20). By using a photolithography process, layout patterns obtained through layout design can be implemented on a silicon substrate. At this time, the optical proximity correction may be a technique for correcting a distortion phenomenon that may occur in the photolithography process. In other words, through optical proximity correction, distortions such as refraction and process effects caused by light characteristics during exposure using a laid-out pattern can be corrected. While performing the optical proximity correction, the shape and position of the designed layout patterns can be slightly changed (biased).

A photomask may be manufactured based on the layout changed by the optical proximity correction (third step, S30). In general, a photomask can be manufactured by using a chrome film applied on a mask substrate (eg, a quartz substrate) to form mask patterns depicting layout patterns.

The light transmittance of the photomask can be corrected (4th step, S40). A specific method of correcting the light transmittance of the photomask will be described later. By correcting the light transmittance of the produced photomask, it is possible to prevent process defects in the photolithography process.

A semiconductor device may be manufactured using a photomask (step 5, S50). Through a photolithography process using a photomask, patterns formed during layout design on a silicon substrate may be sequentially formed.

2 is a conceptual diagram showing a photolithography system using a photomask manufactured according to embodiments of the present invention.

Referring to FIG. 2, the photolithography system PLS may include a light source LS, a photomask PM, a reduced projection device RPA, and a substrate stage (SS). The photomask PM may be manufactured through the first to fourth steps S10, S20, S30, and S40 described above with reference to FIG. 1. The photolithography system (PLS) may further include components not shown in FIG. 2. As an example, the photolithography system PLS may further include a sensor used to measure the height and tilt of the surface of the substrate WF.

The light source LS may emit light. The light emitted from the light source LS may be irradiated with the photomask PM. For example, to adjust the optical focus, a lens may be provided between the light source LS and the photomask PM. The light source LS may include an ultraviolet light source (eg, a KrF light source having a wavelength of 234 nm, an ArF light source having a wavelength of 193 nm, etc.). The light source LS may include one point light source PO, but the present invention is not limited thereto. In other embodiments of the present invention, the light source LS may include a plurality of point light sources.

In order to print (implement) the designed layout on the substrate WF, the photomask PM may include mask patterns. For example, the mask patterns may block light emitted from the light source LS, and an area where the mask patterns are not formed may pass light emitted from the light source LS.

The reduced projection apparatus RPA may be provided with light passing through the photomask PM. The reduced projection apparatus RPA may match layout patterns to be printed on the substrate WF with mask patterns of the photomask PM. The substrate stage SS may support the substrate WF. As an example, the substrate WF may include a silicon wafer.

The reduced projection device RPA may include an aperture. The aperture may be used to increase the depth of focus of ultraviolet light emitted from the light source LS. As an example, the aperture may include a dipole aperture or a quadruple aperture. The reduced projection device RPA may further include a lens to adjust the optical focus.

The light passing through the photomask PM may be irradiated to the substrate WF through the reduction projection device RPA. Thus, resist patterns corresponding to the mask patterns of the photomask PM can be printed on the substrate WF.

3 is a plan view illustrating a reticle including a photomask according to embodiments of the present invention. 4 is a cross-sectional view taken along line I-I 'of FIG. 3.

2, 3 and 4, the reticle (RET) is a photomask (PM), a pellicle (PEL) for protecting the photomask (PM), and between the photomask (PM) and the pellicle (PEL) It may include a frame (FR). The reticle RET including the photomask PM according to the present embodiments may be mounted on the photolithography system PLS of FIG. 2 above, whereby a photolithography process may be performed on the substrate WF. .

The photomask PM may include a mask substrate MS and mask pattern regions MP on the mask substrate MS. Each of the mask pattern regions MP may include a plurality of fine mask patterns. For example, the mask substrate MS may be a quartz substrate, and the mask pattern area MP may include chrome patterns (ie, mask patterns). The mask substrate MS may include first to fourth chip regions CR1-CR4 for transferring a resist pattern on the substrate WF. Mask pattern regions MP may be disposed in the first to fourth chip regions CR1-CR4.

The first to fourth chip regions CR1-CR4 may be substantially the same as each other. Resist patterns may be transferred onto the first to fourth dies of the substrate WF by the first to fourth chip regions CR1-CR4, respectively. In other words, each of the first to fourth chip regions CR1-CR4 may correspond to one die of the substrate WF.

The mask substrate MS further includes an auxiliary pattern area AP surrounding each of the first to fourth chip areas CR1-CR4, and a black border area BB positioned around the mask substrate MS. It can contain.

An auxiliary pattern (not shown) that is not a pattern constituting the integrated circuit to be implemented may be disposed on the auxiliary pattern area AP. The auxiliary pattern may include a pattern that is required in the manufacturing process of the integrated circuit but does not remain in the final semiconductor chip, for example, an alignment key pattern. The auxiliary pattern area AP may correspond to the scribe lane area of the substrate WF, and thus the auxiliary pattern of the auxiliary pattern area AP may be transferred on the scribe lane area of the substrate WF. The black border area BB may be a non-pattern area that does not include a pattern element for transferring a pattern on the substrate WF.

The first surface PELa of the pellicle PEL may be exposed to the outside. The second surface PELb of the pellicle PEL may face the photomask PM. A frame FR may be interposed between the pellicle PEL and the photomask PM. The pellicle PEL may be spaced apart from the photomask PM by the frame FR. The frame FR may be provided on the black border area BB of the mask substrate MS. Although not shown, an adhesive layer may be interposed between the pellicle PEL and the frame FR. An adhesive layer may be interposed between the pellicle PEL and the mask substrate MS.

The pellicle PEL may protect the photomask PM from external contaminants (eg, dust, resist, etc.). If there is no pellicle (PEL) on the photomask PM, external contaminants may be attached to the photomask PM, causing various problems in the photolithography process.

5 is a flowchart illustrating a method of correcting light transmittance of a photomask according to embodiments of the present invention. 6A is a plan view showing one of the mask pattern regions of the photomasks of FIGS. 3 and 4. 6B is a cross-sectional view taken along line I-I 'in FIG. 6A. 7 is a schematic diagram for explaining generating a light intensity map of a photomask. FIG. 8 shows a light intensity map of the mask pattern region of FIG. 6A.

Correcting the light transmittance of the photomask of FIG. 1 (S40), as shown in FIG. 5, captures light passing through the photomask to generate a light intensity map (S410), simulates layout to simulate virtual light It may include generating an intensity map (S420) and correcting the light transmittance of the mask substrate by comparing the light intensity map and the virtual light intensity map (S430).

5, 6A, 6B, 7 and 8, a light intensity map IM may be generated by photographing light that has passed through the photomask PM (S410). The light intensity map IM may indicate the intensity of light irradiated on the substrate WF when light passing through the photomask PM is irradiated on the substrate WF of FIG. 2. The light intensity map IM may be an image showing the light transmittance of the photomask PM. As an example, the light intensity map IM may be a charge-coupled device (CCD) image.

Specifically, referring back to FIGS. 6A and 6B, a photomask PM manufactured based on a layout may be prepared. As described above with reference to FIG. 4, the photomask PM may include a mask substrate MS and a mask pattern region MP on the mask substrate MS.

Referring to FIGS. 7 and 8 again, a photomask PM may be disposed on the image acquisition unit IS. As an example, the image acquisition unit IS may include a CCD camera. Light LI may be irradiated on the photomask PM. The light LI passing through the photomask PM may be incident on the image acquisition unit IS. The image acquisition unit IS may photograph the incident light LI to generate a light intensity map IM. The resulting light intensity map IM is shown in FIG. 8. The light intensity map IM of FIG. 8 may be an image of the mask pattern area MP of FIG. 6A.

As the light LI passes through the photomask PM, the intensity of the light LI may be reduced. As a first factor in which the intensity of the light LI is reduced, the intensity of the light LI may be reduced by mask patterns in the mask pattern area MP. The light transmittance of the mask pattern area MP may vary for each area according to the density of the mask patterns.

As a second factor in which the intensity of the light LI is reduced, the intensity of the light LI may be reduced by the mask substrate MS. The light transmittance of the mask substrate MS may vary depending on the area of the mask substrate MS. The light transmittance of the mask substrate MS varies depending on the region, which may be due to a defect in which the mask substrate MS is not uniformly formed.

Due to the first factor and the second factor, the intensity of the light LI incident on the image acquisition unit IS may vary depending on the region. For example, the intensity of the light LI incident on the first portion PA1 of the image acquisition unit IS is greater than the intensity of the light LI incident on the second portion PA2 of the image acquisition unit IS. It can be bigger. The intensity of the light LI incident on the second portion PA2 of the image acquisition unit IS may be greater than the intensity of the light LI incident on the third portion PA3 of the image acquisition unit IS. have.

The light intensity map IM generated by the image acquisition unit IS may include a plurality of image pixels aPX. The image pixel aPX may represent a value according to the intensity of the light LI incident on the image pixel aPX. For example, the image pixel aPX may have brightness or color according to the intensity of the light LI incident on the image pixel aPX.

The image pixels aPX may include a first image pixel aPX1 adjacent to each other, a second image pixel aPX2, and a third image pixel aPX3. The first to third image pixels aPX1, aPX2, and aPX3 have different light intensities. The light intensity indicated by the first image pixel aPX1 is greater than the light intensity indicated by the second image pixel aPX2 (eg, the brightness of the first image pixel aPX1 is brighter than that of the second image pixel aPX2). ). The light intensity indicated by the second image pixel aPX2 is greater than the light intensity indicated by the third image pixel aPX3 (eg, the brightness of the second image pixel aPX2 is greater than the brightness of the third image pixel aPX3). ). This means that the first image pixel aPX1 is a pixel corresponding to the first portion PA1 of the image acquisition unit IS of FIG. 7, and the second image pixel aPX2 is of the image acquisition unit IS of FIG. 7. This is because the pixel corresponding to the second portion PA2 and the third image pixel aPX3 are pixels corresponding to the third portion PA3 of the image acquisition unit IS of FIG. 7.

FIG. 9 is a flowchart for specifically describing the steps of generating the virtual light intensity map of FIG. 5. 10 is a view schematically showing the layout of the mask pattern area of FIG. 6A. 11A, 12A, 13A, and 14A are enlarged views of the first area of FIG. 10. 11B, 12B, 13B, and 14B are enlarged views of the second area of FIG. 10. 15 is a view showing a virtual light intensity map corresponding to the light intensity map of FIG. 8.

5, 9 and 10, a virtual light intensity map may be generated by simulating the layout LO (S420). Specifically, referring back to FIGS. 9 and 10, a layout LO based on the mask pattern region MP of FIG. 6A may be provided (S421). The layout LO of FIG. 9 may be a layout in which the optical proximity correction S20 described above with reference to FIG. 1 is performed. In other words, the layout LO of FIG. 9 may be a layout that is the basis of manufacturing the photomask PM of FIGS. 6A and 6B.

For example, the layout LO may include a first region RG1 and a second region RG2. The first region RG1 may correspond to the first image pixel aPX1 in FIG. 8, and the second region RG2 may correspond to the second image pixel aPX2 in FIG. 8. The size of the first region RG1 and the size of the second region RG2 may be substantially the same.

Hereinafter, a method of generating a virtual light intensity map around the first area RG1 and the second area RG2 of the layout LO will be described. 9, 11A and 11B, the first region RG1 may include a first layout pattern LP1 and a second layout pattern LP2. The second region RG2 may include a first layout pattern LP1, a second layout pattern LP2, a third layout pattern LP3 and a fourth layout pattern LP4. The first region RG1 may include two layout patterns, and the second region RG2 may include four layout patterns. Since the size (area) of the first region RG1 and the size (area) of the second region RG2 are substantially equal to each other, the pattern density of the second region RG2 is greater than that of the first region RG1. It can be big.

9, 12A, and 12B, the layout LO may be divided into a plurality of grid regions (S422). Specifically, each of the first and second regions RG1 and RG2 may be divided into first to fourth lattice regions GR1-GR4. The first to fourth lattice regions GR1-GR4 may have substantially the same size.

The first layout pattern LP1 may be positioned in the first grid area GR1 of the first area RG1. A portion of the first layout pattern LP1 may be positioned in the second grid area GR2 of the first area RG1. No layout pattern may be located in the third grid area GR3 of the first area RG1. The second layout pattern LP2 may be positioned in the fourth grid area GR4 of the first area RG1.

A portion of the first layout pattern LP1 and the second layout pattern LP2 may be positioned in the first grid region GR1 of the second region RG2. The first layout pattern LP1 and the second layout pattern LP2 may be positioned in the second grid region GR2 of the second region RG2. The third layout pattern LP3 and the fourth layout pattern LP4 may be positioned in the third grid region GR3 of the second region RG2. The third layout pattern LP3 may be positioned in the fourth grid area GR4 of the second area RG2.

9, 13A and 13B, light intensity values may be calculated for each lattice region (S423). Specifically, the light intensity value of the lattice region may be calculated through simulation based on the pattern density in the lattice region. The pattern density may be a ratio of an area of a layout pattern in the grid area to an area of the grid area. The simulation may include OPC model simulation or Optic model simulation. As an example, the calculated light intensity value may be represented by the brightness or color of the grating area.

The pattern density of the first lattice region GR1 of the first region RG1 may be greater than the pattern density of the second lattice region GR2 of the first region RG1. Accordingly, the light intensity value of the first grating area GR1 of the first area RG1 may be smaller than the light intensity value of the second grating area GR2 of the first area RG1. This is because as the pattern density increases, the light transmittance of the photomask decreases, resulting in a decrease in light intensity. Since the pattern density of the third lattice region GR3 of the first region RG1 is 0, it may have the largest light intensity value.

The pattern density of the first lattice region GR1 of the second region RG2 may be smaller than the pattern density of the second lattice region GR2 of the second region RG2. Accordingly, the light intensity value of the first grating area GR1 of the second area RG2 may be greater than the light intensity value of the second grating area GR2 of the second area RG2. The pattern density of the fourth lattice region GR4 of the second region RG2 may be smaller than the pattern density of the first lattice region GR1 of the second region RG2. Therefore, the light intensity value of the fourth grating area GR4 of the second area RG2 may be greater than the light intensity value of the first grating area GR1 of the second area RG2.

9, 14A, 14B, and 15, a virtual light intensity map (sIM) may be generated based on a light intensity value for each lattice area (S424). The virtual light intensity map sIM may include a plurality of virtual pixels sPX. The virtual light intensity map sIM is a simulation result showing the intensity of light to be incident on the substrate WF of FIG. 2 through the photomask PM. The virtual pixel sPX may indicate the intensity of light to be incident on the substrate WF using brightness or color.

The virtual light intensity map sIM of FIG. 15 may correspond to the light intensity map IM of FIG. 8, and the virtual pixels sPX may respectively correspond to the image pixels aPX of FIG. 8. In other words, the virtual light intensity map sIM includes first to third virtual pixels sPX1, sPX2, and sPX3 corresponding to the first to third image pixels aPX1, aPX2, and aPX3 in FIG. 8, respectively. It can contain.

Specifically, the first virtual pixel spX1 may be formed based on the light intensity values of the first to fourth lattice areas GR1-GR4 of the first area RG1. For example, the light intensity of the first virtual pixel sPX1 may be calculated by averaging and correcting light intensity values of the first to fourth lattice areas GR1-GR4 of the first area RG1. The second virtual pixel spX2 may be formed based on the light intensity values of the first to fourth lattice areas GR1-GR4 of the second area RG2. For example, the light intensity of the second virtual pixel sPX2 may be calculated by averaging and correcting light intensity values of the first to fourth lattice areas GR1-GR4 of the second area RG2.

Since the pattern density of the first region RG1 is smaller than the pattern density of the second region RG2, the light intensity value calculated by the simulation of the first virtual pixel sPX1 is calculated by the simulation of the second virtual pixel sPX2. It may be greater than the value of the light intensity (ie, the brightness of the first virtual pixel sPX1 is displayed brighter than the brightness of the second virtual pixel sPX2).

The virtual light intensity map (sIM) of FIG. 15 shows the result of the first factor among the first factor (factor due to mask patterns) and the second factor (factor caused by mask substrate) in which the intensity of light described above is reduced. . The virtual light intensity map sIM of FIG. 15 may be an ideal result indicating the intensity of light passing through the photomask PM and incident on the substrate WF of FIG. 2 when the light transmittance of the mask substrate MS is uniform. have. In other words, the virtual light intensity map sIM of FIG. 15 may be an ideal result indicating the light transmittance of the photomask PM when there is no defect of the mask substrate MS.

16 is a schematic view for explaining correction of light transmittance of a mask substrate of a photomask.

5, 15 and 16, the light transmittance of the mask substrate MS may be corrected by comparing the light intensity map IM of FIG. 8 with the virtual light intensity map of FIG. 15 (sIM) ( S430). The virtual light intensity map sIM of FIG. 15 may be a reference for correcting light transmittance of the mask substrate MS. Specifically, by comparing the light intensity map (IM) of FIG. 8 and the virtual light intensity map (sIM) of FIG. 15, the virtual of the virtual light intensity map (sIM) among the image pixels (aPX) of the light intensity map (IM) Pixels that are different from the pixels sPX can be found.

In the case of the image pixel aPX having a difference from the virtual pixel sPX, the light transmittance of the region of the mask substrate MS corresponding thereto may be corrected. In the case of the image pixel aPX having no difference from the virtual pixel sPX, the light transmittance of the region of the mask substrate MS corresponding thereto may not be corrected.

As an example, the first image pixel aPX1 may have a light intensity value substantially the same as the first virtual pixel sPX1. The first image pixel aPX1 and the first virtual pixel sPX1 may not be different from each other. In other words, the area of the mask substrate MS in which the first image pixel aPX1 is located may not correct light transmittance.

The second image pixel aPX2 may have a larger light intensity value than the second virtual pixel sPX2. Therefore, the area of the mask substrate MS on which the second image pixel aPX2 is located can be corrected so that its light transmittance is lowered. Accordingly, the second image pixel aPX2 may have a light intensity value substantially the same as the second virtual pixel sPX2.

The third image pixel aPX3 may have a smaller light intensity value than the third virtual pixel sPX3. Therefore, the area of the mask substrate MS on which the third image pixel aPX3 is located can be corrected to increase the light transmittance thereof. Accordingly, the third image pixel aPX3 may have a light intensity value substantially the same as the third virtual pixel sPX3.

Correcting the light transmittance of the mask substrate MS may include irradiating a laser LSR to the mask substrate MS. For example, when the laser LSR is irradiated to the mask substrate MS, a vacancy may be formed, and thus the light transmittance of the mask substrate MS may be changed.

3 and 4 again, the pellicle PEL may be disposed on the photomask PM after the mask substrate MS is corrected. The pellicle PEL may be fixed on the photomask PM by the frame FR.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention may be implemented in other specific forms without changing its technical spirit or essential features. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (10)

Designing a layout;
Manufacturing a photomask based on the designed layout;
Correcting the light transmittance of the photomask; And
A photolithography process is performed using the photomask to form a pattern on the substrate.
Correcting the light transmittance of the photomask is:
Generating a light intensity map by photographing light passing through the photomask;
Generating a virtual light intensity map by simulating the layout; And
And comparing the light intensity map and the virtual light intensity map to correct light transmittance of the mask substrate of the photomask.
According to claim 1,
Generating the virtual light intensity map is:
Dividing the layout into a plurality of grid regions;
Calculating a light intensity value of each of the lattice regions; And
A method of manufacturing a semiconductor device, comprising generating a virtual light intensity map based on the light intensity value.
According to claim 2,
The lattice regions include a first lattice region and a second lattice region having a larger pattern density than the first lattice region,
A method of manufacturing a semiconductor device, wherein a light intensity value of the first grating area is greater than a light intensity value of the second grating area.
According to claim 2,
The light intensity map includes a plurality of image pixels,
Generating the virtual light intensity map includes generating a plurality of virtual pixels respectively corresponding to the plurality of image pixels,
Each of the virtual pixels is produced by averaging light intensity values of a plurality of the lattice regions.
According to claim 1,
Generating the light intensity map is:
Placing the photomask on an image acquisition unit comprising a CCD camera;
Irradiating light on the photomask; And
A method of manufacturing a semiconductor device comprising taking the light that has passed through the photomask using the image acquisition unit.
According to claim 1,
The light intensity map includes a plurality of image pixels,
The virtual light intensity map includes a plurality of virtual pixels,
Comparing the light intensity map and the virtual light intensity map, the method of manufacturing a semiconductor device comprising comparing each of the image pixels with the virtual pixels.
According to claim 1,
Correcting the light transmittance of the mask substrate includes a method of manufacturing a semiconductor device comprising irradiating a laser to the mask substrate.
Designing a layout;
Manufacturing a photomask based on the designed layout;
Correcting the light transmittance of the photomask; And
A photolithography process is performed using the photomask to form a pattern on the substrate.
Correcting the light transmittance of the photomask is:
Dividing the layout into a plurality of grid regions;
Calculating a light intensity value of each of the lattice regions; And
A method of manufacturing a semiconductor device, comprising generating a virtual light intensity map based on the light intensity value.
The method of claim 8,
Correcting the light transmittance of the photomask further comprises generating a light intensity map by photographing light passing through the photomask.
The method of claim 9,
The light intensity map includes a plurality of image pixels,
Generating the virtual light intensity map includes generating a plurality of virtual pixels respectively corresponding to the plurality of image pixels,
Each of the virtual pixels is produced by averaging light intensity values of a plurality of the lattice regions.

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