TWI230877B - Method of correcting optical proximity effects - Google Patents

Abstract

Pattern densities of an original designed layout of a workpiece, such as a wafer, are examined. According to the examined results, the original layout is then divided into at least a first region and a second region, a pattern density of the first region being different from a pattern density of the second region. By using an optical proximity correction (OPC) models to correct and modify the first region and the second region, a predetermined modified layout is formed on a photomask. The modified layout can be transfer to a wafer by a photolithography process so that the wafer produces a pattern the same as a pattern of the original layout.

Description

1230877 V. Description of the Invention u) Field of the Invention The present invention provides a method for correcting a layout pattern on a photomask, particularly a method for correcting an optical approximation effect on a wafer. Background note. In order to form a designed integrated circuit on a semiconductor wafer, the crystal pattern factory must first make a photomask, and then form a designed layout pattern on the photomask, and then use lithography ( Photo lithography) process transfers the pattern on the photomask to the photoresist layer on the surface of the semiconductor wafer at a certain ratio, and then smoothly transfers the layout pattern of the integrated circuit to the semiconductor wafer. Therefore, the lithography process can be said to be the most important step in the semiconductor process. Since the critical dimension (CD) of the pattern that can be made on the reticle is limited by the resolution limit (res〇iuti〇I1 limit) of the optical exposure tool, it follows that The design of circuit patterns is getting smaller and smaller. When these high-density mask patterns are exposed to form a circuit pattern, it is easy to produce an optical proximity effect, which makes the pattern overexposed. se) or underexpose, resulting in loss of resolution (resolotisolrls), causing distortion of the graphics there. The current solution is to use computer-assisted design

Page 5 1230877 V. Description of the invention (2) Compute terai ded de si gn (C AD) method to perform an optical proximity correction (0 PC) on the mask pattern to eliminate the optical proximity effect, A mask is then made according to the corrected pattern. Please refer to the figure for the flow diagram of the optical approximation correction method in the prior art. First, before making this correction, a test mask is first used to expose the semiconductor wafer, and the line width after exposure on the semiconductor wafer is measured, and then a series of experimental data is arranged to obtain two test lights. The relative relationship between the mask line width and the line width on the wafer after exposure creates an optical approximation correction module (0PC mOdel) 14. After successfully establishing this 〇PC module, and then after the original layout obtained according to the circuit design i 2 = this 0PC module 丨 4, and through the calculation of the 0PC module ", a correction is generated :: Figure: Will be carried out-verify step 16 to test, if the test fails, a parameter adjustment 18 'and return to the op group 14 to recalculate, Sa thus constantly amends and re-checks the lamp to say 20, do divination Z further obtains a correction of the approximate effect of the layout month H ^ after the correction of the layout loss. Finally, use this modified output layout pattern to design this mask. * The pattern on the body wafer is close to the original pattern after the material is lighted. Because of the traditional optical approximation effect, Yu Zai + uses a 0PC module to correct 〃, and / / the deviation caused by the uneven density of the entire circuit layout area, / ^ due to the layout of the situation Is a single product (such as: single ton of sg B chip design in the past often

Early logic chip, SRAM chip or DRAM

1230877 V. Description of the invention (3) Wafer), so there is not much difference in layout density on the same wafer. However, with the integration trend of semiconductor components, many chips often have several different types of designs at the same time, so the same chip may also have considerable differences in local area density in circuit layout. Therefore, the traditional optical approximation correction method begins to have problems. It often makes overcorrection in some areas, but in some areas it is undercorrected. The corrections made are often incorrect, and there are still many overexposed or underexposed. Problems that seriously affect the reliability of subsequent processes.

SUMMARY OF THE INVENTION The main object of the present invention is to provide a layout pattern correction method that can perform different calculation methods for different parts on a working part, so as to achieve the purpose of correcting the optical approximation effect. In the preferred embodiment of the present invention, an original layout that is intended to be formed on a system on chip (S0C) is first provided, and then the pattern density of the original layout is detected and based on The pattern density divides the original layout into at least two first predetermined areas and second predetermined areas with different pattern densities, and establishes corresponding optical approximate correction modules (OPC Models), which are the first module and the The second module. Subsequently, the first and the second predetermined areas are modified and verified according to the first module and the second module, so as to form a modified layout that is predetermined to be formed on a photomask.

Page 7 1230877 V. Description of the invention (4) The revised layout can be transferred from the photomask to the system integration chip through a photolithography process, and the pattern obtained by the system integration chip and the The original layout is the same. Since the correction method of the present invention first detects the original layout pattern and calculates it with different modules according to the local density of the layout pattern, an optimal revised layout pattern can be obtained, which can effectively improve Product reliability.

Detailed description of the invention Please refer to FIG. 2. FIG. 2 is a flowchart 30 of the method for correcting the optical approximation effect in the present invention. First, before a batch of photomasks is subjected to layout pattern correction, an exposure experiment of a test photomask is performed to determine the relationship between the design line width on the photomask and the line width on the photoresist layer after exposure. In addition, computer aided design (CAD) can be used to perform an optical proximity correction (0PC) on the reticle pattern to eliminate corner rounding effects and straight end shrinkage. Optical proximity effect such as line end shortening effect. It is worth noting that the layout pattern correction calculation method obtained by the present invention does not optimize the data of the entire photomask together, but divides this photomask into several parts according to the layout pattern density or circuit functional blocks, and Every

Page 8 1230877 V. Description of the Invention (5) Each part is optimized to obtain several different line width correspondences, that is, to generate several optical approximation correction modules at different layout density levels. As shown in FIG. 2, in the first embodiment of the present invention, a system integrated chip is taken as an example. The layout pattern density is divided into four levels, which are A (pattern density less than 40%) 34a, B ( Pattern density 4 0-6 0%) 34b, C (pattern density 60-80%) 34c and D (pattern density more than 80%) 3 4d. And corresponding to OPC module A 36a, module B 36b, module C 3 6c and module D 3 6d. Next, the original circuit layout 32 to be modified is detected to understand the pattern density distribution of each part, and the original circuit layout 32 to be modified for optical effects is divided into a plurality of blocks according to different pattern density levels. ). After the partitioning of the original circuit layout is completed, ^ = like effect correction is performed on each block. Each block is modified according to the layout density level to which it belongs. Knife = Enter the corresponding 0PC module 36 to correct it. Ϊ Width :: The relationship is calculated to obtain the initial of each block.

After the amendment of the plan, the area of each area is then: go to 8, complete the layout of each block, and output the entire circuit layout to 42. End == 4. Formation: J-like effect correction. ^ The optics of the layout pattern on the cover is nearly 1230877 V. Description of the invention (6)

Referring to FIG. 3, in the second embodiment of the present invention, the method for correcting the optical approximation effect is similar to the first embodiment, except that the system is integrated with the original layout pattern 5 2 on the wafer directly according to its circuit. The function of the design is divided into four areas: logic area 54a, random access memory (RAM) area 54b, central processing unit (CPU) area 54c, and mixed mode (Mix Mode) 54d. Although the components with different functions are divided into different blocks at this time, since the pattern density of various components is usually within a certain range in the current semiconductor manufacturing process, this method of classifying component functions is relatively Simple and straightforward, but similar effects to the first embodiment can be achieved. The subsequent operation flow is the same as the first embodiment. First, different 0 PC modules 56 are established for different blocks by experimental tests. After that, the original layout pattern is divided into blocks according to the aforementioned standards, and the blocks belong to each block. The 0PC module 5 6 is modified and verified 5 8. Through continuous modification and verification 5 8, the modified layout patterns obtained in each block are combined 6 0 to form a layout output after correcting the optical approximation effect 6 2. Based on the above description, the optical approximation correction method of the present invention can further correct the deviation caused by different layout densities due to an additional step of partition processing, so as to solve the problem caused by the uneven density of the circuit layout on the system integration chip. problem. Compared with the correction method of the prior art, the present invention first uses a layout

Page 10 1230877 V. Description of the invention (7) Appropriate partitioning of density (circuit function), so different 0PC modules can be created for different layout density levels to achieve a better optimization correction and greatly improve the product Reliability. The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Page 11 1230877 Simple illustration of the diagrams Simple illustration of the diagrams Figure 1 is a flowchart of the optical approximation correction method in the prior art 100. Figure 2 is a flowchart of the optical approximation correction method in the first embodiment of the present invention. FIG. 3 is a flowchart of a method for correcting an optical approximation effect in the second embodiment of the present invention.

Symbol description

10 Flow chart 12 Original layout 14 OPC module 16 Verification 18 Parameter adjustment 20 Layout output 30 Flow chart 32 Original layout 34a A 34b B 34c C 36d D 36a OPC module A 36b 0PC module B 36c OPC module C 36d 0PC module Group D 38 Verification 40 Merge 42 Layout Output 50 Flow Chart 52 System Integrated Chip Original Layout 54a Logic Area 54b Random Access Memory Area 54c CPU Area 54d Mixed Area 56a Logic 0PC Module

Page 12 1230877 Schematic description 5 6b Random access 0PC module 56c CPU 0PC module 56d Hybrid 0PC module 5 8 Verification 6 0 Merge 62 Layout output

Hill Page 13

Claims (1)

1230877 VI. Scope of patent application 1. A method for correcting optical proximity effects on a workpiece, the method includes the following steps: providing an original layout plan to be formed on the workpiece layout); According to the density, the original layout is defined to have at least two predetermined areas with different pattern densities, namely a first predetermined area and a second predetermined area, respectively for the first predetermined area and the second predetermined area. Establish corresponding optical approximation correction modules (OPC Models), which are a first module and a second module, respectively; the first predetermined area and the second predetermined area are corresponding to the first module And the second module is corrected and verified; and the data obtained after the correction and verification is formed into a modified layout that is scheduled to be formed on a photomask; wherein the modified layout can be processed by a lithography process ( photolithographic process) is transferred from the photomask to the working part, and the pattern obtained by the working part is related to the Beginning the same layout view. 2. The method of claim 1 in which the surface of the working part includes a photoresist layer as a photosensitive material. 3. The method according to item 1 of the patent application scope, wherein the original layout is input through an input device and stored in a computer's memory