KR20200027113A - Off-chip driver - Google Patents

Abstract

Provided is an off-chip driver applied to a memory. The off-chip driver includes a first driver circuit used to adjust a slew rate of the off-chip driver. The first driver circuit includes a first pre-driver, a switch row, and a first output stage. The first pre-driver receives a read signal and a first pre-driver control signal. The switch row is arranged to combine the first pre-driver based on the read signal, to divide and operate a power supply voltage, and to generate a first output stage control signal. The first output stage generates a data signal based on the first output stage control signal.

Description

Off-chip driver

The present invention relates to an off-chip driver, and more particularly to an off-chip driver capable of adjusting the slew rate.

Off-chip drivers (Off-Chip Driver, OCD) are used in DRAM (Dynamic Random Access Memory, DRAM) to transfer data from the memory to the host computer. The off-chip driver's slew rate (SR) and driving force are stipulated in the Joint Electronic Device Committee (Joint Electron Device Engineering Council, JEDEC) standard. These parameters are affected by the manufacturing process, voltage and temperature.

Generally, the slew rate of the off-chip driver is adjusted by controlling the gate signal of the output stage of the off-chip driver. However, drift is generated in the actual output of the off-chip driver due to variations in the manufacturing process. Another method is to control the effective time of the off-chip driver, but this method further considers that it is difficult to further design the effective time adjustment circuit and to adjust the timing of the effective time adjustment circuit under variations in the manufacturing process. There is a need.

In addition, based on the current time change rate dI / dt, it is not sufficient for high-speed input / output circuits (IO / circuits) to observe the JEDEC regulations for signal quality (SI). not. Therefore, the high-speed input / output circuit needs to further design a precise slew rate adjustment circuit.

The present invention provides an off-chip driver capable of adjusting the slew rate without using the slew rate adjustment circuit to improve power consumption and layout area.

The present invention provides an off-chip driver applied to a memory, and includes a first driver circuit used to adjust the slew rate of the off-chip driver. The first driver circuit includes a first pre-driver, a switch row, and a first output stage. The first pre-driver receives a read signal and a first pre-driver control signal. The switch row is arranged to be coupled to the first pre-driver, to couple the first pre-driver based on the read signal, and to divide the power supply voltage to produce a first output stage control signal. The first output stage is coupled to the first pre-driver and the switch row, and generates a data signal based on the first output stage control signal.

Based on the above, in some embodiments of the present invention, the off-chip driver applies the partial pressure operation of the first free driver and the switch row to adjust the slew rate, and does not improve power consumption and layout area. Since the circuit structure is symmetrical, it is possible to maintain control of the slew rate under fluctuations in the manufacturing process.

In order to further clarify the above-described features and advantages of the present invention, detailed description will be given below with reference to the drawings.

1 is a schematic diagram of an off-chip driver in the embodiment of the present invention.
2 is a block diagram of the first driver circuit in the embodiment of the present invention.
3 is a schematic diagram of the first driver circuit in the embodiment of the present invention.
4 is a block diagram of a second driver circuit in the embodiment of the present invention.
5 is a schematic diagram of a second driver circuit in the embodiment of the present invention.
6 is a timing diagram of the off-chip driver in the embodiment of the present invention.
7 shows a first driver circuit in another embodiment of the present invention.

1, FIG. 1 shows a schematic diagram of an off-chip driver in an embodiment of the present invention. The off-chip driver 100 includes a first driver circuit 110 and a plurality of second driver circuits 120＿1 to 120＿n. The first driver circuit 110 is used to adjust the slew rate of the off-chip driver 100, and the plurality of second driver circuits 120＿1 to 120＿n is used to adjust the driving force of the off-chip driver 100. . In the embodiment, the minimum driving force of the off-chip driver 100 is 240 ohm based on JEDEC (Joint Electron Device Engineering Council) standard. In the embodiment of this example, the off-chip driver 100 determines its driving force based on the number of turns on of the plurality of second driver circuits 120 ＿ 1 to 120 ＿n. For example, when the number of turns of the plurality of second driver circuits 120＿1 to 120＿n is small, the driving force may be 240 ohm, but when the number of turns of the plurality of second driver circuits 120＿1 to 120＿n is large, The driving force may also be 120 ohm. The present invention does not limit the range of driving force.

In the embodiment of the present example, the plurality of second driver circuits 120＿1 to 120＿n are mutually parallel, and the plurality of second driver circuits 120＿1 to 120µn are mutually parallel to the first driver circuit 110.

In the embodiment of this example, the first driver circuit 110 receives the read signal DataP / DataN and the first pre-driver control signal TmSRt / TmSRc to generate the data signal DQ. The second driver circuit 120 # 1 receives the read signal DataP / DataN, the second pre-driver control signal ZqNEnt <1>, and the second pre-driver control signal ZqNEnc <1> to generate a data signal DQ. The second driver circuit 120 @ n receives the read signal DataP / DataN, the second pre-driver control signal ZqNEnt <n>, and the second pre-driver control signal ZqNEnc <n> to generate a data signal DQ. The second driver circuits 120＿1 to 120＿n-1 (not shown) are the same as the second driver circuit 120＿1 and the second driver circuit 120＿n. In other embodiments of the present invention, the number n of the second driver circuits may be provided based on actual needs, and there is no particular limitation.

Referring to Figs. 2 and 3 at the same time, Fig. 2 shows a block diagram of the first driver circuit in the embodiment of the present invention. 3 shows a schematic diagram of the first driver circuit in the embodiment of the present invention.

Referring to FIG. 2, in the embodiment of the present example, the first driver circuit 110 includes a first pre-driver 210, a switch string 220, and a first output stage 230. In the embodiment of this example, the first pre-driver 210 receives the read signal DataP / DataN and the first pre-driver control signal TmSRt / TmSRc. The switch row 220 is coupled to the first pre-driver 210, and based on the read signal DataP / DataN, combines the first pre-driver 210, divides the power supply voltage VDD, and operates the first output stage. It is arranged to generate a control signal DP1 / DN1. The first output stage 230 is coupled to the first pre-driver 210 and the switch row 220, and the first output stage 230 is a data signal based on the first output stage control signal DP1 / DN1 Create DQ.

Referring to FIGS. 2 and 3 at the same time, it should be noted that in the embodiment of this example, FIG. 2 includes a first output stage 230 of FIG. 3 and a first pre-driver 210＿1 coupled thereto, a switch column 220 (1 ) May be represented, and the first output stage 230 and the first pre-driver 210＿2 and the switch column 220＿2 coupled thereto may also be represented. FIG. 2 shows the first output driver 230 of FIG. 3, the first pre-driver 210＿1 and the switch column 220＿1 coupled thereto, and the first pre-driver 210 includes a read signal DataP, and The first pre-driver control signal TmSRt is received, and the switch column 220 couples the first pre-driver 210 based on the read signal DataP, divides the power supply voltage VDD, and operates the first output stage control signal DP1 Produces Meanwhile, FIG. 2 shows the first output driver 230 of FIG. 3 and the first pre-driver 210＿2 and the switch column 220＿2 coupled to the first output stage 230 of FIG. 3. , Receives the first pre-driver control signal TmSRc, the switch column 220 couples the first pre-driver 210 based on the read signal DataN, divides the power supply voltage VDD, and controls the first output stage Generate signal DN1. In an embodiment, the first output stage 230 generates a data signal DQ based on the first output stage control signal DP1 and the first output stage control signal DN1.

Referring to FIG. 3, the first driver circuit 110 includes a first pre-driver 210＿1, a first pre-driver 210＿2, a switch column 220＿1, a switch column 220＿2, and a first output It includes a stage 230. Here, the first pre-driver 210＿1 and the switch column 220＿1 are coupled to the transistor mp9 of the first output stage 230, and the first pre-driver 210＿2 and the switch column 220＿2 are the first output stage It is coupled to transistor mn9 of 230.

The first pre-driver 210 # 1 includes an inverter (transistor mp1 and transistor mn2), a first switch (transistor mn3), and a second switch (transistor mp6).

The inverter of the first pre-driver 210＿1 is constituted by the combination of the transistor mp1 and the transistor mn2, the gate of the transistor mp1 and the gate of the transistor mn2 are mutually coupled, used to receive the read signal DataP, and the source of the transistor mp1 Is coupled to the power supply voltage VDD, and the drain of the transistor mp1 and the drain of the transistor mn2 are mutually coupled.

For the transistor mn3, which is the first switch of the first pre-driver 210＿1, the source of the transistor mn3 is coupled to the source of the transistor mn2, and the gate of the transistor mn3 receives the first pre-driver control signal TmSRt, so that the transistor mn3 Turn on or off, and the source of the transistor mn3 is coupled to the power supply voltage VSS.

For the transistor mp6, which is the second switch of the first pre-driver 210＿1, the gate of the transistor mp6 is coupled to the gate of the transistor mn3, receives the first pre-driver control signal TmSRt, and turns the transistor mp6 on or off. , The source of the transistor mp6 is coupled to the power supply voltage VDD, and the drain of the transistor mp6 is coupled to the drain of the transistor mp1 and the drain of the transistor mn2.

The switch column 220 # 1 includes a third switch (transistor mn4) and a fourth switch (transistor mn5).

For the transistor mn4, which is the third switch in the switch column 220 # 1, the drain of the transistor mn4 is coupled to the drain of the transistor mp6, the drain of the transistor mp1 and the drain of the transistor mn2, and the gate of the transistor mn4 receives the read signal DataP Thus, the transistor mn4 is turned on or off.

For the transistor mn5, which is the fourth switch in the switch column 220 드레인 1, the drain of the transistor mn5 is coupled to the source of the transistor mn4 in the switch column 220＿1, and the gate of the transistor mn5 receives the power supply voltage VDD, and the transistor mn5 Turn on, and the source of the transistor mn5 is coupled to the power supply voltage VSS.

In the embodiment of this example, the switch columns 220＿1 (transistors mn4 and transistor mn5) are inverters (transistor mp1 and transistor mn2) of first pre-driver 210＿1, first switch (transistor mn3), second switch (transistor) mp6) to generate the first output stage control signal DP1.

The first pre-driver 210＿2 includes an inverter (transistors mp3 and mn1), a first switch (transistor mp2), and a second switch (transistor mn6). The first free driver 210 드라이버 2 is a complementary form of the first free driver 210＿1, and is not described repeatedly.

The switch column 220 # 2 includes a third switch (transistor mp4) and a fourth switch (transistor mp5). The switch row 220_2 is a complementary form of the switch row 220_1 and is not described repeatedly.

In the embodiment of this example, the switch columns 220＿2 (transistor mp4 and transistor mp5) are the inverters (transistor mn1 and transistor mp3) of the first free driver 210＿2, the first switch (transistor mp2), and the second switch (transistor mn6) ) To generate the first output stage control signal DN1.

The first output stage 230 includes a transistor mp9 and a transistor mn9, the transistor mp9 is a P-type transistor, the transistor mn9 is an N-type transistor, and the drain of the transistor mp9 is coupled to the drain of the transistor mn9.

In the embodiment of this example, the first output stage 230 receives the first output stage control signal DP1 and the first output stage control signal DN1, and through the transistor mp9 and the transistor mn9, push-pull. The data signal DQ is output by the method. The operation method of the first driver circuit 110 when the first pre-driver control signal TmSRt and the first pre-driver control signal TmSRc are at different logic levels will be described in detail in the comparison of FIGS. 3 and 5.

4, FIG. 4 shows a block diagram of a second driver circuit in the embodiment of the present invention. The second driver circuit 120 includes a second pre-driver 410 and a second output stage 430.

The second pre-driver 410 receives the read signal DataP / DataN and the second pre-driver control signal ZqNEnt / ZqPEnc to turn the second pre-driver 410 on or off. When turned on, the second pre-driver 410 generates a second output stage control signal DP2 / DN2.

The second output stage 430 is coupled to the second pre-driver 410, and the second output stage 430 generates a data signal DQ based on the second output stage control signal DP2 / DN2.

5 shows a schematic diagram of the second driver circuit in the embodiment of the present invention. Referring to FIGS. 4 and 5 at the same time, it should be noted that in the embodiment of this example, FIG. 4 may show the second output stage 430 of FIG. 5 and a second pre-driver 410＿1 coupled thereto. , The second output stage 430 and the second pre-driver 410 ＿ 2 coupled thereto may be represented. 4 shows the second output driver 410 of FIG. 5 and the second pre-driver 410 # 1 coupled thereto, the second pre-driver 410 includes a read signal DataP and a second pre-driver control signal ZqNEnt And the second pre-driver 410 # 1 is turned on or off. When turned on, the second pre-driver 410 # 1 generates the second output stage control signal DP2. Meanwhile, FIG. 4 shows the second output driver 410 of FIG. 5 and the second pre-driver 410 ＿ 2 coupled thereto, the second pre-driver 410 controls the read signal DataN and the second pre-driver The signal ZqNEnc is received, and the second pre-driver 410 # 2 is turned on or off to generate the second output stage control signal DN2. In the embodiment, the second output stage 430 generates a data signal DQ based on the second output stage control signal DP2 and the second output stage control signal DN2.

Referring to FIG. 5, the second driver circuit 120 includes a second pre-driver 410＿1, a second pre-driver 410＿2, and a second output stage 430. The second pre-driver 410 ＿ 1 is coupled to the transistor mp9 of the second output stage 430, and the second pre-driver 410 ＿ 2 is coupled to the transistor mn9 of the second output stage 430.

The second free driver 410 # 1 includes an inverter (transistor mp1 and transistor mn7) of the second free driver 410_1, a first switch (transistor mn8), and a second switch (transistor mp6).

The inverter of the second pre-driver 410 ＿ 1 is constituted by the combination of the transistor mp1 and the transistor mn7, the gate of the transistor mp1 and the gate of the transistor mn7 are mutually coupled, used to receive the read signal DataP, and the source of the transistor mp1 Is coupled to the power supply voltage VDD, and the drain of the transistor mp1 and the drain of the transistor mn7 are mutually coupled.

For the transistor mn8, which is the first switch of the second pre-driver 410 # 1, the source of the transistor mn8 is coupled to the source of the transistor mn7, and the gate of the transistor mn8 receives the second pre-driver control signal ZqNEnt, so that the transistor mn8 Turn on or off, and the source of the transistor mn8 is coupled to the power supply voltage VSS.

For the transistor mp6 which is the second switch of the second pre-driver 410 # 1, the gate of the transistor mp6 is coupled to the gate of the transistor mn8, receives the second pre-driver control signal ZqNEnt, and turns the transistor mp6 on or off. , The source of the transistor mp6 is coupled to the power supply voltage VDD, and the drain of the transistor mp6 is coupled to the drain of the transistor mp1 and the drain of the transistor mn7.

In the embodiment of this example, when the second pre-driver 410 # 1 is turned on by the read signal DataP / DataN and the second pre-driver control signal ZqNEnt, it generates the second output stage control signal DP2.

The second free driver 410 # 2 includes an inverter (transistor mp8 and transistor mn1), a first switch (transistor mp7), and a second switch (transistor mn6). The second free driver 410＿2 is a complementary form of the second free driver 410＿1, and is not described repeatedly.

In the embodiment of this example, the second pre-driver 410 ＿ 2 combines the inverter (transistor mp8 and transistor mn1), the first switch (transistor mp7), and the second switch (transistor mn6) to obtain the second output stage control signal DN2. To create.

The second output stage 430 includes a transistor mp9 and a transistor mn9, the transistor mp9 is a P-type transistor, the transistor mn9 is an N-type transistor, and the drain of the transistor mp9 is coupled to the drain of the transistor mn9.

In the embodiment of the present example, the second output stage 430 receives the second output stage control signal DP2 and the second output stage control signal, and through the transistor mp9 and the transistor mn9, in a push-pull method. To output the data signal DQ.

Referring to FIG. 5, in the embodiment of the present example, when the second pre-driver control signal ZqNEnt is at a high logic level, and when the second pre-driver control signal ZqPEnc is at a low logic level, the transistor mn8 is on, and the transistor mp6 is off. , Transistor mp7 is on, transistor mn6 is off. At this time, the second pre-driver 410＿1 and the second pre-driver 410＿2 are on, and the second pre-driver 410＿1 is equivalent to the inverter constituted by the transistor mp1 and the transistor mn7, and the second free driver. The driver 410 ＿ 2 is equivalent to the inverter constituted by the transistor mp8 and the transistor mn1. The second pre-driver 410 # 1 generates the second output stage control signal DP2, and the second pre-driver 410 # 2 generates the second output stage control signal DN2, and push-pulls it to the second output stage 430 The data signal DQ is output by the method. At this time, the second driver circuit 120 is in an active state, and may provide a driving force to the off-chip driver 100.

Conversely, the second pre-driver control signal ZqNEnt is at a low logic level, and when the second pre-driver control signal ZqPEnc is at a high logic level, transistor mn8 is off, transistor mp6 is on, transistor mp7 is off, and the transistor is mn6 is on. At this time, the inverters (transistor mp1 and transistor mn7) are opened because transistor mn8 is off, and transistor mp6 is on, so the second output stage control signal DP2 is set to a high logic level. Since the inverter (transistor mp8 and transistor mn1) is open because transistor mp7 is off, and transistor mn6 is on, the second output stage control signal DN2 is set to a low logic level. Since the second output stage control signal DP2 is at a high logic level, and the second output stage control signal DN2 is at a low logic level, both the transistor mp9 and the transistor mn9 are in an off state, so the second output stage 430 is data The signal DQ cannot be output. At this time, the second driver circuit 120 is in an invalid state and cannot provide a driving force to the off-chip driver 100.

Referring to FIGS. 1 and 5 at the same time, the greater the number of Ons of the second driver circuits 120＿1 to 120＿n, the higher the driving force provided by the off-chip driver 100 is. Conversely, the smaller the number of on-ins of the second driver circuits 120＿1 to 120＿n, the lower the driving force provided by the off-chip driver 100 is.

Referring to FIG. 3, in the embodiment, the first driver circuit 110 may be a driving force adjustment mode or a slew rate adjustment mode based on the first pre-driver control signal TmSRt and the first pre-driver control signal TmSRc.

Referring to FIG. 3, in the embodiment of the present example, when the first pre-driver control signal TmSRt is at a high logic level and the first pre-driver control signal TmSRc is at a low logic level, the first driver circuit 110 is in a driving force adjustment mode. . At this time, the transistor mn3 of the first pre-driver 210＿1 is on, the transistor mp6 is off, the transistor mp2 is on, and the transistor mn6 is off. In the embodiment, the sum of the layout widths of transistors mn2 and mn4 of the first driver circuit 110 may be the same as the layout width of the transistor mn7 of the second driver circuit 120, and the first driver circuit The sum of the layout widths of transistor mn3 and transistor mn5 in (110) may be the same as the layout width of transistor mn8. In addition, the operation of the first pre-driver 210＿2 is the same as that of the first pre-driver 210＿1, and the layout width of the first pre-driver 210＿2 and the switch row 220＿2 of the first driver circuit 110 is detailed. It is arranged as described above and is not described repeatedly. Therefore, the equivalent circuit of the first driver circuit 110 in the driving force adjustment mode is the same as the second driver circuit 120. Therefore, the timing of the first driver circuit 110 in the driving force adjustment mode is the same as the second driver circuit 120, and the driving force of the off-chip driver 100 can be adjusted.

Conversely, when the first pre-driver control signal TmSRt is at a low logic level, and the first pre-driver control signal TmSRc is at a high logic level, the first driver circuit 110 is in a slew rate adjustment mode. At this time, the transistor mn3 of the first pre-driver 210＿1 is off, the transistor mp6 is on, the transistor mp2 is off, and the transistor mn6 is on. In the embodiment, the sum of the layout widths of the transistors mn2 and mn4 may be the same as the transistor mn7, and the sum of the layout widths of the transistors mn3 and mn5 may be the same as the transistor mn8. At this time, the first pre-driver 210＿1 and the switch column 220＿1 are equivalent to the divided structure consisting of the transistor mp6, the transistor mn4, and the transistor mn5, and the divided voltage structure divides the power supply voltage VDD. The layout width of transistor mn4 is smaller than transistor mn7, and the layout width of transistor mn5 is smaller than transistor mn8, so the on resistance of transistors mn4 and mn5 is greater than the on resistance of transistors mn7 and mn8, which , Increases the voltage of the first output stage control signal DP1. The operation of the first pre-driver 210＿2 and the switch column 220＿2 is the same as that of the first pre-driver 210＿1 and the switch column 220＿1, and is not described repeatedly. The layout width of the transistor mn4 is smaller than that of the transistor mn7. , Since the layout width of the transistor mn5 is smaller than that of the transistor mn8, and the on resistance of the transistors mn4 and mn5 is greater than that of the transistors mn7 and mn8, the voltage of the first output stage control signal DN1 is lowered.

Accordingly, by increasing the voltage of the first output stage control signal DP1 and decreasing the voltage of the first output stage control signal DN1, the on current of the first output stage 230 is reduced to lower the slew rate and shift. Increase time. Therefore, the first driver circuit 110 in the slew rate adjustment mode can adjust the slew rate of the off-chip driver 100.

As should be mentioned, even if the first driver circuit 110 is in the driving force adjustment mode or the slew rate adjustment mode, the first driver circuit 110 is always valid.

Referring to FIG. 6, FIG. 6 shows a timing diagram of the off-chip driver in the embodiment of the present invention. In the embodiment, the off-chip driver 100 includes a non-test mode and a test mode. In the non-test mode, the first driver circuit 110 is a driving force adjustment mode. In the test mode, the first driver circuit 110 is a slew rate adjustment mode. The timing of the non-test mode includes a data signal V (DQ ＠ 110) output by the first driver circuit in the non-test mode, and a data signal V (DQ ＠ 120) output by the second driver circuit in the non-test mode, and And the data signal V (DQ) of the off-chip driver in the test mode. The timing of the test mode includes the data signal V (DQ ＠ 110) ＿T output from the first driver circuit in the test mode, the data signal V (DQD120＿1) ＿T output from the second driver circuit in the test mode, and the test mode. It includes the off-chip driver's data signal V (DQ) ＿ T at. Here, the data signal V (DQ # 120) output by the second driver circuit in the non-test mode is a data signal DQ output by driver circuits other than the first driver circuit 110 in the non-test mode. The data signal V (DQ ＠ 120＿1) ＿T output by the second driver circuit in the test mode is the data signal DQ output by the second driver circuit 120＿1 in the test mode.

In the non-test mode, the first driver circuit 110 is a driving force adjustment mode, and the transition time is a time between time T1 to time T3. In the test mode, the first driver circuit 110 is a slew rate adjustment mode, and the data signal V (DQ ＠ 110) DT output by the first driver circuit in the test mode and the off-chip driver data signal V ( The transition time of DQ) #T becomes long and is a time between time T1 to time T4. Therefore, the slew rate of the first driver circuit 110 and the off-chip driver 100 decreases when the first driver circuit 110 is in the slew rate adjustment mode.

Referring to Fig. 7, Fig. 7 shows a first driver circuit in another embodiment of the present invention. In another embodiment, in order to reduce the number of transistors and layout area, the first driver circuit 110 may be arranged so as not to have a slew rate adjustment mode. In another embodiment, the first driver circuit 110 has only the first pre-driver 710＿1, the first pre-driver 710＿2, and the first output stage 730. In addition, the first pre-driver 710＿1 of the first driver circuit 110 has only the inverters (transistor mp1 and transistor mn7), and does not have a first switch and a second switch. The first free driver 710＿2 of the first driver circuit 110 is the same, and is not described repeatedly.

From the above, in the present invention, the off-chip driver includes a first driver circuit that adjusts the slew rate, and is used to improve signal quality. The first driver circuit adopts a divided voltage structure, so there is no need to add a delay circuit, and power consumption and layout area can be reduced. In the present invention, since the slew rate adjustment effect in the high threshold voltage manufacturing process and the low threshold voltage manufacturing process is symmetrical, control of the slew rate can be maintained under fluctuations in the manufacturing process. Further, the present invention can further include a second driver circuit to adjust the driving force of the off-chip driver.

Although the text has been shown as in the above embodiments, the scope of protection of the present invention is ionized because it is not intended to limit the present invention, but can be changed or modified without departing from the scope of the spirit of the present invention. It is based on what was limited in the claims.

The present invention adjusts the slew rate of the off-chip driver by the first driver circuit, making it easy to transfer data from the memory to the host computer and improve signal quality. The first driver circuit can reduce the power consumption and layout area without applying a voltage divider structure and adding a delay circuit. The slew rate adjustment effect in the high threshold voltage manufacturing process and the low threshold voltage manufacturing process is symmetrical, and the present invention can maintain control of the slew rate under fluctuations in the manufacturing process. Further, the present invention can further include a second driver circuit to adjust the driving force of the off-chip driver.

100: off-chip driver
110: first driver circuit
120, 120＿1 to 120＿n: second driver circuit
210, 210＿1, 210＿2: first free driver
220, 210＿1, 220＿2: switch column
230: first output stage
410, 410＿1, 410＿2: second free driver
430: second output stage
710＿1, 710＿2: first free driver
730: first output stage
DataP, DataN: Poison signal
TmSRt, TmSRc: first pre-driver control signal
ZqNEnt, ZqNEnc, ZqNEnt <1>, ZqNEnc <1> ... … ZqNEnt <n>, ZqNEnc <n>: second pre-driver control signal
DQ: Data signal
VDD, VSS: Power supply voltage
DP1, DN1: first output stage control signal
DP2, DN2: Second output stage control signal
mp1, mp2, mp3, mp4, mp5, mp6, mp7, mp8, mp9, mn1, mn2, mn3, mn4, mn5, mn6, mn7, mn8, mn9: transistor
V (DQ ＠ 110): Data signal output by the first driver circuit in non-test mode
V (DQ ＠ 120): Data signal output by the second driver circuit in non-test mode
V (DQ): Off-chip driver's data signal in non-test mode
V (DQ ＠ 110) ＿T: Data signal output from the first driver circuit in test mode
V (DQ ＠ 120＿1) ＿T: Data signal output by the second driver circuit in test mode
V (DQ) ＿T: Off-chip driver's data signal in test mode
T1, T2, T3, T4: time

Claims (11)

In the off-chip driver applied to the memory,
And a first driver circuit used to adjust the slew rate of the off-chip driver, the first driver circuit comprising:
A first pre-driver used to receive the read signal and a first pre-driver control signal,
A switch column arranged to combine the first pre-driver and divide the power supply voltage based on the read signal to generate a first output stage control signal,
An off-chip driver that is coupled to the first pre-driver and the switch row and comprises a first output stage that generates a data signal based on the first output stage control signal. According to claim 1,
The first free driver,
An inverter that receives the read signal,
A first switch coupled to the inverter and turned on or off based on the first pre-driver control signal;
An off-chip driver including a second switch coupled to the inverter and the first switch, and turning on or off based on the first pre-driver control signal. According to claim 2,
The switch column,
A third switch coupled to the first pre-driver and turning on or off based on the read signal,
An off-chip driver including a fourth switch coupled to the third switch and turning on or off based on the power supply voltage. According to claim 1,
The first driver circuit is an off-chip driver that is a driving force adjustment mode or a slew rate adjustment mode based on the first pre-driver control signal. According to claim 1,
The first output stage includes a P-type transistor and an N-type transistor, and the drain of the P-type transistor is coupled to the drain of the N-type transistor. According to claim 1,
The first driver circuit is an off-chip driver that is always valid. The method of claim 6,
Mutually parallel, further comprising a plurality of second driver circuits used to adjust the driving force of the off-chip driver, each of the plurality of second driver circuits comprising:
A second pre-driver that receives the read signal and a second pre-driver control signal, turns it on or off, and when on, generates a second output stage control signal;
An off-chip driver, coupled to the second pre-driver, comprising a second output stage that generates the data signal based on the second output stage control signal. The method of claim 7,
The second free driver,
An inverter that receives the read signal,
A first switch coupled to the inverter and turned on or off based on the second pre-driver control signal;
An off-chip driver including a second switch coupled to the inverter and the first switch and turning on or off based on the second pre-driver control signal. The method of claim 7,
The plurality of second driver circuits are off-chip drivers mutually parallel with the first driver circuit. The method of claim 7,
The second output stage includes a P-type transistor and an N-type transistor, and the drain of the P-type transistor is coupled to the drain of the N-type transistor. The method of claim 7,
When one of the plurality of second driver circuits is enabled by the second pre-driver control signal, and when the first pre-driver control signal and the second pre-driver control signal are at the same logic level,
The timings of the second driver circuit and the first driver circuit are the same off-chip driver.

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