CN110838316B - Off-chip driver - Google Patents
Off-chip driver Download PDFInfo
- Publication number
- CN110838316B CN110838316B CN201810935330.8A CN201810935330A CN110838316B CN 110838316 B CN110838316 B CN 110838316B CN 201810935330 A CN201810935330 A CN 201810935330A CN 110838316 B CN110838316 B CN 110838316B
- Authority
- CN
- China
- Prior art keywords
- driver
- control signal
- transistor
- switch
- output stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides an off-chip driver, which comprises a first driving circuit, wherein the first driving circuit is used for adjusting the rotation rate of the off-chip driver. The first driving circuit comprises a first predriver, a switch string and a first output stage. The first predriver receives a read signal and a first predriver control signal. The switch string is configured to divide the power supply voltage in combination with the first pre-driver according to the read signal to generate a first output stage control signal. The first output stage generates a data signal according to the first output stage control signal.
Description
Technical Field
The present invention relates to an off-chip driver, and more particularly, to an off-chip driver with adjustable slew rate.
Background
Off-chip drivers are used in Dynamic Random Access Memory (DRAM) to transfer data from the memory to a host. Wherein, the Slew Rate (Slew Rate) and the driving force of the off-chip driver are specified by Joint Electron Device Engineering Commission (JEDEC) standards. These parameters are affected by process, voltage and temperature.
Generally, the slew rate of the off-chip driver is adjusted by controlling the gate signal of the output stage in the off-chip driver, however, the actual output of the off-chip driver is shifted due to process variation (process variation). Another way is to control the enabling time of the off-chip driver, but this way needs to additionally design the enabling time adjusting circuit, and it is difficult to adjust the timing of the enabling time adjusting circuit in consideration of process variation.
Furthermore, based on the importance of the current time-rate variability dI/dt to Signal Integrity (SI), it is not sufficient to keep the JEDEC specification for high speed Input/output circuits (IO circuits). Therefore, the high-speed input/output circuit also needs to be designed with a precise slew rate adjustment circuit.
Disclosure of Invention
The invention provides an off-chip driver, which can adjust the slew rate without increasing the power consumption and layout area by using a slew rate adjusting circuit.
The invention provides an off-chip driver which is suitable for a memory and comprises a first driving circuit, wherein the first driving circuit is used for adjusting the rotation rate of the off-chip driver. The first drive circuit includes: the circuit comprises a first predriver, a switch string and a first output stage. The first predriver receives a read signal and a first predriver control signal. The switch string is coupled to the first pre-driver and configured to divide the power supply voltage in combination with the first pre-driver according to the read signal to generate a first output stage control signal. The first output stage is coupled to the first pre-driver and the switch string, and generates a data signal according to a first output stage control signal.
Based on the above, in the present invention, the off-chip driver can adjust the slew rate by applying the voltage division operation of the first pre-driver and the switch string, and the power consumption and the layout area are not increased. Due to the symmetrical circuit structure, the control of the slew rate can be maintained under the process variation.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 shows a schematic diagram of an off-chip driver in an embodiment of the invention.
Fig. 2 is a block diagram of a first driving circuit according to an embodiment of the invention.
Fig. 3 shows a schematic diagram of a first driving circuit in an embodiment of the invention.
Fig. 4 is a block diagram of a second driving circuit according to an embodiment of the invention.
Fig. 5 shows a schematic diagram of a second driving circuit in an embodiment of the invention.
FIG. 6 shows a timing diagram of an off-chip driver in an embodiment of the invention.
Fig. 7 shows a schematic diagram of a first driving circuit in another embodiment of the invention.
[ notation ] to show
100: off-chip driver
110: first drive circuit
120. 120 u 1 to 120 u n: second drive circuit
210. 210, 2: first predriver
220. 220_1, 220_2: switch string
230: a first output stage
410. 410_1, 410_2: second predriver
430: second output stage
710_1, 710_2: first predriver
730: a first output stage
DataP, dataN: reading signals
TmSRt, tmSRc: first predriver control signal
ZqNEnt, zqPENc, zqNEnt <1>, zqPENc <1> … … ZqNEnt < n >, zqPENc < n >: second predriver control signal
DQ: data signal
VDD, VSS: supply voltage
DP1, DN1: first output stage control signal
DP2, DN2: second output stage control signal
mp1, mp2, mp3, mp4, mp5, mp6, mp7, mp8, mp9, mn1, mn2, mn3, mn4, mn5, mn6, mn7, mn8, mn9: transistor with a high breakdown voltage
V (DQ @ 110): data signal output by the first driving circuit in non-test mode
V (DQ @ 120): data signal output by the second driving circuit in non-test mode
V (DQ): data signal of off-chip driver in non-test mode
V (DQ @ 110) _ T: data signal output by the first driving circuit in test mode
V (DQ @120_ 1) _ T: data signal output by the second driving circuit in test mode
V (DQ) _ T: data signal of off-chip driver in test mode
T1, T2, T3, T4: time of day
Detailed Description
Referring to fig. 1, the off-chip driver 100 includes a first driving circuit 110 and a plurality of second driving circuits 120 u 1 to 120 u n. The first driving circuit 110 is used for adjusting the slew rate of the off-chip driver 100, and the plurality of second driving circuits 120 u 1 to 120 u n are used for adjusting the driving force of the off-chip driver 100.
In the present embodiment, the plurality of second driving circuits 120 _1to 120 _nare connected in parallel with each other, and the plurality of second driving circuits 120 _1to 120 _nand the first driving circuit 110 are connected in parallel with each other.
The first driving circuit 110 receives the read signal DataP/DataN, the first predriver control signal TmSRt, and the first predriver control signal TmSRc to generate the data signal DQ. The second driving circuit 120 u 1 receives the read signal DataP/DataN, the second pre-driver control signal Zqnent <1>, and the second pre-driver control signal ZqPENc <1> to generate the data signal DQ. The second driving circuit 120\ n receives the read signal DataP/DataN, the second pre-driver control signal Zqnent < n >, and the second pre-driver control signal ZqPENc < n > to generate the data signal DQ. The second driving circuits 120 _2-120 _n-1 (not shown) can be analogized, and thus, the description is omitted. The number n of the second driving circuits may be set according to actual requirements, and is not particularly limited.
Referring to fig. 2 and 3, in the present example embodiment, the first driving circuit 110 includes a first pre-driver 210, a switch string 220 and a first output stage 230. The first predriver 210 receives the read signal DataP/DataN and the first predriver control signal TmSRt/TmSRc. The switch string 220 is coupled to the first pre-driver 210, and configured to divide the power voltage VDD according to the read signal DataP/DataN in combination with the first pre-driver 210 to generate the first output stage control signal DP1/DN1. The first output stage 230 is coupled to the first pre-driver 210 and the switch string 220, and the first output stage 230 generates the data signal DQ according to the first output stage control signal DP1/DN1.
Referring to fig. 2 and 3, fig. 2 may show the first output stage 230 and the coupled first pre-driver 210_1 and switch string 220_1 in fig. 3, and may also show the first output stage 230 and the coupled first pre-driver 210 _u2 and switch string 220 _u2. In one embodiment, the first output stage 230 generates the data signal DQ according to a first output stage control signal DP1 and a first output stage control signal DN1.
Referring to fig. 3, the first driving circuit 110 includes a first pre-driver 210_1, a first pre-driver 210_2, a switch string 220_1, a switch string 220_2, and a first output stage 230. The first pre-driver 210_1 and the switch string 220_1 are coupled to the transistor mp9 of the first output stage 230, and the first pre-driver 210 _2and the switch string 220 _2are coupled to the transistor mn9 of the first output stage 230.
The first pre-driver 210\ u 1 includes an inverter, a first switch, and a second switch.
The inverter of the first pre-driver 210\ u 1 is formed by coupling a transistor mp1 and a transistor mn2, wherein a gate of the transistor mp1 and a gate of the transistor mn2 are coupled to each other for receiving the read signal DataP, a source of the transistor mp1 is coupled to the power voltage VDD, and a drain of the transistor mp1 and a drain of the transistor mn2 are coupled to each other.
The first switch of the first pre-driver 210_1 is a transistor mn3, a drain of the transistor mn3 is coupled to a source of the transistor mn2, a gate of the transistor mn3 receives a first pre-driver control signal TmSRt to turn on or off the transistor mn3, and a source of the transistor mn3 is coupled to the power supply voltage VSS.
A second switch of the first pre-driver 210_1 is a transistor mp6, a gate of the transistor mp6 is coupled to a gate of the transistor mn3 to receive the first pre-driver control signal TmSRt to turn on or off the transistor mp6, a source of the transistor mp6 is coupled to the power supply voltage VDD, and a drain of the transistor mp6 is coupled to a drain of the transistor mp1 and a drain of the transistor mn 2.
The switch string 220_1 includes a third switch and a fourth switch.
The third switch of the switch string 220 _1is a transistor mn4, a drain of the transistor mn4 is coupled to the drain of the transistor mp6, the drain of the transistor mp1, and the drain of the transistor mn2, and a gate of the transistor mn4 receives the read signal DataP to turn on or off the transistor mn4.
The fourth switch of the switch string 220 _u1 is the transistor mn5, the drain of the transistor mn5 is coupled to the source of the transistor mn4 in the switch string 220 _u1, the gate of the transistor mn5 receives the power voltage VDD to turn on the transistor mn5, and the source of the transistor mn5 is coupled to the power voltage VSS.
In this embodiment, the switch string 220_1 combines the inverter, the first switch, and the second switch of the first pre-driver 210 _1to generate the first output stage control signal DP1.
The first pre-driver 210_2 includes an inverter, a first switch, and a second switch. The first pre-driver 210_2 is a complementary type of the first pre-driver 210_1, and will not be described in detail.
The switch string 220_2 includes a third switch (transistor mp 4) and a fourth switch (transistor mp 5). The switch string 220 _u2 is a complementary type of the switch string 220 _u1, and will not be described again.
In the present embodiment, the switch string 220 (transistors mp4 and mp 5) combines the inverter (transistors mn1 and mp 3), the first switch (transistor mp 2) and the second switch (transistor mn 6) of the first pre-driver 210 (u 2) to generate the first output stage control signal DN1.
The first output stage 230 includes a transistor mp9 and a transistor mn9, wherein the transistor mp9 is a P-type transistor, the transistor mn9 is an N-type transistor, and a drain of the transistor mp9 is coupled to a drain of the transistor mn9.
In this embodiment, the first output stage 230 receives the first output stage control signal DP1 and the first output stage control signal DN1, and outputs the data signal DQ in a push-pull (push-pull) manner through the transistors mp9 and mn9. The operation of the first driving circuit 110 when the first predriver control signal TmSRt and the first predriver control signal TmSRc are at different logic levels will be described in detail in comparing fig. 3 and 5.
Referring to fig. 4, the second driving circuit 120 includes a second predriver 410 and a second output stage 430.
The second pre-driver 410 receives the read signal DataP/DataN and the second pre-driver control signal Zqnent/ZqPENc to turn on or off the second pre-driver 410. When the second pre-driver 410 is turned on, the second output stage control signal DP2/DN2 is generated.
The second output stage 430 is coupled to the second pre-driver 410, and the second output stage 430 generates the data signal DQ according to the second output stage control signal DP2/DN2.
Referring to fig. 4 and 5, it should be noted that, in the exemplary embodiment, fig. 4 may represent the second output stage 430 and the coupled second pre-driver 410\ u 1 in fig. 5, and may also represent the second output stage 430 and the coupled second pre-driver 410_2. In one embodiment, the second output stage 430 generates the data signal DQ according to a second output stage control signal DP2 and a second output stage control signal DN2.
Referring to fig. 5, the second driving circuit 120 includes a second pre-driver 410_1, a second pre-driver 410_2, and a second output stage 430. The second pre-driver 410_1 is coupled to the transistor mp9 of the second output stage 430, and the second pre-driver 410 _2is coupled to the transistor mn9 of the second output stage 430.
The second pre-driver 410_1 includes an inverter, a first switch, and a second switch (transistor mp 6) of the second pre-driver 410_1.
The inverter of the second pre-driver 410\ u 1 is formed by coupling a transistor mp1 and a transistor mn7, wherein a gate of the transistor mp1 and a gate of the transistor mn7 are coupled to each other for receiving the read signal DataP, a source of the transistor mp1 is coupled to the power voltage VDD, and a drain of the transistor mp1 and a drain of the transistor mn7 are coupled to each other.
The first switch of the second pre-driver 410\ u 1 is a transistor mn8, a drain of the transistor mn8 is coupled to a source of the transistor mn7, a gate of the transistor mn8 receives a second pre-driver control signal ZqNEnt to turn on or off the transistor mn8, and a source of the transistor mn8 is coupled to the power supply voltage VSS.
The second switch of the second pre-driver 410 u 1 is a transistor mp6, a gate of the transistor mp6 is coupled to a gate of the transistor mn8 for receiving the second pre-driver control signal ZqNEnt to turn on or off the transistor mp6, a source of the transistor mp6 is coupled to the power supply voltage VDD, and a drain of the transistor mp6 is coupled to a drain of the transistor mp1 and a drain of the transistor mn 7.
In the present exemplary embodiment, the second output stage control signal DP2 is generated when the second pre-driver 410_1 is turned on by the read signal DataP/DataN and the second pre-driver control signal ZqNEnt.
The second pre-driver 410 u 2 includes an inverter (transistor mp8 and transistor mn 1), a first switch (transistor mp 7) and a second switch (transistor mn 6). The second pre-driver 410_2 is a complementary type of the second pre-driver 410_1, and will not be described in detail.
In the present exemplary embodiment, the second pre-driver 410 u 2 combines the inverter (transistors mp8 and mn 1), the first switch (transistor mp 7) and the second switch (transistor mn 6) to generate the second output stage control signal DN2.
The second output stage 430 includes a transistor mp9 and a transistor mn9, wherein the transistor mp9 is a P-type transistor, the transistor mn9 is an N-type transistor, and a drain of the transistor mp9 is coupled to a drain of the transistor mn9.
In the present exemplary embodiment, the second output stage 430 receives the second output stage control signal DP2 and the second output stage control signal DN2, and outputs the data signal DQ in a push-pull (push-pull) manner through the transistors mp9 and mn9.
Referring to fig. 5, in the present exemplary embodiment, when the second pre-driver control signal ZqNEnt is at a high logic level and the second pre-driver control signal ZqPEnc is at a low logic level, the transistor mn8 is turned on and the transistor mp6 is turned off, the transistor mp7 is turned on and the transistor mn6 is turned off. At this time, the second pre-driver 410_1 and the second pre-driver 410_2 are turned on, the second pre-driver 410 _u1 is equivalent to an inverter composed of a transistor mp1 and a transistor mn7, and the second pre-driver 410 _u2 is equivalent to an inverter composed of a transistor mp8 and a transistor mn 1. The second pre-driver 410 u 1 generates a second output stage control signal DP2 and the second pre-driver 410 u 2 generates a second output stage control signal DN2 for the second output stage 430 to output the data signal DQ in a push-pull manner. At this time, the second driving circuit 120 is in an enabled state, and can provide a driving force for the off-chip driver 100.
Conversely, when the second pre-driver control signal ZqNEnt is at a low logic level and the second pre-driver control signal ZqPEnc is at a high logic level, the transistor mn8 is turned off and the transistor mp6 is turned on, the transistor mp7 is turned off and the transistor mn6 is turned on. At this time, the inverter (the transistor mp1 and the transistor mn 7) is turned off by the transistor mn8 being turned off, and the transistor mp6 is turned on so that the second output stage control signal DP2 is at a high logic level. The inverter (the transistor mp8 and the transistor mn 1) is turned off by the transistor mp7 being turned off, and the transistor mn6 is turned on so that the second output stage control signal DN2 is at a low logic level. The second output stage control signal DP2 is at a high logic level and the second output stage control signal DN2 is at a low logic level, so that the transistor mp9 and the transistor mn9 are both turned off, and thus the second output stage 430 cannot output the data signal DQ. At this time, the second driving circuit 120 is disabled and cannot provide the driving force for the off-chip driver 100.
Referring to fig. 1 and 5, as the number of the plurality of second driving circuits 120_1-120 _nis greater, the driving force provided by the off-chip driver 100 is higher. Conversely, the fewer the number of turns on in the plurality of second driver circuits 120_1-120_n, the lower the driving force provided by the off-chip driver 100.
Referring to fig. 3, in an embodiment, the first driving circuit 110 may be in a driving force adjustment mode or a slew rate adjustment mode according to the first predriver control signal TmSRt and the first predriver control signal TmSRc.
Referring to fig. 3, in the present exemplary embodiment, when the first predriver control signal TmSRt is at a high logic level and the first predriver control signal TmSRc is at a low logic level, the first drive circuit 110 is in the driving force adjustment mode. At this time, the transistor mn3 of the first pre-driver 210\ u 1 is turned on and the transistor mp6 is turned off, and the transistor mp2 is turned on and the transistor mn6 is turned off. In an embodiment, the sum of the layout widths (width size) of the transistors mn2 and mn4 in the first driving circuit 110 may be equal to the layout width of the transistor mn7 in the second driving circuit 120, and the sum of the layout widths of the transistors mn3 and mn5 in the first driving circuit 110 may be equal to the layout width of the transistor mn8. In addition, the operation of the first pre-driver 210_2 is similar to the first pre-driver 210_1, and the layout width configuration of the first pre-driver 210 _u2 and the switch string 220 _u2 in the first driving circuit 110 is the same as above, and will not be described again. Therefore, the equivalent circuit of the first driving circuit 110 in the driving force adjustment mode is the same as that of the second driving circuit 120. Therefore, the first driving circuit 110 in the driving force adjusting mode has the same timing as the second driving circuit 120, and can be used to adjust the driving force of the off-chip driver 100.
Conversely, when the first predriver control signal TmSRt is at a low logic level and the first predriver control signal TmSRc is at a high logic level, the first drive circuit 110 is in slew rate adjustment mode. At this time, the transistor mn3 of the first pre-driver 210\ u 1 is turned off and the transistor mp6 is turned on, and the transistor mp2 is turned off and the transistor mn6 is turned on. In one embodiment, the sum of the layout widths (width size) of the transistors mn2 and mn4 can be equal to the transistor mn7, and the sum of the layout widths of the transistors mn3 and mn5 can be equal to the transistor mn8. At this time, the first pre-driver 210 _1and the switch string 220 _1are equivalent to a voltage division structure composed of the transistor mp6, the transistor mn4 and the transistor mn5, and the voltage division structure performs a voltage division operation on the power voltage VDD. Since the layout width of the transistor mn4 is smaller than that of the transistor mn7, and the layout width of the transistor mn5 is smaller than that of the transistor mn8, the on-resistances of the transistor mn4 and the transistor mn5 are larger than those of the transistor mn7 and the transistor mn8, which causes the voltage of the first output stage control signal DP1 to rise. The operation of the first pre-driver 210 _2and the switch string 220 _2is not described in detail as the above-mentioned first pre-driver 210 _1and the switch string 220 _1. Since the layout width of the transistor mp4 is smaller than that of the transistor mp7, and the layout width of the transistor mp5 is smaller than that of the transistor mp8, the on-resistances of the transistor mp4 and the transistor mp5 are larger than those of the transistor mp7 and the transistor mp8, which causes the voltage of the first output stage control signal DN1 to drop.
Accordingly, the voltage rise of the first output stage control signal DP1 and the voltage fall of the first output stage control signal DN1 cause the on-current of the first output stage 230 to fall, so as to reduce the slew rate and increase the slew time. Therefore, the first driving circuit 110 can be used to adjust the slew rate of the off-chip driver 100 in the slew rate adjustment mode.
It should be noted that the first driving circuit 110 is always enabled no matter whether it is in the driving force adjusting mode or the slew rate adjusting mode.
Referring to fig. 6, in an embodiment, the off-chip driver 100 includes a non-test mode and a test mode. In the non-test mode, the first drive circuit 110 is in the drive force adjustment mode. In the test mode, the first driving circuit 110 is in the slew rate adjustment mode. The timing sequence of the non-test mode comprises a data signal V (DQ @ 110) output by the first driving circuit in the non-test mode, a data signal V (DQ @ 120) output by the second driving circuit in the non-test mode and a data signal V (DQ) of the off-chip driver in the non-test mode. The timing sequence of the test mode comprises a data signal V (DQ @ 110) _ T output by the first driving circuit in the test mode, a data signal V (DQ @120_ 1) _ T output by the second driving circuit in the test mode, and a data signal V (DQ) _ T of the off-chip driver in the test mode. The data signal V (DQ @ 120) output by the second driving circuit in the non-test mode is the data signal DQ output by other driving circuits other than the first driving circuit 110 in the non-test mode. The data signal V (DQ @120_ 1) _ T output by the second driving circuit in the test mode is the data signal DQ output by the second driving circuit 120 u 1 in the test mode.
In the non-test mode, the first driving circuit 110 is in the driving force adjustment mode, and the transition time is a time period between time T1 and time T3. In the test mode, since the first driving circuit 110 is in the slew rate adjustment mode, the transition time between the data signal V (DQ @ 110) _ T output by the first driving circuit in the test mode and the data signal V (DQ) _ T of the off-chip driver in the test mode is longer, which is the time period between time T1 and time T4. Therefore, when the first driving circuit 110 is in the slew rate adjustment mode, the slew rate of the first driving circuit 110 and the off-chip driver 100 is reduced. The time T2 is between the time T1 and the time T3, and is a time point of the transition process.
Referring to fig. 7, in another embodiment, in order to reduce the number of transistors and the layout area, the first driving circuit 110 may also be configured without the slew rate adjustment mode. In another embodiment, the first driving circuit 110 has only the first pre-driver 710_1, the first pre-driver 710_2, and the first output stage 730. In addition, the first pre-driver 710_1 in the first driving circuit 110 has only an inverter (composed of a transistor mp1 and a transistor mn 7) and does not have a first switch and a second switch. The first pre-driver 710_2 in the first driving circuit 110 is the same, and will not be described again.
In summary, in the present invention, the off-chip driver includes a first driving circuit for adjusting the slew rate to improve the signal integrity. The first driving circuit uses a voltage division structure without additionally adding a delay circuit, so that the power consumption and the layout area can be saved. Because the slew rate adjusting effect of the invention under the high threshold voltage process and the low threshold voltage process is symmetrical, the control of the slew rate can be kept under the process variation. Furthermore, the present invention may further include a second driving circuit to adjust a driving force of the off-chip driver.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (11)
1. An off-chip driver, suitable for use in a memory, comprising:
the first driving circuit is used for adjusting the turn rate of the off-chip driver and comprises:
a first pre-driver for receiving a read signal and a first pre-driver control signal;
the switch string is coupled with the first pre-driver, is configured to receive the reading signal, and is combined with a power supply voltage to perform voltage division operation by the first pre-driver according to the reading signal so as to generate a first output stage control signal; and
a first output stage coupled to the first pre-driver and the switch string for generating a data signal according to the first output stage control signal,
wherein the first predriver comprises:
an inverter receiving the read signal;
a first switch coupled to the inverter and turned on or off according to the first predriver control signal; and
a second switch coupled to the inverter and the first switch, turned on or off according to the first pre-driver control signal,
the first driving circuit determines whether to adjust the turn rate of the off-chip driver according to the first pre-driver control signal.
2. The off-chip driver of claim 1, wherein the switch string comprises:
a third switch coupled to the first pre-driver and turned on or off according to the read signal;
and the fourth switch is coupled with the third switch and is turned on according to the power voltage.
3. The off-chip driver of claim 1, wherein the first drive circuit is in a drive force adjustment mode or a slew rate adjustment mode as a function of the first predriver control signal.
4. The off-chip driver of claim 1, wherein the first output stage comprises a P-type transistor and an N-type transistor, wherein a drain of the P-type transistor is coupled to a drain of the N-type transistor.
5. The off-chip driver of claim 1, wherein the first drive circuit is always enabled.
6. The off-chip driver of claim 5, further comprising:
a plurality of second driving circuits connected in parallel to each other and used to adjust a driving force of the off-chip driver, each of the plurality of second driving circuits comprising:
the second predriver receives the reading signal and a second predriver control signal to be turned on or off, and generates a second output stage control signal when the second predriver is turned on; and
the second output stage is coupled to the second pre-driver and generates the data signal according to the second output stage control signal.
7. The off-chip driver of claim 6, wherein the second pre-driver comprises:
an inverter of the second predriver receiving the read signal;
a first switch of the second pre-driver coupled to the inverter of the second pre-driver, for turning on or off the first switch of the second pre-driver according to the second pre-driver control signal; and
a second switch of the second pre-driver, coupled to the inverter of the second pre-driver and the first switch of the second pre-driver, for turning on or off the second switch of the second pre-driver according to the second pre-driver control signal.
8. The off-chip driver of claim 6, wherein the plurality of second drive circuits and the first drive circuit are in parallel with each other.
9. The off-chip driver of claim 6, wherein the second output stage comprises a P-type transistor and an N-type transistor, wherein a drain of the P-type transistor is coupled to a drain of the N-type transistor.
10. The off-chip driver of claim 6, wherein when one of the plurality of second driving circuits is enabled by the second pre-driver control signal and the first and second pre-driver control signals are at the same logic level, the second driving circuit is at the same timing as the first driving circuit.
11. The off-chip driver of claim 1, wherein
When the first pre-driver control signal is at a high logic level, the first driving circuit is in a driving force adjusting mode to adjust the driving force of the off-chip driver; and
when the first pre-driver control signal is at a low logic level, the first driving circuit is in a slew rate adjustment mode to adjust the slew rate of the off-chip driver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810935330.8A CN110838316B (en) | 2018-08-16 | 2018-08-16 | Off-chip driver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810935330.8A CN110838316B (en) | 2018-08-16 | 2018-08-16 | Off-chip driver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110838316A CN110838316A (en) | 2020-02-25 |
| CN110838316B true CN110838316B (en) | 2023-04-18 |
Family
ID=69574120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810935330.8A Active CN110838316B (en) | 2018-08-16 | 2018-08-16 | Off-chip driver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110838316B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114448451B (en) * | 2020-11-04 | 2023-10-31 | 瑞昱半导体股份有限公司 | Transmitter with controllable slew rate |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090000511A (en) * | 2007-06-28 | 2009-01-07 | 주식회사 하이닉스반도체 | Data output driver circuit |
| JP2012119883A (en) * | 2010-11-30 | 2012-06-21 | Toshiba Corp | Semiconductor device |
| CN103093800A (en) * | 2011-11-07 | 2013-05-08 | 海力士半导体有限公司 | Semiconductor memory device |
| KR20140006459A (en) * | 2012-07-05 | 2014-01-16 | 에스케이하이닉스 주식회사 | Data output apparatus for semiconductor apparatus |
| CN105207658A (en) * | 2014-06-11 | 2015-12-30 | 华邦电子股份有限公司 | Output buffer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100408412B1 (en) * | 2001-06-02 | 2003-12-06 | 삼성전자주식회사 | Data output buffer for detecting variation of supply voltage |
| KR100640782B1 (en) * | 2004-04-16 | 2006-11-06 | 주식회사 하이닉스반도체 | A semiconductor memory device |
| JP2013187594A (en) * | 2012-03-06 | 2013-09-19 | Toshiba Corp | Interface circuit |
-
2018
- 2018-08-16 CN CN201810935330.8A patent/CN110838316B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090000511A (en) * | 2007-06-28 | 2009-01-07 | 주식회사 하이닉스반도체 | Data output driver circuit |
| JP2012119883A (en) * | 2010-11-30 | 2012-06-21 | Toshiba Corp | Semiconductor device |
| CN103093800A (en) * | 2011-11-07 | 2013-05-08 | 海力士半导体有限公司 | Semiconductor memory device |
| KR20140006459A (en) * | 2012-07-05 | 2014-01-16 | 에스케이하이닉스 주식회사 | Data output apparatus for semiconductor apparatus |
| CN105207658A (en) * | 2014-06-11 | 2015-12-30 | 华邦电子股份有限公司 | Output buffer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110838316A (en) | 2020-02-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9225334B2 (en) | Methods, integrated circuits, apparatuses and buffers with adjustable drive strength | |
| KR20090022108A (en) | Output driver in semiconductor memory device | |
| JP2011147038A (en) | Semiconductor device and data processing system including the same | |
| US20230370060A1 (en) | Semiconductor integrated circuit device and semiconductor system including the same | |
| US20150002206A1 (en) | Semiconductor device having level shift circuit | |
| KR100211758B1 (en) | Multi-power data buffer | |
| CN109949838B (en) | Gate signal generating circuit and semiconductor device including the same | |
| CN113970951B (en) | Clock distribution network, semiconductor device using the same, and semiconductor system | |
| CN110838316B (en) | Off-chip driver | |
| JP6538629B2 (en) | Semiconductor memory device | |
| US20030210090A1 (en) | Internal power voltage generating circuit of semiconductor memory device and internal power voltage controlling method thereof | |
| KR100996193B1 (en) | Output driving device | |
| US10001801B2 (en) | Voltage providing circuit | |
| KR102214629B1 (en) | Off-chip driver | |
| JP6743095B2 (en) | Off-chip driver | |
| KR20140002915A (en) | Power supply circuit | |
| US10777234B2 (en) | Off-chip driver | |
| JP2007149207A (en) | Semiconductor integrated circuit device | |
| KR940003399B1 (en) | Output buffer for low noise of data | |
| JP2011147037A (en) | Semiconductor device and data processing system including the same | |
| KR101559500B1 (en) | Circuit for driving bitline sense amplifier of semiconductor memory device and method of operating driver for bitline sense amplifier | |
| US5831450A (en) | System for improved response time output buffer unit having individual stages for signal generation and buffering and output stage applying signal determined by input signal | |
| JP2010041062A (en) | Level shift circuit | |
| JP2005217860A (en) | Delay circuit | |
| KR100865711B1 (en) | Output driver in dram |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |