CN114448451B - Transmitter with controllable slew rate - Google Patents
Transmitter with controllable slew rate Download PDFInfo
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- CN114448451B CN114448451B CN202011215764.4A CN202011215764A CN114448451B CN 114448451 B CN114448451 B CN 114448451B CN 202011215764 A CN202011215764 A CN 202011215764A CN 114448451 B CN114448451 B CN 114448451B
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- 239000003990 capacitor Substances 0.000 claims description 43
- 238000001514 detection method Methods 0.000 claims description 13
- 230000000630 rising effect Effects 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 16
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
Abstract
The transmitter comprises a front driving stage circuit system, a rear driving stage circuit system and a plurality of resistance value adjusting circuits. The front driving stage circuit system is used for outputting a second data signal according to the first data signal. The post-driver stage circuit system is used for outputting a third data signal according to the second data signal. The resistance adjusting circuits are used for providing a first variable resistor and a second variable resistor, and transmitting a first power supply voltage and a second power supply voltage to at least one circuit system in the front driving stage circuit system or the rear driving stage circuit system so as to adjust the turning rate of the third data signal.
Description
Technical Field
The present invention relates to transmitters, and more particularly to transmitters having a controllable slew rate (slew rate).
Background
In general, the slew rate of the data signal output by the transmitter may be dependent on the receiving capability of the rear receiver and/or the system requirements. In the prior art, the control mechanism at the slew rate requires the use of complex circuitry or voltage or current sources that provide adjustable output capabilities. As such, the circuit complexity and/or associated costs of the transmitter may increase.
Disclosure of Invention
In some embodiments, the transmitter includes front driver stage circuitry, back driver stage circuitry, and a plurality of resistance adjustment circuits. The front driving stage circuit system is used for outputting a second data signal according to the first data signal. The post-driver stage circuit system is used for outputting a third data signal according to the second data signal. The resistance adjusting circuits are used for providing a first variable resistor and a second variable resistor, and transmitting a first power supply voltage and a second power supply voltage to at least one circuit system in the front driving stage circuit system or the rear driving stage circuit system so as to adjust the turning rate of the third data signal.
In some embodiments, the transmitter includes a first resistance adjustment circuit, a second resistance adjustment circuit, a first switch, a second switch, and post driver stage circuitry. The first resistance adjusting circuit is used for providing a first variable resistor. The second resistance adjusting circuit is used for providing a second variable resistor. The control end of the first switch receives a first data signal, the first end of the first switch receives a first power supply voltage through the first resistance adjusting circuit, and the second end of the first switch is used for generating a second data signal. The control end of the second switch receives the first data signal, the first end of the second switch is coupled to the second end of the first switch, and the second end of the second switch receives a second power supply voltage through the second resistance adjusting circuit. The back driving stage circuit system is used for outputting a third data signal according to the second data signal, wherein the first variable resistor and the second variable resistor are used for adjusting the turning rate of the third data signal.
The features, operation and effects of the present invention are described in detail with reference to the preferred embodiments shown in the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram depicting an emitter according to some embodiments of the present application;
FIG. 2A is a schematic diagram of the resistance adjustment circuit of FIG. 1 according to some embodiments of the present application;
FIG. 2B is a schematic diagram of the resistance adjustment circuit of FIG. 1 according to some embodiments of the present application;
FIG. 3 is a schematic diagram depicting an emitter according to some embodiments of the present application;
FIG. 4 is a schematic diagram depicting an emitter according to some embodiments of the present application;
FIG. 5 is a schematic diagram depicting an emitter according to some embodiments of the present application;
FIG. 6 is a schematic diagram depicting an emitter according to some embodiments of the present application; and
fig. 7 is a schematic diagram depicting a transmitter according to some embodiments of the present application.
Symbol description:
100. 300, 400, 500, 600, 700: transmitter
120: front drive stage circuitry
122. 124, 142, 144: inverter circuit
131. 132, 133, 134, 131', 132', 133', 134': resistance value adjusting circuit
140: post-driver stage circuit system
201 to 203: switching circuit
510: rotation rate detection circuit
C1-C4: capacitance device
Data_ P, DATA _ N, OUT _ P, OUT _ N, S1, S2: data signal
GND, VDD, V _SW: power supply voltage
M1 to M4, SW: switch
N1 to N4: node
R: resistor
R1, R2, R3, R4, R1', R2', R3', R4': variable resistor
RSEL1 to RSEL3, SC: control signal
Detailed Description
All terms used herein have their ordinary meaning. The foregoing definitions of words and phrases are provided throughout this specification and in the following description, any examples of uses of words and phrases that may be included within the context of the present application are by way of example only, and should not be limiting as to the scope and meaning of the present application. As such, the present application is not limited to the various embodiments shown in this specification.
As used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or that two or more elements are in operation or action with each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuit" may be a device connected in a manner by at least one transistor and/or at least one active and passive component to process a signal.
As used herein, the term "and/or" includes any combination of one or more of the listed associated items. First, second, third, etc. words are used herein to describe and identify various components. Thus, a first component could also be termed a second component herein without departing from the spirit of the present application. For ease of understanding, similar components in the various figures will be designated by the same reference numerals.
Fig. 1 is a schematic diagram of a transmitter 100 according to some embodiments of the present application. In some embodiments, the transmitter 100 may be applied to, but is not limited to, a wired communication system.
The transmitter 100 includes pre-driver stage circuitry 120, a plurality of resistance adjustment circuits 131-134, and post-driver stage circuitry 140. The pre-driver stage circuit 120 generates the DATA signal S1 according to the DATA signal DATA_P and generates the DATA signal S2 according to the DATA signal DATA_N. The post-driver stage circuitry 140 generates a data signal out_p according to the data signal S1 and generates a data signal out_n according to the data signal S2.
In detail, the pre-driver stage circuitry 120 includes an inverter circuit 122 and an inverter circuit 124. The post driver stage circuitry 140 includes an inverter circuit 142 and an inverter circuit 144. The resistance adjusting circuit 131, the inverter circuit 122, the resistance adjusting circuit 132 and the inverter circuit 142 correspond to a channel for processing the DATA signal data_p to output the DATA signal out_p. The resistance adjustment circuit 133, the inverter circuit 124, the resistance adjustment circuit 134 and the inverter circuit 144 correspond to another channel for processing the DATA signal DATA_N to output the DATA signal OUT_N. In some embodiments, the DATA signals DATA_P and DATA_N may be differential signals.
The resistance adjusting circuit 131 is used for transmitting the power supply voltage VDD to the inverter circuit 122 and providing a variable resistor R1 to adjust the slew rate of the data signal out_p. The resistance adjustment circuit 132 is used to transmit a power supply voltage GND (which may be, but is not limited to, a ground voltage in this example) to the inverter circuit 122 and to provide a variable resistor R2 for adjusting the slew rate of the data signal out_p.
In some embodiments, inverter circuit 122 includes switch M1 (which may be implemented by a P-type transistor) and switch M2 (which may be implemented by an N-type transistor). The inverter circuit 142 generates a data signal out_p according to the data signal S1. In some embodiments, inverter circuit 142 includes switch M3 (which may be implemented by a P-type transistor) and switch M4 (which may be implemented by an N-type transistor). The resistance adjusting circuit 131 is coupled between a first terminal (indicated as a node N1) of the switch M1 and a node N2 for receiving the power supply voltage VDD. In other words, the first end of the switch M1 can receive the power supply voltage VDD via the resistance adjusting circuit 131. The second terminal of the switch M1 is used for generating a DATA signal S1, and the control terminal of the switch M1 receives a DATA signal DATA_P. The first terminal of the switch M2 is coupled to the second terminal of the switch M1, and the control terminal of the switch M2 receives the DATA signal data_p. The resistance adjusting circuit 132 is coupled between a second terminal (indicated as a node N3) of the switch M2 and a node N4 for receiving the power supply voltage GND. In other words, the second end of the switch M2 can receive the power supply voltage GND through the resistance adjusting circuit 132.
The first terminal of the switch M3 receives the power supply voltage v_sw, the second terminal of the switch M3 is used for generating the data signal out_p, and the control terminal of the switch M3 is coupled to the second terminal of the switch M1 to receive the data signal S1. The first terminal of the switch M4 is coupled to the second terminal of the switch M3, the second terminal of the switch M4 receives the power supply voltage GND, and the control terminal of the switch M4 is coupled to the second terminal of the switch M1 to receive the data signal S1. In some embodiments, the power supply voltage v_sw may be used to set the voltage swing (voltage swing) of the data signal out_p (and the data signal out_n output by the inverter circuit 144). The higher the level of the power supply voltage v_sw, the larger the voltage swing of the data signal out_p (and the data signal out_n).
It should be appreciated that the rise time (rising time) and the fall time (falling time) of the data signal S1 are related to at least one resistor (e.g., parasitic capacitance/resistance of transistors and/or wires) and at least one capacitor coupled to the output of the inverter circuit 122. When the data signal S1 goes from low to high, the output of the inverter circuit 122 is charged by a current (not shown) flowing through the variable resistor R1. Therefore, if the resistance adjusting circuit 131 transmits the power supply voltage VDD to the inverter circuit 122, the variable resistor R1 can be used to adjust the charging time constant of the data signal S1. Alternatively, when the data signal S1 goes from high to low, the output terminal of the inverter circuit 122 is discharged by a current (not shown) flowing through the variable resistor R2. Therefore, if the resistance adjusting circuit 132 transmits the power supply voltage GND to the inverter circuit 122, the variable resistor R2 can be used to adjust the discharge time constant of the data signal S1. Since the phases of the data signal S1 and the data signal out_p are opposite (i.e., 180 degrees OUT of phase), the variable resistor R1 can be used to adjust the falling time of the data signal out_p, and the variable resistor R2 can be used to adjust the rising time of the data signal out_p. The larger the resistance value of the variable resistor R1, the larger the charging time constant of the data signal S1 (i.e., the slower the charging speed), and the smaller the slew rate (e.g., the falling slew rate) of the data signal out_p. The larger the resistance value of the variable resistor R2, the larger the discharge time constant of the data signal S1 (i.e., the discharge rate becomes slow), and the smaller the slew rate (e.g., the rising slew rate) of the data signal out_p. Therefore, by setting the resistance values of the variable resistor R1 and the variable resistor R2, the charge time constant and the discharge time constant of the data signal S1 can be adjusted, so as to adjust the slew rate of the data signal out_p to meet the system requirements.
The resistance adjusting circuit 133 is used for transmitting the power supply voltage VDD to the inverter circuit 124 and for providing the variable resistor R3 to adjust the slew rate of the data signal out_n. The resistance adjustment circuit 134 is configured to transmit a power supply voltage GND (in this example, a ground voltage) to the inverter circuit 124, and to provide a variable resistor R4 for adjusting the slew rate of the data signal out_n. The inverter circuit 144 generates the data signal out_n according to the data signal S2 output from the inverter circuit 124. The setting manners of the resistance adjusting circuit 133, the inverter circuit 124, the resistance adjusting circuit 134 and the inverter circuit 144 are the same as the setting manners of the resistance adjusting circuit 131, the inverter circuit 122, the resistance adjusting circuit 132 and the inverter circuit 142, so that the detailed description is not repeated. The resistance of the variable resistor R3 can be used to adjust the charging time constant of the data signal S2, so that the falling time and the slew rate (e.g., the falling slew rate) of the data signal out_n can be adjusted. The resistance of the variable resistor R4 can be used to adjust the discharge time constant of the data signal S2, so that the rising time and slew rate (e.g., rising slew rate) of the data signal out_n can be adjusted. Similarly, the embodiments of the resistance adjusting circuit 133, the inverter circuit 124, the resistance adjusting circuit 134 and the inverter circuit 144 can refer to the embodiments of the resistance adjusting circuit 131, the inverter circuit 122, the resistance adjusting circuit 132 and the inverter circuit 142, respectively, so the description thereof will not be repeated.
Fig. 2A is a schematic diagram illustrating the resistance adjustment circuit 131 in fig. 1 according to some embodiments of the present application. In some embodiments, the resistance adjustment circuit 131 includes a plurality of switching circuits 201-203. In this example, the plurality of switching circuits 201-203 are coupled in series between the node N1 and the node N2 in FIG. 1. The plurality of switching circuits 201 to 203 are selectively turned on according to the plurality of control signals RSEL1 to RSEL3, respectively, to provide the variable resistor R1. In some embodiments, each of the plurality of switching circuits 201-203 includes a resistor R and a switch SW. The resistor R is coupled in parallel with the switch SW, and the switch SW is selectively turned on according to a corresponding one of the plurality of control signals RSEL 1-RSEL 3. In this example, as the number of on switches SW increases, the resistance of the variable resistor R1 decreases. Conversely, the smaller the number of switches SW turned on, the higher the resistance of the variable resistor R1. Therefore, by the plurality of control signals RSEL1 to RSEL3, the resistance value of the variable resistor R1 can be adjusted to control the slew rate of the data signal out_p.
Fig. 2B is a schematic diagram illustrating the resistance adjustment circuit 131 in fig. 1 according to some embodiments of the present application. In comparison with fig. 2A, in this example, the plurality of switching circuits 201 to 203 are coupled in parallel between the node N1 and the node N2 in fig. 1, and the switch SW and the resistor R of each of the plurality of switching circuits 201 to 203 are coupled in series. In this example, as the number of on switches SW increases, the resistance of the variable resistor R1 decreases. Conversely, the smaller the number of switches SW turned on, the higher the resistance of the variable resistor R1.
It should be understood that fig. 2A and 2B are only examples, and the present application is not limited thereto. For example, the number of switching circuits can be adjusted accordingly according to the practical application requirements. In addition, it should be understood that the circuit arrangement in fig. 2A and 2B may also be used to implement the resistance adjustment circuit 132, the resistance adjustment circuit 133, or the resistance adjustment circuit 134 in fig. 1. For example, if the resistance value adjusting circuit 132 of fig. 1 is implemented by using the plurality of switching circuits 201 to 203, the node N1 and the node N2 in fig. 2A and 2B may be replaced with the node N3 and the node N4 in fig. 1, respectively.
Fig. 3 is a schematic diagram of a transmitter 300 according to some embodiments of the present application. In this example, the transmitter 300 further includes a capacitor C1 and a capacitor C2, as compared to fig. 1. The capacitor C1 is coupled between the front driving stage 120 and the rear driving stage 140, and is used to adjust the slew rate of the data signal out_p in cooperation with the resistance adjusting circuit 131 and the resistance adjusting circuit 132. In detail, the capacitor C1 is coupled to the second terminal of the switch M1 (i.e. the output terminal of the inverter circuit 122). In the previous example of fig. 1, the charge time constant of the data signal S1 is determined based on the variable resistor R1 and at least one parasitic capacitor (not shown) coupled to the second terminal of the switch M1, and the discharge time constant of the data signal S1 is determined based on the variable resistor R2 and at least one parasitic capacitor (not shown) coupled to the second terminal of the switch M1. In comparison with the above example, in fig. 3, the capacitance of the capacitor coupled to the second terminal of the switch M1 is mainly determined by the capacitor C1. Therefore, the charge time constant of the data signal S1 can be determined based on the variable resistor R1 and the capacitor C1, and the discharge time constant of the data signal S1 can be determined based on the variable resistor R2 and the capacitor C1. If the capacitance of the capacitor C1 is larger, the charge time constant and the discharge time constant of the data signal S1 are larger, so that the slew rate of the data signal out_p can be reduced.
Similar to the arrangement of the capacitor C1, the capacitor C2 is coupled between the inverter circuit 124 and the inverter circuit 144. The arrangement between the capacitor C2 and the inverter circuit 124 is similar to that between the capacitor C1 and the inverter circuit 122, so that the description thereof will not be repeated. In some embodiments, each of the capacitors C1 and C2 may be implemented by a capacitor having a fixed capacitance value. In other embodiments, each of the capacitors C1 and C2 may be implemented by a variable capacitor.
Fig. 4 is a schematic diagram of a transmitter 400 according to some embodiments of the present application. In this example, the transmitter 400 further includes a capacitor C3 and a capacitor C4, as compared to fig. 1. The capacitor C3 and the capacitor C4 are coupled to the plurality of output terminals of the post driver stage circuit 140, respectively. In detail, the capacitor C3 is coupled to the output terminal of the inverter circuit 142, and the capacitor C4 is coupled to the output terminal of the inverter circuit 144. The capacitor C3 can cooperate with the resistance adjusting circuit 131 and the resistance adjusting circuit 132 to adjust the slew rate of the data signal out_p. For example, the larger the capacitance value of the capacitor C3, the smaller the slew rate of the data signal out_p. Similarly, the capacitor C4 can adjust the slew rate of the data signal out_n in cooperation with the resistance adjusting circuit 133 and the resistance adjusting circuit 134.
In some embodiments, each of the capacitors C3 and C4 may be implemented by a capacitor having a fixed capacitance value. In other embodiments, each of the capacitors C3 and C4 may be implemented by a variable capacitor. In some embodiments, the capacitance of capacitor C3 (or capacitor C4) is generally greater than the capacitance of capacitor C1 (or capacitor C2) of FIG. 3 due to the amplifying effect of the post driver stage circuitry 140. The arrangement in fig. 3 and fig. 4 is used for illustration, and the present application is not limited thereto. For example, in other embodiments, the transmitter may include all of the capacitances C1-C4.
Fig. 5 is a schematic diagram of a transmitter 500 according to some embodiments of the present application. In this example, the transmitter 500 further includes a slew rate detection circuit 510, as compared to fig. 1. The slew rate detection circuit 510 is configured to detect slew rates of the data signal out_p and the data signal out_n to generate a plurality of control signals SC (e.g., the plurality of control signals RSEL 1-RSEL 3 in fig. 2A or 2B). In this way, the resistance adjusting circuit 131, the resistance adjusting circuit 132, the resistance adjusting circuit 133, and the resistance adjusting circuit 134 can adjust the resistances of the plurality of variable resistors R1 to R4 according to the plurality of control signals.
In some embodiments, slew rate detection circuit 510 may comprise a plurality of high pass filter circuits (not shown), a peak detector circuit (not shown), at least one comparator circuit (not shown), and control logic circuits (not shown). The high-pass filter circuits respectively generate a plurality of first signals according to the data signal OUT_P and the data signal OUT_N. The peak detector circuit samples the plurality of first signals to generate a plurality of second signals, respectively. At least one comparator circuit compares one corresponding one of the plurality of first signals with a high reference voltage to generate a first detection signal and compares another corresponding one of the plurality of first signals with a low reference voltage to generate a second detection signal. The control logic circuit can output the control signals according to the first detection signal and the second detection signal. In some embodiments, the high reference voltage may be 0.8 times the power supply voltage v_sw, and the low reference voltage may be about 0.2 times the power supply voltage v_sw. In still other embodiments, the high reference voltage may be about 0.9 times the power supply voltage v_sw, and the low reference voltage may be about 0.1 times the power supply voltage v_sw.
The above embodiments regarding the slew rate detection circuit 510 are used as examples, and the present application is not limited thereto. Various types of slew rate detection circuits 510 are within the scope of the present invention.
Fig. 6 is a schematic diagram of a transmitter 600 according to some embodiments of the present application. In the foregoing embodiments, the resistance adjusting circuits 131 to 134 are used for adjusting the time constants of the data signal S1 and the data signal S2 output by the front driving stage circuit system 120, and further adjusting the slew rates of the data signal out_p and the data signal out_n. In comparison with the previous embodiment, in this example, the resistance adjusting circuits 131-134 are used for transmitting the power supply voltage v_sw and the power supply voltage GND to the post-driver circuitry 140 and for providing the variable resistors R1-R4 to directly adjust the slew rates of the data signal out_p and the data signal out_n.
If the resistance adjusting circuits 131 and 132 transmit the power supply voltage v_sw and the power supply voltage GND to the inverter circuit 142, the variable resistor R1 can be used to directly adjust the rising slew rate of the data signal out_p, and the variable resistor R2 can be used to directly adjust the falling slew rate of the data signal out_p. For example, the larger the resistance value of the variable resistor R1, the larger the charge time constant of the data signal out_p, so the smaller the rising slew rate of the data signal out_p. The larger the resistance value of the variable resistor R2, the larger the discharge time constant of the data signal out_p, so the smaller the falling slew rate of the data signal out_p. Similarly, the larger the resistance of the variable resistor R3 is, the larger the charge time constant of the data signal out_n is, so the smaller the rising slew rate of the data signal out_n is. The larger the resistance value of the variable resistor R4 is, the larger the discharge time constant of the data signal out_n is, so the smaller the falling slew rate of the data signal out_n is.
In addition, in this example, the front driving stage circuit 120 does not receive the power supply voltage VDD and the power supply voltage GND through the plurality of resistance adjusting circuits 131 to 134. The arrangement of the resistance adjusting circuit 131, the inverter circuit 142, and the resistance adjusting circuit 132 is similar to the arrangement of the resistance adjusting circuit 131, the inverter circuit 122, and the resistance adjusting circuit 132 in fig. 1. Similarly, the setting manners of the resistance adjusting circuit 133, the inverter circuit 144 and the resistance adjusting circuit 134 are similar to those of the resistance adjusting circuit 133, the inverter circuit 124 and the resistance adjusting circuit 134 in fig. 1, so that the detailed description thereof will not be repeated here.
Fig. 7 is a schematic diagram of a transmitter 700 according to some embodiments of the present application. In this example, the transmitter 700 further includes a plurality of resistance adjustment circuits 131 'to 134' as compared to the configuration of the transmitter 100 in the embodiment of fig. 1. The resistance adjusting circuits 131 'to 134' are used for transmitting the power supply voltage v_sw and the power supply voltage GND to the post driver stage circuitry 140, and for providing the variable resistors R1 'to R4' to adjust the slew rates of the data signals out_p and out_n. The larger the resistance value of the variable resistor R1', the larger the charge time constant of the data signal out_p, so the smaller the rising slew rate of the data signal out_p. The larger the resistance value of the variable resistor R2', the larger the discharge time constant of the data signal out_p, so the smaller the falling slew rate of the data signal out_p. Similarly, the larger the resistance value of the variable resistor R3', the larger the charging time constant of the data signal out_n, so the smaller the rising slew rate of the data signal out_n. The larger the resistance value of the variable resistor R4', the larger the discharge time constant of the data signal out_n, so the smaller the falling slew rate of the data signal out_n.
The arrangement between the resistance adjustment circuit 131', the inverter circuit 142, and the resistance adjustment circuit 132' is similar to the arrangement between the resistance adjustment circuit 131, the inverter circuit 122, and the resistance adjustment circuit 132 of fig. 1. Similarly, the setting manners of the resistance adjusting circuit 133', the inverter circuit 144 and the resistance adjusting circuit 134' are similar to those of the resistance adjusting circuit 133, the inverter circuit 124 and the resistance adjusting circuit 134 in fig. 1, so the detailed description is omitted.
According to the above embodiments, it should be understood that, in various embodiments, the plurality of resistance adjustment circuits 131-134 (and/or the plurality of resistance adjustment circuits 131 '-134') can provide the plurality of variable resistors R1-R4 (and/or the plurality of variable resistors R1 '-R4') and transmit the plurality of power supply voltages VDD and GND (or the plurality of power supply voltages v_sw and GND) to at least one of the front driving stage circuit system 120 or the rear driving stage circuit system 140.
Again, it should be understood that transmitter 600 (or transmitter 700) may also be applied to the various embodiments shown in fig. 3, 4, and 5. For example, the transmitter 600 (or the transmitter 700) may include a capacitor C1 and a capacitor C2 respectively coupled to the plurality of output terminals of the inverter circuit 122 and the inverter circuit 124. Alternatively, the transmitter 600 (or the transmitter 700) may include a capacitor C3 and a capacitor C4 respectively coupled to the plurality of output terminals of the inverter circuit 142 and the inverter circuit 144. The transmitter 600 (or the transmitter 700) may include a slew rate detection circuit 510 for detecting a plurality of data signals OUT_P and OUT_N to generate a plurality of control signals to adjust a plurality of variable resistors R1-R4 (and/or a plurality of variable resistors R1 '-R4').
In one or more embodiments, the partial transistors are N-type transistors and the partial transistors are P-type transistors. The transistors may be implemented by metal oxide field effect transistors (MOSFETs), but the present invention is not limited thereto. Transistors of various types or conductivity types that may perform similar operations are within the scope of the present application. Furthermore, the embodiments described above with respect to the front driver stage circuitry 120 and the rear driver stage circuitry 140 are for illustration, and the present application is not limited thereto. Various embodiments of the front driver stage 120 and the back driver stage 140 suitable for the wired communication system are within the scope of the present application.
In summary, the transmitter in some embodiments of the present invention can adjust the charge-discharge time constant of the front driver stage circuit system by using the variable resistor to adjust the slew rate of the output signal of the transmitter.
While the present disclosure has been disclosed in terms of the specific embodiments, the embodiments are not intended to limit the scope of the disclosure, and those skilled in the art should appreciate that various modifications and adaptations to the teachings of the disclosure can be made without departing from the spirit and scope of the disclosure.
Claims (9)
1. A transmitter, the transmitter comprising:
front driving stage circuit system for outputting the second data signal according to the first data signal;
post-driver stage circuitry to output a third data signal in accordance with the second data signal;
the resistance value adjusting circuits are used for providing a first variable resistor and a second variable resistor, transmitting a first power supply voltage and a second power supply voltage to at least one circuit system in the front driving stage circuit system or the rear driving stage circuit system, and adjusting the slew rate of the third data signal;
the slew rate detection circuit is used for detecting the slew rate of the third data signal to generate a plurality of control signals, and the resistance adjustment circuits are further used for adjusting the first variable resistor and the second variable resistor according to the control signals.
2. The transmitter of claim 1, wherein each of the plurality of resistance adjustment circuits comprises:
the switching circuits are coupled in series or in parallel between the front driving stage circuit system or the rear driving stage circuit system and a node for selectively conducting according to a plurality of control signals to provide the first variable resistor or the second variable resistor, wherein the node is used for receiving the first power supply voltage or the second power supply voltage.
3. The transmitter of claim 2, wherein each of the plurality of switching circuits comprises:
a resistor; and
the switch is coupled with the resistor and is used for conducting according to one signal of the control signals.
4. The transmitter of claim 1, wherein the transmitter further comprises:
the capacitor is coupled between the front driving stage circuit system and the rear driving stage circuit system and is used for adjusting the turning rate in cooperation with the plurality of resistance adjusting circuits.
5. The transmitter of claim 1, wherein the transmitter further comprises:
the capacitor is coupled to the output end of the rear driving stage circuit system and used for adjusting the turning rate in cooperation with the plurality of resistance adjusting circuits.
6. The transmitter of claim 1, wherein the first variable resistor is configured to adjust a charging time constant of the second data signal if the plurality of resistance adjustment circuits transmit the first power supply voltage and the second power supply voltage to the front driver stage circuitry.
7. The transmitter of claim 1, wherein the second variable resistor is configured to adjust a discharge time constant of the second data signal if the plurality of resistance adjustment circuits transmit the first power supply voltage and the second power supply voltage to the front driver stage circuitry.
8. The transmitter of claim 1, wherein if the plurality of resistance adjustment circuits transmit the first power supply voltage and the second power supply voltage to the post driver stage circuitry, the first variable resistor is configured to adjust a rising slew rate of the third data signal and the second variable resistor is configured to adjust a falling slew rate of the third data signal.
9. A transmitter, the transmitter comprising:
the first resistance value adjusting circuit is used for providing a first variable resistor;
the second resistance value adjusting circuit is used for providing a second variable resistor;
a first switch, wherein a control end of the first switch receives a first data signal, a first end of the first switch receives a first power supply voltage through the first resistance adjusting circuit, and a second end of the first switch is used for generating a second data signal;
a second switch, wherein a control terminal of the second switch receives the first data signal, a first terminal of the second switch is coupled to the second terminal of the first switch, and a second terminal of the second switch receives a second power supply voltage via the second resistance adjustment circuit; and
a post-driver stage circuit system for outputting a third data signal according to the second data signal, wherein the first variable resistor and the second variable resistor are used for adjusting the slew rate of the third data signal;
a slew rate detection circuit for detecting the slew rate of the third data signal to generate a plurality of control signals, wherein
The first resistance value adjusting circuit and the second resistance value adjusting circuit are further used for adjusting the first variable resistor and the second variable resistor according to the control signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011215764.4A CN114448451B (en) | 2020-11-04 | 2020-11-04 | Transmitter with controllable slew rate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011215764.4A CN114448451B (en) | 2020-11-04 | 2020-11-04 | Transmitter with controllable slew rate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114448451A CN114448451A (en) | 2022-05-06 |
| CN114448451B true CN114448451B (en) | 2023-10-31 |
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| CN202011215764.4A Active CN114448451B (en) | 2020-11-04 | 2020-11-04 | Transmitter with controllable slew rate |
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| CN114448451A (en) | 2022-05-06 |
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