KR20190124856A - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor element which is resistant to external impact. The semiconductor element comprises: a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the second semiconductor layer. The semiconductor structure includes: a first upper surface through which the first semiconductor layer is exposed; a second upper surface on which the second semiconductor layer is disposed; an inclined surface connecting the first upper surface and the second upper surface; and a groove formed between the first upper surface and the inclined surface. A depth of the groove is equal to or less than 30% of a vertical distance between the first upper surface and the second upper surface.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The embodiment relates to a semiconductor device.

A light emitting diode (LED) is one of light emitting devices that emit light when a current is applied. Light emitting diodes can emit high-efficiency light at low voltage, resulting in excellent energy savings. Recently, the luminance problem of the light emitting diode has been greatly improved, and has been applied to various devices such as a backlight unit, a display board, a display, and a home appliance of a liquid crystal display.

A semiconductor device including a compound such as GaN, AlGaN, etc. has many advantages, such as having a wide and easy-to-adjust band gap energy, and can be used in various ways as a light emitting device, a light receiving device, and various diodes.

Particularly, light emitting devices such as light emitting diodes and laser diodes using semiconductors of Group 3-5 or Group 2-6 compound semiconductors have been developed through the development of thin film growth technology and device materials. Various colors such as blue and ultraviolet light can be realized, and efficient white light can be realized by using fluorescent materials or combining colors.Low power consumption, semi-permanent lifespan, and fast response speed compared to conventional light sources such as fluorescent and incandescent lamps can be realized. It has the advantages of safety, environmental friendliness.

Recently, researches have been made on a technology of manufacturing a light emitting diode in a micro size and using the same as a pixel of a display. However, since the light emitting diode is reduced in size to micro size, there is a weak problem in external impact.

The embodiment provides a semiconductor device resistant to external impact.

In addition, the present invention provides a semiconductor device having improved light output.

The problem to be solved in the examples is not limited thereto, and the object or effect that can be grasped from the solution means or the embodiment described below will also be included.

A semiconductor device according to an aspect of the present invention may include a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; A first electrode electrically connected to the first semiconductor layer; And a second electrode electrically connected to the second semiconductor layer, wherein the semiconductor structure includes a first upper surface on which the first semiconductor layer is exposed, a second upper surface on which the second semiconductor layer is disposed, and the An inclined surface connecting the first upper surface and the second upper surface, and a groove formed between the first upper surface and the inclined surface, the depth of the groove being between the first upper surface and the second upper surface. Is less than 30% of the vertical distance.

The second semiconductor layer includes a first sub semiconductor layer exposed to the first upper surface, and a second sub semiconductor layer disposed on the first sub semiconductor layer, wherein the first sub semiconductor layer and the second sub semiconductor layer are disposed on the first sub semiconductor layer. The etching rate difference of the sub-semiconductor layer may be 30% or less under the same etching conditions.

According to an embodiment, the semiconductor device may be resistant to external shock. Therefore, the problem that the semiconductor element is damaged in the transfer process can be solved.

In addition, a semiconductor device having improved light output can be manufactured.

Various and advantageous advantages and effects of the present invention are not limited to the above description, and will be more readily understood in the course of describing specific embodiments of the present invention.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure;
2 is a plan view of a semiconductor device according to an embodiment of the present disclosure;
3A to 3B are views for explaining why the groove of FIG. 1 occurs,
4 is a view for explaining a reason that the semiconductor device is damaged by the groove of FIG.
5 is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure;
6A through 6E are views illustrating a method of manufacturing a semiconductor device array according to an embodiment of the present invention.
7A to 7E are views illustrating a method of transferring a semiconductor device according to an embodiment of the present invention.
8 is a conceptual diagram of a display device to which a semiconductor device is transferred according to an exemplary embodiment.

The embodiments may be modified in other forms or in various embodiments, and the scope of the present invention is not limited to the embodiments described below.

Although matters described in a specific embodiment are not described in other embodiments, it may be understood as descriptions related to other embodiments unless there is a description that is contrary to or contradictory to the matters in other embodiments.

For example, if a feature is described for component A in a particular embodiment and a feature for component B in another embodiment, a description that is contrary or contradictory, even if the embodiments in which configuration A and configuration B are combined are not explicitly described. Unless otherwise, it should be understood to fall within the scope of the present invention.

In the description of the embodiment, when one element is described as being formed "on or under" of another element, it is on (up) or down (on). or under) includes both two elements being directly contacted with each other or one or more other elements are formed indirectly between the two elements. In addition, when expressed as "on" or "under", it may include the meaning of the downward direction as well as the upward direction based on one element.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In addition, the semiconductor device package according to the present embodiment may include a semiconductor device of a micro size or nano size. Here, the small semiconductor device may refer to the structural size of the semiconductor device. The small semiconductor device may have a size of about 1 μm to about 100 μm. In addition, the semiconductor device according to the embodiment may have a size of 30 μm to 60 μm, but is not limited thereto. In addition, the technical features or aspects of the embodiment may be applied to the semiconductor device on a smaller scale.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention, and FIGS. 3A to 3B illustrate a reason why the groove of FIG. 1 occurs. 4 is a view for explaining a reason that the semiconductor device is damaged by the groove of FIG.

1 and 2, a semiconductor device according to an embodiment may include a first semiconductor layer 12, a second semiconductor layer 14, and a space between the first semiconductor layer 12 and the second semiconductor layer 14. A semiconductor structure 11 including an active layer 13 disposed thereon, a first electrode 15 electrically connected to the first semiconductor layer 12, and a second electrode electrically connected to the second semiconductor layer 14. (16).

The active layer 13 may generate light in one or more of the blue, green, and red wavelength bands. In other words, the semiconductor device may emit various visible light.

The insulating layer 18 is disposed on the upper surface S1 and the side surfaces S2, S3, S4, and S5 of the semiconductor structure 11, and the first holes H1 and the first electrodes 15 are exposed. The second electrode 16 may include a second hole H2 through which the second electrode 16 is exposed. The insulating layer 18 may include a material such as SiO ₂ , SiNx, TiO ₂ , polyimide, resin, or the like.

The upper surface S1 of the semiconductor structure may include a first upper surface S11 on which the first semiconductor layer 12 is exposed, a second upper surface S13 on which the second semiconductor layer 14 is disposed, and a first upper surface. It may include an inclined surface (S12) connecting the (S11) and the second upper surface (S13).

The area of the first upper surface S11 may be 30% to 110% of the area of the second upper surface S13. For example, the area of the first upper surface S11 may be 40% to 110% of the area of the second upper surface S13.

Since the semiconductor device according to the embodiment is a micro semiconductor device having a small size, the mesa etching area may be relatively increased even if the minimum area of the first electrode 15 is secured. Therefore, when the area of the first upper surface S11 is 30% or more, the first electrode 15 may be widened to reduce ohmic resistance. Thus, the operating voltage can be reduced and the light output can be improved.

The first vertical height d1 from the bottom surface B1 of the semiconductor structure 11 to the second upper surface S13 and the bottom surface B1 of the semiconductor structure 140 from the first upper surface S11. The ratio d1: d2 of the second vertical height d2 may be 1: 0.6 to 1: 0.95. If the height ratio (d1: d2) is less than 1: 0.6, the step height may increase, and a defect rate may be increased during the transfer process, and when the height ratio is greater than 1: 0.95, the mesa etching depth is lowered to partially reduce the first conductive semiconductor layer ( 141 may not be exposed.

The first vertical height d1 may be 5 μm to 8 μm. That is, the first vertical height d1 may be the overall thickness of the semiconductor structure 140. The second vertical height d2 may be 3.0 μm to 7.6 μm. In this case, the difference d3 between the first vertical height d1 and the second vertical height d2 may be 350 nm or more and 2.0 μm or less. If the height difference d3 is larger than 2.0 μm, a distortion occurs during transfer of the semiconductor element, which makes it difficult to transfer the semiconductor element to a desired position. In addition, when the height difference d3 is smaller than 350 nm, the first conductive semiconductor layer 121 may not be partially exposed.

When the difference d3 between the first vertical height d1 and the second vertical height d2 is 1.0 μm or less, the upper surface of the semiconductor structure is substantially flat, which facilitates transfer and suppresses crack generation. For example, the difference d3 between the first vertical height d1 and the second vertical height d2 may be 0.6 μm ± 0.2 μm, but is not limited thereto.

The first angle θ2 that the inclined surface S12 makes with the virtual horizontal plane may be 20 ° to 80 ° or 20 ° to 50 °. When the first angle θ2 is smaller than 20 °, the area of the second upper surface S13 may be reduced, thereby lowering the light output. In addition, when the first angle θ2 is greater than 80 °, the inclination angle may be increased to increase the risk of damage due to external impact.

In addition, the second angle θ1 of the side surfaces S2, S3, S4, and S5 of the semiconductor structure 140 may be 70 ° to 90 °. When the second angle θ1 is smaller than 70 °, the area of the second upper surface S13 may be reduced, thereby lowering the light output. In this case, the first angle θ2 may be smaller than the second angle θ1. In this case, the inclined surface S12 may be smoothed, thereby reducing the risk of cracking of the external impact.

In this case, when all of the side surfaces S2, S3, S4, and S5 of the semiconductor structure 140 are inclined, the width (the width in the Y-axis direction) of the inclined surface S12 is the second upper surface S13 from the first upper surface S11. Can be narrowed toward the direction of.

The first semiconductor layer 12 may include a plurality of sub-semiconductor layers 12a and 12b. The plurality of sub-semiconductor layers 12a and 12b may include various semiconductor layers for improving epi crystallinity and / or improving light extraction efficiency. Alternatively, the semiconductor layer may include a semiconductor layer necessary for epitaxial growth. There is no limitation on the number of sub-semiconductor layers.

For example, the first semiconductor layer 12 may include a first sub-semiconductor layer 12a on which the first electrode 15 is disposed, and a second sub-semiconductor disposed between the first sub-semiconductor layer 12a and the active layer 13. Layer 12b.

The first sub-semiconductor layer 12a may be exposed by mesa etching. A plurality of sub-semiconductor layers may be further disposed below the first sub-semiconductor layer 12a.

The semiconductor structure 11 may include a groove 17 formed between the first upper surface S11 and the inclined surface S12.

The groove 17 may be formed by a difference in etching rates of the semiconductor layers. The depth d4 of the groove 17 may be 30% or less of a vertical distance (etch depth d3) between the first upper surface S11 and the second upper surface S13. If the depth d4 of the groove 17 is greater than 30% of the vertical distance d3, cracks may occur in the groove 17 during the transfer process. Therefore, it is necessary to control the depth d4 of the groove 17 to 30% or less of the vertical distance d3 between the first upper surface S11 and the second upper surface S13. In addition, when the depth d4 of the groove 17 is controlled to 10% or less of the vertical distance d3 between the first upper surface S11 and the second upper surface S13, the semiconductor device becomes more resistant to external impact. Can be.

The depth d4 of the groove 17 may be adjusted by controlling the etching rates of the sub-semiconductor layers 12a and 12b. For example, the etching rate difference between the sub-semiconductor layers 12a and 12b may be controlled to 30% or less. If the etching speeds of the sub-semiconductor layers 12a and 12b are the same, the groove 17 may not be generated.

3A and 3B, a portion of the semiconductor structure 11 may be mesa-etched to form the first electrode 15 to expose the first sub-semiconductor layer 12a. The first sub-semiconductor layer 12a may be a layer having a relatively low resistance and a low contact resistance with the first electrode 15.

The second sub-semiconductor layer 12b may be a layer disposed between the active layer 13 and the first sub-semiconductor layer 12a. For example, the first sub-semiconductor layer 12a may be a contact layer in contact with the N-type ohmic electrode, and the second sub-semiconductor layer 12b may be an N-type semiconductor layer, but is not limited thereto.

The first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b may include the same dopant. For example, the first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b may include an N-type dopant, but are not limited thereto. In exemplary embodiments, the first sub-semiconductor layer 12a may not include a dopant.

The first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b may have different compositions or different composition ratios. For example, when the semiconductor device is a red device, the first sub-semiconductor layer 12a may be a layer including GaAs, and the second sub-semiconductor layer 12b may be a semiconductor layer including AlInP, but is not limited thereto.

Referring to FIG. 3B, a mask 19 may be formed in an area not to be etched and the plasma E1 may be irradiated. At this time, the etching plasma E1 is irradiated to the first upper surface S11 of the semiconductor structure 11 almost vertically, but the boundary area RE1 between the first upper surface S11 and the inclined surface S12 is an etching plasma ( E1, E2) can be scattered. That is, since the plasma E1 irradiated perpendicularly and the plasma E2 refracted on the inclined plane S12 and refracted are simultaneously irradiated to the boundary area RE1, the plasma may be concentrated.

Therefore, before the first sub-semiconductor layer 12a is completely removed, the region RE1 close to the inclined surface S12 may already be removed. In contrast, the first sub-semiconductor layer 12c may still remain in a part of the first upper surface S11.

Referring to FIG. 3C, when the etching plasma is irradiated to remove the remaining first sub-semiconductor layer 12c, the second sub-semiconductor layer 12b exposed to the boundary region RE1 is etched to form the groove 17. This can be formed. In this case, if the etching rate of the second sub-semiconductor layer 12b is faster than that of the first sub-semiconductor layer 12a, the depth d4 of the groove 17 may be deeper.

In the boundary area RE1 between the first upper surface S11 and the inclined surface S12, the plasma is concentrated and the etching speed of the second sub-semiconductor layer 12b is high, so that the remaining first sub-semiconductor layer 12c is completely removed. The groove 17 can be formed very deep before it is removed.

Referring to FIG. 4, the micro semiconductor device may be selectively transferred to another substrate through a transfer process. For example, to form a pixel of the display, the micro-semiconductor device may be separated from the growth substrate by the transfer device 210 and then transferred to the substrate of the display.

In this process, a physical shock may be applied to the micro-semiconductor device, and cracks C1 may be generated in the grooves 17 by an external stress applied thereto. Thus, a problem may occur in which some pixels of the display malfunction.

Therefore, it may be important to control the depth of the groove 17 in the semiconductor device. In the case of a general visible light semiconductor device, since the size of the chip is relatively large, such a groove may be ignored.

Referring back to FIGS. 1 and 2, the etching rate of the first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b may be 30% or less when etching under the same conditions. The same condition may be defined as maintaining various control factors such as an etching source, a temperature, and a voltage that can control the etching rate in the sputter device.

When the difference in etching speed is 30% or less, the depth of the grooves 17 formed in the second sub-semiconductor layer 12b is removed while the first sub-semiconductor layer 12a remaining on the first upper surface S11 is removed. It can be controlled within 30% of the vertical height (d3) between the upper surface (S11) and the second upper surface (S13).

The etching rate of the semiconductor layer can be controlled by changing the composition of the semiconductor layer. InP may etch slower than GaAs. In addition, as the amount of the specific factor, such as indium (In), the etching rate may be relatively slow. For example, in the case of the same InP composition, as the composition of indium is increased, the etching rate may be relatively slow.

When the first sub-semiconductor layer 12a includes GaAs and the second sub-semiconductor layer 12b includes AlInP, the etching speed of GaAs is relatively high, so that the groove 17 may be deeper. In this case, when indium is added to the first sub-semiconductor layer 12a or when the first sub-semiconductor layer 12a is formed of AlInP, the depth of the groove 17 may be reduced.

If the first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b have the same composition, the depth of the groove 17 may be relatively small. For example, both the first sub-semiconductor layer 12a and the second sub-semiconductor layer 12b may be formed of AlInP so that the etching rate may be the same. However, even in this case, when the plasma is concentrated on the inclined surface S12, the groove 17 may be formed near the inclined surface.

In this case, when the indium composition included in the first sub-semiconductor layer 12a is controlled to be larger than the indium composition of the second sub-semiconductor layer 12b, the etching speed of the first sub-semiconductor layer 12a is relatively lowered. It is also possible to control the depth of 17) smaller. Accordingly, the depth of the groove 17 may be controlled by controlling the composition of the etching rate control factor (eg, indium) within the limit of maintaining optical and / or electrical performance.

That is, when the etching speed of the first sub-semiconductor layer 12a is slower than that of the second sub-semiconductor layer 12b, the size of the groove 17 may be controlled to be smaller. In addition, when the first electrode 15 is disposed in the sub-semiconductor layer disposed closest to the lower portion of the active layer 13, the etching rate difference between the sub-semiconductor layer and the active layer 13 may be controlled.

5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

The semiconductor device according to the embodiment is disposed on the sacrificial layer 120, the coupling layer 130 disposed on the sacrificial layer 120, the intermediate layer 170 disposed on the coupling layer 130, and the intermediate layer 170. The first conductive semiconductor layer 141, the first cladding layer 144 disposed on the first conductive semiconductor layer, the active layer 142 disposed on the first cladding layer 144, and the active layer 142 disposed on the active layer The second conductive semiconductor layer 143, the first electrode 151 electrically connected to the first conductive semiconductor layer, the second electrode 152 electrically connected to the second conductive semiconductor layer, and the sacrificial material. The insulating layer 160 surrounding the layer 120, the coupling layer 130, the first conductive semiconductor layer 141, the first cladding layer 144, the active layer 142, and the second conductive semiconductor layer 142. It may include.

The sacrificial layer 120 may be a layer disposed on the bottom of the semiconductor device according to the embodiment. That is, the sacrificial layer 120 may be a layer disposed on the outermost side in the _first-second direction (X ₂ axis direction). The sacrificial layer 120 may be disposed on a substrate (not shown).

The maximum width W ₁ in the second direction (Y-axis direction) of the sacrificial layer 120 may be 30 μm to 60 μm.

Here, the first direction includes a first-first direction and a first-second direction in the thickness direction of the semiconductor structure 140. The first-first direction is a direction from the first conductive semiconductor layer 121 toward the second conductive semiconductor layer 123 in the thickness direction of the semiconductor structure 140. The first-second direction is a direction from the second conductive semiconductor layer 123 toward the first conductive semiconductor layer 121 in the thickness direction of the semiconductor structure 140. In addition, the second direction (Y-axis direction) may be a direction perpendicular to the first direction (X-axis direction). In addition, the second direction (Y-axis direction) includes a second-first direction (Y1-axis direction) and a second-second direction (Y2-axis direction).

The sacrificial layer 120 may be a layer left while transferring the semiconductor device to the display device. For example, when the semiconductor device is transferred to the display device, the sacrificial layer 120 may be partially separated by a laser irradiated during the transfer, and the other part may be left. In this case, the sacrificial layer 120 may include a material that can be separated from the wavelength of the irradiated laser. In addition, the wavelength of the laser may be any one of 266 nm, 532 nm, and 1064 nm, but is not limited thereto.

The sacrificial layer 120 may include oxide or nitride. However, the present invention is not limited thereto. For example, the sacrificial layer 120 may include an oxide-based material as a material having less deformation generated during epitaxial growth.

The sacrificial layer 120 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAZO), indium gallium zinc oxide (IGZO), and indium gallium tin oxide (IGTO). ), Aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx , NiO, RuOx / ITO, Ni / IrOx / Au, or Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt, It may include at least one of Au, Hf.

The sacrificial layer 120 may have a thickness d ₁ of 20 nm or more in a first direction (X-axis direction). Preferably, the sacrificial layer 120 may have a thickness d ₁ of 40 nm or more in the first direction (X-axis direction).

The sacrificial layer 120 may be formed by an E-beam evaporator, a thermal evaporator, a metal organic chemical vapor deposition (MOCVD), a sputtering and a pulsed laser deposition (PLD) method. It is not limited to this.

The bonding layer 130 may be disposed on the sacrificial layer 120. The bonding layer 130 may include a material such as SiO ₂ , SiNx, TiO ₂ , polyimide, resin, or the like.

The thickness d ₂ of the bonding layer 130 may be 30 nm to 1 μm. However, the present invention is not limited thereto. Here, the thickness may be a length in the X-axis direction. The bonding layer 130 may be annealed to bond the sacrificial layer 120 and the intermediate layer 170 to each other. At this time, the peeling may occur while the hydrogen ions in the bonding layer 130 are discharged. Thus, the bonding layer 130 may have a surface roughness of 1 nm or less. By such a configuration, the separation layer and the bonding layer can be easily bonded. The bonding layer 130 and the sacrificial layer 120 may be interchanged with each other.

The intermediate layer 170 may be disposed on the bonding layer 130. The intermediate layer 170 may include GaAs. The intermediate layer 170 may be combined with the sacrificial layer 120 through the bonding layer 130.

The semiconductor structure 140 may be disposed on the intermediate layer 170. The semiconductor structure 140 is on the first conductive semiconductor layer 141 disposed on the intermediate layer 170, the first cladding layer 144 and the first cladding layer 144 disposed on the first conductive semiconductor layer. The active layer 142 may be disposed on the active layer 142, and the second conductive semiconductor layer 143 may be disposed on the active layer 142.

The first conductivity type semiconductor layer 141 may be disposed on the intermediate layer 170. The first conductive semiconductor layer 141 may have a thickness of 1.8 μm to 2.2 μm. However, the present invention is not limited thereto.

The first conductive semiconductor layer 141 may be formed of a compound semiconductor such as a group III-V group or a group II-VI, and may be doped with a first dopant. The first conductivity type first semiconductor layer 112 may have InxAlyGa1-x-yP (0≤x≤1, 0≤y≤1, 0≤x + y≤1) or InxAlyGa1-x-yN (0≤x≤1 , 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

The first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te. When the first dopant is an n-type dopant, the first conductive semiconductor layer 141 doped with the first dopant may be an n-type semiconductor layer.

The first conductive semiconductor layer 141 may include at least one of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.

The first conductive semiconductor layer 141 may be formed using a chemical vapor deposition method (CVD) or a molecular beam epitaxy (MBE) or a method such as sputtering or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto. .

The first clad layer 144 may be disposed on the first conductive semiconductor layer 141. The first clad layer 144 may be disposed between the first conductivity type semiconductor layer 141 and the active layer 142. The first clad layer 144 may include a plurality of layers. The first clad layer 144 may include an AlInP-based layer / AlInGaP-based layer.

The thickness d ₅ of the first cladding layer 144 may be 0.45 μm to 0.55 μm. However, the present invention is not limited thereto.

According to an embodiment, when both the first conductivity-type semiconductor layer 141 and the first cladding layer 144 are made of AlInP series, the etching speed is the same, so that a groove is formed between the first upper surface S11 and the boundary surface S12. (17) can be suppressed from occurring. In this case, when the amount of indium contained in the first conductivity-type semiconductor layer 141 is controlled to be higher than the amount of indium contained in the first cladding layer 144, the depth of the groove 17 may be controlled to be smaller.

The active layer 142 may be disposed on the first clad layer 144. The active layer 142 may be disposed between the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143. The active layer 142 is a layer where electrons (or holes) injected through the first conductive semiconductor layer 141 meet holes (or electrons) injected through the second conductive semiconductor layer 143. The active layer 142 transitions to a low energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.

The active layer 142 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure, and the active layer 142. ) Is not limited thereto.

The active layer 142 may be formed of a pair structure of any one or more of GaInP / AlGaInP, GaP / AlGaP, InGaP / AlGaP, InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs / AlGaAs, InGaAs / AlGaAs. However, the present invention is not limited thereto.

The thickness d ₆ of the active layer 142 may be 0.54 μm to 0.66 μm. However, the present invention is not limited thereto.

Electrons are cooled in the first cladding layer 144 so that the active layer 142 may generate more radiation recombination.

The second conductivity type semiconductor layer 143 may be disposed on the active layer 142. The second conductive semiconductor layer 143 may include a 2-1 conductive semiconductor layer 143a and a 2-2 conductive semiconductor layer 143b.

The 2-1 conductivity type semiconductor layer 143a may be disposed on the active layer 142. The 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a.

The 2-1 conductive semiconductor layer 143a may include TSBR and P-AllnP. The thickness d ₇ of the 2-1 conductive semiconductor layer 143a may be 0.57 μm to 0.70 μm. However, the present invention is not limited thereto.

The 2-1 conductive semiconductor layer 143a may be formed of a compound semiconductor, such as a III-V group or a II-VI group. The second dopant may be doped in the 2-1 conductive semiconductor layer 143a.

The 2-1 conductive semiconductor layer 143a may have InxAlyGa1-x-yP (0≤x≤1, 0≤y≤1, 0≤x + y≤1) or InxAlyGa1-x-yN (0≤x≤1 , 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). When the second conductivity-type semiconductor layer 143 is a p-type semiconductor layer, the p-type dopant may include Mg, Zn, Ca, Sr, Ba, or the like.

The 2-1 conductive semiconductor layer 143a may be a p-type semiconductor layer when the 2-1 conductive semiconductor layer 143a doped with the second dopant is doped.

The 2-2 conductivity type semiconductor layer 143b may be disposed on the 2-1 conductivity type semiconductor layer 143a. The second-second conductive semiconductor layer 143b may include a p-type GaP-based layer.

The second-second conductivity type semiconductor layer 143b may include a superlattice structure of a GaP layer / InxGa1-xP layer (where 0 ≦ x ≦ 1).

For example, Mg having a concentration of about 10 × ¹⁰ −18 may be doped into the 2-2 conductivity type semiconductor layer 143b, but is not limited thereto.

In addition, the second conductive semiconductor layer 143b may be formed of a plurality of layers, and Mg may be doped only in some layers.

The thickness d ₈ of the second-2 conductive semiconductor layer 143b may be 0.9 μm to 1.1 μm. However, the present invention is not limited thereto.

The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The first electrode 151 may be electrically connected to the first conductive semiconductor layer 141.

The first electrode 151 may be disposed on a portion of the upper surface where the mesa etching is performed in the first conductivity type semiconductor layer 141. Accordingly, the first electrode 151 may be disposed below the second electrode 152 disposed on the upper surface of the second conductive semiconductor layer 143.

The shortest width W ₂ in the 2-2 direction (Y ₂ axis direction) between the edge and the second electrode 152 in the 2-2 direction (Y ₂ axis direction) of the insulating layer 160 is 2.5 μm to 3.5 μm. Likewise, the shortest width W ₆ is 2.5 μm in the 2-1 direction (Y ₁ axis direction) between the edge and the first electrode 151 in the 2-1 direction (Y ₁ axis direction) of the insulating layer 160. To 3.5 μm. However, it is not limited to this length.

The first electrode 151 may be indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAZO), indium gallium zinc oxide (IGZO), or indium gallium tin (IGTO). oxide), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZO (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, or Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt At least one of Au, Hf, and the like may be formed, but is not limited thereto.

The first electrode 151 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition.

As described above, the second electrode 152 may be disposed on the second-second conductive semiconductor layer 143b. The second electrode 152 may be electrically connected to the second-second conductive semiconductor layer 143b.

The second electrode 152 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAZO), indium gallium zinc oxide (IGZO), and indium gallium tin (IGTO). oxide), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZO (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, or Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt At least one of Au, Hf, and the like may be formed, but is not limited thereto.

The second electrode 152 may be applied to all of the electrode forming methods commonly used, such as stuffing, coating, and deposition.

In addition, the first electrode 151 may have a larger width in the second direction (Y-axis direction) than the second electrode 152. However, it is not limited to this length.

The insulating layer 160 may cover the sacrificial layer 120, the coupling layer 130, and the semiconductor structure 140. The insulating layer 160 may cover the side of the sacrificial layer 120 and the side of the bonding layer 130. The insulating layer 160 may cover a portion of the upper surface of the first electrode 151. By such a configuration, the first electrode 151 may be electrically connected to the electrode or the pad through the exposed upper surface to inject a current. Similarly, the second electrode 152 may include an exposed upper surface like the first electrode 151. The insulating layer 160 may cover the coupling layer 130 and the sacrificial layer 120, and the sacrificial layer 120 and the coupling layer 130 may not be exposed to the outside.

The insulating layer 160 may cover a portion of the upper surface of the first electrode 151. In addition, the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the first electrode 151 may be exposed. A portion of the upper surface of the second electrode 152 may be exposed.

The top surface of the exposed first electrode 151 and the top surface of the exposed second electrode 152 may be circular, but are not limited thereto. The distance W ₄ in the second direction (Y-axis direction) between the center point of the exposed upper surface of the first electrode 151 and the center point of the upper surface of the second electrode 152 may be 20 μm to 30 μm. Here, the center point refers to a point that bisects the width of each of the exposed first electrode and the exposed second electrode in the second direction (Y-axis direction).

The insulating layer 160 may electrically separate the first conductive semiconductor layer 141 and the second conductive semiconductor layer 143 from the semiconductor structure 140. The insulating layer 160 may be formed by selecting at least one selected from the group consisting of SiO ₂ , SixOy, Si ₃ N ₄ , Si _x N _y , SiO _x N _y , Al ₂ O ₃ , TiO ₂ , AlN, and the like. It is not limited to this.

6A to 6G illustrate a method of manufacturing a semiconductor device array according to an embodiment of the present invention.

Referring to FIG. 6A, in the forming of the first substrate, ions may be implanted into the donor substrate S first. The donor substrate S may include an ion layer I. By the ion layer I, the donor substrate S may include an intermediate layer 170 disposed on one side and a first layer 171 disposed on the other side. The ions implanted into the donor substrate S may include hydrogen (H) ions, but are not limited thereto.

Referring to FIG. 6B, the sacrificial layer 120 may be disposed between the substrate 110 and the bonding layer 130.

The substrate 110 may be a light transmissive substrate including sapphire (Al ₂ O ₃ ), glass, or the like. Accordingly, the substrate 110 may transmit the laser light radiated from the bottom. Therefore, the sacrificial layer 120 may absorb the laser light during the laser lift-off.

The sacrificial layer 120 and the bonding layer 130 may be stacked on the substrate 110. The order of the sacrificial layer 120 and the bonding layer 130 may be reversed.

The bonding layer 130 disposed on the substrate may be disposed to face the bonding layer 130 disposed on the donor substrate S. The bonding layer 130 disposed on the substrate and the bonding layer 130 disposed on the donor substrate S may include SiO ₂ , but are not limited thereto.

The bonding layer 130 disposed on the sacrificial layer 120 may be combined with the bonding layer 130 disposed on the donor substrate S through an O ₂ plasma treatment. However, the present invention is not limited thereto, and cutting may be performed by a material other than oxygen.

As a result, the sacrificial layer 120 is disposed on the substrate 110, the bonding layer 130 is disposed on the sacrificial layer 120, and the donor substrate S is disposed to be spaced apart from the bonding layer 130. Can be.

Referring to FIG. 6C, the ion layer I of FIG. 6B may be removed by fluid jet cleaving, so that the first layer 171 may be separated from the intermediate layer 170.

At this time, the first layer 171 separated from the donor substrate may be reused as the substrate. Therefore, the manufacturing cost and cost reduction effect can be provided.

In the forming of the semiconductor structure layer on the first substrate, the semiconductor structure 140 may be formed on the intermediate layer 170. The intermediate layer 170 may contact the semiconductor structure 140. However, since the roughness of the upper surface is poor due to the void generated by the ion implantation process, the intermediate layer 170 may cause defects during red epi deposition.

Therefore, a planarization process may be performed on the upper surface of the intermediate layer 170. For example, chemical mechanical planarization may be performed on the upper surface of the intermediate layer 170, and the semiconductor structure 140 may be disposed on the upper surface of the intermediate layer 170 after the planarization. By such a configuration, the semiconductor structure 140 may have improved electrical characteristics.

The semiconductor structure 140 is disposed on the first conductive semiconductor layer 141 on the intermediate layer 170, on the first cladding layer 144 and on the first cladding layer 144. The active layer 142 may be disposed on the active layer 142 and the second conductive semiconductor layer 143 may be disposed on the active layer 142. A detailed configuration of the semiconductor structure 140 will be described later.

Referring to FIG. 6D, first etching may be performed to expose the first conductivity-type semiconductor layer 141 on the semiconductor structure 140.

Primary etching may be by wet etching or dry etching, but is not limited thereto, and various methods may be applied. Before the first etching is performed, the second electrode 152 of FIG. 6E may be disposed on the second conductive semiconductor layer 143 and patterned as shown in FIG. 6E. However, it is not limited to this method.

Referring to FIG. 6E, in the forming of the electrode on the semiconductor structure, the first electrode 151 and the second electrode 152 may be formed on the semiconductor structure 140.

The second electrode 152 may be electrically connected to the second-second conductive semiconductor layer 143b. The area of the bottom surface of the second electrode 152 may be smaller than the top surface of the second conductive semiconductor layer 143. For example, the second electrode 152 may be disposed 1 μm to 3 μm apart from an edge of the 2-2 conductivity type semiconductor layer 143b.

The first electrode 151 and the second electrode 152 may be applied to all the electrode forming methods commonly used, such as stuffing, coating, and deposition. However, the present invention is not limited thereto.

In addition, as described above, the second electrode 152 is formed before the primary etching, and the first electrode 151 is etched after the primary etching to be disposed on the exposed upper surface of the first conductive semiconductor layer 41. Can be.

The first electrode 151 and the second electrode 152 may be disposed at different positions from the substrate 110. The first electrode 151 may be disposed on the first conductive semiconductor layer 141. The second electrode 152 may be disposed on the second conductive semiconductor layer 143. Thus, the second electrode 152 may be disposed above the first electrode 151.

Referring to FIG. 6F, in the cutting of the plurality of semiconductor structures, secondary etching may be performed to the upper surface of the substrate 110. Secondary etching may be by wet etching or dry etching, but is not limited thereto. In the semiconductor device, the secondary etching may have a thickness greater than that of the primary etching.

The semiconductor structure disposed on the substrate through the secondary etching may be isolated in the form of a plurality of chips. For example, two semiconductor structures may be disposed on the substrate 110 through secondary etching in FIG. 6F. The number of semiconductor structures may be variously set according to the size of the substrate and the size of the semiconductor structure. In this case, the steps of separating the semiconductor structure and forming the electrode may be reversed. That is, after forming the electrode first, the semiconductor structure may be separated, or after separating the semiconductor structure, the electrode may be formed. In addition, an electrode may be formed after first etching the semiconductor structure, and then the semiconductor structure may be separated.

In this case, the secondary etching may proceed to a part of the substrate 110 through the semiconductor structure. Accordingly, the substrate 110 may have a groove H1 disposed between the plurality of semiconductor structures. Since the groove H1 of the substrate is formed in the process of etching the semiconductor structure 140, the sidewalls of the groove H1 may have the same inclination angle as the side surfaces of the plurality of semiconductor structures 140. However, the present invention is not limited thereto, and the groove H1 of the substrate may be formed by a separate etching process.

According to this configuration, the bonding layer 120 and / or the sacrificial layer 130 disposed between the plurality of semiconductor structures can be reliably removed. The depth of the groove H1 is not particularly limited as long as it can remove the bonding layer 120 and / or the sacrificial layer 130 disposed between the semiconductor structures.

If the bonding layer and / or the sacrificial layer of the semiconductor structure are connected to each other, it may affect the neighboring semiconductor structure when the semiconductor structure is separated from the substrate.

For example, when only one semiconductor structure is separated from a substrate, a problem may occur in that a sacrificial layer of a neighboring semiconductor structure is also separated from the substrate.

Referring to FIG. 6G, in the forming of the insulating layer, the insulating layer 160 may be formed on the plurality of semiconductor structures 140 and the groove H1. The insulating layer 160 may cover side surfaces of the sacrificial layer 120, the coupling layer 130, the intermediate layer 170, and the semiconductor structure 140.

The insulating layer 160 may cover a portion of the upper surface of the first electrode 151. A portion of the upper surface of the first electrode 151 may be exposed. An upper surface of the exposed first electrode 151 may be electrically connected to an electrode pad or the like to inject current.

In addition, the insulating layer 160 may cover a portion of the upper surface of the second electrode 152. A portion of the upper surface of the second electrode 152 may be exposed. Like the first electrode 151, the exposed top surface of the second electrode 152 may be electrically connected to an electrode pad or the like to inject current. A portion of the insulating layer 160 may be disposed on the upper surface of the substrate. The insulating layer 160 disposed between the adjacent semiconductor chips may be in contact with the substrate 110.

Referring to FIG. 6G, the fabricated semiconductor device array may include a substrate 110 and a plurality of semiconductor devices 10 disposed on the substrate 110. According to an embodiment, a plurality of semiconductor devices 10 may be disposed on the substrate 110.

The plurality of semiconductor devices 10 may include a first conductive semiconductor layer 144, a second conductive semiconductor layer 143, and a first conductive semiconductor layer 144 and a second conductive semiconductor layer 143. The semiconductor structure 140 including the active layer 142 disposed on the insulating layer 160, the insulating layer 160 disposed on the semiconductor structure 140, and the first conductive semiconductor layer 144 and the first conductive semiconductor layer 144. The first electrode 151 connected to the second electrode 151 and the second electrode 152 electrically connected to the second conductive semiconductor layer 143 through the insulating layer 160 may be included.

As described above, the substrate 110 may include a groove H1 disposed between the plurality of semiconductor structures 140. The groove H1 may have a line shape, but is not limited thereto.

The insulating layer 160 may include a first insulating layer 161 disposed on the top and side surfaces of the semiconductor structure 140, and a second insulating layer 162 disposed in the groove H1 of the substrate 110. have. In this case, the first insulating layer 161 and the second insulating layer 162 may be connected to each other.

The insulating layer 160 may cover the plurality of semiconductor structures 140, one surface of the substrate 110, and the groove H1 of the substrate 110.

The upper surface of the semiconductor structure 140 may include a first upper surface S11 on which the first electrode 151 is disposed, a second upper surface S13 on which the second electrode 152 is disposed, and a first upper surface S1. And an inclined surface S12 disposed between the second upper surface S2.

At this time, the difference between the height d1 from the bottom surface of the semiconductor structure 140 to the second upper surface S13 and the height d2 from the bottom surface of the semiconductor structure 140 to the first upper surface S11 ( d3) may be greater than 0 and less than 2 μm.

When the height difference P3 between the first upper surface S11 and the second upper surface S13 is greater than 2 μm, the chip may be horizontally displaced during the transfer process. That is, the larger the step, the more difficult the chip is to keep horizontal. The transfer process may refer to an operation of moving the chip from the growth substrate to another substrate as shown in FIG. 3.

The first angle θ ₁ formed by the inclined surface S12 with the horizontal plane may be smaller than the second angle θ ₂ formed between the side surface of the semiconductor structure 140 and the horizontal plane. The first angle θ _{1 that the} inclined surface S12 makes with the virtual horizontal surface may be 20 ° to 50 °. When the first angle θ ₁ is smaller than 20 °, the area of the second upper surface S13 may be reduced, thereby lowering the light output. In addition, when the first angle θ ₁ is greater than 50 °, the inclination angle may be increased to increase the risk of damage due to external impact.

The second angle θ ₂ formed at the side surface of the semiconductor structure 120 with the horizontal plane may be greater than 70 ° and less than 90 °. When the second angle θ ₂ is smaller than 70 °, the area of the second upper surface S13 may be reduced, thereby lowering the light output. When the second angle θ ₂ formed at all sides of the semiconductor structure 120 with the horizontal plane is smaller than 90 °, the area of the inclined surface S12 is gradually increased from the first upper surface S11 to the second upper surface S13. Can be narrowed.

7A to 7E are views illustrating a method of transferring a semiconductor device according to an embodiment of the present invention.

7A to 7E, a method of transferring a semiconductor device, according to an embodiment, separates a semiconductor device from a substrate by selectively irradiating a laser to a semiconductor device including a plurality of semiconductor devices disposed on the substrate 110. And disposing the separated semiconductor element on the panel substrate. Here, the semiconductor element before the transfer may include the configuration of FIGS. 1A to 1G as before.

First, referring to FIG. 7A, the substrate 110 may be the same as the substrate 110 described above with reference to FIGS. 1A to 1G. In addition, as described above, a plurality of semiconductor devices may be disposed on the substrate 110. For example, the plurality of semiconductor devices may include a first semiconductor device 10-1, a second semiconductor device 10-2, a third semiconductor device 10-3, and a fourth semiconductor device 10-4. have. However, the present invention is not limited thereto, and the semiconductor device may have various numbers.

Referring to FIG. 7B, at least one semiconductor device selected from the plurality of semiconductor devices 10-1, 10-2, 10-3, and 10-4 may be separated into a growth substrate using the transfer mechanism 210. . The conveyance mechanism 210 may include the first bonding layer 211 and the conveyance frame 212 disposed below. For example, the carrier frame 212 may have an uneven structure, and may easily bond the semiconductor element and the first bonding layer 211 to each other. In this case, the semiconductor device according to the embodiment may have a level less than 2 μm so that the semiconductor device may be horizontal during the transfer process.

Referring to FIG. 7C, when the laser irradiation is selectively performed on the rear surfaces of the semiconductor devices 10-1 and 10-3 to be separated, the sacrificial layers of the semiconductor devices 10-1 and 10-3 are decomposed and the substrate 110 is separated. Can be separated from. Thereafter, when the transfer mechanism 210 is moved upward, the first semiconductor element 10-1 and the third semiconductor element 10-3 may be separated from the transfer mechanism 210. In addition, coupling between the second bonding layer 310, the first semiconductor device 10-1, and the third semiconductor device 10-3 may be performed.

As a method of separating the semiconductor device from the substrate 110, a laser lift-off (LLO) using a photon beam having a specific wavelength band may be applied. For example, the center wavelength of the irradiated laser may be 266 nm, 532 nm, or 1064 nm, but is not limited thereto.

In this case, the bonding layer 130 disposed between the semiconductor device and the substrate 110 may prevent physical damage between the semiconductor devices due to laser lift-off (LLO). The sacrificial layer may be separated from the semiconductor device by laser lift-off (LLO). For example, the sacrificial layer may be partially removed due to separation and the remaining sacrificial layer may be separated together with the bonding layer. Accordingly, in the semiconductor device, the sacrificial layer and the bonding layer, the semiconductor structure, the first electrode, and the second electrode, which are layers disposed on the sacrificial layer, may be separated into the substrate 110.

In addition, the plurality of semiconductor devices separated by the substrate 110 may have a predetermined distance from each other. As described above, the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from the growth substrate, and the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from each other. The second semiconductor device 10-2 and the fourth semiconductor device 10-4 having the same separation distance from each other may be separated in the same manner. As a result, semiconductor devices having the same separation distance may be transferred to the display panel.

Referring to FIG. 7D, the selected semiconductor device may be disposed on the panel substrate 300. For example, the first semiconductor element 10-1 and the third semiconductor element 10-3 may be disposed on the panel substrate 300.

In detail, the second bonding layer 310 may be disposed on the panel substrate 300, and the first semiconductor element 10-1 and the third semiconductor element 10-3 may be disposed on the second bonding layer 310. It can be placed on. Thus, the first semiconductor device 10-1 and the third semiconductor device 10-3 may be in contact with the second bonding layer 310. In this manner, semiconductor devices having spaced intervals may be disposed on the panel substrate to improve the efficiency of the transfer process.

A laser may be irradiated to separate the first bonding layer 211 and the selected semiconductor device. For example, the laser may be irradiated onto the transfer mechanism 210 to physically separate the first bonding layer 211 and the selected semiconductor device. For example, the bonding layer 211 may lose the adhesive function when the laser is irradiated.

Referring to FIG. 7E, when the transfer mechanism 210 is moved upward after laser irradiation, the first semiconductor element 10-1 and the third semiconductor element 10-3 may be separated from the transfer mechanism 210. have. In addition, coupling between the second bonding layer 310, the first semiconductor device 10-1, and the third semiconductor device 10-3 may be performed.

8 is a conceptual diagram of a display device to which a semiconductor device is transferred according to an exemplary embodiment.

Referring to FIG. 8, according to an embodiment, a display device including a semiconductor device includes a second panel substrate 410, a driving thin film transistor T2, a planarization layer 430, a common electrode CE, a pixel electrode AE, and a semiconductor. It may include a device.

The driving thin film transistor T2 includes a gate electrode GE, a semiconductor layer SCL, an ohmic contact layer OCL, a source electrode SE, and a drain electrode DE.

The driving thin film transistor is a driving device and may be electrically connected to the semiconductor device to drive the semiconductor device.

The gate electrode GE may be formed together with the gate line. The gate electrode GE may be covered with the gate insulating layer 440.

The gate insulating layer 440 may be formed of a single layer or a plurality of layers made of an inorganic material, and may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like.

The semiconductor layer SCL may be disposed on the gate insulating layer 440 in a predetermined pattern (or island) form so as to overlap the gate electrode GE. The semiconductor layer SCL may be formed of a semiconductor material including any one of amorphous silicon, polycrystalline silicon, oxide, and organic material, but is not limited thereto.

The ohmic contact layer OCL may be disposed on the semiconductor layer SCL in a predetermined pattern (or island) form. The ohmic contact layer PCL may be for an ohmic contact between the semiconductor layer SCL and the source / drain electrodes SE and DE.

The source electrode SE is formed on the other side of the ohmic contact layer OCL to overlap one side of the semiconductor layer SCL.

The drain electrode DE may be formed on the other side of the ohmic contact layer OCL to be spaced apart from the source electrode SE while overlapping the other side of the semiconductor layer SCL. The drain electrode DE may be formed together with the source electrode SE.

The planarization layer may be disposed on an entire surface of the second panel substrate 410. The driving thin film transistor T2 may be disposed in the planarization layer. The planarization layer according to an embodiment may include an organic material such as benzocyclobutene or photo acryl, but is not limited thereto.

The groove 450 may be a predetermined emission region, and a semiconductor device may be disposed. Here, the light emitting area may be defined as a remaining area of the display apparatus except for a circuit area.

The groove 450 may be concave in the planarization layer 430, but is not limited thereto.

The semiconductor device may be disposed in the groove 450. The first and second electrodes of the semiconductor device may be connected to a circuit (not shown) of the display device.

The semiconductor device may be attached to the groove 450 through the adhesive layer 420. Here, the adhesive layer 420 may be the second bonding layer, but is not limited thereto.

The second electrode 152 of the semiconductor device may be electrically connected to the source electrode SE of the driving thin film transistor T2 through the pixel electrode AE. The first electrode 151 of the semiconductor device may be connected to the common power line CL through the common electrode CE.

The first and second electrodes 151 and 152 may be stepped with each other, and the electrode 151 at a relatively lower position among the first and second electrodes 151 and 152 may be the same as the top surface of the planarization layer 430. It can be located on a horizontal line. However, the present invention is not limited thereto.

The pixel electrode AE may electrically connect the source electrode SE of the driving thin film transistor T2 and the second electrode of the semiconductor device.

The common electrode CE may electrically connect the common power line CL and the first electrode of the semiconductor device.

The pixel electrode AE and the common electrode CE may each include a transparent conductive material. The transparent conductive material may include a material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

According to an exemplary embodiment of the present invention, the display device may have a standard definition (SD) resolution (760 × 480), a high definition (1180 × 720) resolution, a full HD (FHD) resolution (1920 × 1080), or a UH. (Ultra HD) resolution (3480 × 2160), or UHD or higher resolution (eg 4K (K = 1000), 8K, etc.) can be implemented. In this case, the semiconductor device according to the embodiment may be arranged and connected in plurality in accordance with the resolution.

In addition, the display device may be a display panel or a TV having a diagonal size of 100 inches or more, and the pixel may be implemented as a light emitting diode (LED). Thus, power consumption can be lowered and provided with a long life at low maintenance costs, and can be provided with a high brightness self-luminous display.

Since the embodiment implements an image and an image by using a semiconductor device, color purity and color reproduction are excellent.

The embodiment implements an image and an image by using a light emitting device package having excellent linearity, thereby enabling a clear large display device of 100 inches or more.

The embodiment can realize a high resolution 100 inch or larger display device at low cost.

The semiconductor device according to the embodiment may further include an optical member such as a light guide plate, a prism sheet, and a diffusion sheet to function as a backlight unit. In addition, the semiconductor device of the embodiment may be further applied to a display device, a lighting device, and a pointing device.

In this case, the display device may include a bottom cover, a reflector, a light emitting module, a light guide plate, an optical sheet, a display panel, an image signal output circuit, and a color filter. The bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit.

The reflecting plate is disposed on the bottom cover, and the light emitting module emits light. The light guide plate is disposed in front of the reflective plate to guide light emitted from the light emitting module to the front, and the optical sheet includes a prism sheet or the like and is disposed in front of the light guide plate. The display panel is disposed in front of the optical sheet, the image signal output circuit supplies the image signal to the display panel, and the color filter is disposed in front of the display panel.

The lighting apparatus may include a light source module including a substrate and a semiconductor device of an embodiment, a heat dissipation unit for dissipating heat of the light source module, and a power supply unit for processing or converting an electrical signal provided from the outside and providing the light source module to the light source module. . Furthermore, the lighting device may include a lamp, a head lamp, a street lamp or the like.

In addition, the camera flash of the mobile terminal may include a light source module including the semiconductor device of the embodiment.

Although the above description has been made with reference to the embodiments, these are only examples and are not intended to limit the present invention, and those of ordinary skill in the art to which the present invention pertains should not be exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

Claims (10)

A semiconductor structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer;
A first electrode electrically connected to the first semiconductor layer; And
A second electrode electrically connected to the second semiconductor layer;
The semiconductor structure may include a first upper surface on which the first semiconductor layer is exposed, a second upper surface on which the second semiconductor layer is disposed, an inclined surface connecting the first upper surface and the second upper surface, and the first upper surface. A groove formed between the first upper surface and the inclined surface,
And a depth of the groove is 30% or less of a vertical distance between the first upper surface and the second upper surface.
The method of claim 1,
The second semiconductor layer includes a first sub semiconductor layer exposed to the first upper surface, and a second sub semiconductor layer disposed on the first sub semiconductor layer.
The first sub-semiconductor layer and the second sub-semiconductor layer have a etching rate difference of 30% or less under the same etching conditions.
The method of claim 2,
The first sub-semiconductor layer has a faster etching rate than the second sub-semiconductor layer.
The method of claim 2,
The first sub semiconductor layer includes GaAs,
The second sub-semiconductor layer includes AlInP.
The method of claim 4, wherein
The first sub-semiconductor layer further includes In,
The In composition of the first sub-semiconductor layer is higher than the In composition of the second sub-semiconductor layer.
The method of claim 2,
The first sub-semiconductor layer and the second sub-semiconductor layer have the same composition.
The method of claim 1,
The ratio of the first vertical height from the bottom surface of the semiconductor structure to the second upper surface and the second vertical height from the bottom surface of the semiconductor structure to the first upper surface is 1: 0.6 to 1: 0.95 .
The method of claim 7, wherein
And a difference between the first vertical height and the second vertical height is less than 2 μm.
The method of claim 1,
The first angle of the inclined surface and the horizontal plane is smaller than the second angle formed by the side surface of the semiconductor structure and the horizontal plane.
The method of claim 9,
The first angle is 20 ° to 80 °, the second angle is 70 ° to 90 ° semiconductor device.

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