KR102367758B1 - Semiconductor device - Google Patents

Abstract

The embodiment includes a first conductivity type semiconductor layer; an active layer disposed on the first conductivity-type semiconductor layer; a second conductivity-type semiconductor layer disposed on the active layer; a first electrode electrically connected to the first conductivity-type semiconductor layer; and a second electrode electrically connected to the second conductivity-type semiconductor layer, wherein an area ratio between an upper surface of the second conductivity-type semiconductor layer and a lower surface of the second electrode is 1:0.39 to 1:0.86. do.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The embodiment relates to a semiconductor device.

A light emitting diode (LED) is one of light emitting devices that emits light when an electric current is applied thereto. Light-emitting diodes can emit high-efficiency light with a low voltage, and thus have an excellent energy-saving effect. Recently, the luminance problem of light emitting diodes has been greatly improved, and it has been applied to various devices such as a backlight unit of a liquid crystal display device, an electric sign board, a display device, and a home appliance.

A light emitting diode having AlGaInP uses a GaAs substrate as a growth substrate. However, in order to manufacture a semiconductor device type, it is necessary to remove the GaAs substrate to prevent light absorption. However, the GaAs substrate is difficult to remove through the conventional laser lift-off (LLO) process, and there is a problem in that harmful gases are discharged during the process.

The embodiment provides a semiconductor device of a horizontal type.

In addition, an excellent semiconductor device with improved co-velocity is provided.

In addition, there is provided a semiconductor device that prevents low current failure and wavelength shift.

In addition, there is provided a semiconductor device with improved external quantum efficiency.

The problem to be solved in the embodiment is not limited thereto, and it will be said that the purpose or effect that can be grasped from the method of solving the problem described below or the embodiment is also included.

A semiconductor device according to an embodiment includes a first conductivity type semiconductor layer; an active layer disposed on the first conductivity-type semiconductor layer; a second conductivity-type semiconductor layer disposed on the active layer; a first electrode electrically connected to the first conductivity-type semiconductor layer; and a second electrode electrically connected to the second conductivity-type semiconductor layer, wherein an area ratio between an upper surface of the second conductivity-type semiconductor layer and a lower surface of the second electrode is 1:0.39 to 1:0.86.

An edge of the lower surface of the second electrode may be spaced apart from an edge of the upper surface of the second conductivity-type semiconductor layer by 1 µm to 3 µm.

A ratio of an area of an upper surface of the first conductivity-type semiconductor layer to an area of a lower portion of the active layer may be 1:0.5 to 1:0.85.

An area ratio of the upper surface of the active layer and the lower surface of the second electrode may be 1:0.4 to 1:0.67.

An area of the lower surface of the first conductivity type semiconductor layer may be 800 μm ² to 1200 μm ² .

An insulating layer disposed on the first conductivity-type semiconductor layer, the active layer, and the second conductivity-type semiconductor layer, the insulation layer may be partially disposed on upper surfaces of the first electrode and the second electrode .

A semiconductor device according to an embodiment includes a first conductivity type semiconductor layer; an active layer disposed on the first conductivity-type semiconductor layer; a second conductivity-type semiconductor layer disposed on the active layer; a first electrode electrically connected to the first conductivity-type semiconductor layer; and a second electrode electrically connected to the second conductivity-type semiconductor layer, wherein an injection current of the second electrode is 0.1 μA or more, and a current density of the second electrode is 0.025A/cm ² More than that.

An electronic device according to an embodiment includes a semiconductor element; and a case accommodating the semiconductor device, wherein the semiconductor device includes: a first conductivity type semiconductor layer; an active layer disposed on the first conductivity-type semiconductor layer; a second conductivity-type semiconductor layer disposed on the active layer; a first electrode electrically connected to the first conductivity-type semiconductor layer; and a second electrode electrically connected to the second conductivity-type semiconductor layer, wherein an area ratio between an upper surface of the second conductivity-type semiconductor layer and a lower surface of the second electrode is 1:0.39 to 1:0.86.

According to an embodiment, the semiconductor device may be implemented in a horizontal type.

In addition, excellent semiconductor devices with improved luminous flux can be manufactured.

In addition, it is possible to manufacture a semiconductor device with improved external quantum efficiency while preventing low current failure and wavelength shift.

Various and advantageous advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1 is a cross-sectional view and a plan view of a semiconductor device according to an embodiment;
2 to 3 are plan views of a semiconductor device according to the embodiment;
4 is a view showing the wavelength according to the current of the semiconductor device according to the embodiment,
5 is a view showing a change in gradation according to an injection current of a semiconductor device;
6 is a view showing the luminous intensity for each wavelength according to the injection current of the semiconductor device,
7 is a view for explaining a low current failure of a semiconductor device,
8 is a diagram illustrating external quantum efficiency (EQE) according to the size of a semiconductor device;
9A to 9F are flowcharts of a method of manufacturing a semiconductor device according to an embodiment;
10A to 10E are flowcharts illustrating a process of transferring a semiconductor device to a display device according to an embodiment;
11 is a conceptual diagram of a display device to which a semiconductor element is transferred according to an embodiment;
Figure 12 is a modification of Figure 1,
13 is a cross-sectional view of a semiconductor device according to another exemplary embodiment.

Since the present invention may have various changes and may have various embodiments, specific embodiments will be illustrated and described in the drawings. However, this is not intended to limit the present invention to specific embodiments, and it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

Terms including an ordinal number such as second, first, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be referred to as the first component, and similarly, the first component may also be referred to as the second component. and/or includes a combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but it is understood that other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It should be understood that this does not preclude the existence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application. does not

Hereinafter, the embodiment will be described in detail with reference to the accompanying drawings, but the same or corresponding components are given the same reference numerals regardless of reference numerals, and overlapping descriptions thereof will be omitted.

Also, the semiconductor device package according to the present embodiment may include a small semiconductor device. Here, the small semiconductor device may refer to a structural size of the semiconductor device. In addition, the small semiconductor device may have a structural size of 1 μm to 100 μm. In addition, the semiconductor device according to the embodiment may have a structural size of 30 μm to 60 μm as described below, but is not necessarily limited thereto. In addition, the technical features or aspects of the embodiment may be applied to a semiconductor device on a smaller scale.

1 is a cross-sectional view and a plan view of a semiconductor device according to an embodiment.

Referring to FIG. 1 , the semiconductor device 10 according to the embodiment may include a substrate, a semiconductor structure 120 , a first electrode 131 , a second electrode 132 , and an insulating layer 141 .

First, a substrate (not shown) may be disposed under the semiconductor device 10 according to the embodiment.

The substrate (not shown) may be formed of a material selected from among sapphire (Al ₂ O ₃ ), SiC, GaAs, GaN, ZnO, Si, GaP, InP, and Ge, but is not limited thereto.

The semiconductor structure 120 may be disposed on a substrate. A buffer layer (not shown) may be further provided between the semiconductor structure 120 and the substrate. The buffer layer may alleviate a lattice mismatch between the semiconductor structure 120 provided on the substrate (not shown) and the substrate.

For example, the buffer layer may be a combination of Group III and V elements or may include any one of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN. The buffer layer may be doped with a dopant, but is not limited thereto.

The semiconductor structure 120 may include a first conductivity type semiconductor layer 121 , an active layer 122 , and a second conductivity type semiconductor layer 123 . The semiconductor structure 120 may have a structure in which a first conductivity-type semiconductor layer 121 , an active layer 122 , and a second conductivity-type semiconductor layer 123 are sequentially stacked in the 1-1 direction. For example, in the semiconductor structure 120 , the first conductivity type semiconductor layer 121 is disposed on the outermost side in the 1-2 direction, and the second conductivity type semiconductor layer 123 is disposed on the outermost side in the first-1 direction. can be Here, the first direction includes a 1-1 direction and a 1-2 direction in the thickness direction of the semiconductor structure 120 . The 1-1 direction is a direction from the first conductivity type semiconductor layer 121 toward the second conductivity type semiconductor layer 123 among the thickness directions of the semiconductor structure 120 . In addition, the 1-2 direction is a direction from the second conductivity type semiconductor layer 123 toward the first conductivity type semiconductor layer 121 among the thickness directions of the semiconductor structure 120 .

The semiconductor structure 120 may be formed by a metal organic chemical vapor deposition (MOCVD) method, a chemical vapor deposition method (CVD), a plasma-enhanced chemical vapor deposition (PECVD) method, or a molecular beam growth method (Molecular Beam). Epitaxy; MBE), hydride vapor phase epitaxy (HVPE), can be formed using a method such as sputtering (Sputtering).

The first conductivity type semiconductor layer 121 may be implemented with a group III-V group or group II-VI compound semiconductor, and the first conductivity type semiconductor layer 121 may be doped with a first dopant. The first conductivity type semiconductor layer 121 is a semiconductor material having a composition formula of AlxInyGa(1-xy)N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), InAlGaN, AlGaAs, GaP , GaAs, GaAsP, may be formed of any one or more of AlGaInP, but is not limited thereto. When the first dopant is an n-type dopant such as Si, Ge, Sn, Se, or Te, the first conductivity-type semiconductor layer 121 may be an n-type nitride semiconductor layer.

The thickness d ₁ of the first conductivity-type semiconductor layer 121 in the 1-1 direction (X ₁ axis direction) may be 3.0 μm to 6.0 μm. However, it is not limited to this thickness.

The active layer 122 may be disposed on the first conductivity-type semiconductor layer 121 . Also, the active layer 122 may be disposed between the first conductivity-type semiconductor layer 121 and the second conductivity-type semiconductor layer 123 .

The thickness d2 of the active layer 122 in the 1-1 direction (X1-axis direction) may be 100 nm to 180 nm. However, the length is not limited thereto, and may be variously changed according to the size of the semiconductor device 10 .

The active layer 122 is a layer in which electrons (or holes) injected through the first conductivity type semiconductor layer 121 and holes (or electrons) injected through the second conductivity type semiconductor layer 123 meet. The active layer 122 may transition to a low energy level as electrons and holes recombine, and may generate light having a corresponding wavelength.

The active layer 122 may have any one of a single well structure, a multi-well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the active layer 122 . The structure of is not limited thereto. The active layer 122 may include Al.

The second conductivity type semiconductor layer 123 may be disposed on the active layer 122 . The second conductivity-type semiconductor layer 123 is formed on the active layer 122 , and may be implemented with a compound semiconductor such as III-V group or II-VI group, and is formed on the second conductivity-type semiconductor layer 123 on the second conductivity-type semiconductor layer 123 . A dopant may be doped. The second conductivity type semiconductor layer 123 is a semiconductor material having a composition formula of Inx5Aly2Ga1-x5-y2N (0≤x5≤1, 0≤y2≤1, 0≤x5+y2≤1) or AlInN, AlGaAs, GaP, GaAs , GaAsP, may be formed of a material selected from AlGaInP. When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, or Ba, the second conductivity-type semiconductor layer 123 doped with the second dopant may be a p-type semiconductor layer.

The thickness d3 of the second conductivity-type semiconductor layer 123 in the 1-1 direction (X1-axis direction) may be 250 nm to 350 nm. However, it is not limited to this thickness.

The first electrode 131 may be disposed on the first conductivity-type semiconductor layer 121 . Here, the first conductivity type semiconductor layer 121 may be partially exposed by etching. In addition, the first electrode 131 may be disposed on the first conductivity-type semiconductor layer 121 exposed by etching. 1-1 between the lowest surface in the 1-2 direction (X2-axis direction) of the first electrode 131 and the lowest surface in the 1-2 direction (X2-axis direction) of the first conductivity-type semiconductor layer 121 The thickness d5 in the direction (X1-axis direction) may be 3.2 μm to 5.8 μm.

The first electrode 131 may be electrically connected to the first conductivity-type semiconductor layer 121 . The second electrode 132 may be disposed on the second conductivity-type semiconductor layer 123 . The second electrode 132 may be electrically connected to the second conductivity-type semiconductor layer 123 .

The first electrode 131 and the second electrode 132 include indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), and indium gallium zinc oxide (IGZO). ), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx/ITO, may be formed including at least one of Ni/IrOx/Au, but is not limited thereto.

The thickness d6 of the first electrode 131 in the 1-1 direction (X1-axis direction) may be 4.8 nm to 7.2 nm. Also, the thickness d4 of the second electrode 132 in the 1-1 direction (X1-axis direction) may be 4.8 nm to 7.2 nm. However, it is not limited to this thickness.

The insulating layer 141 may be disposed to cover the semiconductor structure 120 while exposing only a portion of the first electrode 131 and the second electrode 132 . The insulating layer 141 may electrically insulate the semiconductor structure 120 from the outside. The insulating layer 141 may include at least one of SiO ₂ , SixOy, Si ₃ N ₄ , SixNy, SiOxNy, Al ₂ O ₃ , TiO ₂ , and AlN, but is not limited thereto.

2 to 3 are plan views of the semiconductor device 10 according to the embodiment.

Referring to FIG. 2 , the second conductivity-type semiconductor layer 123 of the semiconductor device 10 according to the embodiment may include first to fourth surfaces that are outermost surfaces.

Here, the second direction (Y-axis direction) may include a 2-1 direction and a 2-2 direction in a direction perpendicular to the first direction (X-axis direction). The 2-1 direction (Y ₁ axis direction) is a direction from the second electrode 132 of the semiconductor structure 120 toward the first electrode 131 in FIG. 2 . And the 2-2 direction (Y ₂ axis direction) is a direction from the first electrode 131 of the semiconductor structure 120 to the second electrode 132 in a direction opposite to the 2-1 direction (Y ₁ axis direction). am. And the third direction (Z-axis direction) is a direction perpendicular to the first direction (X-axis direction) and the second direction (Y-axis direction), the 3-1 direction (Z ₁ -axis direction) and the 3-2 direction ( Z ₂ axis direction). The 3-1 direction (Z ₁ axis direction) is a direction toward the front surface of the semiconductor structure 120 , and the 3-2 direction (Z ₂ axis direction) is opposite to the 3-1 direction (Z ₁ axis direction). As such, it may be a direction toward the rear surface of the semiconductor structure 120 .

First, the semiconductor device 10 may have a length L ₁ of 30 μm to 60 μm in the second direction (Y-axis direction). In addition, the semiconductor device 10 may have a width W ₁ of 10 μm to 30 μm in the third direction (Z-axis direction). However, it is not limited to these lengths and widths.

The length L ₁ in the second direction (Y-axis direction) and the width W ₁ in the third direction (Z-axis direction) of the semiconductor device 10 are the second direction of the first conductivity-type semiconductor layer 121 . It may be the same as the maximum length in the (Y-axis direction) and the maximum width in the third direction (the Z-axis direction).

And the semiconductor device 10 according to the embodiment is the size of the semiconductor device 10 through the product of the length (L ₁ ) in the second direction (Y-axis direction) and the width (W ₁ ) in the third direction (Z-axis direction) can be calculated.

Since the active layer 122 is disposed on the first conductivity-type semiconductor layer 121 , a planar area of the active layer 122 may be smaller than a planar area of the first conductivity-type semiconductor layer 121 .

Since the second conductivity type semiconductor layer 123 is disposed on the active layer 122 , the planar area of the second conductivity type semiconductor layer 123 is the planar area of the first conductivity type semiconductor layer 121 and the active layer 122 . may be smaller than the area.

The second conductivity-type semiconductor layer 123 may have a length L ₂ of 19.5 μm to 25.5 μm in the second direction (Y-axis direction). In addition, the width W ₂ of the second conductivity-type semiconductor layer 123 in the third direction (Z-axis direction) may be 16 μm to 24 μm. However, it is not limited to these lengths and widths.

The second conductivity-type semiconductor layer 123 of the semiconductor device 10 according to the embodiment has a length L ₂ in the second direction (Y-axis direction) and a width W ₂ in the third direction (Z-axis direction). Through the product, the area S ₁ of the second conductivity-type semiconductor layer 123 on a plane may be calculated. And the area S ₁ of the second conductivity type semiconductor layer 123 may be the area of the outermost surface of the second conductivity type semiconductor layer 123 in the 1-1 direction (X ₁ axis direction).

In addition, the second conductivity-type semiconductor layer 123 may include first to fourth corners. The first corner P ₁ may be a corner formed at the outermost side in the 2-2 direction (Y ₂ axis direction). The second corner P ₂ is connected to the first corner P ₁ and the third corner P ₃ , and may be an outermost corner formed in the 3-2 direction (Z ₂ axis direction) side. The third corner P ₃ is connected to the second corner P ₂ and the fourth corner P ₄ , and may be an outermost corner formed in the 2-1 direction (Y ₁ axis direction) side. And the fourth corner (P ₄ ) is connected to the first corner (P ₁ ) and the third corner (P ₄ ), and may be an outermost corner formed in the 3-1 direction (Z ₁ axis direction).

In addition, the second electrode 132 is disposed on the second conductivity-type semiconductor layer 123 , and the planar area of the second electrode 132 may be smaller than the planar area of the second conductivity-type semiconductor layer 123 . there is. The second electrode 132 may have a length L ₃ of 16.5 μm to 24.5 μm in the second direction (Y-axis direction). In addition, the width W ₃ of the second electrode 132 in the third direction (Z-axis direction) may be 15 μm to 23 μm. The second electrode 132 of the semiconductor device 10 according to the embodiment is flat through the product of the length L ₃ in the second direction (Y-axis direction) and the width W ₃ in the third direction (Z-axis direction). The area S ₂ of the upper second electrode 132 may be calculated. The area S ₂ of the second electrode 132 may be the area of the outermost surface of the second electrode 132 in the 1-2 direction (X ₂ axis direction).

The second electrode 132 may include a fifth corner P _{5 to} an eighth corner P ₈ . The fifth corner P ₅ may be an outermost corner formed in the 2-2 direction (Y ₂ axis direction) side. The sixth corner P ₆ may be a corner connected to the fifth corner P ₅ and the seventh corner P ₇ and formed at the outermost side in the 3-2 direction (Z ₂ axis direction). The seventh corner P ₇ is connected to the sixth corner P ₆ and the eighth corner P ₈ , and may be an outermost corner formed in the 2-1 direction (Y ₁ axis direction) side. And the eighth corner (P ₈ ) is connected to the fifth corner (P ₅ ) and the seventh corner (P ₇ ), and may be an outermost corner formed in the 3-1 direction (Z ₁ axis direction).

And the gap between the first edge (P ₁ ) and the outermost edge of the first conductivity-type semiconductor layer 121 in the 2-2 direction (Y- ₂ axis direction) and the first edge (P ₁ ) and the fifth edge (P ₅ ) The interval between the third edge (P ₃ ) and the third edge (P ₃ ) and the third edge ( It may be smaller than the interval between P ₃ ) and the seventh edge P ₇ . Here, since this spacing is affected by the thickness of each layer of the semiconductor structure 120 , it may be applied when the same height is assumed. And this is because the first inclination angle θ ₁ has an angle greater than the second inclination angle θ ₂ . Here, the first inclination angle θ ₁ is a side inclination angle in the 2-2 direction (Y ₂ axis direction) of the semiconductor structure 120 , and the first inclination angle θ ₁ may be 70° to 90°. The second inclination angle θ ₂ is a side inclination angle in the 2-1 direction (Y ₁ axis direction) of the active layer 122 and the second conductivity-type semiconductor layer 123 , and may be 20° to 50°.

In addition, the active layer 122 and the second conductivity-type semiconductor layer 123 may have first inclined surfaces on side surfaces in the 2-1 direction (Y ₁ axis direction). Similarly, the active layer 122 and the second conductivity-type semiconductor layer 123 may have second inclined surfaces on side surfaces in the 2-2 direction (Y- ₂ axis direction). And since the first inclination angle θ ₁ is greater than the second inclination angle θ ₂ , the first inclined surface may have a smaller inclination angle than the second inclined surface.

In addition, the first edge (P ₁ ) and the fifth edge (P ₅ ) may form a first gap ( G1 ). Similarly, the second edge P ₂ and the sixth edge P ₆ may form a second gap G2. In addition, the third edge P ₃ and the seventh edge P ₇ may form a third gap G3 . And the fourth edge (P ₄ ) and the eighth edge (P ₈ ) may form a fourth gap ( G4 ).

The first gap G1 to the fourth gap G4 may have a length of 1 μm to 3 μm. When the length of the first gap G1 to the fourth gap G4 is less than 1 μm, the second conductivity type semiconductor layer 123 and the second electrode 132 are adjacent to each other during isolation or mesa etching, resulting in low current failure. There is a problem with this occurring. The effect on the relationship between the low current failure and the semiconductor device 10 will be described in detail below with reference to FIG. 7 .

Also, the area of the second electrode 132 may vary according to the length of the first gap G1 to the fourth gap G4 . That is, the area S ₂ of the second electrode 132 may be changed. Due to this configuration, the area ratio between the area S ₁ of the second conductivity type semiconductor layer 123 and the area S ₂ of the second electrode 132 may be 1:0.39 to 1:0.86. .

When the area ratio between the area S ₁ of the second conductivity type semiconductor layer 123 and the area S ₂ of the second electrode 132 is greater than 1:0.86, there is a problem in that the occurrence of low-current defects increases. .

Specifically, the fifth edge (P ₅ ) to the eighth edge (P ₈ ) of the second electrode 132 and the first edge (P ₁ ) to the fourth edge (P ₄ ) of the second conductivity-type semiconductor layer 123 . ) may form a predetermined separation interval between them. For example, during isolation, the fifth edge P ₅ to the eighth edge P ₈ of the second electrode 132 and the first edge P ₁ to the fourth edge P of the second conductivity-type semiconductor layer 123 . ₄ ) If the distance between them is small, the second electrode 132 may be etched like the second conductivity-type semiconductor layer 123 . In addition, re-deposition occurs on the etched second electrode 132 , so that the etched second electrode 132 may generate a low current defect in the semiconductor device. For example, the etched second electrode 132 may be disposed to connect between the first conductivity-type semiconductor layer 121 and the second conductivity-type semiconductor layer 123 to cause an electrical short. These limitations are described in FIG. 7 .

When the area ratio between the area S ₁ of the second conductivity-type semiconductor layer 123 and the area S ₂ of the second electrode 132 is less than 1:0.39, the area S ₂ of the second electrode 132 ) decreases and there is a limit in which the amount of light decreases when a predetermined current is injected.

And according to an area ratio between the area S ₁ of the second conductivity-type semiconductor layer 123 and the area S ₂ of the second electrode 132 , the outer surface of the active layer 122 in the 1-1 direction An area ratio between the area of and the area of the outer surface of the second electrode 132 in the 1-2 direction may be 1:0.4 to 1:0.67.

The first interval G1 to the fourth interval G4 may have the same length. However, the present invention is not limited thereto, and the first gap G1 to the fourth gap G4 has an area S ₁ of the second conductivity-type semiconductor layer 123 and an area S ₂ of the second electrode 132 . The length may be changed differently within the range having the area ratio. For example, some of the first to fourth intervals G1 to G4 may have the same length, and other portions may have different lengths.

Referring to FIG. 3 , as described above, the length L ₁ of the semiconductor device 10 in the second direction (Y-axis direction) may be 30 μm to 50 μm. In addition, the semiconductor device 10 may have a width W ₁ of 10 μm to 30 μm in the third direction (Z-axis direction). The length L ₁ in the second direction (Y-axis direction) and the width W ₁ in the third direction (Z-axis direction) of the semiconductor device 10 are the second direction of the first conductivity-type semiconductor layer 121 . It may be the same as the maximum length in the (Y-axis direction) and the maximum width in the third direction (the Z-axis direction). And the semiconductor device 10 according to the embodiment is the size of the semiconductor device 10 through the product of the length (L ₁ ) in the second direction (Y-axis direction) and the width (W ₁ ) in the third direction (Z-axis direction) can be calculated.

The active layer 122 may have a length L ₄ of 20 μm to 26 μm in the second direction (Y-axis direction). In addition, the active layer 122 may have a width W ₄ of 17 μm to 25 μm in the third direction (Z-axis direction). The area S ₃ of the active layer 122 may be the area of the outermost surface of the active layer 122 in the 1-1 direction (X ₁ axis direction).

The area of the outer surface of the first conductivity-type semiconductor layer 121 in the aforementioned 1-2 direction (X ₂ axis direction) and the outer surface of the active layer 122 in the 1-1 direction (X ₁ axis direction) The area ratio between the areas may be from 1:0.5 to 1:0.85. With this configuration, the external quantum efficiency (EQE) of the semiconductor device 10 according to the embodiment may be improved.

Between the area of the outer surface of the first conductivity-type semiconductor layer 121 in the 1-2 direction (X ₂ axis direction) and the area of the outer surface of the active layer 122 in the 1-1 direction (X ₁ axis direction) When the area ratio is smaller than 1:0.5, the area of the active layer 122 is small compared to the size of the semiconductor device 10 (the maximum area of the first conductivity-type semiconductor layer 121 ), so there is a limit in that the luminous flux is lowered. In addition, the active layer 122 is 0 A/cm ² Exceeded 2.5 A/cm ² When the current density is less than or equal to the current density, the semiconductor device 10 has a problem in that the external quantum efficiency is reduced. This will be described with reference to FIG. 8 .

The area of the outer surface of the first conductivity-type semiconductor layer 121 in the 1-2 direction (X ₂ axis direction) and the area of the outer surface of the active layer 122 in the 1-1 direction (X ₁ axis direction) ( When the area ratio between the area of the active layer 122 and the area S ₃ is greater than 1:0.85, the area of the active layer 122 becomes larger and smaller than the area required for electrical connection of the first electrode 131, making it difficult to inject current. Limitations exist.

The area of the outer surface of the first conductivity-type semiconductor layer 121 in the above-described 1-2 direction (X ₂ axis direction) and the area of the outer surface of the active layer 122 in the 1-1 direction (X ₁ axis direction) The area S ₄ of the first electrode 131 may be adjusted according to an area ratio therebetween.

The first electrode 131 may have a length L ₅ of 1 μm to 24.5 μm in the second direction (Y-axis direction). In addition, the width W ₅ of the first electrode 131 in the third direction (Z-axis direction) may be 15 μm to 23 μm. The first electrode 131 of the semiconductor device 10 according to the embodiment is a plane through the product of the length L ₅ in the second direction (Y-axis direction) and the width W ₅ in the third direction (Z-axis direction). The area S ₄ of the upper first electrode 131 may be calculated. The area S ₄ of the first electrode 131 may be the area of the outermost surface of the second electrode 132 in the 1-2 direction (X ₂ axis direction).

In addition, the outermost corner in the 3-1 direction (Z ₁ axis direction) of the first conductivity type semiconductor layer 121 and the outermost corner in the 3-1 direction (Z ₁ axis direction) of the first electrode 131 The interval (W ₆ ) therebetween may be 2.5 μm to 7.5 μm. And between the outermost edge in the 3-2 direction (Z ₂ axis direction) of the first conductivity type semiconductor layer 121 and the outermost edge in the 3-2 direction (Z ₂ axis direction) of the first electrode 131 The spacing of (W- ₇ ) may be 2.5 μm to 7.5 μm. However, it is not limited to this interval.

Between the outermost corner in the 3-1 direction (Z ₁ axis direction) of the first conductivity-type semiconductor layer 121 and the outermost corner in the 3-1 direction (Z ₁ axis direction) of the first electrode 131 The gap W- ₆ is the outermost edge in the 3-2 direction (Z ₂ axis direction) of the first conductivity type semiconductor layer 121 and the 3-2 direction (Z ₂ axis direction) of the first electrode 131 . ) and may have the same length as the interval (W- ₇ ) between the outermost corners. However, the present invention is not limited thereto, and the outermost edge of the first conductivity type semiconductor layer 121 in the 3-1 direction (Z ₁ axis direction) and the first electrode 131 in the 3-1 direction (Z ₁ axis direction) direction) between the outermost corners (W- ₆ ) is the third of the outermost corner and the first electrode 131 in the 3-2 direction (Z ₂ axis direction) of the first conductivity-type semiconductor layer 121 It may be different from the distance W- ₇ between the outermost corners in the -2 direction (Z ₂ axis direction), and the area S ₄ of the first electrode 131 and the area S ₃ of the active layer 122 ) can be variously changed depending on the ratio of the area between them.

4 is a diagram illustrating wavelengths according to current of a semiconductor device according to an embodiment, FIG. 5 is a diagram illustrating grayscale changes according to injection current of a semiconductor device, and FIG. 6 is a diagram illustrating wavelengths according to injection current of a semiconductor device FIG. 7 is a diagram illustrating a low current failure of a semiconductor device, and FIG. 8 is a diagram illustrating external quantum efficiency (EQE) according to the size of the semiconductor device.

First, referring to FIG. 4 , as shown in Table 1 below, it is a graph measuring the wavelength of light generated in the semiconductor device according to the embodiment according to the current injected into the semiconductor device.

Semiconductor device injection current (㎂) 0.05 0.10 0.50 1.00 2.00 4.00 6.00 8.00 10.00 20.00 gradation One 17 45 64 89 123 149 170 188 255 Wavelength (nm) 514 518 520 520 520 520 520 520 520 520

Referring to Table 1, it can be seen that the semiconductor device generates light of different wavelengths according to an injection current injected into the semiconductor device. In the semiconductor device according to the embodiment, a current of 0.1 μA or more may be injected. In this case, the current density of the semiconductor device according to the embodiment may be 0.025A/cm ² or more. Due to this configuration, in the semiconductor device according to the embodiment, the central wavelength of the generated light may have an error range of about 2 nm or less.

However, the error range of the center wavelength may vary according to a color according to the center wavelength of light emitted from the semiconductor device. For example, in the case of blue light, the error range of the center wavelength of the generated light is less than 2 nm, and it is not easy for a person to recognize or distinguish a color change. In the case of green light, the error range of the center wavelength is 6 nm or less, and in the case of red light, the error range of the center wavelength is 4 nm or less, and it may not be easy for a person to recognize or distinguish a color change. Accordingly, the semiconductor device according to the embodiment may have high color reproducibility because a person does not perceive a color change.

In addition, Table 1 shows the semiconductor device according to the embodiment. When an injection current of 0.1 μA and a current density of 0.025 A/cm ² or more are present, the wavelength shift is minimized, so that detection of a color change may not occur. Here, the current density is a value measured in the area of the second electrode as mentioned above. And, as described above with reference to FIGS. 2 and 3 , when the area ratio between the area of the second conductivity type semiconductor layer and the area of the second electrode is established, the current density may be obtained at the injection current.

In addition, the semiconductor device according to the embodiment may be used in a display for controlling brightness by changing an injection current injected into the semiconductor device. Accordingly, only when the current density and the injection current are applied, the change in the central wavelength of light generated in the semiconductor device is reduced, so that the shift in the central wavelength can be improved.

Referring to FIG. 5 , as shown in Table 1, as the injection current injected into the semiconductor device increases, the gradation increases. (Table 1 shows the gradation of light generated in the semiconductor device according to each injection current based on 256 gradations) And as described above, the semiconductor device according to the embodiment controls brightness by changing the injection current injected into the semiconductor device. Since it is used in a display, 256 grayscales can be expressed as one grayscale level depending on the injected current. Accordingly, in the semiconductor device according to the embodiment, grayscale adjustment can be easily performed in stages. In addition, it indicates that the change in the central wavelength becomes larger as the gray level becomes smaller within the range of the injection current injected into the semiconductor device.

Also, as described in FIG. 4 , it can be seen that the C _x coordinate in the color coordinate increases along the T direction as the gray level increases (injection current increases) because the central wavelength is changed as described in FIG. 4 .

And referring to FIG. 6, as the injection current injected into the semiconductor device increases, the central wavelength of the generated light ranges from 514 nm to 520 nm, and the luminous intensity based on the luminous intensity of the central wavelength according to the wavelength has a similar shape. appear.

Referring to FIG. 7 , FIG. 7A shows a low current defect occurring in a plurality of semiconductor devices on a wafer when the area between the area S ₁ of the second conductivity type semiconductor layer and the area S ₂ of the second electrode is the same. It is a view showing the occurrence, and FIG. 7B is a view showing the occurrence of a low current defect in the semiconductor device according to the embodiment.

Referring to FIG. 7A , when the area ratio between the area of the second conductivity type semiconductor layer and the area of the second electrode is 1:1, the occurrence of low current failure increases, and the yield of a plurality of semiconductor devices on the wafer may be reduced. . In FIGS. 7A and 7B , K indicates a portion in which a low current defect occurs in a plurality of semiconductor devices on a wafer. This low current defect is caused by the distance between the active layer and the second electrode as the second electrode and the second conductivity type semiconductor layer are placed in contact with each other in the process (isolation) of separating a plurality of semiconductor devices on the wafer during the manufacturing process of the semiconductor device. may occur adjacent to Also, as described in FIG. 2 , a low current failure may occur depending on the length of the first interval to the fourth interval.

Referring to FIG. 7B , in the case of the semiconductor device according to the embodiment, it is shown that the low current failure rate is improved.

Referring to FIG. 8 , external quantum efficiency (EQE) with respect to current density is shown according to a change in the size of a semiconductor device. Specifically, the chip size was changed from 55% to 6821% at a relative rate to measure the external quantum efficiency with respect to the current density. As described above, the semiconductor device according to the embodiment may have a size of several micrometers to several hundreds of micrometers, and the current density of the semiconductor device may be 3.0A/cm ² or less in order to perform an operation of the semiconductor device. And it indicates that the external quantum efficiency decreases as the size of the semiconductor device becomes smaller within the current density. This may be because the non-luminous recombination rate within the current density decreases due to the size reduction of the semiconductor device. However, the current density may not be limited according to the size of the semiconductor device.

9A to 9F are flowcharts illustrating a method of manufacturing a semiconductor device according to an embodiment.

Referring to FIG. 9A , the semiconductor structure 120 may be grown on the growth substrate 1 .

The growth substrate 1 may be formed of a material selected from among sapphire (Al ₂ O ₃ ), GaAs, SiC, GaN, ZnO, Si, GaP, InP, and Ge, but is not particularly limited as long as it transmits visible light.

A first conductivity-type semiconductor layer 121 may be disposed on the growth substrate 1 . The first conductivity type semiconductor layer 121 may be implemented with a group III-V group or group II-VI compound semiconductor, and the first conductivity type semiconductor layer 121 may be doped with a first dopant. The first conductivity type semiconductor layer 121 may be formed of a semiconductor material having a composition formula of Inx1Aly1Ga1-x1-y1N (0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1).

An active layer 122 may be formed on the first conductivity-type semiconductor layer 121 . The active layer 122 may have any one of a single well structure, a multi-well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the active layer 122 . The structure of is not limited thereto. The active layer 122 may include Al.

A second conductivity type semiconductor layer 123 may be formed on the active layer 122 . The second conductivity-type semiconductor layer 123 may be implemented with a group III-V or group II-VI compound semiconductor, and the second conductivity-type semiconductor layer 123 may be doped with a second dopant. The second conductivity type semiconductor layer 123 is a semiconductor material having a composition formula of Inx5Aly2Ga1-x5-y2N (0≤x5≤1, 0≤y2≤1, 0≤x5+y2≤1) or AlInN, AlGaAs, GaP, GaAs , GaAsP, may be formed of a material selected from AlGaInP.

Referring to FIG. 9B , the semiconductor structure 120 may be mesa-etched. The mesa etching may be performed up to a portion of the first conductivity type semiconductor layer 121 . The angle of the mesa etching may be 20° to 50°. Here, the second inclination angle θ ₂ described with reference to FIG. 1 may be an angle formed by the mesa etching angle.

By the mesa etching, the second inclination angle of the interface between the first conductivity-type semiconductor layer 121 and the active layer 122 may be formed in a range of 20° to 50°.

Referring to FIG. 9C , the second electrode 132 may be formed on the second conductivity-type semiconductor layer 123 . The second electrode 132 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), and indium gallium tin (IGTO). oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, It may be formed including at least one of RuOx, NiO, RuOx/ITO, and Ni/IrOx/Au, but is not limited thereto.

The second electrode 132 may be formed by forming an electrode layer on the second conductivity type semiconductor layer 123 and etching the electrode layer using a mask (not shown). The second electrode may be formed to be spaced apart from the edge of the second conductivity-type semiconductor layer by a predetermined distance.

Referring to FIG. 9D , the first electrode 131 may be formed on the etched first conductivity-type semiconductor layer 121 . Like the second electrode 132 , the first electrode 131 may be formed by etching the electrode layer formed on the etched first conductivity-type semiconductor layer 121 using a mask (not shown). The first electrode 131 and the second electrode 132 may be formed to be electrically separated through etching. In addition, the first electrode 131 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), and indium (IGTO). gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, It may be formed including at least one of IrOx, RuOx, NiO, RuOx/ITO, and Ni/IrOx/Au, but the material is not limited thereto.

In addition, the first electrode 131 and the second electrode 132 may be formed to have the aforementioned area ratio. The order is not limited thereto, and the second electrode 132 may be formed on the second conductivity-type semiconductor layer 123 and mesa etching may be performed after etching.

Referring to FIG. 9E , the semiconductor device may be separated into one semiconductor device on the substrate through etching. That is, each of the plurality of semiconductor devices may be isolated through etching. This may be the aforementioned isolation process. Specifically, a plurality of semiconductor devices may be formed on the growth substrate 1 and structurally separated through the etching. That is, a separation space may be formed between adjacent semiconductor devices. Accordingly, as described below with reference to FIGS. 10A to 10E , the plurality of semiconductor devices formed on the growth substrate 1 may be respectively transferred to the transfer substrate by laser lift off (LLO) or the like. This will be described in detail below with reference to FIGS. 10A to 10E .

In addition, the etching may be performed by disposing a mask layer (not shown) on the semiconductor structure 120 , the first electrode 131 , and the second electrode 132 . Here, the mask layer (mask layer) may include an organic material, the organic material is SiO _-2 , Oxide may be included. However, it is not limited to these materials.

In addition, a resist layer including photoresist or the like may be formed on the mask layer (not shown). Here, the resist layer may be disposed on the mask layer in the size of a semiconductor device to be manufactured. For example, the resist layer may be formed from the first electrode 131 to the second electrode 132 . In addition, the mask layer (not shown) other than the region where the resist layer is formed may be etched. In this case, the inclination of the outer surface of the semiconductor device may be adjusted by the etching angle. In addition, the first inclination angle θ ₁ described above may be an angle formed by the etching angle. The first inclination angle θ ₁ may be 70° to 90°. When the first inclination angle θ ₁ is less than 70°, the area of the second electrode 132 may be reduced and the operating voltage may increase. In addition, when the semiconductor structure 120 is separated from the growth substrate 1 by laser lift off (LLO) when the first inclination angle θ ₁ is less than 70°, cracks in the semiconductor structure 120 This may cause a problem in the reliability of the semiconductor device. For example, as the first inclination angle θ ₁ decreases, the thickness of the edge of the first conductivity-type semiconductor layer 121 under the semiconductor structure 120 may gradually decrease. As a result, there is a problem in that the semiconductor structure 120 is separated from the growth substrate 1 and cracks are generated at the edge of the first conductivity-type semiconductor layer 121 .

Also, the first inclination angle θ ₁ may be greater than the second inclination angle θ ₂ . In addition, the etching may be performed up to the lower portion of the semiconductor structure 120 . Accordingly, in the semiconductor structure 120 , the first conductivity-type semiconductor layer 121 , the active layer 122 , and the second conductivity-type semiconductor layer 123 may have the same etching plane and inclination angle by the above etching.

And additional etching (E) may be made. As described above with reference to FIG. 1 by patterning and etching the second electrode 132 , a predetermined spacing may be formed between the edge of the second electrode 132 and the edge of the second conductivity-type semiconductor layer 123 . . For this reason, as described above, the second electrode 132 may be etched during isolation. In addition, since re-deposition occurs during the isolation process, the etched second electrode 132 may cause a low current defect in the semiconductor device. For example, the etched second electrode 132 may be disposed to connect between the first conductivity-type semiconductor layer 121 and the second conductivity-type semiconductor layer 123 to cause an electrical short.

10A to 10E are flowcharts illustrating a process of transferring a semiconductor device to a display device according to an exemplary embodiment.

10A to 10E , in the method of manufacturing a display device according to an embodiment, a semiconductor device including a plurality of semiconductor devices disposed on a growth substrate 1 is selectively irradiated with a laser to separate the semiconductor device from the substrate. and disposing the separated semiconductor device on the panel substrate. Here, the semiconductor device includes a first conductivity type semiconductor layer, an active layer disposed on the first conductivity type semiconductor layer, a second conductivity type semiconductor layer disposed on the active layer, a first electrode disposed on the first conductivity type semiconductor layer, and a first It may include a second electrode disposed on the second conductivity type semiconductor layer and an insulating layer covering the semiconductor structure.

First, referring to FIG. 10A , the growth substrate may be the same as the growth substrate 1 described with reference to FIGS. 9A to 9F . In addition, a plurality of semiconductor devices may be disposed on the growth substrate. For example, the plurality of semiconductor devices may include a first semiconductor device 10-1, a second semiconductor device 10-2, a third semiconductor device 10-3, and a fourth semiconductor device 10-4. there is. However, the number is not limited thereto, and the semiconductor device may have various numbers.

Referring to FIG. 10B , at least one semiconductor device selected from among the plurality of semiconductor devices 10 - 1 , 10 - 2 , 10 - 3 and 10 - 4 may be separated into a growth substrate using the transfer mechanism 210 . . The transport mechanism 210 may include a first bonding layer 211 and a transport frame 212 disposed thereunder. Exemplarily, the transport frame 212 has a concave-convex structure, so that the semiconductor device and the first bonding layer 211 can be easily bonded. However, it is not limited to this shape.

Referring to FIG. 10C , the selected semiconductor device may be separated from the growth substrate 1 by irradiating a laser to the lower portion of the selected semiconductor device. At this time, the transport mechanism 210 moves upward, and the semiconductor element may also move along with the movement of the transport mechanism 210 . For example, the growth substrate 10 and the first semiconductor device 10- are irradiated with a laser to the lower region of the growth substrate 10 in which the first semiconductor device 10-1 and the third semiconductor device 10-3 are disposed. 1) and the third semiconductor device 10 - 3 may be separated. The present invention is not limited thereto, and the transport mechanism 210 may be formed such that the bonding layer 211 is bonded to one semiconductor device to separate one semiconductor device at a time.

For example, as a method of separating the semiconductor device from the growth substrate 10 , laser lift-off (LLO) using a photon beam of a specific wavelength band may be applied. At this time, in order to prevent physical damage between the semiconductor devices by laser lift-off (LLO), a protective layer (not shown) may be disposed between the semiconductor device and the growth substrate 10 . can However, it is not limited to this configuration.

In addition, the semiconductor devices separated by the growth substrate 10 may have a predetermined spacing therebetween. As described above, the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from the growth substrate, and the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated. The second semiconductor device 10 - 2 and the fourth semiconductor device 10 - 4 having the same separation distance as the separation distance of can be separated in the same manner. Accordingly, semiconductor devices having the same separation distance may be transferred to the display panel.

Referring to FIG. 10D , a selected semiconductor device may be disposed on a panel substrate. For example, the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 may be disposed on the panel substrate 300 . Specifically, the second bonding layer 310 may be disposed on the panel substrate 300 , and the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 are formed by the second bonding layer 310 . may be placed on the Accordingly, the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 may be in contact with the second bonding layer. Through this method, the efficiency of the transfer process may be improved by arranging semiconductor devices having spaced apart intervals on the panel substrate.

In addition, a laser may be irradiated to separate the first bonding layer 211 from the selected semiconductor device. For example, a laser may be irradiated onto the transfer mechanism 210 to physically separate the first bonding layer 211 from the selected semiconductor device.

Referring to FIG. 10C , if the transport mechanism 210 is moved upward after laser irradiation, the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 may be separated from the transport mechanism 210 . there is. In addition, coupling between the second bonding layer 310 and the first semiconductor device 10 - 1 and the third semiconductor device 10 - 3 may be formed.

11 is a conceptual diagram of a display device to which a semiconductor element is transferred according to an embodiment.

Referring to FIG. 11 , in an embodiment, a display device including a semiconductor device includes a second panel substrate 410 , a driving thin film transistor T2 , a planarization layer 430 , a common electrode CE, a pixel electrode AE, and It may include a semiconductor device.

The driving thin film transistor T2 includes a gate electrode GE, a semiconductor layer SCL, an ohmic contact layer OCL, a source electrode SE, and a drain electrode DE.

The driving thin film transistor is a driving device and may be electrically connected to the semiconductor device to drive the semiconductor device.

The gate electrode GE may be formed together with the gate line. The gate electrode GE may be covered with a gate insulating layer 440 .

The gate insulating layer 440 may be formed of a single layer or a plurality of layers made of an inorganic material, and may be made of silicon oxide (SiOx), silicon nitride (SiNx), or the like.

The semiconductor layer SCL may be disposed in the form of a preset pattern (or island) on the gate insulating layer 440 to overlap the gate electrode GE. The semiconductor layer SCL may be made of a semiconductor material made of any one of amorphous silicon, polycrystalline silicon, oxide, and an organic material, but is not limited thereto.

The ohmic contact layer OCL may be disposed in a preset pattern (or island) shape on the semiconductor layer SCL. The ohmic contact layer PCL may be for ohmic contact between the semiconductor layer SCL and the source/drain electrodes SE and DE.

The source electrode SE is formed on the other side of the ohmic contact layer OCL to overlap one side of the semiconductor layer SCL.

The drain electrode DE may be formed on the other side of the ohmic contact layer OCL to be spaced apart from the source electrode SE while overlapping the other side of the semiconductor layer SCL. The drain electrode DE may be formed together with the source electrode SE.

The planarization layer may be disposed over the entire surface of the second panel substrate 410 . A driving thin film transistor T2 may be disposed inside the planarization layer. The planarization layer according to an embodiment may include an organic material such as benzocyclobutene or photo acryl, but is not limited thereto.

The groove 450 is a predetermined light emitting area, and a semiconductor device may be disposed therein. Here, the light emitting area may be defined as an area other than the circuit area in the display device.

The groove 450 may be concavely formed in the planarization layer 430 , but is not limited thereto.

The semiconductor device may be disposed in the groove 450 . The first and second electrodes of the semiconductor device may be connected to a circuit (not shown) of the display device.

The semiconductor device may be adhered to the groove 450 through the adhesive layer 420 . Here, the adhesive layer 420 may be the second bonding layer, but is not limited thereto.

The second electrode 132 of the semiconductor device may be electrically connected to the source electrode SE of the driving thin film transistor T2 through the pixel electrode AE. In addition, the first electrode 131 of the semiconductor device may be connected to the common power line CL through the common electrode CE.

The first and second electrodes 131 and 132 may have a step difference from each other, and the electrode 131 located at a relatively lower position among the first and second electrodes 131 and 132 is identical to the top surface of the planarization layer 430 . It may be located on a horizontal line. However, the present invention is not limited thereto.

The pixel electrode AE may electrically connect the source electrode SE of the driving thin film transistor T2 and the second electrode of the semiconductor device.

The common electrode CE may electrically connect the common power line CL and the first electrode of the semiconductor device.

Each of the pixel electrode AE and the common electrode CE may include a transparent conductive material. The transparent conductive material may include a material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

A display device according to an embodiment of the present invention includes a standard definition (SD) level resolution (760×480), a high definition (HD) level resolution (1180×720), a full HD (Full HD) level resolution (1920×1080), and UH (Ultra HD) level resolution (3480×2160), or UHD level or higher resolution (eg, 4K (K=1000), 8K, etc.) may be implemented. In this case, a plurality of semiconductor devices according to the embodiment may be arranged and connected to suit the resolution.

In addition, the display device may be an electric billboard or TV having a diagonal size of 100 inches or more, and the pixel may be implemented as a light emitting diode (LED). Accordingly, power consumption is reduced, and a long lifespan can be provided with a low maintenance cost, and a high-brightness self-luminous display can be provided.

Since the embodiment implements an image and an image using a semiconductor device, color purity and color reproduction are excellent.

In the embodiment, since images and images are implemented using a light emitting device package having excellent straightness, a large display device of 100 inches or more can be implemented with clarity.

The embodiment may implement a high-resolution, 100-inch or larger large display device at a low cost.

The semiconductor device according to the embodiment may further include an optical member such as a light guide plate, a prism sheet, and a diffusion sheet to function as a backlight unit. In addition, the semiconductor device of the embodiment may be further applied to a display device, a lighting device, and a pointing device.

In this case, the display device may include a bottom cover, a reflector, a light emitting module, a light guide plate, an optical sheet, a display panel, an image signal output circuit, and a color filter. The bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit.

The reflector is disposed on the bottom cover, and the light emitting module emits light. The light guide plate is disposed in front of the reflection plate to guide light emitted from the light emitting module to the front, and the optical sheet includes a prism sheet and the like, and is disposed in front of the light guide plate. A display panel is disposed in front of the optical sheet, an image signal output circuit supplies an image signal to the display panel, and a color filter is disposed in front of the display panel.

In addition, the lighting device may include a light source module including a substrate and the semiconductor device of the embodiment, a heat dissipation unit for dissipating heat of the light source module, and a power supply unit for processing or converting an electrical signal received from the outside and providing it to the light source module. . Furthermore, the lighting device may include a lamp, a head lamp, or a street lamp.

In addition, the camera flash of the mobile terminal may include a light source module including the semiconductor device of the embodiment.

12 is a modification of FIG. 1 .

Referring to FIG. 12 , the semiconductor device 10 ′ according to the modified example may be applied in the same manner as in the configuration of the semiconductor device described with reference to FIG. 1 .

However, the insulating layer may be exposed without being disposed in the 2-1 direction (the Y ₁ axis direction) in the first electrode 131 . And the area (O ₂ ) of the exposed top surface of the first electrode 131 may be the same as the area (O ₁ ) of the exposed top surface of the first electrode in FIG. 1 . In addition, the insulating layer 141 is longer than the semiconductor device of FIG. 1 from the edge of the 2-2 direction (Y ₂ axis direction) in the 2-1 direction (Y ₁ axis direction) on the upper surface of the first electrode 131 . It may be formed to extend.

13 is a cross-sectional view of a semiconductor device according to another exemplary embodiment.

Referring to FIG. 13 , a semiconductor device 200 according to another exemplary embodiment may be, for example, a semiconductor device generating red light. Accordingly, the structure of each layer described below may be different from that of FIG. 1 , but the X-axis direction and the Y-axis direction with respect to the thickness are equally applied. In addition, the ratio of the area of the outer surface in the 1-1 direction (X ₁ axis direction) of the second conductivity type semiconductor layer described above to the area of the outer surface in the 1-2 direction (X ₂ axis direction) of the second electrode is the same can be applied

The semiconductor device 200 includes a sacrificial layer 220 , a bonding layer 230 disposed on the sacrificial layer 220 , a first conductivity type semiconductor layer 241 , a 2-2 conductivity type semiconductor layer 244b , and a second conductivity type semiconductor layer 244b . The semiconductor structure 240 including the active layer 243 disposed between the first conductivity type semiconductor layer 241 and the second conductivity type semiconductor layer 244b and disposed on the bonding layer 230, the first conductivity type It may include a first electrode 251 connected to the semiconductor layer 241 and a second electrode 252 connected to the 2-2 conductivity-type semiconductor layer 244b.

The sacrificial layer 220 may be disposed on a substrate (not shown). The sacrificial layer 220 may be removed while transferring the semiconductor device to the display device. For example, when the semiconductor device is transferred to the display device, the sacrificial layer 220 may be separated by a laser irradiated during transfer. In this case, the sacrificial layer 220 may be formed to be separated from the wavelength of the irradiated laser. Also, the wavelength of the laser may be 532 nm or 1064 nm.

The sacrificial layer 220 may include oxide or nitride. However, the present invention is not limited thereto. When the sacrificial layer 220 is an SOG thin film (Spin on Glass), it may be of a silicate or silicic acid type. When the sacrificial layer 220 is a Spin On Dielectrics (SOD) thin film, it may include silicate, siloxane, methyl silsequioxane (MSQ), hydrogen silsequioxane (HSQ), MQS + HSQ, perhydrosilazane (TCPS), or polysilazane, ITO, or Ti. there is. However, the present invention is not limited thereto.

The sacrificial layer 220 may be formed by E-beam evaporator, thermal evaporator, MOCVD (Metal Organic Chemical Vapor Deposition), sputtering, and PLD (Pulsed Laser Deposition) methods. , but is not limited thereto.

The bonding layer 230 may be disposed on the sacrificial layer 220 . However, the present invention is not limited thereto, and may be disposed under the sacrificial layer 220 . The bonding layer 230 may include any one of Si, C, O, N, and H, for example, the bonding layer 230 may include a resin, SiO ₂ .

As described above, the sacrificial layer 220 and the bonding layer 230 are layers for transfer, and laser lift-off (LLO) is performed by irradiating a high-wavelength laser to transfer the semiconductor device to the display panel. may be removed in some cases.

The thickness d7 of the bonding layer 230 may be 1.8 μm to 2.2 μm. However, the present invention is not limited thereto. Here, the thickness may be a length in the Y-axis direction.

The semiconductor structure 240 may be disposed on the bonding layer 230 .

The semiconductor structure 240 includes a first conductivity type semiconductor layer 241 , a 2-2 conductivity type semiconductor layer 244b , and between the first conductivity type semiconductor layer 241 and the 2-2 conductivity type semiconductor layer 244b . It may include an active layer 243 disposed on the.

The first conductivity-type semiconductor layer 241 may be disposed on the bonding layer 230 . The thickness d8 of the first conductivity type semiconductor layer 241 may be 1.8 μm to 2.2 μm. However, the present invention is not limited thereto.

The first conductivity-type semiconductor layer 241 may be implemented with a group III-V or group II-VI compound semiconductor, and may be doped with a first dopant. The first conductivity type first semiconductor layer 112 is InxAlyGa1-x-yP (0≤x≤1, 0≤y≤1, 0≤x+y≤1) or InxAlyGa1-x-yN (0≤x≤1) , 0≤y≤1, 0≤x+y≤1) may include a semiconductor material having a composition formula.

In addition, the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te. When the first dopant is an n-type dopant, the first conductivity-type semiconductor layer 241 doped with the first dopant may be an n-type semiconductor layer.

The first conductivity type semiconductor layer 241 may include at least one of AlGaP, InGaP, AlInGaP, InP, GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, and GaP.

The first conductivity type semiconductor layer 241 may be formed using a method such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering or hydroxide vapor phase epitaxy (HVPE), but is not limited thereto. .

A first electrode 251 may be disposed on the first conductivity type semiconductor layer 241 . The first conductivity-type semiconductor layer 241 may be electrically connected to the first electrode 251 .

The first electrode 251 may be disposed on a portion of the upper surface of the first conductivity-type semiconductor layer 241 . The first electrode 251 may be disposed below the second electrode 252 .

The first electrode 251 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), and indium gallium tin (IGTO). oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, It may be formed including one, but is not limited to these materials.

For the first electrode 251 , all commonly used electrode forming methods such as stuffing, coating, and deposition may be applied.

The first clad layer 242 may be disposed on the first conductivity-type semiconductor layer 241 . The first clad layer 242 may be disposed between the first conductivity-type semiconductor layer 241 and the active layer 243 . The first clad layer 242 may include a plurality of layers. The first clad layer 242 may include an AlInP-based layer/AlInGaP-based layer.

A thickness d9 of the first cladding layer 242 may be 0.45 μm to 0.55 μm. However, the present invention is not limited thereto.

The active layer 243 may be disposed on the first clad layer 242 . The active layer 243 may be disposed between the first conductivity type semiconductor layer 241 and the second conductivity type semiconductor layer 244b. The active layer 243 is a layer in which electrons (or holes) injected through the first conductivity type semiconductor layer 241 and holes (or electrons) injected through the 2-1 conductivity type semiconductor layer 244a meet. The active layer 243 may transition to a low energy level as electrons and holes recombine, and may generate light having an ultraviolet wavelength.

The active layer 243 may have any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the active layer 243 ) structure is not limited thereto.

The active layer 243 may be formed of any one or more pair structures of GaInP/AlGaInP, GaP/AlGaP, InGaP/AlGaP, InGaN/GaN, InGaN/InGaN, GaN/AlGaN, InAlGaN/GaN, GaAs/AlGaAs, InGaAs/AlGaAs. However, the present invention is not limited thereto.

The thickness d10 of the active layer 243 may be 0.54 μm to 0.66 μm. However, the present invention is not limited thereto.

As electrons are cooled in the first cladding layer 242 , the active layer 243 may generate more radiation recombination.

The second conductivity type semiconductor layer 244 may be disposed on the active layer 243 . The second conductivity type semiconductor layer 244 may include a 2-1 conductivity type semiconductor layer 244a and a 2-2 conductivity type semiconductor layer 244b.

The 2-1-th conductivity type semiconductor layer 244a may be disposed on the active layer 243 . The 2-2 conductivity type semiconductor layer 244b may be disposed on the 2-1 conductivity type semiconductor layer 244a.

The 2-1-th conductivity type semiconductor layer 244a may include TSBR and P-AllnP. The thickness d11 of the 2-1 conductivity-type semiconductor layer 244a may be 0.57 μm to 0.70 μm. However, the present invention is not limited thereto.

The 2-1-th conductivity type semiconductor layer 244a may be implemented with a compound semiconductor of group III-V, group II-VI, or the like. A second dopant may be doped into the 2-1-th conductivity type semiconductor layer 244a.

The 2-1-th conductivity type semiconductor layer 244a is InxAlyGa1-x-yP (0≤x≤1, 0≤y≤1, 0≤x+y≤1) or InxAlyGa1-x-yN (0≤x≤1) , 0≤y≤1, 0≤x+y≤1) may include a semiconductor material having a composition formula. When the second conductivity-type semiconductor layer 244 is a p-type semiconductor layer, Mg, Zn, Ca, Sr, Ba, or the like may be included as a p-type dopant.

The 2-1-th conductivity-type semiconductor layer 244a is doped with a second dopant, and the 2-1-th conductivity-type semiconductor layer 244a may be a p-type semiconductor layer.

The 2-2 conductivity type semiconductor layer 244b may be disposed on the 2-1 conductivity type semiconductor layer 244a. The 2-2 conductivity type semiconductor layer 244b may include a p-type GaP-based layer.

The 2-2 conductivity type semiconductor layer 244b may include a superlattice structure of a GaP layer/InxGa1-xP layer (where 0≤x≤1).

For example, the 2-2 conductivity type semiconductor layer 244b may be doped with Mg having a concentration of about 10× ^10-18 , but is not limited thereto.

In addition, the 2-2 conductivity type semiconductor layer 244b may be formed of a plurality of layers and only some layers may be doped with Mg.

The thickness d12 of the second-second conductivity type semiconductor layer 244b may be 0.9 μm to 1.1 μm. However, the present invention is not limited thereto.

The second electrode 252 may be disposed on the 2-2 conductivity type semiconductor layer 244b. The second electrode 252 may be electrically connected to the 2-2 conductivity-type semiconductor layer 244b.

The second electrode 252 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), and indium gallium tin (IGTO). oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, It may be formed including one, but is not limited to these materials.

For the second electrode 252 , all of the commonly used electrode forming methods such as stuffing, coating, and deposition may be applied.

In the above, the embodiment has been mainly described, but this is only an example and does not limit the present invention, and those of ordinary skill in the art to which the present invention pertains are not exemplified above in the range that does not depart from the essential characteristics of the present embodiment. It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiment can be implemented by modification. And differences related to such modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims.

Claims (8)

a first conductivity type semiconductor layer;
an active layer disposed on the first conductivity-type semiconductor layer;
a second conductivity-type semiconductor layer disposed on the active layer;
a first electrode electrically connected to the first conductivity-type semiconductor layer; and
a second electrode electrically connected to the second conductivity-type semiconductor layer; and
The area ratio of the upper surface of the second conductivity type semiconductor layer and the lower surface of the second electrode is 1:0.39 to 1:0.86,
The edge of the lower surface of the second electrode is disposed 1㎛ to 3㎛ spaced apart from the edge of the upper surface of the second conductivity type semiconductor layer,
A ratio of an area of an upper surface of the first conductivity-type semiconductor layer to an area of a lower portion of the active layer is in a range of 1:0.5 to 1:0.85.
delete delete According to claim 1,
The ratio of the area of the upper surface of the active layer to the area of the lower surface of the second electrode is 1:0.4 to 1:0.67.
According to claim 1,
The area of the lower surface of the first conductivity type semiconductor layer is 800㎛ ² to 1200㎛ ² A semiconductor device.
According to claim 1,
Further comprising an insulating layer disposed on the first conductivity-type semiconductor layer, the active layer, and the second conductivity-type semiconductor layer,
The insulating layer is partially disposed on upper surfaces of the first electrode and the second electrode.
delete semiconductor devices; and
and a case for accommodating the semiconductor device,
The semiconductor device is
a first conductivity type semiconductor layer;
an active layer disposed on the first conductivity-type semiconductor layer;
a second conductivity-type semiconductor layer disposed on the active layer;
a first electrode electrically connected to the first conductivity-type semiconductor layer; and
a second electrode electrically connected to the second conductivity-type semiconductor layer; and
The area ratio of the upper surface of the second conductivity type semiconductor layer and the lower surface of the second electrode is 1:0.39 to 1:0.86,
The edge of the lower surface of the second electrode is disposed 1㎛ to 3㎛ spaced apart from the edge of the upper surface of the second conductivity-type semiconductor layer,
The ratio of the area of the upper surface of the first conductivity type semiconductor layer to the area of the lower surface of the active layer is in a range of 1:0.5 to 1:0.85.

Images