KR20190108893A - Semiconductor device package and lighting device including the same - Google Patents

Abstract

According to an embodiment of the present invention, disclosed are a semiconductor device package and a light source device including the same. The semiconductor device package comprises: a substrate; a plurality of semiconductor structures arranged in a central area of the substrate, and arranged to be spaced apart from each other in a first direction and a second direction perpendicular to the first direction; a plurality of first wiring electrodes electrically connected to the semiconductor structures, and arranged to be spaced apart from each other in the first direction; a plurality of second wiring electrodes electrically connected to the semiconductor structures, and arranged to be spaced apart from each other in the second direction; and a first insulating layer arranged between the first wiring electrodes and the second wiring electrodes, wherein the first wiring electrodes and the second wiring electrodes are extended from the central area to an edge area of the substrate, the semiconductor structures include a plurality of first semiconductor structures arranged in a first area of the central area and a plurality of second semiconductor structures arranged in a second area of the central area, and the size of the first semiconductor structures is different from the size of the second semiconductor structures.

Description

Semiconductor device package and light source device including same {SEMICONDUCTOR DEVICE PACKAGE AND LIGHTING DEVICE INCLUDING THE SAME}

Embodiments relate to a semiconductor device package and a light source device including the same.

A semiconductor device including a compound such as GaN, AlGaN, etc. has many advantages, such as having a wide and easy-to-adjust band gap energy, and can be used in various ways as a light emitting device, a light receiving device, and various diodes.

Particularly, light emitting devices such as light emitting diodes and laser diodes using semiconductors of Group 3-5 or Group 2-6 compound semiconductors have been developed through the development of thin film growth technology and device materials. Various colors such as blue and ultraviolet light can be realized, and efficient white light can be realized by using fluorescent materials or combining colors.Low power consumption, semi-permanent lifespan, and fast response speed compared to conventional light sources such as fluorescent and incandescent lamps can be realized. It has the advantages of safety, environmental friendliness.

In addition, when a light-receiving device such as a photodetector or a solar cell is also manufactured using a group 3-5 or 2-6 compound semiconductor material of a semiconductor, the development of device materials absorbs light in various wavelength ranges to generate a photocurrent. As a result, light in various wavelengths can be used from gamma rays to radio wavelengths. It also has the advantages of fast response speed, safety, environmental friendliness and easy control of device materials, making it easy to use in power control or microwave circuits or communication modules.

Therefore, the semiconductor device may replace a light emitting diode backlight, a fluorescent lamp, or an incandescent bulb, which replaces a cold cathode tube (CCFL) constituting a backlight module of an optical communication means, a backlight of a liquid crystal display (LCD) display device. Applications are expanding to include white LED lighting devices, automotive headlamps and traffic lights, and sensors to detect gas or fire. In addition, the semiconductor device may be extended to high frequency application circuits, other power control devices, and communication modules.

In the case of an automobile head lamp, a plurality of light emitting devices (chips) may be used as a package. In particular, in recent years, interest in a head lamp capable of independent lighting of a plurality of chips is increasing. Such smart headlamps can prevent glare of the opposite vehicle. Also, an image or text may be output on the road surface.

Smart headlamps do not require high resolution to ensure visibility and prevent glare, but require high resolution to print images or text on the road. Therefore, there is a problem in that the structure becomes complicated to simultaneously perform such a function.

The embodiment provides a semiconductor device package having different sizes of semiconductor structures and a light source device including the same.

The present invention also provides a light source device for independently time-division control of semiconductor structures having different sizes.

The problem to be solved in the examples is not limited thereto, and the object or effect that can be grasped from the solution means or the embodiment described below will also be included.

A semiconductor device package according to an aspect of the present invention, a substrate; A plurality of semiconductor structures disposed in a central region of the substrate and spaced apart from each other in a first direction and a second direction perpendicular to the first direction; A plurality of first wiring electrodes electrically connected to the semiconductor structure and spaced apart from each other in the first direction; A plurality of second wiring electrodes electrically connected to the semiconductor structure and spaced apart from each other in the second direction; And a first insulating layer disposed between the first wiring electrode and the second wiring electrode, wherein the first wiring electrode and the second wiring electrode extend from the center region to the edge region of the substrate. The plurality of semiconductor structures may include a plurality of first semiconductor structures disposed in a first region of the central region, and a plurality of second semiconductor structures disposed in a second region of the central region. The size of the structure is different from the size of the plurality of second semiconductor structures.

The area of the first region and the second region may be the same.

The number of the plurality of first semiconductor structures disposed in the first region may be greater than the number of the plurality of second semiconductor structures disposed in the second region.

The size of the plurality of first semiconductor structures disposed in the first region may be smaller than the size of the plurality of second semiconductor structures disposed in the second region.

The first direction width of the second semiconductor structure may be smaller than the first direction width of the first semiconductor structure.

The first region and the second region may be disposed in the second direction.

The second region may surround the first region.

The plurality of semiconductor structures include a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein the first wiring line And a first through portion electrically connected to the first conductive semiconductor layer through the active layer, the second conductive semiconductor layer and the first insulating layer, and a first end portion extending to an edge of the substrate. The second wiring line may include a second end portion extending to an edge region of the substrate.

A plurality of first pads electrically connected to the first wiring lines; And a plurality of second pads electrically connected to the second wiring lines, respectively, wherein the first pad includes a first area electrically connected to the first end portion through the first insulating layer; And a second region extending from the first region and protruding on an edge region of the substrate.

A light source device according to an aspect of the present invention includes a semiconductor device including a substrate, a plurality of first semiconductor structures disposed in a first region of the substrate, and a plurality of second semiconductor structures disposed in a second region of the substrate. package; And a controller configured to output driving signals to the plurality of first and second semiconductor structures, wherein the sizes of the plurality of first semiconductor structures are different from the sizes of the plurality of second semiconductor structures. Time-divisionally controlling the first semiconductor structure of the first region and the second semiconductor structure of the second region independently.

According to an embodiment, it is possible to simultaneously realize visibility, prevent glare, and display information on a single light source device.

In addition, since a plurality of functions are possible in one light source device, the manufacturing cost can be lowered.

Various and advantageous advantages and effects of the present invention are not limited to the above description, and will be more readily understood in the course of describing specific embodiments of the present invention.

1 is a conceptual diagram illustrating a light source device according to an embodiment of the present invention;
2 is a cross-sectional view of a semiconductor device package according to an embodiment;
3 is a plan view of a semiconductor device package according to an embodiment;
4 is a cross-sectional view of I in FIG. 3,
FIG. 5 is a view illustrating a first wiring line in FIG. 3.
FIG. 6 is a view illustrating a second wiring line in FIG. 3.
7 and 8 illustrate a passive matrix driving method according to an embodiment;
9 is a view for explaining the effect of the light source device according to the embodiment;
10 is a conceptual diagram illustrating a light source device according to another embodiment of the present invention;
11 is a first modification of the semiconductor structure,
12 is a second modification of the semiconductor structure,
13 is a view showing a field of view (FOV) of the headlamp,
14 is a third modification of the semiconductor structure,
15 is a fourth modification of the semiconductor structure,
FIG. 16 is a view illustrating a field of view (FOV) covered by the semiconductor structure of FIG. 15.
17 is a fourth modified example of the semiconductor structure;
18 is a view illustrating a lamp structure in which a light source device and an optical system are combined.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated and described in the drawings. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms including ordinal numbers, such as second and first, may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be referred to as the first component, and similarly, the first component may also be referred to as the second component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be given the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted.

The semiconductor device according to the present embodiment may be a light emitting device.

Such semiconductor devices emit light by recombination of electrons and holes, and the wavelength of the light may be determined by an energy band gap inherent in the material. And the light emitted may vary depending on the composition of the material.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

The semiconductor device according to the present embodiment may be a light emitting device.

Such semiconductor devices emit light by recombination of electrons and holes, and the wavelength of the light may be determined by an energy band gap inherent in the material. And the light emitted may vary depending on the composition of the material.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

1 is a conceptual diagram illustrating a light source device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a light source device 10 according to an embodiment may include a semiconductor device package 100 including a plurality of semiconductor structures 120, a plurality of data lines DL, a plurality of scan lines SL, The first driver 200, the second driver 300, and the controller 400 may be included.

The semiconductor device package 100 may include a plurality of semiconductor structures 120. Here, the plurality of semiconductor structures 120 may each be one pixel PX.

The plurality of data lines DL may be electrically connected to first wiring lines connected to the plurality of semiconductor structures 120. The plurality of data lines DL may be different from the semiconductor structure 120 depending on the driving method of the light source device 10.

For example, the light source device 10 may be driven by two-time division during passive matrix driving. In this case, the plurality of data lines DL may be electrically connected to first wiring lines connected to the two semiconductor structures 120, respectively. However, as described above, the plurality of data lines DL may have a different connection method from the first wiring line according to the number of time divisions. For example, in a passive matrix driven at four time divisions, one data line DL may be electrically connected to four semiconductor structures 120.

Hereinafter, each data line DL will be described as a structure connected to two semiconductor structures 120. In addition, the light source device 10 will also be described based on two-time division (when the number of time divisions are two). However, the exemplary embodiment is not limited thereto and may have various time division structures.

The plurality of data lines DL may apply a current to the semiconductor structure according to a signal provided from the first driver 200. A plurality of switches (not shown) are disposed on the plurality of data lines DL, and the first driving unit 200 supplies a control signal for switching (on / off) the plurality of switches (not shown). (Not shown). The control signal may be a PWM signal. However, it is not limited to this kind.

In addition, the plurality of switches (not shown) may include a transistor, for example, may be a FET. Accordingly, the first driver 200 may control the plurality of switches (not shown) by adjusting gate voltages applied to the plurality of switches (not shown). However, it is not limited to this kind.

The plurality of scan lines SL may be electrically connected to a second wiring line connected to the plurality of semiconductor structures 120. Similar to the data line DL described above, the plurality of scan lines SL may be different from the semiconductor structure 120 depending on the driving method of the light source device 10. For example, the light source device 10 may be driven by two-time division during passive matrix driving. In this case, the plurality of scan lines SL may be electrically connected to second wiring lines connected to the two semiconductor structures 120, respectively. However, as described above, the plurality of scan lines SL may have a different connection method from the second wiring line according to the number of time divisions.

The plurality of data lines DL are electrically connected to the first conductive semiconductor layer of the semiconductor structure 120 through the first wiring line, and the plurality of scan lines SL are connected to the second semiconductor structure through the second wiring line. It may be electrically connected to the second conductivity type semiconductor layer of 120. In this configuration, the plurality of data lines DL and the scan lines SL may inject current into the plurality of semiconductor structures 120, and the plurality of semiconductor structures 120 may operate.

That is, the light source device 10 according to the embodiment controls the PWM signals provided to the first data line DL and the second data line SL through the first driver 200 and the second driver 300. The semiconductor structures 120 may be selectively operated.

The controller 400 may provide a control signal to the first driver 200 and the second driver 300. The controller 400 may determine the number of time divisions for the image data input in one frame, and may provide a control signal corresponding to the determined time division number to the first driver 200 and the second driver 300. With this configuration, the light source device 10 according to the embodiment may change the number of time divisions according to the image data.

2 is a cross-sectional view of a semiconductor device package according to an embodiment.

Referring to FIG. 2, the semiconductor device package 100 according to the embodiment may include a substrate 170, a bonding layer 171, a semiconductor structure 120, a channel layer 130, a first electrode 141, and a second electrode. 142, reflective layer 143, first wiring line 151, second wiring line 152, first insulating layer 161, second insulating layer 162, passivation layer 163, and first pad 181 and a second pad 182. In addition, the semiconductor structure 120 may be disposed on the substrate 170.

FIG. 2 illustrates one semiconductor structure 120 disposed between the first pad 181 and the second pad 182 for convenience of description. However, as shown in FIG. 3, a plurality of semiconductor structures 120 and 2 are spaced apart at predetermined intervals on the substrate 170, and the first pad 181 and the second pad 182 may be separated from each other. It may be disposed to surround the edge of the substrate 170.

The substrate 170 may serve to support the semiconductor structure 120. The substrate 170 may include a material having heat dissipation characteristics. Therefore, heat dissipation characteristics may be improved through the substrate 170. For example, the substrate 170 may include a ceramic, but is not limited thereto. In particular, since the manufacturing process, package mounting, and heat dissipation of the semiconductor device package 100 are easily performed by the substrate 170, the reliability of the device may be improved. However, the present disclosure is not limited thereto, and the substrate 170 may be a metal substrate of various materials.

The bonding layer 171 may bond the substrate 170 and the semiconductor structure 120. In other words, the semiconductor structure 120 and the structures disposed under the semiconductor structure 120 may be disposed on the substrate 170 by the bonding layer 171. The bonding layer 171 may be selected from at least one of AuSn, NiSn, AuIn, CuSn, SiO _2, and resin, but is not limited thereto. For example, the bonding layer 171 may include a barrier metal or a bonding metal, and may include, for example, at least one of Ti, Au, Sn, Ni, Cr, Ga, In, Bi, Cu, Ag, or Ta. have.

The semiconductor structure 120 may be disposed on the substrate 170. The semiconductor structure 120 includes an active layer disposed between the first conductive semiconductor layer 121, the second conductive semiconductor layer 122, and the first conductive semiconductor layer 121 and the second conductive semiconductor layer 122. 123 may be included. In the drawing, the first conductivity type semiconductor layer 121 is shown to face upward, and the second conductivity type semiconductor layer 122 faces the substrate 170, but is not limited thereto.

The first conductivity-type semiconductor layer 121 may be implemented with at least one of compound semiconductors such as group III-V and group II-VI. The first conductive semiconductor layer 121 is a semiconductor material having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x + y≤1) or AlInN, AlGaAs, GaP, GaAs It may be formed of a material selected from GaAsP, AlGaInP. The first dopant may be doped into the first conductive semiconductor layer 121. The first dopant may be an n-type dopant such as Si, Ge, Sn, Se, Te, or the like. That is, the first conductivity-type semiconductor layer 121 may be an n-type semiconductor layer doped with an n-type dopant.

Meanwhile, an uneven structure may be formed on the first conductive semiconductor layer 121. The uneven structure may improve light extraction efficiency of the semiconductor structure 120.

The second conductivity-type semiconductor layer 122 may be implemented with at least one of compound semiconductors such as group III-V and group II-VI. The second conductive semiconductor layer 122 is a semiconductor material having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x + y≤1) or AlInN, AlGaAs, GaP, GaAs It may be formed of a material selected from GaAsP, AlGaInP. The second dopant may be doped in the second conductive semiconductor layer 122. The second dopant may be a p-type dopant such as Mg, Zn, Ca, Sr, or Ba. That is, the second conductive semiconductor layer 122 may be a p-type semiconductor layer doped with a p-type dopant.

The active layer 123 may be disposed between the first conductive semiconductor layer 121 and the second conductive semiconductor layer 122. The active layer 123 is a layer where electrons (or holes) injected through the first conductive semiconductor layer 121 and holes (or electrons) injected through the second conductive semiconductor layer 122 meet each other. The active layer 123 may transition to a low energy level as electrons and holes recombine, and may generate light having a corresponding wavelength.

The active layer 123 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure. It does not limit. When the active layer 123 is formed in a well structure, the well layer / barrier layer of the active layer 123 may be InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs, GaP (InGaP). / AlGaP may be formed of any one or more pair structure, but is not limited thereto. The well layer may be formed of a material having a band gap smaller than the band gap of the barrier layer.

Meanwhile, the semiconductor structure 120 may include a first recess R1 having a predetermined depth. In detail, the first recess R1 may be formed by mesa etching through the second conductive semiconductor layer 122 and the active layer 123 to a portion of the first conductive semiconductor layer 121. Thus, a portion of the first conductivity type semiconductor layer 121 may be exposed. Therefore, the first electrode 141 and the first wiring line 151 may be electrically connected to the first conductive semiconductor layer 121 through the first recess R1.

The channel layer 130 may be disposed in a portion of the lower portion of the semiconductor structure 120. In addition, the channel layer 130 may be disposed to surround the edge of the lower portion of each semiconductor structure 120. A portion of the channel layer 130 may be disposed under the first recess R1. In addition, the channel layer 130 may be disposed between the substrate 170 and the semiconductor structure 120.

In detail, the channel layer 130 may have a side surface of the active layer 123 exposed by the first recess R1 and the first recess R1, a portion of the first conductive semiconductor layer 121, and a second conductivity. A portion of the type semiconductor layer 122 may be covered. In this case, the channel layer 130 may be disposed to expose a portion of the first conductivity-type semiconductor layer 121 in the first recess R1. Similarly, the channel layer 130 may be disposed to expose a portion of the second conductivity type semiconductor layer 122.

The channel layer 130 may be disposed between the adjacent semiconductor structures 120, between the first pads 181 connected to the semiconductor structures 120, and between the second pads 182 connected to the semiconductor structures 120. In addition, the channel layer 130 may cover a portion of the second conductivity-type semiconductor layer 122. For example, the channel layer 130 may expose a portion of the second conductivity type semiconductor layer 122 through the first hole H1.

The channel layer 130 may be made of an insulating material. In detail, the channel layer 130 may be formed of an oxide or a nitride that is non-conductive. For example, the channel layer 130 may be formed of one selected from a silicon oxide (SiO ₂ ) layer, a silicon nitride (Si ₃ N ₄ ) layer, a titanium oxide (TiOx), or an aluminum oxide (Al ₂ O ₃ ) layer. This does not limit the present invention.

The channel layer 130 may be electrically connected to the semiconductor structure 120 only through the first wiring line 151 and the second wiring line 152, and may provide structural insulation between adjacent semiconductor structures 120. In addition, the channel layer 130 may include the second electrode 142, the first insulating layer 161, the second insulating layer 162, and the bonding layer 171 disposed under the channel layer 130 and the semiconductor structure 120. ) And the substrate 170 may be protected from external contaminants. As a result, the support layer for the semiconductor structure 120 may be improved, and the channel layer 130 may be protected from damage that may occur in the manufacturing process.

The first electrode 141 may be disposed on the first conductive semiconductor layer 121 and electrically connected to the first conductive semiconductor layer 121. The second electrode 142 may be disposed on the second conductive semiconductor layer 122 and electrically connected to the second conductive semiconductor layer 122.

In detail, the first electrode 141 may be disposed in the first recess R1. The first electrode 141 may be disposed in an area exposed by the channel layer 130 in the first recess R1.

The second electrode 142 may be disposed on the second conductivity type semiconductor layer 122 exposed by the channel layer 130 in the first hole H1.

The first electrode 141 and the second electrode 142 may be made of a material having electrical conductivity. In addition, the first electrode 141 and the second electrode 142 may be formed of a material having high reflectance.

For example, the first electrode 141 and the second electrode 142 are Ti, Ru, Rh, Ir, Mg, Zn, Al, In, Ta, Pd, Co, Ni, Si, Ge, Ag, Pt, and It may be made of any one selected from Au, or an alloy thereof.

In this case, the light generated from the semiconductor structure 120 may be reflected from the first electrode 141 and the second electrode 142 and emitted upward. As a result, light extraction efficiency of the semiconductor structure may be improved. However, it is not necessarily limited to these materials.

In addition, the first electrode 141 and the second electrode 142 may include various materials for ohmic bonding.

The reflective layer 143 may be disposed under the second electrode 142. The reflective layer 143 may be made of a material having electrical conductivity. In addition, the reflective layer 143 may be formed of a metal material having a high reflectance.

For example, the reflective layer 143 may be formed of a metal or an alloy including at least one of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Cu, Au, and Hf.

In addition, the reflective layer 143 may be made of the metal or alloy. For example, the reflective layer 143 may include at least one of Ag, Al, Ag-Pd-Cu alloy, or Ag-Cu alloy, but is not limited thereto.

The first insulating layer 161 may protect the components of the semiconductor device package 100 and electrically insulate between adjacent components. As the first insulating layer 161, an insulating layer having a high transmittance may be used. For example, the first insulating layer 161 may be any one selected from SiO ₂ , SixOy, Si ₃ N ₄ , SixNy, SiOxNy, TiO ₂ , ZrO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , AlN, and MgF ₂ . It may be formed, but is not limited to these materials.

The first insulating layer 161 may partially cover the first electrode 141 to expose a portion of the first electrode 141. The first insulating layer 161 may be disposed under the second electrode 142, the channel layer 130, and the second wiring line 152 to cover the second electrode 142 and the channel layer 130. . By such a configuration, the first insulating layer 161 may provide electrical insulation between the first wiring line 151 and the second wiring line 152.

The second insulating layer 162 may be disposed under the first insulating layer 161 and the first wiring line 151. The second insulating layer 162 may cover the first wiring line 151 and the first insulating layer 161. By such a configuration, the second insulating layer 162 may protect the first wiring line 151 from the outside while being electrically insulated from the outside. As a result, the second insulating layer 162 may improve reliability of the semiconductor device package.

The passivation layer 163 may be disposed on the semiconductor device package. That is, the passivation layer 163 may be disposed on the upper portion of the semiconductor structure 120 and the edge region of the substrate. In addition, when the first conductivity-type semiconductor layer 121 has a concave-convex structure, the passivation layer 163 disposed on the first conductivity-type semiconductor layer 121 has a concave-convex structure similar to the first conductivity-type semiconductor layer 121. It can have

The first wiring line 151 may be electrically connected to the first electrode 141. The second wiring line 152 may be electrically connected to the second electrode 142.

The first wiring line 151 may be electrically connected to the first electrode 141 and may extend to one side of the semiconductor structure 120 to be connected to the first pad 181.

In addition, the second wiring line 152 may be electrically connected to the second electrode 142 to extend to the other side of the semiconductor structure 120 to be electrically connected to the second pad 182.

The first wiring line 151 and the second wiring line 152 may extend in different directions on the substrate 170. For example, the direction in which the first wiring line 151 and the second wiring line 152 extend may be perpendicular to each other.

The second wiring line 152 may be disposed between the semiconductor structure 120 and the substrate 170. In addition, the second wiring line 152 may be disposed on the second electrode 142 and electrically connected to the second electrode 142.

The second wiring line 152 may extend from the second electrode 142 in the direction toward the outer surface of the semiconductor structure 120. For example, the second wiring line 152 may include a second end portion 152c extending to protrude more than an outer surface of the semiconductor structure 120. In other words, one end of the second wiring line 152 may be connected to the second electrode 142.

The second end portion 152c of the second wiring line 152 may extend in the edge direction of the substrate 170 at one end of the second wiring line 152. As a result, the second end portion 152c may be electrically connected to the second pad 182 which will be described later.

The second end portion 152c may extend to the edge of the substrate 170 to be easily connected to the second pad 182 disposed on the side surface of the semiconductor structure 120.

The first wiring line 151 may be disposed on the first electrode 141 between the semiconductor structure 120 and the substrate 170. In addition, the first wiring line 151 may extend from the first electrode 141 toward the edge of the semiconductor structure 120.

The first wiring line 151 may include a first through portion 151a, a first connection portion 151b, and a first end portion 151c. The first wiring line 151 may be spaced apart from the second wiring line 152 by the first insulating layer 161 and may be insulated.

The first through part 151a may pass through the active layer 123, the second conductive semiconductor layer 122, and the first insulating layer 161. In addition, the first through part 151a may partially pass through the first conductive semiconductor layer 121.

One end of the first through part 151a may be connected to the first electrode 141. The first through part 151a may extend from the first electrode 141 toward the substrate 170. The other end of the first through part 151a may be connected to one end of the first connection part 151b.

The first connector 151b may extend from one end toward the edge of the substrate 170 along one surface of the first insulating layer 161. The other end of the first connecting portion 151b may be connected to one end of the first end portion 151c.

The first end portion 151c may be disposed in the edge region P1 of the substrate as compared with the semiconductor structure 120. Accordingly, the first wiring line 151 may be easily connected to the first pad 181 disposed on the side of the semiconductor structure 120.

The first pad 181 and the second pad 182 may be spaced apart from the semiconductor structure 120 on the substrate 170. In detail, the first pad 181 and the second pad 182 may be disposed to surround the semiconductor structure 120 at the side of the semiconductor structure 120 or the edge of the substrate 170.

The first pad 181 may be electrically connected to the first conductive semiconductor layer 121 through the first wiring line 151 and the first electrode 141. The second pad 182 may be electrically connected to the second conductive semiconductor layer 122 through the second wiring line 152 and the second electrode 142.

The first pad 181 may include a first region 181a and a second region 181b.

One end of the first region 181a may be connected to the other end of the first end portion 151c. The first region 181a may pass through the first insulating layer 161, the channel layer 130, and the passivation layer 163.

The second region 181b may be disposed to protrude from the passivation layer 163. The first pad 181 may be spaced apart from the semiconductor structure 120. In particular, the first pad 181 may be disposed spaced apart from the side surface of the semiconductor structure 120 and the passivation layer 163 covering the side surface, but is not limited thereto.

The second pad 182 may include a first region 182a and a second region 182b.

The first region 182a may penetrate the channel layer 130 and the passivation layer 163. One end of the first region 181a may be connected to the other end of the second end portion 152c of the second wiring line 152.

One end of the second region 182b may be connected to the other end of the second end portion 152c. The second region 182b may be disposed to protrude from the passivation layer 163.

3 is a plan view of a semiconductor device package according to an embodiment, FIG. 4 is a cross-sectional view of I in FIG. 3, FIG. 5 is a view showing a first wiring line in FIG. 3, and FIG. 6 is a second wiring in FIG. 3. It is a figure which shows a line.

Referring to FIG. 3, the semiconductor device package 100 according to the embodiment may include a plurality of semiconductor structures 120 disposed on one substrate 170.

Specifically, the semiconductor device package 100 may include a plurality of semiconductor structures 120 disposed on the substrate 170, a plurality of first wiring lines 151-n spaced apart in a first direction (X-axis direction), It may include a plurality of second wiring lines 152-n, a plurality of first pads 181-n, and a plurality of second pads 182-n spaced apart in a second direction (Y-axis direction). .

The plurality of first pads 181-n and the plurality of second pads 182-n may be spaced apart from the plurality of semiconductor structures 120. The plurality of first pads 181-n and the plurality of second pads 182-n may be disposed in the edge region P1 of the substrate 170 to surround the plurality of semiconductor structures 120.

The first wiring line 151-n is disposed between the semiconductor structure 120 and the plurality of first pads 181-n to form a first conductive semiconductor layer and a plurality of first pads of the semiconductor structure 120. (181-n) can be electrically connected.

Similarly, the second wiring line 152-n is disposed between the semiconductor structure 120 and the plurality of second pads 182-n such that the second conductive semiconductor layer and the plurality of second conductive semiconductor layers of the semiconductor structure 120 are disposed. The pads 182-n may be electrically connected to each other.

In addition, the first pad 181-n may be disposed to face the top and bottom of an edge region of the substrate 170. The second pad 182-n may be disposed to face left and right among the edge regions of the substrate 170. However, in some cases, the position and arrangement of the first pad 181-n and the second pad 182-n may be changed.

The substrate 170 may be divided into a central region C1 and an edge region P1. For example, the central region C1 may be a region in which the semiconductor structure is disposed in the center of the substrate. In addition, the first wiring line 151-n and the second wiring line 152-n may be disposed in the central region C1 to be electrically connected to the plurality of semiconductor structures.

In the edge area P1, a plurality of first pads 181-n and a plurality of second pads 182-n may be disposed in areas other than the center area C1. In addition, a portion of the first wiring line 151-n and the second wiring line 152-n may be disposed in the edge region P1.

As a result, the first wiring line 151-n and the second wiring line 152-n extend to the edge region P1 to electrically connect with the first pad 181-n and the second pad 182-n, respectively. It may be connected to, and may include a region overlapping in the thickness direction.

In the substrate 170, the plurality of semiconductor structures may be spaced apart from each other at a central portion and may emit light. Here, although the semiconductor structures 120 are illustrated as being arranged in 16 pieces in both horizontal and vertical directions, the present invention is not limited thereto. The size of each semiconductor structure may be 500 μm × 500 μm or less. That is, the horizontal and vertical lengths may be 500 μm or less, respectively. For example, the size of the semiconductor structure may be 300 μm × 300 μm, 250 μm × 250 μm, 110 μm × 110 μm. More preferably, the length of each of the width and length of the individual semiconductor structure may be between 70 μm and 80 μm. However, this does not limit the present invention.

In the plurality of semiconductor structures, 1-8 lines are defined as A regions and 9-16 lines are defined as B regions from the top of the substrate 170. In addition, in the plurality of semiconductor structures, lines 1-8 are defined as C regions and lines 9-16 are defined as D regions from the left side.

The plurality of first wiring lines 151-n and n≥1 may extend to the edge region P1 of the substrate 170. In this case, one first-n wiring line 151-n may be electrically connected to eight semiconductor structures 120. Accordingly, 64 first wiring lines 151-n may be disposed at upper and lower portions of the substrate 170, respectively. That is, four first-n wiring lines 151-n may be disposed under one semiconductor structure 120. However, this is only an example for explaining the present invention, and this does not limit the present invention. That is, the number of semiconductor structures 120 connected to one first-n wiring line 151-n and the number of first-n wiring lines 151-n disposed under one semiconductor structure 120. Can be changed. Hereinafter, for convenience of description, the first-first wiring line 151-1 and the first-second wiring in order from the left side of the first-n wiring line 151-n connected to the semiconductor structure 120 in the region A for the convenience of description. It is defined as the line 151-2 and the first-32 wiring lines 151-32.

For example, the first-first wiring line 151-1 may be electrically connected to the eight semiconductor structures 120 arranged in the first left column of the A region. Here, the column is defined as a vertical line in the first direction (y-axis direction) in the substrate 170, and the row is defined as a horizontal line in the second direction (x-axis direction) in the substrate 170.

The phosphor layer 190 may be disposed on the plurality of semiconductor structures 120 and the passivation layer 163 to cover the plurality of semiconductor structures 120. As a result, the phosphor layer 190 may absorb the light emitted from the plurality of semiconductor structures 120 and convert the light into another wavelength band to emit the light. For example, the phosphor layer 190 may form white light.

5 and 6, the first-first wiring line 151-1 may include the first-firsta wiring line 151-1a, the first-first-b wiring line 151-1b, and the first-first c wiring. It may include a line 151-1c and a 1-1d wiring line 151-1d.

In addition, the first-first wiring line 151-1 may be electrically connected to eight semiconductor structures arranged in the first left column of the A region. Similarly, the first-second wiring line 151-2 may be electrically connected to eight semiconductor structures disposed in the second left column of the region A, which may be equally applied to the first-32 wiring lines 151-32. have. However, the first-17th wiring lines 151-17 to the first-32th wiring lines 151-32 may be electrically connected to the semiconductor structures of the C region and the D region.

The plurality of second wiring lines 152-n and n ≧ 1 may be disposed on the left and right sides of the edge region P1 of the substrate 170. In this case, one second-n wiring line 152-n may be electrically connected to eight semiconductor structures.

Sixteenth 2-n wiring lines 152-n may be disposed on the left and right sides of the substrate 170, respectively. That is, unlike the first-n wiring line 151-n, one second-n wiring line 152-n may be disposed under the one semiconductor structure 120. However, this is only an example for explaining the present invention, and this does not limit the present invention. That is, the number of semiconductor structures connected to one second-n wiring line 152-n and the number of second-n wiring lines 152-n disposed below one semiconductor structure may be changed.

Hereinafter, for convenience of description, the second wiring line 152-n disposed on the left side of the substrate 170 in the order from the top, the 2-1 wiring line 152-1 and the 2-2 wiring line 152. -2), … 2-16 wiring lines 152-16. Similarly, the second wiring line 152-n disposed on the right side of the substrate 170 includes the second-17th wiring lines 152-17 to the second-32th wiring lines 152-32 in order from the top. can do.

The second-first wiring line 152-1 may be electrically connected to eight semiconductor structures disposed in the upper first row of the C region. In detail, the second-first wiring line 152-1 may be electrically connected to the second conductive semiconductor layers of the eight semiconductor structures disposed in the upper first row.

Similarly, the second-second wiring line 152-2 may be electrically connected to eight semiconductor structures disposed in the upper second row of the C region. The same may be applied to the 2-16 wiring line 152-16.

The same may also be applied to the D region. That is, the second 2-n wiring lines 152-n may be electrically connected to eight semiconductor structures. For example, one second n-wire line 152-n may be electrically connected to eight semiconductor structures in each row of the D region in order from the top of the substrate 170.

As such, the first-n wiring line 151-n may be electrically connected to eight semiconductor structures per one in regions A and B (or regions C and D) in order from the left.

In addition, the second 2-n wiring line 152-n may be electrically connected to eight semiconductor structures of regions C and D in order from the top.

The plurality of first pads 181-n and n ≧ 1 may be disposed on upper and lower portions of the edge region P1 of the substrate 170. In this case, four first-n pads 181-n may be disposed on each of the first wiring lines 151-n. That is, a total of 128 first-n pads 181-n may be disposed with respect to 32 first wiring lines 151-n.

For example, the first-first pad 181-1 may be disposed in the order from the top of the substrate 170 to the left in the order of the first-first a pad 181-1a, the first-first b pad 181-1b, and the first-first pad. It may include a 1-1c pad 181-1c and a 1-1d pad 181-1d. The 1-1a pads (181-1a), the 1-1b pads (181-1b), the 1-1c pads (181-1c), and the 1-1d pads (181-1d) are respectively wired 1-1a. The line 151-1a, the 1-1b wiring line 151-1b, the 1-1c wiring line 151-1c, and the 1-1d wiring line 151-1d may be electrically connected to each other.

The first-first a wiring line 151-1 a, the first-first b wiring line 151-1 b, the first-first c wiring line 151-1 c, and the first-first d wiring line 151-1 d are 8 One of the two semiconductor structures may be electrically connected to the first conductive semiconductor layers of two adjacent semiconductor structures.

In addition, the plurality of first-n pads 181-n may include the first-first pad 181-1, the first-second pad 181-2,. It may be defined as a 1-16 pad (181-16). In addition, the plurality of first-n pads 181-n may be defined as the first-17th pads 181-17 and the first-32th pads 181-32 in order from the left side of the substrate.

Accordingly, the first-first pads 181-1 to 1-16-pads 181-16 may include the first-first wiring lines 151-1 to 1-16 wiring lines 151-disposed in the area A. 16) can be electrically connected.

The first through seventeenth pads 181-17 to the first through thirty-two pads 181-32 may include the first through seventeenth wiring lines 151-17 and the first through thirty first wiring lines 151-32 disposed in the B region. ) Can be electrically connected.

The plurality of second pads 182-n and n ≧ 1 may be disposed in the edge region P1 of the substrate 170. In this case, the second-n pads 182-n may be disposed on the second-n wiring line 152-n one by one. As described above, 16 second-n pads 182-n may be disposed on the left and right sides of the substrate 170, respectively. In addition, one second n pad 182-n may be electrically connected to eight semiconductor structures in the same row. However, this is only an example for explaining the present invention, and this does not limit the present invention.

First, the second-n pads 182-n disposed on the left side of the substrate 170 are arranged in order from the top to the second-first pad 182-1, the second-second pad 182-2,. It may be defined as a 2-16 pad 182-16. Here, the second-first pad 182-1 may be disposed on the second-first wiring line 152-1 and electrically connected thereto. The second-first pad 182-1 may be electrically connected to eight semiconductor structures disposed in the upper first row of the C region. This may be equally applied to the 2-16 pads 182-16. In addition, the same may be applied to the second pads 182-17 to 182-32 disposed on the right side of the substrate 170.

As described above, the plurality of first pads and the second pads 181-n and 182-n may be disposed along the edge area P1 of the substrate 170. In addition, the plurality of semiconductor structures may be disposed inside the plurality of pads 181-n and 182-n. That is, the plurality of first pads and the second pads 181-n and 182-n may be arranged to surround the plurality of semiconductor structures. In addition, the plurality of first wiring lines and the second wiring lines 151-n and 152-n may be connected to the substrate from the first to second conductive semiconductor layers 121 and 122 or the first to second electrodes 141 and 142. It may extend to an edge area and be connected to the plurality of pads 181-n and 182-n. The plurality of semiconductor structures are not formed separately, but the first to second conductivity type semiconductor layers 121 and 122 and the active layer 123 are grown at one time, and are isolated by one chip (device) through etching. It can be formed by. Therefore, the light emitting area can be increased while improving the processability.

7 and 8 illustrate a passive matrix driving method according to an embodiment.

7 and 8, the first driver may apply a first control signal to the selected data line DL. In addition, the second driver may apply a second control signal to the scan line SL.

As illustrated in FIG. 7, the plurality of semiconductor structures 120 may include a display area DP. In addition, as described above, the display area DP may include a pixel PX, which is each semiconductor structure 120.

In this case, the display area DP may be divided into a plurality of divided display areas DP1 and DP2 according to the number of time divisions by the scan line SL. The division display areas DP1 and DP2 may include scan lines SL equal to the number of time divisions corresponding to the structure of the semiconductor device package 100, respectively. Here, the time division number corresponding to the structure of the semiconductor device package 100 may be the number of semiconductor structures connected to one data line DL. Accordingly, the scan line SL may include group scan lines divided for each scan line equal to the number of time divisions. For example, in two-time division, the first group scan line may include a first scan line SL1 and a second scan line SL.

In the division display areas DP1 and DP2, the second control signal may be applied to the scan line SL at different time intervals during one frame FR. Here, one frame FR refers to a time when image data is displayed through the display area DP. In general, one frame (FR) is 60 Hz, 1/60 (s), but is not limited to this frequency, it can be variously changed according to the light source device.

In the case of two-time division, each of the first divided display area DP1 and the second divided display area DP2 may include two scan lines SL. For example, the first divided display area DP1 may include a first scan line SL1 and a second scan line SL2, and the second divided display area DP2 may include a third scan line SL3 and a third scan line SL3. It may include four scan lines SL4.

In this case, a second control signal may be applied to one scan line in the first divided display area DP1 and one scan line in the second divided display area DP2 in a first time period within one frame FR. have.

In addition, the other scan line in the first divided display area DP1 and the other scan line in the second divided display area DP2 have a second time period (for example, in the case of two time division) within one frame FR. The second control signal may be applied in a time period other than the first time period within the frame FR.

When the second control signal is applied to one scan line in the first divided display area DP1, the same second control signal may be applied to one scan line in the second divided display area DP2. That is, the second control signal may be applied to the plurality of divided display regions DP through one scan line for each time division.

In addition, the second control signal may be sequentially applied to the scan lines for each of the divided display regions DP. For example, a second control signal is applied to the first scan line SL1 and the third scan line SL3 of the first group scan line GSL1 during the first time period, and the second scan signal of the second group scan line GSL2 is applied. The second control signal may be applied to the second scan line SL2 and the fourth scan line SL4 in the second time period. This may be equally applied to other group scan lines.

However, the present invention is not limited to this sequential method, and in the first scan line SL1 and the fourth scan line SL4 during the first time period, the second scan line SL2 and the third scan during the second time period. The second control signal may be applied at the line SL3, respectively.

According to this configuration, the light source device according to the embodiment may display the image data applied by the passive matrix method through the semiconductor structure 100.

In addition, the number of scan lines SL, data lines DL, and display regions DP may be changed according to the number of semiconductor structures 120 of the semiconductor device package as described above, and may also be changed depending on the number of time divisions. can be changed.

9 is a view for explaining the effect of the light source device according to the embodiment.

Referring to FIG. 9, the light flux (y-axis) according to the average current (x-axis) injected into the semiconductor structure in the case of the two-time division (a) and the four time division (b). Here, the average current injected into the semiconductor device package is the same in the case of the 2 time division (a) and the 4 time division (b), but the peak current is 1/2 times that of the 4 time division (b) in the case of the 2 time division (a). Can be.

In the case of 2 time division (a) and 4 time division (b), current is injected into one scan line in one time interval of four frames in one scan line, but in the case of two time division (a) two in one frame Since current is injected in one of the time periods, the peak current per scan line may be twice the peak current per scan line in the case of two-time division in the four-hour division (b).

Thus, it can be seen that the light flux does not increase in proportion to the average current even when the same average current is injected in the case of the four time division. This is because current spreading does not increase linearly even when a high peak current is injected.

Therefore, the luminous flux can be increased by decreasing the number of time divisions as necessary. Alternatively, if necessary, the number of time divisions may be increased to display necessary information on the road surface.

10 is a conceptual diagram illustrating a light source device according to another exemplary embodiment of the present disclosure, FIG. 11 is a first modified example of the semiconductor structure, FIG. 12 is a second modified example of the semiconductor structure, and FIG. It is a three variant example.

Referring to FIG. 10, the light source device according to the embodiment may include a semiconductor device package 100, a first driver 200, a second driver 300, and a controller 400.

The semiconductor device package 100 may be spaced apart from each other in a central direction C1 of the substrate 170 in a first direction (X-axis direction) and a second direction perpendicular to the first direction (Y-axis direction). ), A plurality of first wire electrodes 151 electrically connected to the semiconductor structure 120 and spaced apart in the first direction, and a plurality of second wires electrically connected to the semiconductor structure 120 and spaced apart in the second direction The wiring electrode 152 may be included.

The first driver 200 is connected to the plurality of first wire electrodes 151 to output a first control signal, and the second driver 300 is connected to the plurality of second wire electrodes 152 to provide a second control signal. You can output

The above-described information may be applied to the basic structure of the light source device and the time division control method. However, the present embodiment has an additional feature in that the size and number of semiconductor structures vary according to regions, and that time-division control of semiconductor structures having different sizes and numbers is independently performed.

The plurality of first semiconductor structures 120A may be disposed in the first region CA1 of the substrate 170. In addition, the plurality of second semiconductor structures 120B may be disposed in the second region CA2 of the substrate 170. The first area CA1 and the second area CA2 may be disposed in the central area C1 of the substrate 170. The area of the first area CA1 and the second area CA2 may be the same, but is not necessarily limited thereto.

The sizes of the plurality of first semiconductor structures 120A may be different from the sizes of the plurality of second semiconductor structures 120B. According to such a structure, the size of the semiconductor structure may be differently manufactured according to a region requiring a relatively high resolution and a region not requiring a high resolution, and thus, various functions may be simultaneously implemented in one light source device.

The size of the semiconductor structure may refer to shape as well as size. For example, the first semiconductor structure 120A disposed in the first region CA1 has a square having the same horizontal and vertical lengths, whereas the second semiconductor structure 120B disposed in the second region CA2 has a horizontal and vertical length. May be rectangular with different lengths. Since the size of the semiconductor structure is different there is an advantage that can improve the visibility. In this case, an area of the first semiconductor structure 120A and an area of the second semiconductor structure 120B may be the same.

According to an embodiment, the number of first semiconductor structures 120A in the first region CA1 and the number of second semiconductor structures 120B in the second region CA2 may be the same, but are not limited thereto.

The controller 400 may independently time-division control the first semiconductor structure 120A of the first region CA1 and the second semiconductor structure 120B of the second region CA2.

For example, the first area CA1 may be controlled by 4 hours and the second area CA2 may be controlled by 2 hours. Therefore, when the first semiconductor structure 120A of the first region CA1 is arranged in four lines, and the second semiconductor structure 120B of the second region CA2 is arranged in four lines, the second semiconductor The structure 120B may be alternately lit by two lines, while the first semiconductor structure 120A may be sequentially lit by one line.

However, the present invention is not limited thereto, and the number and method of time division of the first area CA1 and the second area CA2 may be variously modified according to the size and driving purpose of the chip. In this case, the structures of the first wiring electrode and the second wiring electrode may be variously modified according to the number of time divisions.

Referring to FIG. 11, the semiconductor structure may include a plurality of first semiconductor structures 120A disposed in the first region CA1, a second semiconductor structure 120B disposed in the second region CA2, and a third region ( Third semiconductor structure 120C disposed in CA3).

According to an embodiment, three semiconductor structures having different sizes may be disposed. In this case, the number and size of the first to third semiconductor structures 120A, 120B, and 120C may be different from each other. In exemplary embodiments, the first semiconductor structure 120A may be 8 × 16, and the second semiconductor structure 120B and the third semiconductor structure 120C may be 2 × 32, respectively. However, the present invention is not necessarily limited thereto, and the number and shape of each semiconductor structure may vary depending on the purpose.

Referring to FIG. 12, the size of the first semiconductor structure 120A of the first region CA1 may be smaller than the size of the second semiconductor structure 120B of the second region CA2. For example, the first semiconductor structure 120A may have a rectangular shape in which the length in the horizontal direction (X-axis direction) is longer than the length in the vertical direction (Y-axis direction), and the second semiconductor structure 120B may be formed in the horizontal direction. It may be a rectangular shape whose length is shorter than the length in the longitudinal direction.

It may be advantageous that the first semiconductor structure 120A is formed long in the horizontal direction to display information on the road surface, and the second semiconductor structure 120B is formed long in the vertical direction to secure visibility in the front and prevent glare. May be advantageous. However, the present invention is not limited thereto, and the shape of the semiconductor structure may be variously modified as necessary.

FIG. 13 is a view illustrating a field of view (FOV) of the head lamp, and FIG. 14 is a fourth modified example of the semiconductor structure.

Referring to FIG. 13, the FOV of the high beam HB of the smart head lamp may be divided into an upper region HB12 and a lower region HB11. The high beam area HB may partially overlap the low beam area LB. The upper area HB12 of the high beam may be an area for irradiating light to the front so that the driver can check the front. Thus, the upper region HB12 requires high brightness but may not require high resolution. In contrast, the lower area HB11 may be an area for displaying information SG1 such as a text or an image on the road surface. Therefore, the lower region HB11 does not require high brightness but may require high resolution.

Therefore, referring to FIG. 14, the first region CA1 irradiating light to the lower region HB11 of the high beam may be manufactured to have a small size and a large number of first semiconductor structures 120A. Therefore, high resolution can be achieved and various information SG1 can be displayed on the road surface. In addition, time division control can be independently performed to enable information display. After receiving the information to be displayed, the controller 400 may determine the number of time divisions of the first area CA1.

In addition, since the second area CA2 for irradiating light to the upper area HB12 of the high beam needs visibility and anti-glare functions, the number of the second semiconductor structures 120B may be smaller than that of the first semiconductor structures 120A. have. In addition, the size of the second semiconductor structure 120B may be larger than that of the first semiconductor structure 120A. The controller 400 may determine the number of time divisions of the second area CA2 independently of the time division control of the first area CA1. If there is no information to be output on the road surface, the number of time divisions of the first area CA1 and the second area CA2 may be the same.

The second area CA2 may improve glare by blocking light emitted to vehicles in neighboring lanes. That is, by turning off the semiconductor structure for irradiating light to a vehicle in a neighboring lane, a blocking region (HB13 in FIG. 13) may be formed to improve glare. In this case, in order to improve visibility and prevent glare, the second semiconductor structure 120B may be formed long in the vertical direction, but is not necessarily limited thereto.

The controller 400 may independently time-division control the first semiconductor structure 120A of the first region CA1 and the second semiconductor structure 120B of the second region CA2.

For example, the first area CA1 may be controlled by 4 hours and the second area CA2 may be controlled by 2 hours. Therefore, when the first semiconductor structure 120A of the first region CA1 is arranged in four lines, and the second semiconductor structure 120B of the second region CA2 is arranged in four lines, the second semiconductor The structure 120B may be alternately lit by two lines, while the first semiconductor structure 120A may be sequentially lit by one line.

However, the present invention is not limited thereto, and the number and method of time division of the first area CA1 and the second area CA2 may be variously modified according to the size and driving purpose of the chip. In this case, the structures of the first wiring electrode and the second wiring electrode may be variously modified according to the number of time divisions.

FIG. 15 is a fifth modified example of the semiconductor structure, FIG. 16 is a view illustrating a field of view (FOV) covered by the semiconductor structure of FIG. 15, and FIG. 17 is a fourth modified example of the semiconductor structure.

Referring to FIG. 15, the number of the first semiconductor structures 120A and the second semiconductor structures 120B may be greater. In this case, the size of the semiconductor device package may increase. Referring to FIG. 16, the semiconductor structure of FIG. 15 may cover areas HB11 and HB12 covered by the high beam and the low beam of the vehicle. That is, one light source device may perform both the low beam and the high beam.

Referring to FIG. 17, the second area CA2 may be disposed to surround the first area CA1. That is, a part corresponding to the first area CA1 performs a function of displaying information on the road surface, and the second area CA2 serves to secure visibility by irradiating light around the first area CA1. can do. However, the present invention is not limited thereto, and the first region CA1 may be disposed at one corner of the entire region of the semiconductor structure.

Referring to FIG. 18, in the light source device according to the embodiment, since a plurality of semiconductor structures 120 are disposed on one substrate 170, a head lamp function may be performed using one optical system 30. In addition, the light source device 10 according to the embodiment may adjust the size and number of the semiconductor structure in various ways. On the other hand, the conventional semiconductor package has a disadvantage in that a plurality of optical systems are required because the head lamp is implemented by arranging a plurality of modules in which ten or less semiconductor chips are mounted.

The semiconductor device package described above may be used as a light source of various illuminations in addition to the above-described head lamp. For example, it may be used as a light source of an image display device or a light source of an illumination device.

When used as a backlight unit of the image display device may be used as a backlight unit of the edge type or a backlight unit of the direct type, may be used as a luminaire or bulb type when used as a light source of the lighting device.

Although the above description has been made with reference to the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains are not illustrated above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

Claims (14)

Board;
A plurality of semiconductor structures disposed in a central region of the substrate and spaced apart from each other in a first direction and a second direction perpendicular to the first direction;
A plurality of first wiring electrodes electrically connected to the semiconductor structure and spaced apart from each other in the first direction;
A plurality of second wiring electrodes electrically connected to the semiconductor structure and spaced apart from each other in the second direction; And
A first insulating layer disposed between the first wiring electrode and the second wiring electrode,
The first wiring electrode and the second wiring electrode extend from the central region to the edge region of the substrate,
The plurality of semiconductor structures,
A plurality of first semiconductor structures disposed in a first region of the central region, and a plurality of second semiconductor structures disposed in a second region of the central region,
The size of the plurality of first semiconductor structures is different from the size of the plurality of second semiconductor structures.
The method of claim 1,
The area of the first region and the second region is the same semiconductor device package.
The method of claim 2,
The semiconductor device package of claim 1, wherein the number of the plurality of first semiconductor structures disposed in the first region is greater than the number of the plurality of second semiconductor structures disposed in the second region.
The method of claim 1,
The size of the plurality of first semiconductor structures disposed in the first region is smaller than the size of the plurality of second semiconductor structures disposed in the second region.
The method of claim 4, wherein
The first device width of the second semiconductor structure is smaller than the first device width of the semiconductor structure package.
The method of claim 1,
And the first region and the second region are disposed in the second direction.
The method of claim 1,
The second region surrounds the first region.
The method of claim 1,
The plurality of semiconductor structures include a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer,
The first wiring line extends through the active layer, the second conductive semiconductor layer, and the first insulating layer to a first through part electrically connected to the first conductive semiconductor layer, and an edge of the substrate. 1 end,
The second wiring line includes a second end portion extending to an edge region of the substrate.
The method of claim 8,
A plurality of first pads electrically connected to the first wiring lines; And
A plurality of second pads electrically connected to the second wiring lines, respectively;
The first pad may include a first region penetrating the first insulating layer and electrically connected to the first end portion; And a second region extending from the first region and protruding on an edge region of the substrate.
A semiconductor device package comprising a substrate, a plurality of first semiconductor structures disposed in a first region of the substrate, and a plurality of second semiconductor structures disposed in a second region of the substrate; And
A controller for outputting control signals to the plurality of first and second semiconductor structures,
Sizes of the plurality of first semiconductor structures are different from sizes of the plurality of second semiconductor structures,
And the controller independently time-divisionally controls the first semiconductor structure of the first region and the second semiconductor structure of the second region.
The method of claim 10,
And the controller controls the time division number of the first semiconductor structure of the first region and the time division number of the second semiconductor structure of the second region differently.
The method of claim 10,
And an area of the first area and the second area is the same.
The method of claim 12,
The number of the plurality of first semiconductor structures disposed in the first region is greater than the number of the plurality of second semiconductor structures disposed in the second region.
The method of claim 10,
The size of the plurality of first semiconductor structures disposed in the first region is smaller than the size of the plurality of second semiconductor structures disposed in the second region.

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