KR20190070768A - Display Device - Google Patents

Abstract

The present invention relates to a display device capable of increasing a degree of freedom of design and an opening ratio by adjusting a size of a circuit region and a light emitting region of each of sub-pixels. According to an embodiment of the present invention, the display device comprises at least first and second sub-pixels located on a substrate. The first and second sub-pixels individually include a light emitting region including an organic light emitting diode, and a circuit region including a plurality of thin film transistors and capacitors. The capacitor of the second sub-pixel surrounds at least two sides of the capacitor of the first sub-pixel.

Description

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a display device, and more particularly, to a display device capable of improving a degree of freedom of design and an aperture ratio by adjusting the size of a circuit region and a light emitting region of each subpixel.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) that replaces bulky cathode ray tubes (CRTs). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED).

Among these organic electroluminescent display devices, self-luminous elements emit self-luminous elements, which have the advantage of high response speed and high luminous efficiency, brightness and viewing angle. In particular, the organic light emitting display device can be formed on a flexible flexible substrate, and can be driven at a lower voltage than a plasma display panel or an inorganic electroluminescence (EL) display, and the power consumption is relatively low It has the advantage of excellent color.

In the organic light emitting diode display, three subpixels of red, green, and blue form one unit pixel, or four subpixels constitute one unit pixel by adding white. The organic light emitting display device is designed to improve the display quality by increasing the aperture ratio of each subpixel. Each sub-pixel includes a light emitting region and a circuit region in which thin film transistors and a capacitor are formed. The sizes of the emission regions of the red, green, blue, and white sub-pixels are slightly different, and the sizes of the capacitors are slightly different depending on the colors. However, since the size of the circuit area of all the subpixels is designed to be the same, an extra space is unnecessarily generated in the circuit area, and the design of the data line is complicated to design the size of the light emitting area differently.

Accordingly, the present invention provides a display device capable of improving the degree of freedom of design and the aperture ratio by adjusting the sizes of the circuit region and the light emitting region of each subpixel.

In order to achieve the above object, a display device according to an embodiment of the present invention includes at least first and second sub-pixels positioned on a substrate, and the first and second sub- And a circuit region including a plurality of thin film transistors and capacitors, wherein the capacitor of the second subpixel surrounds at least two sides of the capacitor of the first subpixel.

The area of the circuit area of the first sub-pixel and the area of the circuit area of the second sub-pixel are different from each other.

The area of the circuit region of the second subpixel is larger than the area of the circuit region of the first subpixel.

A first power line and a sensing line neighboring each other with the first subpixel and the second subpixel interposed therebetween, wherein the first power supply line and the sensing line are connected to the first subpixel and the second subpixel, Pixel.

A third subpixel and a fourth subpixel symmetrical to the first subpixel and the second subpixel with respect to the sensing line, the sensing line being shared by the third subpixel and the fourth subpixel, do.

And a second power supply line adjacent to the sensing line with the third subpixel and the fourth subpixel interposed therebetween, and the second power supply line is shared with the third subpixel and the fourth subpixel.

A capacitor of the first subpixel and a capacitor of the second subpixel are disposed between the light emitting region of the first subpixel and the light emitting region of the second subpixel.

Wherein the first sub-pixel and the second sub-pixel further include a first data line connected to the first sub-pixel and a second data line connected to the second sub-pixel, Line.

A third data line connected to the third subpixel and a fourth data line connected to the fourth subpixel, wherein the third subpixel and the fourth subpixel are connected to the third data line and the fourth data line, Line.

And a first data line shared by the first subpixel and the second subpixel, wherein the first subpixel and the second subpixel are disposed between the first data line and the sensing line.

The third subpixel and the fourth subpixel are disposed between the second data line and the sensing line. The third subpixel and the fourth subpixel are disposed between the second data line and the sensing line.

A circuit region of the first subpixel is disposed between the first data line and a light emitting region of the first subpixel, and a circuit region of the second subpixel is disposed between the light emitting region of the first data line and the second subpixel A circuit region is disposed.

Each of the emission regions of the first to fourth subpixels is disposed adjacent to the sensing line, the emission regions of the first subpixel and the second subpixel are disposed on one side of the sensing line, And the emission region of the fourth sub-pixel is disposed on the other side of the sensing line.

The sensing line may further include a sensing connection line extending to the first to fourth subpixels, wherein the sensing connection line includes a first branch portion connected at one end to the first and second subpixels, And a second branch connected to the third and fourth sub-pixels.

The display device according to embodiments of the present invention may be configured so that the capacitors of the second subpixel surround at least two sides of the capacitors of the first subpixel so that the sizes of the respective emissive regions of the first and second subpixels are adjusted At least one data line may be formed in a straight line without having to be bent. Therefore, the size of the capacitor, the circuit region, and the light emitting region can be freely adjusted within the subpixel, and the data lines can also be formed as a straight line, which is advantageous in designing the layout of the subpixels.

Also, the display device according to the embodiments of the present invention can prevent the light leakage between adjacent sub-pixels from being generated by forming the capacitors between the light emitting regions of the adjacent sub-pixels.

Further, the display device according to the embodiments of the present invention can arrange the capacitors between the light emitting regions of each sub-pixel so that the color filter, the bank layer, and the first electrode can have margins that can be further formed on the capacitors, There is an advantage that it is easy.

1 is a schematic block diagram of an organic light emitting diode display.
2 is a schematic circuit configuration diagram of a subpixel.
3 is a detailed circuit diagram of a subpixel.
4 is a sectional view of a display panel;
Figure 5 schematically illustrates a planar layout of subpixels according to the present invention;
6 illustrates a planar layout of a subpixel of the present invention.
7 is a simplified plan view layout of subpixels in accordance with an embodiment of the present invention.
FIG. 8 illustrates a detailed layout of subpixels according to an embodiment of the present invention; FIG.
9 is a sectional view taken along the cutting line B-B 'in Fig. 8;
10 is a sectional view taken along the cutting line C-C 'in Fig. 8;
Figure 11 schematically illustrates a planar layout of subpixels according to another embodiment of the present invention.
12 illustrates a detailed layout of subpixels according to another embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

A display device according to the present invention is a display device in which a display element is formed on a glass substrate or a flexible substrate. As an example of the display device, an organic light emitting display device, a liquid crystal display device, an electrophoretic display device, or the like can be used. In the present invention, an organic light emitting display device will be described as an example. The organic light emitting diode display includes an organic layer between the first electrode, which is an anode, and the second electrode, which is a cathode. Therefore, the holes supplied from the first electrode and the electrons supplied from the second electrode are combined in the organic layer to form excitons, which are hole-electron pairs, and the excitons emit light by energy generated when the excitons return to the ground state Emitting display device.

FIG. 1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is a schematic circuit configuration diagram of a subpixel, FIG. 3 is a detailed circuit configuration diagram of a subpixel, and FIG.

1, the OLED display includes an image processor 110, a timing controller 120, a data driver 130, a scan driver 140, and a display panel 150.

The image processing unit 110 outputs a data enable signal DE together with a data signal DATA supplied from the outside. The image processing unit 110 may output at least one of a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of explanation.

The timing controller 120 receives a data signal DATA from a video processor 110 in addition to a data enable signal DE or a driving signal including a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal. The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130, .

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120 and converts the sampled data signal into a gamma reference voltage . The data driver 130 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an IC (Integrated Circuit).

The scan driver 140 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 140 outputs a scan signal through the gate lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or a gate-in-panel (GATE) panel in the display panel 150.

The display panel 150 displays an image corresponding to the data signal DATA and the scan signal supplied from the data driver 130 and the scan driver 140. The display panel 150 includes sub-pixels SP that operate to display an image.

The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel or a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP may have one or more different emission areas depending on the emission characteristics.

As shown in FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED.

The switching transistor SW is operated so that a data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst in response to a scan signal supplied through the first gate line GL1. The driving transistor DR operates so that the driving current flows between the power supply line EVDD (high potential voltage) and the cathode power supply line EVSS (low potential voltage) in accordance with the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light in accordance with the driving current generated by the driving transistor DR.

The compensation circuit CC is a circuit added in the sub-pixel to compensate the threshold voltage of the driving transistor DR and the like. The compensation circuit CC is composed of one or more transistors. The configuration of the compensation circuit (CC) varies greatly according to the external compensation method. An example of the compensation circuit (CC) is as follows.

As shown in Fig. 3, the compensation circuit CC includes a sensing transistor ST and a sensing line VREF (or a reference line). The sensing transistor ST is connected between the source electrode of the driving transistor DR and the anode electrode of the organic light emitting diode OLED (hereinafter referred to as a sensing node). The sensing transistor ST supplies the initialization voltage (or sensing voltage) transmitted through the sensing line VREF to the sensing node of the driving transistor DR or the voltage of the sensing node VREF Or to sense the current.

A drain electrode of the switching transistor SW is connected to the first data line DL1, and a source electrode of the switching transistor SW is connected to a gate electrode of the driving transistor DR. In the driving transistor DR, a drain electrode is connected to the power supply line EVDD and a source electrode is connected to the anode electrode of the organic light emitting diode OLED. In the capacitor Cst, the upper electrode is connected to the gate electrode of the driving transistor DR, and the lower electrode is connected to the anode electrode of the organic light emitting diode OLED. In the organic light emitting diode OLED, an anode electrode is connected to the source electrode of the driving transistor DR and a cathode electrode is connected to the second power supply line EVSS. In the sensing transistor ST, a drain electrode is connected to the sensing line VREF, and a source electrode is connected to the anode electrode of the organic light emitting diode OLED, which is a sensing node, and the source electrode of the driving transistor DR.

The operating time of the sensing transistor ST may be similar to, or the same as, or different from that of the switching transistor SW depending on the external compensation algorithm (or the configuration of the compensation circuit). For example, the gate electrode of the switching transistor SW may be connected to the first gate line GL1, and the gate electrode of the sensing transistor ST may be coupled to the second gate line GL2. In this case, a scan signal (Scan) is transmitted to the first gate line (GL1) and a sensing signal (Sense) is transmitted to the second gate line (GL2). As another example, the first gate line GL1 connected to the gate electrode of the switching transistor SW and the second gate line GL2 connected to the gate electrode of the sensing transistor ST may be connected in common.

The sensing line VREF may be connected to the data driver. In this case, the data driver can sense the sensing node of the subpixel during the non-display period of the real time image, or the N frame (N is an integer of 1 or more) and generate the sensing result. On the other hand, the switching transistor SW and the sensing transistor ST can be turned on at the same time. In this case, the sensing operation through the sensing line (VREF) and the data output operation for outputting the data signal are separated (separated) based on the time division system of the data driver.

In addition, the object to be compensated according to the sensing result may be a digital data signal, an analog data signal, gamma, or the like. The compensation circuit for generating the compensation signal (or the compensation voltage) based on the sensing result may be implemented in the interior of the data driver, in the timing controller, or in a separate circuit.

The light blocking layer LS may be disposed only below the channel region of the driving transistor DR or may be disposed not only below the channel region of the driving transistor DR but also below the channel region of the switching transistor SW and the sensing transistor ST. The light blocking layer LS may be used merely for blocking external light, or the light blocking layer LS may be connected to other electrodes or lines and used as an electrode constituting a capacitor or the like. Therefore, the light blocking layer LS is selected as a multi-layered metal layer having a light shielding property.

3, a sub-pixel of a 3T (Capacitor) structure including a switching transistor SW, a driving transistor DR, a capacitor Cst, an organic light emitting diode OLED, and a sensing transistor ST However, if the compensation circuit CC is added, it may be composed of 3T2C, 4T2C, 5T1C, 6T2C, and the like.

As shown in FIG. 4, subpixels are formed on the display area AA of the substrate (or thin film transistor substrate) SUB1 based on the circuit described in FIG. The subpixels formed on the display area AA are sealed by a protective film (or protective substrate) SUB2. NA not otherwise described means non-display area. The substrate SUB1 may be made of glass or a material having ductility.

The subpixels are arranged horizontally or vertically in the order of red (R), white (W), blue (B) and green (G) on the display area AA. The subpixels are red (R), white (W), blue (B), and green (G) However, the arrangement order of the subpixels can be variously changed depending on the light emitting material, the light emitting area, the structure (or structure) of the compensation circuit, and the like. Also, the subpixels may be red (R), blue (B), and green (G) as one pixel (P).

5 is a schematic diagram illustrating a planar layout of subpixels according to the present invention.

4 and 5, a first sub-pixel SPn1 to a fourth sub-pixel SPn4 having a light emitting area EMA and a circuit area DRA are formed on the display area AA of the substrate SUB1, . An organic light emitting diode (light emitting element) is formed in the light emitting region EMA and a circuit including a switching, sensing and driving transistor for driving the organic light emitting diode is formed in the circuit region DRA. The first subpixel SPn1 to the fourth subpixel SPn4 are turned on in response to the operation of switching and driving transistors located in the circuit region DRA so that the organic light emitting diode located in the light emitting region EMA emits light do. WA "positioned between the first subpixel SPn1 to the fourth subpixel SPn4 is a wiring region and includes the power supply line EVDD, the sensing line VREF, the first to fourth data lines DL1- DL4 are disposed. The first and second gate lines GL1 and GL2 are disposed across the first to fourth subpixels SPn1 to SPn4.

The electrodes constituting the thin film transistor as well as the wirings such as the power supply line EVDD, the sensing line VREF and the first to fourth data lines DL1 to DL4 are located on different layers but are connected to each other through the contact holes And are electrically connected due to the contact. The sensing line VREF is connected to each sensing transistor (not shown) of the first to fourth sub-pixels SPn1 to SPn4 through a sensing connection line VREFC. The power supply line EVDD is connected to each driving transistor (not shown) of the first to fourth sub-pixels SPn1 to SPn4 through a power supply connection line EVDDC. The first and second gate lines GL1 and GL2 are connected to respective sensing and switching transistors (not shown) of the first to fourth sub-pixels SPn1 to SPn4.

6 is a diagram showing a plane layout of a subpixel of the present invention.

Referring to FIG. 6, the OLED display of the present invention includes first to fourth sub-pixels GL1 and GL2 intersecting first and second gate lines GL1 and GL2 and first to fourth data lines DL1 to DL4, SPn1 to SPn4) are defined. Specifically, the first to fourth sub-pixels SPn1 to SPn4 connected to the first to fourth data lines DL1 to DL4 are commonly connected to the sensing line VREF. The sensing line VREF is directly connected to the second and third subpixels SPn2 and SPn3 and is connected to the first and fourth subpixels SPn1 and SPn4 through a sensing connection line VREFC. A power supply line EVDD is disposed on both edges of the first to fourth subpixels SPn1 to SPn4 and first and fourth subpixels SPn1 and SPn4 adjacent to the power supply line EVDD are directly connected to each other. 2 and the third sub-pixels SPn2 and SPn3 are connected through a power supply connection line EVDDC.

The first electrode ANO of the organic light emitting diode OLED is disposed in the emission region EMA of each subpixel and the driving transistor DR, the capacitor Cst, and the sensing transistor ST are connected to the circuit region DRA. And a switching transistor SW are disposed. For example, the sensing transistor ST is composed of a gate electrode 240, a drain electrode 250D, a source electrode 250S, and a semiconductor layer 220. [ The sensing line VREF is connected to each sensing transistor ST of the first to fourth sub-pixels SPn1 to SPn4 through a sensing connection line VREFC. The power supply line EVDD is connected to each driving transistor DR of the first to fourth sub-pixels SPn1 to SPn4 through a power supply connection line EVDDC. The first and second gate lines GL1 and GL2 are connected to the respective sensing and switching transistors ST and SW of the first to fourth sub-pixels SPn1 to SPn4.

Each circuit area DRA of the first to fourth subpixels SPn1 to SPn4 may be defined as an area in the vertical direction from the sensing line VREF to the power supply connection line EVDDC, The circuit areas DRA of the pixels SPn1 to SPn4 all have the same area. However, since the area of the capacitor Cst of the first and fourth sub-pixels SPn1 and SPn4 is made larger than the area of the capacitor Cst of the second and third sub-pixels SPn2 and SPn3, The design of the circuits in the circuit area DRA of the three subpixels SPn2 and SPn3 is designed to be relatively easy.

In addition, since the area of the light emitting region EMA of the first and fourth subpixels SPn1 and SPn4 is made smaller than the area of the capacitor Cst of the second and third subpixels SPn2 and SPn3, The first to fourth data lines DL1 to DL4 are formed so as not to be formed as a straight line but to be partially bent so as to enlarge the emission area EMA of the third subpixels SPn2 and SPn3. Therefore, the layout of the subpixels becomes complicated due to the shape of the first to fourth data lines DL1 to DL4.

In the following, a display device capable of easily designing the layout of subpixels by adjusting the size of the light emitting region and the circuit region of the subpixels is disclosed.

<Examples>

8 is a detailed plan view of a subpixel according to an exemplary embodiment of the present invention. FIG. 9 is a cross-sectional view of the subpixel of FIG. 8, Sectional view taken along the perforated line B-B ', and FIG. 10 is a sectional view taken along the perforated line C-C' shown in FIG.

Referring to FIG. 7, first to fourth subpixels SPn1 to SPn4 having light emitting regions E1 to E4 and circuit regions D1 to D4, respectively, are disposed on a substrate SUB1. The organic light emitting diodes are formed in the light emitting regions E1 to E4 and the switching, sensing and driving transistors driving the organic light emitting diodes are formed in the circuit regions D1 to D4. The capacitors C1 to C4 . The first to fourth subpixels SPn1 to SPn4 emit light by the organic light emitting diodes located in the emission regions E1 to E4 corresponding to the operations of switching and driving transistors and the like. The first and second power supply lines EVDD1 and EVDD2, the sensing line VREF and the first to fourth data lines DL1 to DL4 are arranged in the first to fourth subpixels SPn1 to SPn4. do. The first gate line GL1 is arranged across the first subpixel SPn1 to the fourth subpixel SPn4 and the first gate line GL1 is disposed across the light emitting regions E1 to E4 of the first to fourth subpixels SPn1 to SPn4, E4.

The electrodes constituting the thin film transistor as well as the wirings such as the first and second power supply lines EVDD1 to EVDD2, the sensing line VREF and the first to fourth data lines DL1 to DL4 are located on different layers And are electrically connected due to contact through contact holes (not shown). The sensing line VREF is connected to each sensing transistor (not shown) of the first to fourth sub-pixels SPn1 to SPn4. The first power supply line EVDD1 is connected to each driving transistor (not shown) of the first and second subpixels SPn1 and SPn2. And the second power supply line EVDD2 is connected to each driving transistor (not shown) of the third and fourth subpixels SPn3 and SPn4. The first gate line GL1 is connected to each switching transistor (not shown) and a sensing transistor (not shown) of the first to fourth sub-pixels SPn1 to SPn4.

Each of the subpixels SPn1 to SPn4 of the present invention includes light emitting regions E1 to E4 and circuit regions D1 to D4. Specifically, the first sub-pixel SPn1 includes a light emitting region E1 and a circuit region D1, and the circuit region D1 includes a capacitor C1. A first data line DL1 connected to the first subpixel SPn1 is disposed on one side of the first subpixel SPn1 and a first gate line GL1 crossing the first data line DL1 is arranged do. The circuit region D1 of the first subpixel SPn1 is disposed surrounding at least two sides of the light emitting region E1. As shown, the lower side and the right side of the light emitting region E1 are surrounded by the circuit region D1.

The second sub-pixel SPn2 includes a light emitting region E2 and a circuit region D2, and the circuit region D2 includes a capacitor C2. A second data line DL2 connected to the second subpixel SPn2 is disposed on one side of the second subpixel SPn2 and a second data line DL2 intersects the first gate line GL1. The circuit region D2 of the second subpixel SPn2 is disposed surrounding at least two sides of the light emitting region E2. As shown, the lower side and the left side of the light emitting region E2 are surrounded by the circuit region D2.

The capacitor C1 of the first subpixel SPn1 and the capacitor C1 of the second subpixel SPn2 are connected between the light emitting region E1 of the first subpixel SPn1 and the light emitting region E2 of the second subpixel SPn2 A capacitor C2 is disposed. In addition, the first subpixel SPn1 and the second subpixel SPn2 are disposed between the first data line DL1 and the second data line DL2.

The first power supply line EVDD1 is disposed adjacent to the first subpixel SPn1 with the first data line DL1 therebetween. The first power supply line EVDD1 is shared by the first subpixel SPn1 and the second subpixel SPn2, respectively. The sensing line VREF is disposed adjacent to the second subpixel SPn2 with the second data line DL2 therebetween. The sensing line VREF is shared by the first subpixel SPn1 and the second subpixel SPn2, respectively. The first power supply line EVDD1 and the sensing line VREF are disposed adjacent to each other with the first and second subpixels SPn1 and SPn2 interposed therebetween.

And a third subpixel SPn3 and a fourth subpixel SPn4 that are symmetric with respect to the first subpixel SPn1 and the second subpixel SPn2 with respect to the sensing line VREF. The third sub-pixel SPn3 includes a light emitting region E3 and a circuit region D3, and the circuit region D3 includes a capacitor C3. A third data line DL3 connected to the third subpixel SPn3 is disposed on one side of the third subpixel SPn3 and a third data line DL3 intersects the first gate line GL1. The circuit region D3 of the third subpixel SPn3 is disposed so as to surround at least two sides of the light emitting region E3. As shown in the figure, the lower side and the right side of the light emitting region E3 are surrounded by the circuit region D3.

The fourth sub-pixel SPn4 includes a light emitting region E4 and a circuit region D4, and the circuit region D4 includes a capacitor C4. A fourth data line DL4 connected to the fourth subpixel SPn4 is disposed on one side of the fourth subpixel SPn4 and a fourth data line DL4 intersects the first gate line GL1. The circuit region D4 of the fourth subpixel SPn4 is disposed surrounding at least two sides of the light emitting region E4. As shown in the figure, the lower side and the left side of the light emitting region E4 are surrounded by the circuit region D4. The third subpixel SPn3 and the fourth subpixel SPn4 are disposed between the third data line DL3 and the fourth data line DL4.

The second power supply line EVDD2 is disposed adjacent to the fourth subpixel SPn4 with the fourth data line DL4 therebetween. And the second power supply line EVDD2 is shared by the third subpixel SPn3 and the fourth subpixel SPn4, respectively.

In the present invention, in order to form different capacitors required in each sub-pixel, the sub-pixel having a small capacitor has a small circuit area and the sub-pixel having a large capacitor has a large circuit area.

Specifically, the area of the circuit region D1 of the first subpixel SPn1 and the area of the circuit region D2 of the second subpixel SPn2 are different from each other, and the capacitor C1 of the first subpixel SPn1, And the capacitor C2 of the second sub-pixel SPn2 are different from each other. Therefore, the area of the circuit region D2 of the second subpixel SPn2 is made larger than the area of the circuit region D1 of the first subpixel SPn1. To this end, a capacitor C2 of the second sub-pixel SPn2 is formed to surround at least two sides of the capacitor C1 of the first sub-pixel SPn1.

The area of the circuit area D1 of the first subpixel SPn1 and the area of the circuit area D2 of the second subpixel SPn2 are formed differently and the capacitor C2 of the second subpixel SPn2 is formed The first and second subpixels SPn1 and SPn2 may be formed so as to surround at least two sides of the capacitor C1 of the first subpixel SPn1 to control the size of each of the emission regions E1 and E2 of the first and second subpixels SPn1 and SPn2. 1 and the second data lines DL1 and DL2 may be formed in a straight line without being bent. As shown in the figure, the first data line DL1 and the second data line DL2 are formed in a line parallel to each other, and the sizes of the light emitting regions E1 and E2 may be formed differently. Therefore, the size of the capacitor, the circuit region, and the light emitting region can be freely adjusted within the subpixel, and the data lines can also be formed as a straight line, which is advantageous in designing the layout of the subpixels.

The structure of the first subpixel SPn1 will be described with reference to FIG. The first subpixel SPn1 is defined by intersecting the first gate line GL1 and the first data line DL1. The first sub-pixel SPn1 includes a driving transistor DR, a sensing transistor ST, a switching transistor SW, a capacitor Cst, and an organic light emitting diode (not shown).

A first electrode ANO of an organic light emitting diode (not shown) is disposed in the light emitting region E1. A driving transistor DR, a sensing transistor ST, a switching transistor SW, (Cst). For example, the switching transistor SW is composed of a first gate line GL1, a drain electrode 250D, a source electrode 250S, and a semiconductor layer 220. [ The sensing transistor ST also includes a source electrode 240S connected to a sensing connection line VREFC extending from the sensing line VREF, a first gate line GL1 and a semiconductor layer 210. [ The driving transistor DR is composed of a semiconductor layer 230, a gate electrode 260, a drain electrode 270D and a source electrode 270S connected to a power supply connection line EVDDC extending from the first power supply line EVDD . The capacitor Cst is composed of a capacitor lower electrode LCst, a capacitor middle electrode MCst, and a first electrode ANO. The first electrode ANO is connected to the drain electrode 270D of the driving transistor DR through the via hole VIA.

The present invention includes a first branching portion VC1 at one end of a sensing connection line VREFC extending from a sensing line VREF and a second branching portion VC2 at the other end. The first branch VC1 is connected to the first and second subpixels SPn1 and SPn2 and the second branch VC2 is connected to the third and fourth subpixels SPn3 and SPn4. In other words, since the sensing connection lines VREFC are connected to the two subpixels via the branch portions VC1 and VC2 at the respective ends of the sensing connection line VREFC, a plurality of sensing connection lines VREFC need not be formed, Can be easily designed.

Referring to FIG. 9, the display device according to the exemplary embodiment of the present invention includes a light blocking layer LS on a substrate SUB1. The light blocking layer LS functions to prevent external light from entering the thin film transistor, thereby preventing a photocurrent from being generated in the thin film transistor. A buffer layer (BUF) is located on the light blocking layer (LS). The buffer layer BUF protects the thin film transistor formed in a subsequent process from impurities such as alkali ions or the like, which are emitted from the light blocking layer LS. The buffer layer BUF may be silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof.

The semiconductor layer 230 is located on the buffer layer BUF. The semiconductor layer 230 may be formed of a silicon semiconductor or an oxide semiconductor. The silicon semiconductor may include amorphous silicon or crystallized polycrystalline silicon. Here, the polycrystalline silicon has high mobility (100 cm 2 / Vs or more), low energy consumption power and excellent reliability, and can be applied to a gate driver for a driving device and / or a multiplexer (MUX) have. On the other hand, since the oxide semiconductor has low off-current, it is suitable for a switching TFT which has a short ON time and a long OFF time. Further, since the off current is small, the voltage holding period of the pixel is long, which is suitable for a display device requiring low speed driving and / or low power consumption. Further, the semiconductor layer 230 includes a source region and a drain region including a p-type or n-type impurity, and includes a channel therebetween.

A gate insulating film GI is positioned on the semiconductor layer 230. The gate insulating film GI may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof. The gate electrode 260 is located on a gate insulating film GI at a position corresponding to a certain region of the semiconductor layer 230, that is, a channel when impurities are implanted. The gate electrode 260 may be formed of a material selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Any one of them or an alloy thereof. The gate electrode 260 may be formed of one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Or an alloy of any one selected from the above. For example, the gate electrode 260 may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

An interlayer insulating film (ILD) for insulating the gate electrode 260 is located on the gate electrode 260. The interlayer insulating film ILD may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. A source electrode 270S and a drain electrode 270D are located on the interlayer insulating film ILD. The source electrode 270S and the drain electrode 270D are connected to the semiconductor layer 230 through the contact hole exposing the source region of the semiconductor layer 230. [ The source electrode 270S and the drain electrode 270D may be formed of a single layer or a multilayer and the source electrode 270S may be formed of a single layer such as molybdenum (Mo), aluminum (Al), chromium (Cr) (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). When the source electrode 270S and the drain electrode 270D are multilayered, a double layer of molybdenum / aluminum-neodymium, titanium / aluminum / titanium, molybdenum / aluminum / molybdenum or molybdenum / aluminum- neodymium / molybdenum &Lt; / RTI &gt; The driving transistor DR including the semiconductor layer 230, the gate electrode 260, the source electrode 270S, and the drain electrode 270D is constituted.

A passivation film PAS is disposed on the substrate SUB1 including the driving transistor DR. The passivation film PAS may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof as an insulating film for protecting underlying devices. An overcoat layer OC is placed on the passivation film PAS. The overcoat layer OC may be a planarizing film for alleviating the step difference of the lower structure and is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. The overcoat layer OC may be formed by a method such as spin on glass (SOG) in which the organic material is coated in a liquid form and then cured.

A via hole VIA for exposing the drain electrode 270D is located in a part of the overcoat layer OC. An organic light emitting diode (OLED) is located on the overcoat layer (OC). More specifically, the first electrode ANO is located on the overcoat layer OC. The first electrode ANO acts as a pixel electrode and is connected to the drain electrode 270D of the driving transistor DR through the via hole VIA. The first electrode ANO may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). When the first electrode ANO is a reflective electrode, the first electrode ANO further includes a reflective layer. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni) or an alloy thereof, preferably APC (silver / palladium / copper alloy).

A bank layer BNK for partitioning a pixel is disposed on a substrate SUB1 including a first electrode ANO. The bank layer BNK is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. In the bank layer BNK, a pixel defining portion OP for exposing the first electrode ANO is located. An organic film layer (EML) which contacts the first electrode (ANO) is disposed on the entire surface of the flexible substrate (PI). The organic layer EML may include a hole injecting layer or a hole transporting layer between the organic layer EML and the first electrode ANO and may be formed on the organic layer EML. An electron transport layer or an electron injection layer.

A second electrode (CAT) is located on the organic film layer (EML). The second electrode CAT is disposed on the front surface of the display unit A / A and may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag) have. The second electrode (CAT) is a transparent electrode. The second electrode (CAT) is thin enough to transmit light. The second electrode (CAT) is thick enough to reflect light when the electrode is a reflective electrode.

On the other hand, in Fig. 6 described above, the emission regions of the respective subpixels are arranged adjacent to each other in the direction in which the gate lines extend. Therefore, light leakage may occur between adjacent sub-pixels. 7, a capacitor of the first subpixel SPn1 is connected between the emissive region E1 of the first subpixel SPn1 and the emissive region E2 of the second subpixel SPn2, C1 and the capacitor C2 of the second sub-pixel SPn2 are arranged. Accordingly, light leaking sideways between the first subpixel SPn1 and the second subpixel SPn2 is blocked by the capacitor C1 of the first subpixel SPn1 and the capacitor C2 of the second subpixel SPn2 .

10, on the substrate SUB1 of the first and second subpixels SPn1 and SPn2, a capacitor lower electrode LCst, a capacitor center electrode MCst, and a first electrode ANO And a capacitor Cst including a capacitor Cst. A passivation film PAS is disposed on the capacitor center electrode MCst and a red color filter RCF is disposed on the passivation film PAS. An overcoat layer OC is positioned on a red color filter (RCF), and first electrodes (ANO) of each subpixel are disposed on the overcoat layer (OC). Further, a bank layer BNK for partitioning the light emitting region of each subpixel is located.

In FIG. 10, the capacitor C1 of the first sub-pixel SPn1 and the capacitor C2 of the second sub-pixel SPn2, which are wide between the first and second sub-pixels SPn1 and SPn2, The interval between the first and second sub-pixels SPn1 and SPn2 can be significantly widened, and light leakage can be prevented. In addition, as the interval between the first and second subpixels SPn1 and SPn2 becomes wider, the red color filter RCF can have a margin that can be further formed toward the second subpixel SPn2, . As the interval between the first and second subpixels SPn1 and SPn2 becomes wider, the bank layer BNK may have a margin, and the margin of the first electrode ANO of the first subpixel SPn1 It becomes wider. As the margins of the red color filter (RCF), the bank layer (BNK), and the first electrode (ANO) are widened, the design becomes free and the aperture ratio can be improved and the process can be facilitated.

Referring again to FIG. 7, the third subpixel SPn3 and the fourth subpixel SPn4 are arranged in the same manner as the first subpixel SPn1 and the second subpixel SPn2, Can be prevented. A sensing line VREF, a second data line DL2 and a third data line DL3 are arranged between the second subpixel SPn2 and the third subpixel SPn3 to form the second subpixel SPn2, Emitting region E2 of the third sub-pixel SPn3 and the light-emitting region E3 of the third sub-pixel SPn3.

Meanwhile, the present invention may have a subpixel array structure according to another embodiment that facilitates designing the layout of subpixels.

FIG. 11 is a simplified plan view of a subpixel according to another embodiment of the present invention, and FIG. 12 is a detailed plan view of a subpixel according to another embodiment of the present invention. In the following, description of the same components as those of Figs. 7 to 10 described above will be omitted.

Referring to FIG. 11, first subpixels SPn1 through SPn4 having light emitting regions E1 through E4 and circuit regions D1 through D4 are arranged on a substrate SUB1. Sensing and driving transistors for driving the organic light emitting diodes are formed in the circuit regions D1 to D4 and the capacitors C1 to C4 are formed in the light emitting regions E1 to E4 and the organic light emitting diodes .

The first and second power supply lines EVDD1 and EVDD2, the sensing line VREF and the first and second data lines DL1 and DL2 are disposed in the first subpixel SPn1 to the fourth subpixel SPn4. do. The first gate line GL1 and the second gate line GL2 are arranged across the first subpixel SPn1 to the fourth subpixel SPn4 and the first subpixel SPn1 to the fourth subpixel SPn4 Emitting regions E1 to E4 of the light-emitting elements SP1 to SPn4.

The electrodes constituting the thin film transistor as well as the wirings such as the first and second power supply lines EVDD1 to EVDD2, the sensing line VREF and the first and second data lines DL1 and DL2 are located on different layers And are electrically connected due to contact through contact holes (not shown). The sensing line VREF is connected to each sensing transistor ST of the first to fourth sub-pixels SPn1 to SPn4. The first power supply line EVDD1 is connected to each driving transistor DR of the first and second subpixels SPn1 and SPn2. And the second power supply line EVDD2 is connected to each driving transistor DR of the third and fourth subpixels SPn3 and SPn4. The first gate line GL1 is connected to the switching transistor SW of the first and fourth subpixels SPn1 and SPn4 and the second gate line GL2 is connected to the second and third subpixels SPn2 and SPn3. Of the sensing transistor ST. The first data line DL1 is shared and connected to the switching transistors SW of the first and second subpixels SPn1 and SPn2 and the second data line DL2 is connected to the third and fourth subpixels SPn3, And is connected to the switching transistor SW of the transistor SPn4. The shared structure of this data line is a DRD (Double Rate Driving) structure.

Each of the subpixels SPn1 to SPn4 of the present invention includes light emitting regions E1 to E4 and circuit regions D1 to D4. Specifically, the first sub-pixel SPn1 includes a light emitting region E1 and a circuit region D1, and the circuit region D1 includes a capacitor C1. A first data line DL1 connected to the first subpixel SPn1 is disposed on one side of the first subpixel SPn1 and a first gate line GL1 crossing the first data line DL1 is arranged do. The second sub-pixel SPn2 includes a light emitting region E2 and a circuit region D2, and the circuit region D2 includes a capacitor C2. The first data line DL1 connected to the second subpixel SPn2 is disposed on one side of the second subpixel SPn2 and the first data line DL1 is connected to the first and second gate lines GL1 and GL2 ).

The first subpixel SPn1 and the second subpixel SPn2 are disposed between the first data line DL1 and the sensing line VREF. The circuit region D1 of the first subpixel SPn1 is disposed between the first data line DL1 and the light emitting region E1 of the first subpixel SPn1 and the circuit region D1 of the second subpixel SPn2 The second data line D2 is disposed between the first data line DL1 and the light emitting region E2 of the second subpixel SPn2.

The first power supply line EVDD1 is disposed adjacent to the first and second subpixels SPn1 and SPn2 with the first data line DL1 therebetween. The first power supply line EVDD1 is shared by the first subpixel SPn1 and the second subpixel SPn2, respectively. The sensing line VREF is connected to the circuit region D1 of the first subpixel SPn1 with the light emitting region E1 of the first subpixel SPn1 and the light emitting region E2 of the second subpixel SPn2 interposed therebetween, And the circuit region D2 of the second sub-pixel SPn2. The sensing line VREF is shared by the first subpixel SPn1 and the second subpixel SPn2, respectively. The first power supply line EVDD1 and the sensing line VREF are disposed adjacent to each other with the first and second subpixels SPn1 and SPn2 interposed therebetween.

And a third subpixel SPn3 and a fourth subpixel SPn4 that are symmetric with respect to the first subpixel SPn1 and the second subpixel SPn2 with respect to the sensing line VREF. The third sub-pixel SPn3 includes a light emitting region E3 and a circuit region D3, and the circuit region D3 includes a capacitor C3. A second data line DL2 connected to the third subpixel SPn3 is disposed on one side of the third subpixel SPn3 and a second data line DL2 intersects the first gate line GL1. The fourth sub-pixel SPn4 includes a light emitting region E4 and a circuit region D4, and the circuit region D4 includes a capacitor C4. A second data line DL2 connected to the fourth subpixel SPn4 is disposed on one side of the fourth subpixel SPn4. The third subpixel SPn3 and the fourth subpixel SPn4 are disposed between the second data line DL2 and the sensing line VREF.

The second power supply line EVDD2 is disposed adjacent to the third subpixel SPn3 and the fourth subpixel SPn4 with the second data line DL2 therebetween. And the second power supply line EVDD2 is shared by the third subpixel SPn3 and the fourth subpixel SPn4, respectively.

In the present invention, in order to form different capacitors required in each sub-pixel, the sub-pixel having a small capacitor has a small circuit area and the sub-pixel having a large capacitor has a large circuit area.

Specifically, the area of the circuit region D1 of the first subpixel SPn1 and the area of the circuit region D2 of the second subpixel SPn2 are different from each other, and the capacitor C1 of the first subpixel SPn1, And the capacitor C2 of the second sub-pixel SPn2 are different from each other. Therefore, the area of the circuit region D2 of the second subpixel SPn2 is made larger than the area of the circuit region D1 of the first subpixel SPn1. To this end, a capacitor C2 of the second sub-pixel SPn2 is formed to surround at least two sides of the capacitor C1 of the first sub-pixel SPn1.

The area of the circuit area D1 of the first subpixel SPn1 and the area of the circuit area D2 of the second subpixel SPn2 are formed differently and the capacitor C2 of the second subpixel SPn2 is formed The first and second subpixels SPn1 and SPn2 may be formed so as to surround at least two sides of the capacitor C1 of the first subpixel SPn1 to control the size of each of the emission regions E1 and E2 of the first and second subpixels SPn1 and SPn2. 1 and the second data line DL1 may be formed in a straight line without being bent. As shown, the first data line DL1 is formed as a straight line, and the sizes of the light emitting regions E1 and E2 may be formed differently. Therefore, the size of the capacitor, the circuit region, and the light emitting region can be freely adjusted within the subpixel, and the data lines can also be formed as a straight line, which is advantageous in designing the layout of the subpixels.

On the other hand, the structure of the first subpixel SPn1 will be described with reference to FIG. 12, with reference to FIG. The first subpixel SPn1 is defined by intersecting the first gate line GL1 and the first data line DL1. The first sub-pixel SPn1 includes a driving transistor DR, a sensing transistor ST, a switching transistor SW, a capacitor Cst, and an organic light emitting diode (not shown).

A first electrode ANO of an organic light emitting diode (not shown) is disposed in the light emitting region E1. A driving transistor DR, a sensing transistor ST, a switching transistor SW, (Cst). For example, the switching transistor SW is composed of a first gate line GL1, a drain electrode 250D, a source electrode 250S, and a semiconductor layer 220. [ The sensing transistor ST also includes a source electrode 240S connected to a sensing connection line VREFC extending from the sensing line VREF, a first gate line GL1 and a semiconductor layer 210. [ The driving transistor DR is composed of a semiconductor layer 230, a gate electrode 260, a drain electrode 270D and a source electrode 270S connected to a power supply connection line EVDDC extending from the first power supply line EVDD . The capacitor Cst is composed of a capacitor lower electrode LCst, a capacitor middle electrode MCst, and a first electrode ANO. The first electrode ANO is connected to the drain electrode 270D of the driving transistor DR through the via hole VIA.

The present invention includes a first branching portion VC1 at one end of a sensing connection line VREFC extending from a sensing line VREF and a second branching portion VC2 at the other end. The first branch VC1 is connected to the first and second subpixels SPn1 and SPn2. The second subpixel SPn2 is a subpixel neighboring the first subpixel SPn1 with the first gate line GL1 therebetween. And the second branch VC2 is connected to the third and fourth subpixels SPn3 and SPn4. The third subpixel SPn3 is a subpixel neighboring the fourth subpixel SPn4 with the first gate line GL1 therebetween. Since the sensing connection lines VREFC are connected to two subpixels via the branch portions VC1 and VC2 at the respective ends of the sensing connection line VREFC, a plurality of sensing connection lines VREFC need not be formed, .

As described above, the display device according to the embodiments of the present invention forms the capacitor of the second sub-pixel so as to surround at least two sides of the capacitor of the first sub-pixel, At least one data line may be formed in a straight line without having to be bent in order to adjust the size of the data line. Therefore, the size of the capacitor, the circuit region, and the light emitting region can be freely adjusted within the subpixel, and the data lines can also be formed as a straight line, which is advantageous in designing the layout of the subpixels.

In addition, the display device according to the embodiments of the present invention can prevent the light leakage between adjacent sub-pixels from being generated by forming the capacitors between the light emitting regions of the adjacent sub-pixels.

Further, the display device according to the embodiments of the present invention can arrange the capacitors between the light emitting regions of each sub-pixel so that the color filter, the bank layer, and the first electrode can have margins that can be further formed on the capacitors, There is an advantage that it is easy.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

GL1 to GL2: first and second gate lines DL1 to DL4: first to fourth data lines
VREF: sensing lines EVDD1 to EVDD2: first and second power lines
SPn1 to SPn4: First to fourth sub-pixels E1 to E4:
C1 to C4: Capacitors D1 to D4: Circuit area

Claims (14)

And at least first and second sub-pixels located on the substrate,
The first and second subpixels each include a light emitting region including an organic light emitting diode and a circuit region including a plurality of thin film transistors and a capacitor,
And the capacitor of the second subpixel surrounds at least two sides of the capacitor of the first subpixel. The method according to claim 1,
And the area of the circuit area of the first sub pixel and the area of the circuit area of the second sub pixel are different from each other. 3. The method of claim 2,
And the area of the circuit region of the second subpixel is larger than the area of the circuit region of the first subpixel. The method of claim 3,
And a first power supply line and a sensing line neighboring each other with the first subpixel and the second subpixel interposed therebetween,
Wherein the first power supply line and the sensing line are shared by the first subpixel and the second subpixel, respectively. 5. The method of claim 4,
A third subpixel and a fourth subpixel symmetrical to the first subpixel and the second subpixel with respect to the sensing line, the sensing line being shared by the third subpixel and the fourth subpixel, / RTI &gt; 6. The method of claim 5,
And a second power supply line adjacent to the sensing line with the third subpixel and the fourth subpixel interposed therebetween, and the second power supply line includes a display shared by the third subpixel and the fourth subpixel Device. The method according to claim 6,
And a capacitor of the first sub pixel and a capacitor of the second sub pixel are disposed between the light emitting area of the first sub pixel and the light emitting area of the second sub pixel. 8. The method of claim 7,
A first data line connected to the first sub-pixel and a second data line connected to the second sub-pixel,
And the first subpixel and the second subpixel are disposed between the first data line and the second data line. 9. The method of claim 8,
A third data line coupled to the third subpixel and a fourth data line coupled to the fourth subpixel,
And the third subpixel and the fourth subpixel are disposed between the third data line and the fourth data line. The method according to claim 6,
Wherein the first sub-pixel and the second sub-pixel are disposed between the first data line and the sensing line, wherein the first sub-pixel and the second sub-pixel share a first data line, . 11. The method of claim 10,
Wherein the third subpixel and the fourth subpixel are disposed between the second data line and the sensing line, wherein the third subpixel and the fourth subpixel are shared by the first subpixel and the fourth subpixel, . 12. The method of claim 11,
A circuit region of the first subpixel is disposed between the first data line and a light emitting region of the first subpixel, and a circuit region of the second subpixel is disposed between the light emitting region of the first data line and the second subpixel Wherein the circuit region is disposed. 13. The method of claim 12,
Each of the emission regions of the first to fourth subpixels is disposed adjacent to the sensing line, the emission regions of the first subpixel and the second subpixel are disposed on one side of the sensing line, And the emission region of the fourth sub-pixel is disposed on the other side of the sensing line. The method according to claim 9 or 13,
The sensing line may further include a sensing connection line extending to the first to fourth sub-pixels,
Wherein the sensing connection line includes a first branch portion connected to the first and second subpixels at one end and a second branch portion connected to the third and fourth subpixels at the other end.

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