KR20180024314A - Display Device - Google Patents

Abstract

Provided is a display device which can prevent a decrease in an aperture ratio inside a limited space of a subpixel, and can prevent a short circuit between wires. According to an embodiment of the present invention, the display device comprises: a substrate; at least four subpixels arranged in a first row and at least four subpixels arranged in a second row on the substrate; and a power line vertically crossing the subpixels of the first and second rows to divide them into halves, including a power branch unit positioned between the first and second rows, and extended from the power branch unit so as to be connected to the at least four subpixels arranged in the first row and the at least four subpixels arranged in the second row.

Description

[0001]

The present invention relates to a display device.

2. Description of the Related Art In recent years, various flat panel display devices capable of reducing weight and volume, which are disadvantages of CRT (Cathode Ray Tube), have been developed. Examples of such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting display (OLED) Organic Light Emitting Diode Display). Among them, the organic light emitting display (OLED) is a self-emission type display device which excites an organic compound to emit light, and it does not require a backlight used in an LCD, . In addition, it can be manufactured at low temperature, has a response speed of 1ms or less, has a high response speed, exhibits characteristics such as low power consumption, wide viewing angle, and high contrast.

The organic light emitting diode display includes a light emitting layer made of an organic material between a first electrode, which is an anode, and a second electrode, which is a cathode, and holes injected from the first electrode and electrons received from the second electrode are combined in the light emitting layer to form a hole- An exciton is formed, and then the exciton emits light by energy generated when the exciton returns to the ground state. The organic light emitting display can be divided into a back light emitting type and a front light emitting type according to the direction in which light is emitted. In the bottom emission type, light is emitted in the lower direction of the substrate, that is, in the direction from the light emitting layer toward the first electrode, and in the top emission type, light is emitted from the upper direction of the substrate, that is, from the light emitting layer toward the second electrode.

A smaller pixel size is required as the display device gradually becomes higher resolution. When the distance between the subpixels is short, color mixing occurs between adjacent subpixels, and a light leakage phenomenon occurs in which light of adjacent subpixels leaks out. In addition, there is a limitation in the layout in which a circuit must be formed within a limited space of subpixels, so that there is a problem that the aperture ratio is reduced and an overlapping area is increased between wirings, resulting in a short circuit between wirings.

The present invention provides a display device capable of preventing an aperture ratio decrease within a limited space of a subpixel and preventing a short circuit between wirings.

In order to achieve the above object, a display device according to an embodiment of the present invention includes a substrate, at least four subpixels arranged in a first row on the substrate, at least four subpixels arranged in a second row, And a power line crossing in the vertical direction to divide the sub-pixels of the first row and the sub-pixels of the second row. The power supply line includes a power supply branch located between the first row and the second row, the power supply line comprising at least four subpixels extending from the power branch and arranged in the first row and at least four subpixels arranged in the second row, Pixels, respectively.

The sensing line further comprises a sensing line crossing in a vertical direction to divide at least four subpixels arranged in a third row and subpixels in a second row and a third row and the sensing line is arranged between the second row and the third row And the sensing line is connected to at least four sub-pixels extending from the sensing branch and arranged in the second row and at least four sub-pixels arranged in the third row, respectively.

The power supply line includes a vertical power supply line arranged in the vertical direction and a horizontal power supply line connected to the vertical power supply line and horizontally crossing the vertical power supply line.

The horizontal power supply line includes first and second horizontal power supply lines directly branched from the vertical power supply line and includes a third horizontal power supply line connected to the vertical power supply line and the power supply contact hole.

The third horizontal power supply line is disposed on a different layer from the vertical power supply line.

Pixels of the first row adjacent to the vertical power supply line are connected to both ends of the first horizontal power supply line and subpixels of the second row adjacent to the vertical power supply line are connected to both ends of the second horizontal power supply line, One end of the horizontal power supply line is branched to two or more, at least one of which is connected to the subpixel of the first row, the other is connected to the subpixel of the second row, and the other end of the third horizontal power supply line is branched to two or more So that at least one is connected to the sub-pixels of the first row and the other is connected to the sub-pixels of the second row.

The sensing line includes a vertical sensing line arranged in the vertical direction and a horizontal sensing line connected to the vertical sensing line and crossing the vertical sensing line in the horizontal direction.

The horizontal sensing line includes first and second horizontal sensing lines directly branched from the vertical sensing line and includes a third horizontal sensing line connected to the vertical sensing line and the power contact hole.

The third horizontal sensing line is disposed on a different layer from the vertical sensing line.

Pixels of the second row adjacent to the vertical sensing line are connected to both ends of the first horizontal sensing line and subpixels of the third row adjacent to the vertical power supply line are connected to both ends of the second horizontal sensing line, One end of the horizontal sensing line is branched to two or more, at least one of which is connected to the sub-pixels of the second row, the other is connected to the sub-pixels of the third row, and the other end of the third horizontal sensing line is branched to two or more So that at least one is connected to the subpixel of the second row and the other is connected to the subpixel of the third row.

A plurality of data lines arranged in a direction parallel to the power supply lines and disposed adjacent to the subpixels, and first and second gate lines arranged in a direction perpendicular to the power supply lines and intersecting the plurality of data lines and the power supply lines, .

In one of the subpixels, a switching transistor is disposed in an area where the data line and the first gate line intersect, a sensing transistor is disposed in an area where the data line and the second gate line cross each other, And a first electrode connected to the driving transistor.

Each sub-pixel includes an opening through which light is emitted, and capacitors are disposed between the openings of each sub-pixel.

The present invention reduces the number of intersections where the sensing line, the data line, and the power line and the data line cross each other, thereby significantly reducing the probability of short-circuiting between the sensing line and the data line and between the power line and the data line, There is an advantage.

Further, the present invention has an advantage in that the capacitor is disposed between the openings of the subpixels, thereby increasing the distance between the openings of the subpixels, thereby preventing the light of adjacent subpixels from being mixed.

1 is a schematic block diagram of an organic light emitting diode display according to an embodiment of the present invention;
2 is a schematic circuit configuration diagram of a subpixel.
3 is a diagram illustrating a first circuit configuration example of a subpixel according to an embodiment of the present invention;
4 is a diagram illustrating a second circuit configuration example of a subpixel according to an embodiment of the present invention;
5 is a plan view schematically illustrating a subpixel array according to an embodiment of the present invention.
6 is a plan view of a subpixel array of region A of FIG. 5;
FIG. 7 is a plan view showing a subpixel array of a region B in FIG. 5; FIG.
8 is a cross-sectional view taken along the percutaneous line I-I 'of Fig. 6;
9 is a cross-sectional view taken along the perforated line II-II 'of FIG. 6;
10 is a plan view schematically showing a subpixel array of a display device according to a comparative example.
11 is a plan view showing a subpixel array of the C region of FIG. 10;
12 is a plan view schematically showing a subpixel array of a display device according to a comparative example.
13 is a plan view schematically showing a subpixel array of a display device according to an embodiment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

The display device according to the present invention may be an organic light emitting display, a liquid crystal display, an electrophoretic display, or the like. The organic light emitting display includes a light emitting layer made of an organic material between a first electrode, which is an anode, and a second electrode, which is a cathode. Therefore, the holes supplied from the first electrode and the electrons supplied from the second electrode are combined in the light emitting layer to form excitons as a hole-electron pair, and the excitons emit light due to energy generated when the excitons return to the ground state Emitting display device. The OLED display according to the present invention may be a plastic display device having a display device formed on a flexible plastic substrate in addition to a glass substrate.

FIG. 1 is a schematic block diagram of an organic light emitting display according to an embodiment of the present invention, FIG. 2 is a schematic circuit configuration diagram of a subpixel, FIG. 3 is a circuit diagram of a first circuit of a subpixel FIG. 4 is a diagram illustrating a second circuit configuration of a subpixel according to an embodiment of the present invention. Referring to FIG.

1, the OLED display includes an image processor 110, a timing controller 120, a data driver 130, a scan driver 140, and a display panel 150, .

The image processing unit 110 outputs a data enable signal DE together with a data signal DATA supplied from the outside. The image processing unit 110 may output at least one of a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of explanation.

The timing controller 120 receives a data signal DATA from a video processor 110 in addition to a data enable signal DE or a driving signal including a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal. The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130, .

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120 and converts the sampled data signal into a gamma reference voltage . The data driver 130 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an IC (Integrated Circuit).

The scan driver 140 outputs a scan signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 140 outputs a scan signal through the scan lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or a gate-in-panel (GATE) panel in the display panel 150.

The display panel 150 displays an image corresponding to the data signal DATA and the scan signal supplied from the data driver 130 and the scan driver 140. The display panel 150 includes sub-pixels SP that operate to display an image.

The subpixels are formed in a top emission mode, a bottom emission mode, or a dual emission mode depending on the structure. The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel or a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP may have one or more different emission areas depending on the emission characteristics.

As shown in FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED.

The switching transistor SW is operated so that a data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst in response to a scan signal supplied through the first scan line GL1. The driving transistor DR operates so that a driving current flows between the high potential power supply line EVDD and the low potential power supply line EVSS in accordance with the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light in accordance with the driving current generated by the driving transistor DR.

The compensation circuit CC is a circuit added in the sub-pixel to compensate the threshold voltage of the driving transistor DR and the like. The compensation circuit CC is composed of one or more transistors. The configuration of the compensation circuit (CC) varies greatly according to the compensation method. An example of the compensation circuit (CC) is as follows.

As shown in Figs. 3 and 4, the compensation circuit CC includes a sensing transistor ST and a sensing line VREF. The sensing transistor ST is connected between a source line of the driving transistor DR and an anode electrode (first electrode) of the organic light emitting diode OLED (hereinafter referred to as a sensing node). The sensing transistor ST operates to supply the initialization voltage (or sensing voltage) transmitted through the sensing line VREF to the sensing node or to sense the voltage or current of the sensing node.

The switching transistor SW has a source electrode connected to the first data line DL1 and a drain electrode connected to the gate electrode of the driving transistor DR. The source electrode of the driving transistor DR is connected to the high potential power supply line EVDD and the drain electrode of the driving transistor DR is connected to the anode electrode of the organic light emitting diode OLED. In the capacitor Cst, the lower electrode is connected to the gate electrode of the driving transistor DR, and the upper electrode is connected to the anode electrode of the organic light emitting diode OLED. In the organic light emitting diode OLED, the anode electrode is connected to the drain electrode of the driving transistor DR, and the cathode electrode is connected to the second power supply line EVSS. In the sensing transistor ST, a source electrode is connected to the sensing line VREF, and a drain electrode is connected to the anode electrode of the organic light emitting diode OLED, which is a sensing node.

The operation time of the sensing transistor ST may be similar to or different from the switching transistor SW according to the compensation algorithm (or the configuration of the compensation circuit). For example, the gate electrode of the switching transistor SW may be connected to the first scan line GL1a, and the gate electrode of the sensing transistor ST may be coupled to the first scan line GL1b. As another example, the first scan line GL1a connected to the gate electrode of the switching transistor ST and the first b scan line GL1b connected to the gate electrode of the sensing transistor ST may be connected in common.

The sensing line VREF may be connected to the data driver. In this case, the data driver can sense the sensing node of the subpixel during the non-display period of the real time image, or the N frame (N is an integer of 1 or more) and generate the sensing result. On the other hand, the switching transistor SW and the sensing transistor ST can be turned on at the same time. In this case, the sensing operation through the sensing line (VREF) and the data output operation for outputting the data signal are separated (separated) based on the time division system of the data driver.

In addition, the object to be compensated according to the sensing result may be a digital data signal, an analog data signal, gamma, or the like. The compensation circuit for generating the compensation signal (or the compensation voltage) based on the sensing result may be implemented in the interior of the data driver, in the timing controller, or in a separate circuit.

3 and 4 illustrate the structure of a 3T (Capacitor) transistor structure including a switching transistor SW, a driving transistor DR, a capacitor Cst, an organic light emitting diode OLED, and a sensing transistor ST Subpixel has been described as an example, but it may also be composed of 3T2C, 4T2C, 5T1C, 6T2C, etc. when a compensation circuit CC is added.

On the other hand, when the circuit of the subpixel of FIG. 3 is compared with the circuit of the subpixel of FIG. 4, the configuration of the light blocking layer (LS) differs between the two circuits. The light blocking layer (LS) exists for blocking external light. When the light blocking layer LS is formed of a metallic material, a problem of charging the parasitic voltage is caused. Therefore, the light blocking layer LS is connected to the source electrode of the driving transistor DR.

More specifically, the light blocking layer LS may be disposed only under the channel region of the driving transistor DR, as shown in FIG. 3. Alternatively, the light blocking layer LS may be formed not only under the channel region of the driving transistor DR, And may be disposed under the channel region of the transistor SW and the sensing transistor ST.

The light blocking layer LS may be used merely for blocking external light (FIG. 3), or may be used as an electrode constituting a capacitor or the like by connecting the light blocking layer LS to another electrode or line.

Hereinafter, the structure of a specific subpixel array of the above-described display device will be described.

<Examples>

FIG. 5 is a plan view schematically illustrating a subpixel array according to an embodiment of the present invention, FIG. 6 is a plan view showing a subpixel array of the A region of FIG. 5, and FIG. 7 is a view showing a subpixel array of the B region of FIG. FIG. 8 is a sectional view taken along the cutting line I-I 'of FIG. 6, and FIG. 9 is a sectional view taken along the cutting line II-II' of FIG.

Referring to Figure 5, a subpixel array according to an embodiment of the present invention includes at least four subpixels arranged in a first row (n-1) on a substrate and at least four subpixels arranged in a second row (n) Subpixels and at least four subpixels arranged in the third row are arranged. For example, in the first row (n-1), the red subpixel R1, the white subpixel W1, the blue subpixel B1, and the green subpixel G1 constitute the first unit pixel SP1 And the red subpixel R2, the white subpixel W2, the blue subpixel B2 and the green subpixel G2 in the horizontal direction of the first unit pixel SP1 form the second unit pixel SP2 Respectively. The red subpixel R3, the white subpixel W3, the blue subpixel B3 and the green subpixel G3 constitute the third unit pixel SP3 in the second row n, The red subpixel R4, the white subpixel W4, the blue subpixel B4 and the green subpixel G4 constitute the fourth unit pixel SP4 in the horizontal direction of the pixel SP3. The red subpixel R5, the white subpixel W5, the blue subpixel B5 and the green subpixel G5 constitute the fifth unit pixel SP5 in the third row (n + 1) The red subpixel R6, the white subpixel W6, the blue subpixel B6 and the green subpixel G6 constitute the sixth unit pixel SP6 in the horizontal direction of the five unit pixel SP5 .

A sensing line for applying a sensing voltage to the sensing transistor of each sub-pixel is connected to the sub-pixels, and a common line for applying a common power to the driving transistor is connected to the sub-pixels. Although not shown, a data line for applying a data voltage to the switching transistor of each sub-pixel is connected to a gate line for applying a scan voltage. In the present invention, eight subpixels arranged in the direction perpendicular to the sensing line are connected to one sensing line, and eight subpixels arranged in the direction perpendicular to the common line are connected to one common line . This structure is for reducing the area where the sensing lines and the branch lines branched from the common line to each sub-pixel are arranged in the horizontal direction to intersect with the data lines.

For example, in the subpixel array in which the first to third power supply lines EVDD1 to EVDD3 and the first and second sensing lines VREF1 to VREF2 are arranged, the blue subpixel B1 of the first unit pixel SP1 The red subpixel R2 and the white subpixel W2 of the second unit pixel SP2 and the blue subpixel B3 and the green subpixel B3 of the third unit pixel SP3, And the red subpixel R4 and the white subpixel W4 of the fourth unit pixel SP4 are connected to the power supply branch VPP1 of the second power supply line EVDD2. That is, eight subpixels are connected to one branch portion of the power supply line. The red subpixel R3 of the third unit pixel SP3, the white subpixel W3, the blue subpixel B3 and the green subpixel G3, and the red subpixel G3 of the fifth unit pixel SP5, The red subpixel R5, the white subpixel W5, the blue subpixel B5 and the green subpixel G5 are connected to the sensing branch SPP1 of the first sensing line VREF1. That is, eight subpixels are connected to one branch of the sensing line.

The power supply branching part VPP1 of the second power supply line EVDD2 is disposed between the first row n-1 and the second row n but the sensing branching part of the first or second sensing line VREF1-2, (SPP1) is not disposed. The power supply branch VPP2 of the second power supply line EVDD2 is not disposed between the second row n and the third row n + 1, but the first or second sensing line VREF1-2, The sensing branching unit SPP1 is disposed. That is, in the present invention, a branch portion of the power supply line and a branch portion of the sensing line are alternately arranged between the rows of subpixels.

Hereinafter, the area A in FIG. 5 will be described in detail with reference to FIG. In the following description, the reference numerals and names of the respective subpixels of the first through fifth unit pixels are different. For example, the red subpixel R3 of the third unit pixel SP3 is referred to as a first subpixel SPn1. In addition, the structure of each subpixel will be specifically described as a representative of the first subpixel.

Referring to FIG. 6, the first to fourth sub-pixels SPn1 to SPn4 are arranged in the horizontal direction. For example, the first subpixel SPn1 is a red subpixel, the second subpixel SPn2 is a white subpixel, the third subpixel SPn3 is a blue subpixel, and the fourth subpixel SPn4 is a green May be selected as sub-pixels. In the present invention, the first to fourth sub-pixels SPn1 to SPn4 may be a unit pixel.

A first power supply line (EVDD1) is arranged on the left side of the first subpixel (SPn1) along the vertical direction. The first power supply line EVDD1 is commonly connected to the first subpixel SPn1 and the second subpixel SPn2. The first power supply line EVDD1 is directly connected to the first subpixel SPn1 by being branched from the first power supply line EVDD1 and connected to the first power supply line EVDD1 through the first power supply contact hole VCH1. And is connected to the second sub-pixel SPn2 through the three horizontal power supply lines EVDDS3. Although not shown, the first power supply line EVDD1 is commonly connected to two subpixels disposed on the left side of the first power supply line EVDD1 and four subpixels located on the top. The connection structure of the power supply line and the sub-pixel will be described later with reference to FIG.

A first data line DLn1 arranged in parallel with the first power line EVDD1 of the first subpixel SPn1 and a second data line DLn2 adjacent to the first data line DLn1 of the second subpixel SPn2 DLn2. The first data line DLn1 is connected to the first subpixel SPn1 and the second data line DLn2 is connected to the second subpixel SPn2.

 The third data line DLn3 is disposed in a region farther from the second subpixel SPn2 of the third subpixel SPn3 and the fourth data line DLn3 adjacent to the third subpixel SPn3 of the fourth subpixel SPn4, And the line DLn4 is disposed. The third data line DLn3 is connected to the third subpixel SPn3 and the fourth data line DLn4 is connected to the fourth subpixel SPn4. On the right side of the fourth sub-pixel SPn4, the second power source line EVDD2 is arranged along the vertical direction. The second power supply line EVDD2 is commonly connected to the third subpixel SPn3 and the fourth subpixel SPn4.

The first scan line GL1a and the second scan line GL1b which are perpendicular to the first power source line EVDD1 are disposed in the first subpixel SPn1 to the fourth subpixel SPn4. The first scan line GL1a is arranged on the upper side of the first to fourth subpixels SPn1 to SPn4 and the second scan line GL1b is arranged on the lower side of the first to fourth subpixels SPn1 to SPn4 do. The first scan line GL1a is connected to the gate electrode of the switching transistor SW of each of the first to fourth sub-pixels SPn1 to SPn4. The second scan line GL1b is connected to the sensing transistor ST of each of the first to fourth sub-pixels SPn1 to SPn4.

The switching transistor SW of each of the first to fourth sub-pixels SPn1 to SPn4 is connected to the driving transistor DR of each of the first to fourth sub-pixels SPn1 to SPn4, The sensing transistors ST of the first to fourth sub-pixels SPn1 to SPn4 are also connected to the driving transistors DR of the first to fourth sub-pixels SPn1 to SPn4. The pixel electrodes PXL are connected to the driving transistors DR of the first to fourth sub-pixels SPn1 to SPn4.

The fifth unit pixel SPn1 is formed below the first to fourth subpixels SPn1 to SPn4 and is symmetrical with respect to an arbitrary line in a direction parallel to the second gate line GL1b under the second gate line GL1b. Fifth to eighth subpixels SPn5 to SPn8 of the second subpixel SP5 are arranged. The fifth to eighth subpixels SPn5 to SPn8 of the fifth unit pixel SP5 have the same structure as that of the first to fourth subpixels SPn1 to SPn4 described above and will not be described here.

On the other hand, between the second subpixel SPn2 and the third subpixel SPn3 of the third unit pixel SP3, the sixth subpixel SPn6 and the seventh subpixel SPn7 of the fifth unit pixel SP5, A first sensing line VREF1 is disposed. The first sensing line VREF1 is connected to the first to fourth subpixels SPn1 to SPn4 of the third unit pixel SP3 and the fifth to eighth subpixels SPn5 to SPn8 of the fifth unit pixel SP5 Respectively.

The first sensing line VREF1 includes a vertical sensing line VREFM arranged along the vertical direction and first through third horizontal sensing lines VREFS1 through VREFS3 arranged along the horizontal direction. The vertical sensing line VREFM vertically crosses the first to third horizontal sensing lines VREFS1 to VREFS3. Here, the first and second horizontal sensing lines VREFS1 and VREFS2 are directly branched from the vertical sensing line VREFM, and the third horizontal sensing line VREFS3 is connected to the first sensing contact hole SCH1 And connected to a vertical sensing line (VREFM). The vertical sensing line VREFM is arranged in parallel to the first power source line EVDD1 and the first to third horizontal sensing lines VREFS1 to VREFS3 are arranged in parallel with the first and second scan lines GL1a and GL1b .

One end of the first horizontal sensing line VREFS1 is connected to the sensing transistor of the second sub pixel SPn2 and the other end of the first horizontal sensing line VREFS1 is connected to the sensing transistor of the third sub pixel SPn3. One end of the second horizontal sensing line VREFS2 is connected to the sensing transistor of the sixth sub pixel SPn6 and the other end of the second horizontal sensing line VREFS2 is connected to the sensing transistor of the seventh sub pixel SPn7 do.

One end of the third horizontal sensing line VREFS3 branches to the third horizontal sensing line 1VREFS3 and the third horizontal sensing line 2VREFS3 and the other end of the third horizontal sensing line VREFS3 branches to the third horizontal sensing line 3 Line 3VREFS3 and the third horizontal sensing line 4VREFS3. Here, the third horizontal sensing line (1VREFS3) is connected to the sensing transistor of the first subpixel (SPn1), and the third horizontal sensing line (2VREFS3) is connected to the sensing transistor of the fifth subpixel (SPn5). The third horizontal sensing line 3VREFS3 is connected to the sensing transistor of the fourth subpixel SPn4 and the third horizontal sensing line 4VREFS3 is connected to the sensing transistor of the eighth subpixel SPn8. Accordingly, the first sensing line VREF1 may be connected to all of the first through eighth subpixels SPn1 through SPn8 through the first through third horizontal sensing lines VREFS1 through VREFS3 in one sensing branch SPP1. have.

A switching transistor SW is disposed in a region where the first data line DLn1 and the first scan line GL1a cross each other and a third transistor The sensing transistor ST is arranged in a region where the horizontal sensing line 1VREFS3 and the second scan line GL1b are adjacent to each other.

The capacitor lower electrode LCst extending from the switching transistor SW and the capacitor upper electrode UCst extending from the first power source line EVDD1 constitute a capacitor Cst. A driving transistor DR is disposed between the first power supply line EVDD1 and the switching transistor SW and a first electrode ANO connected to the driving transistor DR through the via hole VIA is disposed. 1 sub-pixel SPn1. Although not shown, a bank layer on the first electrode ANO defines an opening OP on which the light emitting layer and the second electrode are located.

In the present invention, the capacitor Cst of each sub-pixel is disposed between the openings OP of the sub-pixels. For example, a capacitor of the second subpixel SPn2 is disposed between the opening OP of the first subpixel SPn1 and the opening of the second subpixel SPn2. Thereby, the distance between the openings of each sub-pixel can be increased to prevent the light of adjacent sub-pixels from being mixed.

On the other hand, the description will be continued with reference to Fig. 7, which specifically shows area B in Fig. In the following description, the reference numerals and names of the respective subpixels of the first through fifth unit pixels are described in the same manner as in FIG. For example, the red subpixel R4 of the fourth unit pixel SP4 is referred to as a ninth subpixel SPn9. Since the structure of each sub-pixel has been described above, the description is omitted.

Referring to FIG. 7, the third, fourth, ninth, and tenth subpixels SPn3, SPn4, SPn9, and SPn10 are arranged in the horizontal direction. The ninth subpixel SPn9 is a red subpixel, and the tenth subpixel SPn10 is a white subpixel.

A first sensing line (VREF1) is arranged on the left side of the third subpixel (SPn3) along the vertical direction. The first sensing line VREF1 is commonly connected to the third subpixel SPn3 and the fourth subpixel SPn4 and the second sensing line VREF2 is commonly connected to the ninth subpixel SPn9 and the tenth subpixel SPn4. SPn10. Although not shown, the connection structure of the sensing lines and the subpixels has been described above, so that the description is omitted.

A third data line DLn3 arranged in parallel with the first sensing line VREF1 of the third subpixel SPn3 and a fourth data line DLn2 adjacent to the third data line DLn3 of the fourth subpixel SPn4 DLn4. The third data line DLn3 is connected to the third subpixel SPn3 and the fourth data line DLn4 is connected to the fourth subpixel SPn4.

 The fifth data line DLn5 is disposed in a region far from the fourth subpixel SPn4 of the ninth subpixel SPn9 and the sixth data line DLn5 adjacent to the ninth subpixel SPn9 of the tenth subpixel SPn10, The line DLn6 is arranged. The fifth data line DLn5 is connected to the ninth subpixel SPn9 and the sixth data line DLn6 is connected to the tenth subpixel SPn10. On the right side of the tenth subpixel SPn10, a second sensing line VREF2 is arranged along the vertical direction.

A first scan line GL1a and a second scan line GL1b intersecting the first sensing line VREF1 perpendicularly to the third, fourth, ninth, and tenth subpixels SPn3, SPn4, SPn9, and SPn10, . The first scan line GL1a is arranged above the third, fourth, ninth and tenth subpixels SPn3, SPn4, SPn9 and SPn10 and the second scan line GL1b is arranged above the third, The ninth and tenth subpixels SPn3, SPn4, SPn9 and SPn10. The first scan line GL1a is connected to the gate electrodes of the switching transistors SW of the third, fourth, ninth and tenth subpixels SPn3, SPn4, SPn9 and SPn10. The second scan line GL1b is connected to the sensing transistors ST of the third, fourth, ninth and tenth sub-pixels SPn3, SPn4, SPn9 and SPn10.

The switching transistors SW of the third, fourth, ninth and tenth subpixels SPn3, SPn4, SPn9 and SPn10 are connected to the third, fourth, ninth and tenth subpixels SPn3, SPn4, SPn9, And the sensing transistors ST of the third, fourth, ninth, and tenth sub-pixels SPn3, SPn4, SPn9, and SPn10 are connected to the respective driving transistors DR, 9 and the tenth sub-pixels SPn3, SPn4, SPn9, and SPn10, respectively. The pixel electrodes PXL are connected to the driving transistors DR of the third, fourth, ninth and tenth sub-pixels SPn3, SPn4, SPn9 and SPn10.

An upper portion of the first, second, third, fourth, ninth, and tenth subpixels SPn3, SPn4, SPn9, and SPn10 is provided with an arbitrary line in a direction parallel to the first gate line GL1a, The 11th and 12th subpixels SPn11 and SPn12 of the first unit pixel SP1 and the 13th and 14th subpixels SPn13 and SPn14 of the second unit pixel SP2 are arranged . The eleventh and twelfth subpixels SPn11 and SPn12 of the first unit pixel SP1 and the thirteenth and fourteenth subpixels SPn13 and SPn14 of the second unit pixel SP2 correspond to the third, The ninth and tenth subpixels SPn3, SPn4, SPn9, and SPn10. Therefore, the description thereof will be omitted.

On the other hand, between the fourth subpixel SPn4 of the third unit pixel SP3 and the ninth subpixel SPn9 of the fourth unit pixel SP4 and the twelfth subpixel SPn12 of the first unit pixel SP1 And the thirteenth subpixel SPn13 of the second unit pixel SP2, the second power line EVDD2 is disposed. The second power supply line EVDD2 is connected to the third and fourth subpixels SPn3 and SPn4 of the third unit pixel SP3 and the ninth and tenth subpixels SPn9 and SPn10 of the fourth unit pixel SP4, The eleventh and twelfth subpixels SPn11 and SPn12 of the first unit pixel SP1 and the thirteenth and fourteenth subpixels SPn13 and SPn14 of the second unit pixel SP2.

The second power supply line EVDD2 includes a vertical power supply line EVDDM arranged along the vertical direction and first through third horizontal power supply lines EVDDS1 through EVDDS3 arranged along the horizontal direction. The vertical power supply line (EVDDM) vertically crosses the first to third horizontal power supply lines EVDDS1 to EVDDS3. Here, the first and second horizontal power supply lines EVDDS1 and EVDDS2 are directly branched from the vertical power supply line EVDDM and the third horizontal power supply line EVDDS3 is connected to the second power supply contact hole VCH2 And connected to a vertical power line (EVDDM). The vertical power supply line EVDDM is arranged in parallel with the first sensing line VREF1 and the first to third horizontal power supply lines EVDDS1 to EVDDS3 are arranged in parallel with the first and second scan lines GL1a and GL1b .

One end of the first horizontal power supply line EVDDS1 is connected to the sensing transistor of the fourth subpixel SPn4 and the other end of the first horizontal power supply line EVDDS1 is connected to the sensing transistor of the ninth subpixel SPn9. One end of the second horizontal power supply line EVDDS2 is connected to the sensing transistor of the twelfth subpixel SPn12 and the other end of the second horizontal power supply line EVDDS2 is connected to the sensing transistor of the thirteenth subpixel SPn13 do.

One end of the third horizontal power supply line EVDDS3 branches to the third horizontal power supply line 1EVDDS3 and the third horizontal power supply line 2EVDDS3 and the other end of the third horizontal power supply line EVDDS3 branches to the third horizontal power supply 3 Line 3EVDDS3 and the fourth horizontal power supply line 4EVDDS3. Here, the third horizontal power source 1 line (1EVDDS3) is connected to the sensing transistor of the third subpixel (SPn3), and the third horizontal power source 2 line (2EVDDS3) is connected to the sensing transistor of the eleventh subpixel (SPn11). The third horizontal power supply line 3EVDDS3 is connected to the sensing transistor of the tenth subpixel SPn10 and the fourth horizontal power supply line 4EVDDS3 is connected to the sensing transistor of the fourteenth subpixel SPn14. Accordingly, the second power supply line EVDD2 is connected to the third, fourth, ninth, tenth, eleventh, and eleventh to eighth power supply lines VPP1 through the first to third horizontal power supply lines EVDDS1 to EVDDS3, 14 subpixels (SPn3, SPn4, SPn9, SPn10, SPn11 to SPn14) can be connected.

The cross-sectional structure of the subpixel will be described with reference to a portion of the first subpixel as an example. In the following, the structure of the transistor will be described with reference to the drive transistor, and the structure of the sensing transistor is the same as that of the drive transistor, so that the description is omitted.

Referring to FIG. 8, a light blocking layer LS and a third horizontal sensing line VREFS3 are disposed on a substrate SUB. The light blocking layer LS blocks light incident from the outside to prevent the leakage current of the transistor from being generated. Accordingly, the light blocking layer LS is formed corresponding to the channel region of the driving transistor DR, or separately formed to correspond to the channel regions of the driving transistor DR, the sensing transistor ST, and the switching transistor SW, respectively. The third horizontal sensing line VREFS3 is located on the same layer with the same material as the light blocking layer LS as a bridge for connecting the sensing line to the sensing transistor.

A buffer layer BUF is positioned on the light blocking layer LS and the third horizontal sensing line VREFS3. The buffer layer BUF serves to protect the transistors formed in the subsequent process from impurities such as alkali ions or the like that flow out from the light blocking layer LS or the substrate SUB. The buffer layer BUF may be silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof.

A semiconductor layer (ACT) is placed on the buffer layer (BUF). The semiconductor layer ACT may be formed of a silicon semiconductor or an oxide semiconductor. The silicon semiconductor may include amorphous silicon or crystallized polycrystalline silicon. Here, the polycrystalline silicon has high mobility (100 cm 2 / Vs or more), low energy consumption power and excellent reliability, and can be applied to a gate driver for a driving device and / or a multiplexer (MUX) have. On the other hand, since the oxide semiconductor has a low off-current, it is suitable for a switching transistor having a short ON time and a long OFF time. Further, since the off current is small, the voltage holding period of the pixel is long, which is suitable for a display device requiring low speed driving and / or low power consumption. Further, the semiconductor layer (ACT) includes a drain region including a p-type or n-type impurity and a source region and includes a channel region therebetween.

A gate insulating film GI is located on the semiconductor layer ACT. The gate insulating film GI may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof. The gate electrode GAT is located on a gate insulating film GI at a position corresponding to a certain region of the semiconductor layer ACT, that is, a channel when an impurity is injected. The gate electrode GAT is selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Any one of them or an alloy thereof. The gate electrode GAT may be formed of one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy of any one selected from the above. For example, the gate electrode (GAT) may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

An interlayer insulating film (ILD) for insulating the gate electrode (GAT) is located on the gate electrode (GAT). The interlayer insulating film ILD may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. The first and second contact holes CH1 and CH2 exposing a part of the semiconductor layer ACT are located in a part of the interlayer insulating film ILD.

The drain electrode DE and the source electrode SE are located on the interlayer insulating film ILD. The source electrode SE is connected to the semiconductor layer ACT through a first contact hole CH1 branched from the first power source line EVDD1 and exposing a source region of the semiconductor layer ACT, Is connected to the semiconductor layer (ACT) through a second contact hole (CH2) exposing a drain region of the semiconductor layer (ACT). The source electrode SE and the drain electrode DE may be formed of a single layer or a multilayer. When the source electrode SE and the drain electrode DE are a single layer, molybdenum (Mo), aluminum (Al) (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). When the source electrode SE and the drain electrode DE are multilayered, a triple layer of molybdenum / aluminum-neodymium, titanium / aluminum / titanium, molybdenum / aluminum / molybdenum or molybdenum / aluminum- neodymium / molybdenum &Lt; / RTI &gt; Therefore, the driving transistor DR including the semiconductor layer ACT, the gate electrode GAT, the drain electrode DE and the source electrode SE is constituted.

On the other hand, the sensing transistor ST is formed in the same manner as the structure of the driving transistor DR. However, the source electrode SE of the sensing transistor ST is connected to the third horizontal sensing line VREFS3 through the second sensing contact hole SCH2. The first data line DLn1 and the second data line DLn2 are disposed on the interlayer insulating layer ILD on the third horizontal sensing line VREFS3. The third horizontal sensing line VREFS3 is connected to the vertical sensing line VREFM through the first sensing contact hole SCH1.

The passivation film PAS is located on the substrate SUB including the driving transistor DR and the sensing transistor ST described above. The passivation film PAS may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof as an insulating film for protecting underlying devices. A color filter CF is placed on the passivation film PAS. The color filter CF converts the white light emitted from the organic light emitting diode OLED to a selected color of red, green and blue. In the present embodiment, it may be a red color filter (CF). An overcoat layer OC is placed on the color filter CF. The overcoat layer OC may be a planarizing film for alleviating the step difference of the lower structure and is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. The overcoat layer OC may be formed by a method such as spin on glass (SOG) in which the organic material is coated in a liquid form and then cured.

A via hole VIA for exposing the drain electrode DE is located in a part of the overcoat layer OC. An organic light emitting diode (OLED) is located on the overcoat layer (OC). More specifically, the first electrode ANO is located on the overcoat layer OC. The first electrode ANO acts as a pixel electrode and is connected to the drain electrode DE of the driving transistor DR through the via hole VIA. The first electrode ANO may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). When the first electrode ANO is a reflective electrode, the first electrode ANO further includes a reflective layer. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni) or an alloy thereof, preferably APC (silver / palladium / copper alloy).

On the substrate SUB including the first electrode ANO, a bank layer BNK for partitioning the pixels is located. The bank layer BNK is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. In the bank layer BNK, a pixel defining portion OP for exposing the first electrode ANO is located. A light emitting layer (EML) which contacts the first electrode (ANO) is located in the pixel defining portion (OP) of the bank layer (BNK). The light emitting layer (EML) may include a hole injecting layer or a hole transporting layer between the light emitting layer (EML) and the first electrode (ANO), and may include an electron transporting layer And an electron injection layer.

A second electrode (CAT) is located on the light emitting layer (EML). The second electrode CAT is disposed on the front surface of the display unit A / A and may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag) have. The second electrode (CAT) is a transparent electrode. The second electrode (CAT) is thin enough to transmit light. The second electrode (CAT) is thick enough to reflect light when the electrode is a reflective electrode.

Referring to FIG. 9, a light blocking layer LS and a third horizontal power supply line EVDDS3 are located on a substrate SUB. The third horizontal power supply line EVDDS is located on the same layer with the same material as the light blocking layer LS as a bridge for connecting the power supply line to the driving transistor. A buffer layer BUF is located on the light blocking layer LS and the third horizontal power supply line EVDDS and a semiconductor layer ACT, a gate insulating film GI, a gate electrode GAT, an interlayer insulating film ILD, and a drain electrode DE and a source electrode SE are positioned to constitute a driving transistor DR.

The source electrode SE of the driving transistor DR is connected to the third horizontal power supply line EVDDS3 through the third power supply contact hole VCH3. The third data line DLn3 and the fourth data line DLn4 are disposed on the interlayer insulating film ILD on the third horizontal power supply line EVDDS3. The third horizontal power supply line EVDDS3 is connected to the vertical power supply line EVDDM through the second power supply contact hole VCH2.

6 to 9, according to the present invention, the third horizontal power supply line (EVDDS3) and the third horizontal sensing line (VREFS3) are located on the same plane, and are positioned on the same plane as the light blocking layer (LS) do. That is, the third horizontal power supply line (EVDDS3) and the third horizontal sensing line (VREFS3) are simultaneously patterned using the same material as the light blocking layer (LS). Therefore, the buffer layer BUF and the interlayer insulating film ILD are disposed between the data lines crossing the third horizontal power supply line EVDDS3 and the third horizontal sensing line VREFS3. Accordingly, there is an advantage that a short circuit can be prevented from occurring due to the provision of the thick insulating films between the third horizontal power supply line (EVDDS3), the third horizontal sensing line (VREFS3) and the data lines.

FIG. 10 is a plan view schematically showing a subpixel array of a display device according to a comparative example, FIG. 11 is a plan view showing a subpixel array of the C region of FIG. 10, and FIG. 12 is a plan view showing a subpixel array of a display device according to a comparative example 13 is a plan view schematically showing a subpixel array of a display device according to an embodiment. In the following, the same reference numerals are assigned to the same components as those in the above-described embodiment, and the description thereof will be omitted.

<Comparative Example>

10, a red sub-pixel R1, a white sub-pixel W1, a blue sub-pixel B1 and a green sub-pixel G1 are arranged in a first row (n-1) And the red subpixel R2, the white subpixel W2, the blue subpixel B2 and the green subpixel G2 are arranged in the horizontal direction of the first unit pixel SP1 as the second unit pixel SP2 ). The red subpixel R3, the white subpixel W3, the blue subpixel B3 and the green subpixel G3 constitute the third unit pixel SP3 in the second row n, The red subpixel R4, the white subpixel W4, the blue subpixel B4 and the green subpixel G4 constitute the fourth unit pixel SP4 in the horizontal direction of the pixel SP3.

A sensing line is connected to the above-described subpixels, and a common line for applying a common power to the driving transistor is connected. In the comparative example, four subpixels arranged in the direction perpendicular to the sensing line are connected to one sensing line, and four subpixels arranged in the direction perpendicular to the common line are connected to one common line .

In the subpixel array in which the first to third power supply lines EVDD1 to EVDD3 and the first and second sensing lines VREF1 to VREF2 are arranged, the red subpixel R1 of the first unit pixel SP1, The pixel W1, the blue sub-pixel B1 and the green sub-pixel G1 are connected to one sensing branch SPP1. That is, four subpixels are connected to one branch portion of the power supply line. The blue sub-pixel B1 and the green sub-pixel G1 of the first unit pixel SP1 and the red sub-pixel R2 and the white sub-pixel W2 of the second unit pixel SP2 are connected to one power branching portion VPP1. That is, four subpixels are connected to one branch of the sensing line. A power branching unit VPP1 of the second power supply line EVDD2 and a sensing branch SPP1 of the first sensing line VREF1 are disposed between the first row n-1 and the second row n. Although not shown, the power branching portion of the second power supply line EVDD2 and the sensing branching portion of the first sensing line VREF1 are also disposed under the second row n. That is, in the comparative example, the branching portions of the power supply lines and the branching portions of the sensing lines are arranged between the rows of subpixels.

Hereinafter, the C region in Fig. 10 will be described in detail with reference to Fig. In the following description, the reference numerals and names of the subpixels of the first unit pixel are different. For example, the red subpixel R1 of the first unit pixel SP1 is referred to as a first subpixel SPn1.

Referring to FIG. 11, the first to fourth sub-pixels SPn1 to SPn4 are arranged in the horizontal direction. A first power supply line (EVDD1) is arranged on the left side of the first subpixel (SPn1) along the vertical direction. The first power supply line EVDD1 is commonly connected to the first subpixel SPn1 and the second subpixel SPn2. The first power supply line EVDD1 is directly connected to the first subpixel SPn1 by being branched from the first power supply line EVDD1 and connected to the first power supply line EVDD1 through the first power supply contact hole VCH1. And is connected to the second sub-pixel SPn2 through the three horizontal power supply lines EVDDS3. Although not shown, the first power supply line EVDD1 is commonly connected to two subpixels disposed on the left side of the first power supply line EVDD1. Hereinafter, a connection structure of a sensing line and a sub-pixel will be described.

A first data line DLn1 arranged in parallel with the first power line EVDD1 of the first subpixel SPn1 and a second data line DLn2 adjacent to the first data line DLn1 of the second subpixel SPn2 DLn2. The first data line DLn1 is connected to the first subpixel SPn1 and the second data line DLn2 is connected to the second subpixel SPn2. The third data line DLn3 is disposed in a region farther from the second subpixel SPn2 of the third subpixel SPn3 and the fourth data line DLn3 adjacent to the third subpixel SPn3 of the fourth subpixel SPn4, And the line DLn4 is disposed. The third data line DLn3 is connected to the third subpixel SPn3 and the fourth data line DLn4 is connected to the fourth subpixel SPn4. On the right side of the fourth sub-pixel SPn4, the second power source line EVDD2 is arranged along the vertical direction. The second power supply line EVDD2 is commonly connected to the third subpixel SPn3 and the fourth subpixel SPn4.

The first scan line GL1a and the second scan line GL1b which are perpendicular to the first power source line EVDD1 are disposed in the first subpixel SPn1 to the fourth subpixel SPn4. The first scan line GL1a and the second scan line GL1b are disposed adjacent to each other. The first scan line GL1a is connected to the gate electrode of the switching transistor SW of each of the first to fourth sub-pixels SPn1 to SPn4. The second scan line GL1b is connected to the sensing transistor ST of each of the first to fourth sub-pixels SPn1 to SPn4.

The switching transistor SW of each of the first to fourth sub-pixels SPn1 to SPn4 is connected to the driving transistor DR of each of the first to fourth sub-pixels SPn1 to SPn4, The sensing transistors ST of the first to fourth sub-pixels SPn1 to SPn4 are also connected to the driving transistors DR of the first to fourth sub-pixels SPn1 to SPn4. The pixel electrodes PXL are connected to the driving transistors DR of the first to fourth sub-pixels SPn1 to SPn4.

Meanwhile, a first sensing line VREF1 is disposed between the second subpixel SPn2 and the third subpixel SPn3. The first sensing line VREF1 is commonly connected to the first to fourth subpixels SPn1 to SPn4. The first sensing line VREF1 includes a vertical sensing line VREFM arranged along the vertical direction and first and second horizontal sensing lines VREFS1 and VREFS2 arranged along the horizontal direction. The first horizontal sensing line VREFS1 is branched directly from the vertical sensing line VREFM and the third horizontal sensing line VREFS3 is connected to the vertical sensing line VREFM through the first sensing contact hole SCH1. Connected.

One end of the first horizontal sensing line VREFM1 is connected to the sensing transistor of the second subpixel SPn2 and the other end of the first horizontal sensing line VREFS1 is connected to the sensing transistor of the third subpixel SPn3. One end of the second horizontal sensing line VREFS2 is connected to the sensing transistor of the first sub pixel SPn1 and the other end of the second horizontal sensing line VREFS2 is connected to the sensing transistor of the fourth sub pixel SPn4. Therefore, the first sensing line VREF1 can connect all of the first to fourth subpixels SPn1 to SPn4 through the first and second horizontal sensing lines VREFS1 and VREFS2 in one sensing branch SPP1 have.

Referring to FIG. 12, in the case of the subpixel array of the comparative example described above, the sensing line VREF is branched at one sensing branch SPP1 and connected to four subpixels SPn. Therefore, there exist a total of eight intersections where the first to fourth data lines DLn1 to DLn4 and the sensing line VREF intersect in two unit pixels of the 4x2 array.

Referring to FIG. 13, in the case of the subpixel array of the embodiment of the present invention, the sensing line VREF is branched at one sensing branch SPP1 and connected to eight subpixels SPn. Therefore, there are a total of four intersections where the first to fourth data lines DLn1 to DLn4 and the sensing line VREF intersect at two unit pixels of the 4x2 array.

Therefore, the present invention has an advantage in that the probability of short-circuiting between the sensing line and the data line can be remarkably reduced by reducing the number of intersections where the sensing lines and the data lines overlap and intersect with each other. Although not shown, the number of intersections between the power supply lines and the data lines can be reduced from eight to four. In addition, by reducing the number of intersections between the sensing lines and the data lines and the number of intersections between the power lines and the data lines, the aperture ratio can be improved.

Further, the present invention has an advantage in that the capacitor is disposed between the openings of the subpixels, thereby increasing the distance between the openings of the subpixels, thereby preventing the light of adjacent subpixels from being mixed.

In the above embodiment of the present invention, eight subpixels are connected from each branch of the sensing line and the power supply line. However, the present invention is not limited thereto, and further subpixels may be connected. In the embodiment of the present invention, the third horizontal power line and the third horizontal sensing line are made of the same material as the light blocking layer and disposed on the same layer. However, the third horizontal power line and the third horizontal sensing line are not limited thereto. The horizontal sensing line may be made of the same material as the metal located on the other layer, for example, the gate electrode, and may be disposed on the same layer.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SPn1 to SPn4: first to fourth sub-pixels EVDD1 to EVDD2: first and second power lines
VREF: sensing lines GL1a to GL1b: first and second scan lines
SW: switching transistor ST: sensing transistor
DR: driving transistor Cst: capacitor
ANO: first electrodes DLn1 to DLn4: first to fourth data lines

Claims (13)

Board;
At least four subpixels arranged in a first row on the substrate and at least four subpixels arranged in a second row; And
And a power line crossing in the vertical direction to divide the sub-pixels of the first row and the second row,
The power supply line includes a power supply branch located between the first row and the second row,
Wherein the power supply line is connected to at least four subpixels extending from the power branching portion and arranged in the first row and at least four subpixels arranged in the second row, respectively. The method according to claim 1,
At least four subpixels arranged in a third row; And
Further comprising: a sensing line crossing in a vertical direction to divide the sub-pixels of the second row and the third row,
Wherein the sensing line includes a sensing branch portion located between the second row and the third row,
Wherein the sensing line is connected to at least four sub-pixels extending from the sensing branch and arranged in the second row, and at least four sub-pixels arranged in the third row, respectively. The method according to claim 1,
Wherein the power supply line includes a vertical power supply line arranged in a vertical direction and a horizontal power supply line connected to the vertical power supply line and crossing the vertical power supply line in a horizontal direction. The method of claim 3,
Wherein the horizontal power supply line includes first and second horizontal power supply lines directly branched from the vertical power supply line, and a third horizontal power supply line connected to the vertical power supply line and the power supply contact hole. 5. The method of claim 4,
Wherein the third horizontal power supply line is disposed on a different layer from the vertical power supply line. 5. The method of claim 4,
Wherein both ends of the first horizontal power supply line are connected to subpixels of the first row adjacent to the vertical power supply line and both ends of the second horizontal power supply line are connected to subpixels of the second row adjacent to the vertical power supply line, Respectively,
One end of the third horizontal power supply line is branched into two or more, at least one of which is connected to the subpixels of the first row and the other of which is connected to the subpixels of the second row, Wherein at least one is connected to the sub-pixels of the first row and the other is connected to the sub-pixels of the second row. 3. The method of claim 2,
Wherein the sensing line includes a vertical sensing line arranged in a vertical direction and a horizontal sensing line connected to the vertical sensing line and crossing the vertical sensing line in a horizontal direction. 8. The method of claim 7,
Wherein the horizontal sensing line includes first and second horizontal sensing lines directly branched from the vertical sensing line and a third horizontal sensing line connected to the vertical sensing line and the power contact hole. 9. The method of claim 8,
Wherein the third horizontal sensing line is disposed on a different layer from the vertical sensing line. 9. The method of claim 8,
Wherein both ends of the first horizontal sensing line are connected to subpixels of the second row adjacent to the vertical sensing line and both ends of the second horizontal sensing line are connected to subpixels of the third row adjacent to the vertical power supply line, Respectively,
One end of the third horizontal sensing line is branched into two or more, at least one of which is connected to the sub-pixels of the second row and the other of which is connected to the sub-pixels of the third row, Wherein at least one is connected to the sub-pixels of the second row and the other is connected to the sub-pixels of the third row. 3. The method of claim 2,
A plurality of data lines arranged in a direction parallel to the power supply lines and disposed adjacent to the subpixels, respectively; And
And first and second gate lines arranged in a direction perpendicular to the power source line and intersecting the plurality of data lines and the power source line. 12. The method of claim 11,
In one of the subpixels, a switching transistor is disposed in an area where the data line and the first gate line intersect, a sensing transistor is disposed in an area where the data line and the second gate line cross each other, And a first electrode connected to the driving transistor. 3. The method of claim 2,
Wherein each of the subpixels includes an opening through which light is emitted, and capacitors are disposed between the openings of the subpixels.

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