KR20190036636A - Flexible circuit board for all in one chip on film and chip pakage comprising the same, and electronic device comprising the same - Google Patents

Abstract

A flexible circuit board for an all-in-one chip on film according to one embodiment comprises: a first substrate; a second substrate disposed on the first substrate; a first conductive pattern part including a first wire pattern layer disposed on a lower surface of the first substrate, and a plating layer disposed on the first wire pattern layer and including a tin; a second conductive pattern part including a second wire pattern layer disposed on an upper surface of the second substrate, and the plating layer disposed on the second wire pattern layer and including a tin; a third conductive pattern part including a third wire pattern layer disposed between the first and second substrates; and, a protective layer partially disposed on the first and second conductive pattern parts, wherein the second conductive pattern part includes first to fourth inner lead pattern parts disposed in a first open region of the protective layer, and an extension pattern part covered by the protective layer, the first and fourth inner lead pattern parts are connected to the extension pattern part, the second inner lead pattern part is directly connected to the first conductive pattern part through a first via penetrating the first and second substrates, and the third inner lead pattern part is directly connected to the third conductive pattern part through a second via penetrating the second substrate.

Description

TECHNICAL FIELD [0001] The present invention relates to a flexible circuit board for an all-in-one chip-on-film, a chip package including the same, and an electronic device including the chip package.

Embodiments relate to a flexible circuit board for an all-in-one chip-on film, a chip package including the same, and an electronic device including the same.

In detail, the flexible circuit board for the all-in-one chip on film is a flexible circuit board on which different types of chips can be mounted on one substrate, a chip package thereof, and an electronic device have.

Recently, a variety of electronic products are becoming thinner, smaller, and lighter. Accordingly, various studies for mounting a semiconductor chip at a high density in a narrow region of an electronic device have been carried out.

Among them, since a COF (Chip On Film) method uses a flexible substrate, it can be applied to both a flat panel display and a flexible display. That is, the COF method is attracting attention because it can be applied to various wearable electronic devices. Further, since the COF method can realize a fine pitch, it can be used to realize a display of high resolution (QHD) as the number of pixels increases.

COF (Chip On Film) is a method of mounting a semiconductor chip on a flexible circuit board in the form of a thin film. For example, the semiconductor chip may be an integrated circuit (IC) chip or a large scale integrated circuit (LSI) chip.

However, the COF flexible circuit board can not be directly connected between the display panel and the main board.

That is, at least two printed circuit boards are required between the display panel and the main board.

An electronic device having a display portion has a problem in that the thickness thereof increases as a plurality of printed circuit boards are required. In addition, the size of a plurality of printed circuit boards may be a limitation to miniaturization of electronic devices. In addition, poor bonding of a plurality of printed circuit boards may lower the reliability of the electronic device.

Therefore, a new flexible circuit board capable of solving such a problem is required.

An embodiment provides a flexible circuit board for an all-in-one chip-on-film capable of mounting a plurality of chips on a single board, a chip package including the same, and an electronic device including the same.

A flexible circuit board for an all-in-one chip-on film according to an embodiment includes: a first substrate; A second substrate disposed on the first substrate; A first wiring pattern layer disposed on a lower surface of the first substrate; a first conductive pattern portion disposed on the first wiring pattern layer and including a plating layer including tin; A second wiring pattern layer disposed on an upper surface of the second substrate; a second conductive pattern portion disposed on the second wiring pattern layer and including a plating layer including tin; A third conductive pattern portion including a third wiring pattern layer disposed between the first substrate and the second substrate; And a protective layer partially disposed on the first and second conductive pattern portions, wherein the second conductive pattern portion includes first to fourth inner lead pattern portions disposed on a first open region of the protective layer, And an extension pattern portion covered by the protective layer, wherein the first and fourth inner lead pattern portions are connected to the extended pattern portion, and the second inner lead pattern portion penetrates through the first substrate and the second substrate And the third inner lead pattern portion is directly connected to the third conductive pattern portion through a second via passing through the second substrate.

In a chip package including a flexible circuit board for an all-in-one chip-on film according to an embodiment, a flexible circuit board for an all-in-one chip-on film includes a first substrate; A second substrate disposed on the first substrate; A first wiring pattern layer disposed on a lower surface of the first substrate; a first conductive pattern portion disposed on the first wiring pattern layer and including a plating layer including tin; A second wiring pattern layer disposed on an upper surface of the second substrate; a second conductive pattern portion disposed on the second wiring pattern layer and including a plating layer including tin; A third conductive pattern portion including a third wiring pattern layer disposed between the first substrate and the second substrate; And a protective layer partially disposed on the first and second conductive pattern portions, wherein the second conductive pattern portion includes first to fourth inner lead pattern portions disposed on a first open region of the protective layer Wherein the first chip and the second chip are disposed on the first connection portion on the first open region, and the first and fourth inner lead pattern portions are connected to the extension pattern portion and the second pattern portion, And the second inner lead pattern portion is directly connected to the first conductive pattern portion through a first via passing through the first substrate and the second substrate, And is directly connected to the third conductive pattern portion through a second via penetrating the substrate.

Further, an electronic device according to an embodiment includes: a first substrate; A second substrate disposed on the first substrate; A first wiring pattern layer disposed on a lower surface of the first substrate; a first conductive pattern portion disposed on the first wiring pattern layer and including a plating layer including tin; A second wiring pattern layer disposed on an upper surface of the second substrate; a second conductive pattern portion disposed on the second wiring pattern layer and including a plating layer including tin; A third conductive pattern portion including a third wiring pattern layer disposed between the first substrate and the second substrate; And a protective layer partially disposed on the first and second conductive pattern portions, wherein the second conductive pattern portion includes first to fourth inner lead pattern portions disposed on a first open region of the protective layer Wherein the first and fourth inner lead pattern portions are connected to the extended pattern portion and the second inner lead pattern portion includes a first inner lead pattern portion and a second outer lead pattern portion, Wherein the second conductive pattern portion is directly connected to the first conductive pattern portion through a first via penetrating through the second substrate and the third inner lead pattern portion is directly connected to the third conductive pattern portion via a second via penetrating through the second substrate, A flexible circuit board for all-in-one chip-on film to be connected; A display panel connected to one end of the flexible circuit board for the all-in-one chip-on film; And a main board connected to the other end opposite to the one end of the all-in-one chip-on-film flexible circuit board.

A flexible circuit board for an all-in-one chip-on-film according to an embodiment includes a first substrate, a second substrate, a first conductive pattern portion disposed on a lower surface of the first substrate, a second conductive pattern portion disposed on an upper surface of the second substrate, And a third conductive pattern portion disposed between the first substrate and the second substrate. The first and second conductive pattern portion angles may include a wiring pattern layer, a first plating layer, and a second plating layer. The third conductive pattern portion may include only the wiring pattern layer.

A protective layer may be disposed on one of the first and second conductive pattern portions to form a protective portion, and a protective portion may not be disposed in a region other than the one region. The plurality of regions in which the protection portion is not disposed may be the first open region and the second open region.

The content of tin (Sn) in the second plating layer in the first open region may be different from the content of tin (Sn) in the second plating layer in the second open region.

A first connection portion may be disposed on the first open region, and a first chip may be disposed on the first connection portion. The first connection portion may electrically connect the second conductive pattern portion and the first chip.

A second connection portion may be disposed on the second open region, and a second chip may be disposed on the second connection portion. The second connection portion may electrically connect the second conductive pattern portion and the second chip.

Accordingly, the embodiment can provide a flexible circuit board chip package for an all-in-one chip-on-film having improved reliability, because the first chip and the second chip of different kinds can be mounted on one flexible circuit board.

In addition, the flexible printed circuit board for one all-in-one chip-on-film according to the embodiment can directly connect the display panel and the main board. Accordingly, the size and thickness of the flexible circuit board for transmitting signals generated from the display panel to the main board can be reduced.

Accordingly, the flexible circuit board for an all-in-one chip-on-film, the chip package including the same, and the electronic device including the same can expand the space and / or the battery space of other components.

Further, since the connection of a plurality of printed circuit boards is not required, the convenience of the process and the reliability of the electrical connection can be improved.

Accordingly, the flexible circuit board for an all-in-one chip-on-film, the chip package including the same, and the electronic device including the same can be suitable for electronic devices having a high-resolution display portion.

1A is a cross-sectional view of an electronic device having a display portion including a conventional printed circuit board.
FIG. 1B is a cross-sectional view of the printed circuit board according to FIG. 1A in a bent form. FIG.
1C is a plan view of the printed circuit board according to FIG. 1A in a bent form.
2A is a cross-sectional view of an electronic device having a display portion including a flexible circuit board for an all-in-one chip-on film according to an embodiment.
FIG. 2B is a cross-sectional view of the flexible circuit board for all-in-one chip-on-film according to FIG.
FIG. 2C is a plan view of the flexible circuit board for an all-in-one chip-on-film according to FIG.
3A is a cross-sectional view of a flexible circuit board for a cross-sectional all-in-one chip-on film according to an embodiment.
3B is a cross-sectional view of a chip package including a flexible circuit board for a cross-sectional all-in-one chip-on film according to an embodiment.
4 to 6 are sectional views showing a manufacturing process of a chip package including a flexible circuit board for an all-in-one chip-on-film according to the embodiment
7 is a cross-sectional view of a chip package including a flexible circuit board for a both-side all-in-one chip-on film according to an embodiment.
8A is another cross-sectional view of a flexible circuit board for a both-side all-in-one chip-on film according to an embodiment.
8B is a cross-sectional view of a chip package including a flexible circuit board for a both-side all-in-one chip-on film shown in FIG. 8A.
9 is another cross-sectional view of a chip package including a flexible circuit board for a both-side all-in-one chip-on film according to an embodiment.
10 is an enlarged cross-sectional view of one region of a flexible circuit board for a both-side all-in-one chip-on film according to an embodiment.
11 is a plan view of a flexible circuit board for a both-side all-in-one chip-on film shown in Fig. 8A.
Fig. 12 is a bottom view of a flexible circuit board for a both-side all-in-one chip-on film shown in Fig. 8A.
Fig. 13 is a schematic plan view of a chip package including a flexible circuit board for a both-side all-in-one chip-on film according to Fig. 8B.
Figs. 14 to 16 are views showing a process of manufacturing a flexible circuit board for a both-side all-in-one chip-on-film according to Fig. 8A into a chip package including a flexible circuit board for a both-
17 is a cross-sectional view of a chip package including a flexible circuit board for a both-side all-in-one chip-on film shown in Fig.
18 to 22 are views of various electronic devices including a flexible circuit board for an all-in-one chip-on film.

In the description of the embodiments, it is to be understood that each layer (film), area, pattern or structure may be referred to as being "on" or "under / under" Quot; includes all that is formed directly or through another layer. The criteria for top / bottom or bottom / bottom of each layer are described with reference to the drawings.

Also, when a part is referred to as being "connected" to another part, it includes not only a case of being "directly connected" but also a case of being "indirectly connected" with another member in between. Also, when an element is referred to as "comprising ", it means that it can include other elements, not excluding other elements unless specifically stated otherwise.

The thickness or the size of each layer (film), region, pattern or structure in the drawings may be modified for clarity and convenience of explanation, and thus does not entirely reflect the actual size.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A printed circuit board according to a comparative example will be described with reference to Figs. 1A to 1C.

An electronic device having a display portion requires at least two printed circuit boards in order to transmit signals of the display panel to the main board.

The electronic device including the display unit according to the comparative example may have at least two printed circuit boards.

The electronic device including the display unit according to the comparative example may include the first printed circuit board 10 and the second printed circuit board 20. [

The first printed circuit board 10 may be a flexible printed circuit board. In detail, the first printed circuit board 10 may be a flexible printed circuit board for a chip on film (COF). The first printed circuit board 10 may be a COF flexible printed circuit board on which the first chip C1 is mounted. More specifically, the first printed circuit board 10 may be a flexible printed circuit board for a COF for disposing a drive IC chip.

The second printed circuit board 20 may be a flexible printed circuit board. In detail, the second printed circuit board 20 may be a flexible printed circuit board (FPCB) for disposing a second chip C2 of a different kind from the first chip C1. Here, the second chip C2 may be electrically connected to a flexible printed circuit board such as a chip, a semiconductor device, or a socket other than a drive IC chip, other than a drive IC chip. May refer to various chips that are deployed. The second printed circuit board 20 may be a flexible printed circuit board (FPCB) for arranging the plurality of second chips C2. For example, the second printed circuit board 20 may be a flexible printed circuit board for disposing a plurality of second chips C2a and C2b of different kinds.

The first printed circuit board 10 and the second printed circuit board 20 may have different thicknesses. The thickness of the second printed circuit board (20) may be smaller than the thickness of the first printed circuit board (10). For example, the first printed circuit board 10 may have a thickness of about 20 [mu] m to 100 [mu] m. The second printed circuit board 20 may have a thickness of about 100 [mu] m to 200 [mu] m. For example, the total thickness t1 of the first printed circuit board 10 and the second printed circuit board may be 200 [mu] m to 250 [mu] m.

Since the first and second printed circuit boards are required between the display panel and the main board, the electronic device having the display unit according to the comparative example can increase the overall thickness of the electronic device. In detail, since the electronic device having the display portion according to the comparative example requires the first and second printed circuit boards stacked on and under, the overall thickness of the electronic device can be increased.

The first printed circuit board 10 and the second printed circuit board 20 may be formed in different processes. For example, the first printed circuit board 10 may be manufactured by a roll-to-roll process. The second printed circuit board 20 may be manufactured by a sheet method.

Different types of chips may be disposed on the first printed circuit board 10 and the second printed circuit board 20 and pitches of the conductive pattern portions to be connected to the respective chips may be different from each other. For example, the pitch of the conductive pattern portions disposed on the second printed circuit board 20 may be greater than the pitch of the conductive pattern portions disposed on the first printed circuit board 10. For example, the pitch of the conductive pattern portions disposed on the second printed circuit board 20 is 100 탆 or more, the pitch of the conductive pattern portions disposed on the first printed circuit board 10, May be less than 100 mu m.

In detail, the first printed circuit board 10 having a conductive pattern portion arranged at a fine pitch can be manufactured through a roll-to-roll process in a process-efficient manner, and the process cost can be reduced. On the other hand, since it is difficult to handle the second printed circuit board 20 having a conductive pattern portion arranged at an interval of 100 mu m or more in the roll-to-roll process, it is common to use a sheet process.

Since the first and second printed circuit boards according to the comparative example are formed by different processes, the process efficiency may be lowered.

In addition, since the chip package including the flexible circuit board according to the comparative example has a difficulty in arranging different types of chips on one substrate, separate first and second printed circuit boards are required.

In addition, the chip package including the flexible circuit board according to the comparative example has a problem that it is difficult to connect different kinds of chips on one substrate.

That is, the first and second printed circuit boards may be disposed between the conventional display panel and the main board.

The first printed circuit board 10 is connected to the display panel 30 in order to control, process, or transfer the R, G, and B signals generated from the display panel 30. The first printed circuit board 10 is connected to the second printed circuit board 20 so that the second printed circuit board 20 can be connected to the main board 40.

One end of the first printed circuit board 10 may be connected to the display panel 30. The display panel 30 may be connected to the first printed circuit board 10 by an adhesive layer 50.

The other end opposite to the one end of the first printed circuit board 10 may be connected to the second printed circuit board 20. The first printed circuit board 10 may be connected to the second printed circuit board 20 by the adhesive layer 50.

One end of the second printed circuit board 20 is connected to the first printed circuit board 10 and the other end opposite to the one end of the second printed circuit board 20 is connected to the main board 40 have. The second printed circuit board (20) may be connected to the main board (40) by the adhesive layer (50).

The electronic device having the display unit according to the comparative example is disposed between the display panel 30 and the first printed circuit board 10 and between the first printed circuit board 10 and the second printed circuit board 20 A separate adhesive layer 50 may be required between the second printed circuit board 20 and the main board 40, respectively. That is, since the electronic device having the display unit according to the comparative example requires a plurality of adhesive layers, the reliability of the electronic device may deteriorate due to poor connection of the adhesive layer. In addition, the adhesive layer disposed between the first printed circuit board 10 and the second printed circuit board 20 connected in an up-and-down direction can increase the thickness of the electronic device.

1B and 1C, a first printed circuit board 10, a second printed circuit board 20, a display panel 30, and a main board 40 housed in an electronic device according to a comparative example Explain.

FIG. 1B is a cross-sectional view of the printed circuit board according to FIG. 1A in a bent form, and FIG. 1C is a plan view of the lower surface of FIG. 1B.

The display panel 30 and the main board 40 may be disposed to face each other. A first printed circuit board 10 including a bending area may be disposed between the display panel 30 and the main board 40 which are disposed facing each other.

The first printed circuit board 10 is bent in one area, and the first chip C1 may be disposed in a region where the first printed circuit board 10 is not bent.

The second printed circuit board 20 may be disposed facing the display panel 30. And the second chip C2 may be disposed in an unbending region of the second printed circuit board 20. [

Referring to FIG. 1C, since a plurality of substrates are required in the comparative example, the length L1 in one direction is the sum of the lengths of the first printed circuit board 10 and the second printed circuit board 20 . The length L1 of the first printed circuit board 10 and the second printed circuit board 20 in one direction is determined by the length of the short side of the first printed circuit board 10 and the length of the first printed circuit board 10 20). ≪ / RTI > For example, the length L1 of the first printed circuit board 10 and the second printed circuit board 20 in one direction may be 30 mm to 40 mm. However, the length L1 of the first printed circuit board 10 and the second printed circuit board 20 in one direction may vary according to the type of chip to be mounted and the type of the electronic device.

As the electronic device according to the comparative example requires a plurality of printed circuit boards, the space for mounting other components or the space for arranging the battery 60 can be reduced.

2. Description of the Related Art [0002] In recent years, electronic devices such as smart phones have been added with various functions to enhance user convenience and security. For example, a plurality of camera modules (dual camera module, dual camera module) may be mounted on an electronic device such as a smart phone or a smart watch, or a component having various functions such as an iris recognition function and a virtual reality (VR) Has been added. Accordingly, it is important to secure a space for mounting additional components.

In addition, various electronic devices including a wearable device are required to have an expanded battery space for the convenience of the user.

Therefore, replacing a plurality of printed circuit boards used in existing electronic devices with a single printed circuit board, the importance of securing a space for mounting new components or securing a space for enlarging the battery size becomes important.

In the electronic device according to the comparative example, the first chip and the second chip of different kinds may be disposed on the first printed circuit board 10 and the second printed circuit board 30, respectively. The thickness of the adhesive layer 50 between the first printed circuit board 10 and the second printed circuit board 30 and the thickness of the second printed circuit board 30 increase the thickness of the electronic device .

In addition, there is a problem that the space for mounting the battery space or other parts is reduced by the size of the second printed circuit board 30.

In addition, defective junctions of the first and second printed circuit boards have a problem of lowering the reliability of the electronic device.

In order to solve this problem, the embodiment can provide a flexible circuit board for an all-in-one chip-on-film having a novel structure capable of mounting a plurality of chips on a single board, a chip package including the same, and an electronic device including the same have. The same reference numerals in the embodiment and the comparative example denote the same components, and the description overlapping with the comparative example described above is excluded.

An electronic device including a flexible circuit board for an all-in-one chip-on film according to an embodiment will be described with reference to Figs. 2A to 2C.

The electronic device according to the embodiment may use one printed circuit board to transmit signals of the display panel to the main board. The printed circuit board included in the electronic device including the display unit according to the embodiment may be one flexible printed circuit board. Accordingly, the flexible circuit board 100 for the all-in-one chip on film according to the embodiment is bended between the display unit and the main board facing each other to connect the display unit and the main board have.

In detail, the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be a single substrate for arranging a plurality of chips of different kinds.

The flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be a substrate for disposing the first chip c1 and the second chip c2 of different kinds.

The thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be 20 탆 to 100 탆. For example, the thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be 30 탆 to 80 탆. For example, the thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be 50 탆 to 75 탆. However, the thickness of the flexible circuit board 100 for the all-in-one chip on film according to the embodiment may be designed in various sizes depending on the type of the chip to be mounted and the type of the electronic device .

The thickness t2 of the all-in-one chip on film flexible printed circuit board 100 according to the embodiment is equal to the thickness t1 of the plurality of first and second printed circuit boards according to the comparative example, / 5 to 1/2 level. That is, the thickness t2 of the all-in-one chip on film flexible printed circuit board 100 according to the embodiment is smaller than the thickness t1 of the first and second printed circuit boards according to the comparative example, To about 20% to about 50% of the thickness. For example, the thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is determined by the thickness t2 of the plurality of first and second printed circuit boards 0.0 > tl) < / RTI > For example, the thickness t2 of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is determined by the thickness t2 of the plurality of first and second printed circuit boards lt; RTI ID = 0.0 > tl. < / RTI >

Since the electronic device having the display unit according to the embodiment requires the flexible circuit board 100 for only one all-in-one chip on film between the display panel and the main board, the overall thickness of the electronic device Can be reduced. In detail, since the electronic device having the display portion according to the embodiment requires a single-layer printed circuit board, the overall thickness of the electronic device can be reduced.

In addition, the embodiment can omit the adhesive layer 50 between the first printed circuit board and the second printed circuit board included in the comparative example, and can be applied to a chip package including a flexible circuit board for all-in- The overall thickness of the electronic device can be reduced.

In addition, the embodiment can omit the adhesive layer 50 between the first printed circuit board and the second printed circuit board, thereby solving the problem caused by poor adhesion, thereby improving the reliability of the electronic device.

Further, since the step of adhering a plurality of printed circuit boards can be omitted, the process efficiency can be increased and the process cost can be reduced.

In addition, by replacing the substrate that has been managed as a separate process with one process, the process efficiency and product yield can be improved.

The flexible circuit board 100 for an all-in-one chip on film according to the embodiment may include a bent region and a non-bent region. The flexible circuit board 100 for an all-in-one chip on film according to the embodiment includes the display panel 30 and the main board 40, which are disposed to face each other, They can be connected to each other.

The non-bending region of the flexible circuit board 100 for the all-in-one chip on film according to the embodiment can be disposed facing the display panel 30 with respect to each other. The first chip C1 and the second chip C2 may be disposed on the non-bent region of the flexible circuit board 100 for the all-in-one chip on film. Accordingly, the flexible circuit board 100 for an all-in-one chip on film according to the embodiment can be stably mounted on the first chip c1 and the second chip c2.

2C is a plan view of the bottom of FIG. 2B.

Referring to FIG. 2C, since one substrate is required in the embodiment, the length L2 in one direction may be the length of one substrate. The length L2 in one direction of the flexible circuit board 100 for the all-in-one chip on film according to the embodiment may be set to be less than the length L2 of the all-in-one chip on film May be the length of the short side of the flexible circuit board 100. For example, the length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film may be 10 mm to 50 mm. For example, the length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be 10 mm to 30 mm. For example, the length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment may be 15 mm to 25 mm. However, the embodiment is not limited thereto, and it is of course possible to design various sizes according to the type and / or number of chips to be arranged and the type of electronic device.

The length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is equal to the length L2 in one direction of the plurality of first and second printed circuit boards according to the comparative example And may have a length of about 50% to about 70% of the length L1 at the center. For example, the length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is smaller than the length L2 of the first and second printed circuits And may have a length on the order of 55% to 70% of the length L1 in one direction of the substrate. The length L2 in one direction of the flexible circuit board 100 for an all-in-one chip on film according to the embodiment is equal to the length L2 in one direction of the plurality of first and second printed circuit boards according to the comparative example Of the length L1 in the first direction.

Accordingly, the embodiment can reduce the size of the chip package including the flexible circuit board 100 for the all-in-one chip on film in the electronic device, so that the space for arranging the battery 60 Can be enlarged. In addition, the chip package including the flexible circuit board 100 for all-in-one chip on film according to the embodiment can be reduced in planarity, and space for mounting other components can be secured .

Referring to FIGS. 3A, 3B, 7, 8A, 8B, 9 and 10, a flexible circuit board 100 for an all-in-one chip on film, Describe the package.

3A and 3B, a flexible circuit board 100 for an all-in-one chip on film according to an embodiment includes a flexible circuit board 100 for a cross-sectional all-in-one chip on film having an electrode pattern on one side .

The flexible circuit board 100 for an all-in-one chip on film according to the embodiment includes a substrate 110, a wiring pattern layer 120 disposed on the substrate 110, a plating layer 130, And may include a protective layer 140.

The substrate 110 may be a supporting substrate for supporting the wiring pattern layer 120, the plating layer 130, and the protective layer 140.

The substrate 110 may include regions other than the bending region and the bending region. That is, the substrate 110 may include a bending region where bending is performed and a non-bending region other than the bending region.

The substrate 110 may be a flexible substrate. Accordingly, the substrate 110 may be partially bendable. That is, the substrate 110 may include a soft plastic. For example, the substrate 110 may be a polyimide (PI) substrate. However, the present invention is not limited thereto, and the substrate may be a substrate made of a polymer material such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). Accordingly, the flexible circuit board including the substrate 110 can be used in various electronic devices having a curved display device. For example, the flexible circuit board including the substrate 110 may be suitable for mounting a semiconductor chip of a wearable electronic device because of its excellent flexibility characteristics. In particular, embodiments may be suitable for electronic devices including a curved display.

The substrate 110 may be an insulating substrate. That is, the substrate 110 may be an insulating substrate supporting various wiring patterns.

The substrate 110 may have a thickness of 20 탆 to 100 탆. For example, the substrate 110 may have a thickness of 25 [mu] m to 50 [mu] m. For example, the substrate 100 may have a thickness of 30 [mu] m to 40 [mu] m. When the thickness of the substrate 100 is more than 100 mu m, the thickness of the entire flexible circuit board may increase. When the thickness of the substrate 100 is less than 20 mu m, it may be difficult to arrange the first chip C1 and the second chip C2 at the same time. When the thickness of the substrate 110 is less than 20 μm, the substrate 110 may be vulnerable to heat / pressure during a process of mounting a plurality of chips, and it may be difficult to arrange a plurality of chips at the same time. 110 may be arranged with wirings. The wiring may be a plurality of patterned wirings. For example, the plurality of wirings on the substrate 110 may be disposed apart from each other. That is, the wiring pattern layer 120 may be disposed on one surface of the substrate 110.

The area of the substrate 110 may be larger than the area of the wiring pattern layer 120. In detail, the planar area of the substrate 110 may be larger than the planar area of the wiring pattern layer 120. That is, the wiring pattern layer 120 may be partially disposed on the substrate 110. For example, the lower surface of the wiring pattern layer 120 may be in contact with the substrate 110, and the substrate 110 may be exposed between the plurality of wirings. The wiring pattern layer 120 may include a conductive material.

For example, the wiring pattern layer 120 may include a metal material having excellent electrical conductivity. More specifically, the wiring pattern layer 120 may include copper (Cu). However, the embodiment is not limited thereto, and copper, aluminum, chromium, nickel, silver and molybdenum may be used. And may include at least one of gold (Au), titanium (Ti), and alloys thereof.

The wiring pattern layer 120 may be arranged to have a thickness of 1 탆 to 15 탆. For example, the wiring pattern layer 120 may be arranged to have a thickness of 1 탆 to 10 탆. For example, the wiring pattern layer 120 may be arranged to have a thickness of 2 탆 to 10 탆.

When the thickness of the wiring pattern layer 120 is less than 1 占 퐉, the resistance of the wiring pattern layer may increase. If the thickness of the wiring pattern layer 120 is more than 10 mu m, it may be difficult to realize a fine pattern.

A plating layer 130 may be disposed on the wiring pattern layer 120. The plating layer 130 may include a first plating layer 131 and a second plating layer 132.

A first plating layer 131 may be disposed on the wiring pattern layer 120 and the second plating layer 132 may be disposed on the first plating layer 131. The first plating layer 131 and the second plating layer 132 may be formed in two layers on the wiring pattern layer 120 in order to prevent formation of a whisker (kr00000374075b1). Thus, a short circuit between the patterns of the wiring pattern layer 120 can be prevented. Further, since the two plating layers are disposed on the wiring pattern layer 120, the bonding characteristics with the chip can be improved. In the case where the wiring pattern layer contains copper (Cu), the wiring pattern layer can not be directly bonded to the first chip (C1), and separate bonding processing may be required. On the other hand, when the plating layer disposed on the wiring pattern layer includes tin (Sn), the surface of the plating layer may be a pure tin layer, so that bonding with the first chip (C1) can be facilitated. At this time, the wire connected to the first chip (C1) can be easily connected to the pure tin layer only by heat and pressure, so that the accuracy of the chip wire bonding and the convenience of the manufacturing process can be improved.

The region where the first plating layer 131 is disposed may correspond to the region where the second plating layer 132 is disposed. That is, the area where the first plating layer 131 is disposed may correspond to the area where the second plating layer 132 is disposed.

The plating layer 130 may include tin (Sn). For example, the first plating layer 131 and the second plating layer 132 may include tin (Sn).

For example, the wiring pattern layer 120 may be formed of copper (Cu), and the first plating layer 131 and the second plating layer 132 may be formed of tin (Sn). When the plating layer 130 contains tin, oxidation of the wiring pattern layer 120 can be prevented because tin (Sn) has excellent corrosion resistance.

Meanwhile, the material of the plating layer 130 may be lower in electrical conductivity than the material of the wiring electrode layer 120. The plating layer 130 may be electrically connected to the wiring electrode layer 120.

The first plating layer 131 and the second plating layer 132 are formed of the same tin (Sn), but they may be formed by a separate process.

When the manufacturing process of the flexible circuit board according to the embodiment includes a heat treatment process such as thermal curing, the diffusion action of copper (Cu) of the wiring pattern layer 120 or tin (Sn) of the plating layer 130 Can happen. In detail, diffusion of copper (Cu) of the wiring pattern layer 120 or tin (Sn) of the plating layer 130 may occur through the curing of the protective layer 140.

Accordingly, as the diffusion concentration of copper (Cu) decreases from the first plating layer 131 to the surface of the second plating layer 132, the content of copper (Cu) can be continuously reduced. On the other hand, the content of tin (Sn) can be continuously increased from the first plating layer (131) to the surface of the second plating layer (132). Accordingly, the uppermost portion of the plating layer 130 may include pure tin.

That is, at least a part of the plating layer 130 may be an alloy of tin and copper due to a chemical action at the lamination interface of the wiring pattern layer 120 and the plating layer 130. After the protective layer 140 is cured on the plating layer 130 to a thickness of the tin and copper alloy after the plating layer 130 is formed on the wiring pattern layer 120, The thickness can be increased.

The alloy of tin and copper contained in at least a part of the plating layer 130 has a chemical formula of Cu _x Sn _y , and 0 < x + y < For example, in the above formula, the sum of x and y may be 4? X + y? 11. For example, the tin and copper alloy contained in the plating layer 130 may be Cu ₃ Sn and Cu ₆ Sn ₅ Or the like. In detail, the first plating layer 131 may be an alloy layer of tin and copper.

In addition, the content of tin and copper in the first plating layer 131 and the second plating layer 132 may be different from each other. The first plating layer 131 directly contacting the copper wiring pattern layer may have a copper content greater than that of the second plating layer 132.

The second plating layer 132 may have a tin content greater than that of the first plating layer 131. The second plating layer 132 may include pure tin. Here, pure tin may mean that the content of tin (Sn) is 50 atomic% or more, 70 atomic% or more, and 90 atomic% or more. At this time, the element other than tin may be copper. For example, the content of tin (Sn) in the second plating layer 132 may be 50 atomic% or more. For example, the second plating layer 132 may have a tin (Sn) content of 70 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132 may be 90 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132 may be 95 atomic% or more. For example, the second plating layer 132 may have a tin (Sn) content of 98 atomic% or more.

The plating layer according to the embodiment can prevent electrochemical migration resistance due to the diffusion phenomenon of Cu / Sn, and can prevent short-circuit defects due to metal growth.

However, the present invention is not limited thereto. The plating layer 130 may be formed of Ni / Au alloy, Au, electroless nickel immersion gold (ENIG), Ni / Pd alloy, Solderability Preservative, OSP).

The first plating layer 131 may have a thickness corresponding to the second plating layer 132 or may have different thicknesses. The total thickness of the first plating layer 131 and the second plating layer 132 may be 0.3 탆 to 1 탆. The total thickness of the first plating layer 131 and the second plating layer 132 may be 0.3 탆 to 0.7 탆. The total thickness of the first plating layer 131 and the second plating layer 132 may be 0.3 탆 to 0.5 탆. The plating layer of any one of the first plating layer 131 and the second plating layer 132 may have a thickness of 0.05 탆 to 0.15 탆 or less. For example, the plating layer of any one of the first plating layer 131 and the second plating layer 132 may have a thickness of 0.07 μm to 0.13 μm or less.

The protective layer 140 may be partially disposed on the wiring pattern layer 120. For example, the protective layer 140 may be disposed on the plating layer 130 on the wiring pattern layer 120. The protective layer 140 may cover the plating layer 130 to prevent damage or de-filming due to oxidation of the wiring pattern layer 120 and the plating layer 130.

The protective layer 140 is formed on the wiring pattern layer 120 and / or the plating layer 130 so as to be electrically connected to the display panel 30, the main board 40, the first chip C1 or the second chip C2. May be partially disposed in an area other than the area to be connected to the &lt; RTI ID = 0.0 &gt;

Accordingly, the protective layer 140 may be partially overlapped with the wiring pattern layer 120 and / or the plating layer 130.

The area of the protective layer 140 may be smaller than the area of the substrate 110. The protective layer 140 may be disposed in a region other than an end of the substrate, and may include a plurality of open regions.

The passivation layer 140 may include a first open region OA1 having the same shape as a hole. The first open area OA1 may be a non-disposition region of the protection layer 140 in which the wiring pattern layer 120 and / or the plating layer 130 are electrically connected to the first chip C1.

The passivation layer 140 may include a second open region OA2 having the same shape as a hole. The second open region OA2 may be a non-disposition region of the protection layer 140 for electrically connecting the wiring pattern layer 120 and / or the plating layer 130 to the second chip C2 . Accordingly, in the second open area OA2, the plating layer 130 may be exposed to the outside.

In the second open area OA2, the content of copper in the plating layer 130 may be 50 atomic% or more. For example, the content of copper in the plating layer 130 may be 60 atomic% or more. For example, the content of copper in the plating layer 130 may be 60 atom% to 80 atom%. In detail, the content of copper in the first plating layer 131 measured in the second open area OA2 may be 60 atom% to 80 atom%.

The protective layer 140 may not be disposed on the conductive pattern portion to be electrically connected to the main board 40 or the display panel 30. The embodiment may include a third open area OA3 that is a non-layout area of the protection layer 140 on the main board 40 or the conductive pattern part to be electrically connected to the display panel 30. [ Accordingly, in the third open area OA3, the plating layer 130 may be exposed to the outside.

In the third open area OA3, the content of copper in the plating layer 130 may be 50 atomic% or more. Alternatively, in the third open area OA3, the content of copper in the plating layer 130 may be less than 50 atomic%. The third open area OA3 may be located outside the first open area OA1. Also, the third open area OA3 may be located on the outer side of the substrate than the second open area OA2.

The first open area OA1 and the second open area OA2 may be located in a central area of the substrate than the third open area OA3.

The protective layer 140 may be disposed in the bending region. Accordingly, the protective layer 140 can disperse stress that may occur during bending. Therefore, the reliability of the all-in-one chip-on-film flexible circuit board according to the embodiment can be improved.

The passivation layer 140 may include an insulating material. The protective layer 140 may include various materials that can be applied to protect the surface of the conductive pattern portion and then cured by heating. The protective layer 140 may be a resist layer. For example, the protective layer 140 may be a solder resist layer containing an organic polymer material. For example, the protective layer 140 may include an epoxy acrylate resin. In detail, the protective layer 140 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic based monomer, or the like. However, the present invention is not limited thereto, and the protective layer 140 may be a photo-solder resist layer, a cover-lay, or a polymer material.

The thickness of the protective layer 140 may be in the range of 1 탆 to 20 탆. The thickness of the protective layer 140 may be between 1 탆 and 15 탆. For example, the thickness of the protective layer 140 may be 5 to 20 占 퐉. If the thickness of the protective layer 140 is more than 20 占 퐉, the thickness of the all-in-one chip-on-film flexible circuit board may increase. If the thickness of the protective layer 140 is less than 1 탆, the reliability of the conductive pattern portion included in the all-in-one chip-on-film flexible circuit board may be reduced.

Referring to FIG. 3B, a chip package including a flexible circuit board 100 for a cross-sectional all-in-one chip-on film according to an embodiment will be described.

The flexible circuit board 100 for a cross-sectional all-in-one chip-on-film according to the embodiment includes a substrate 110, a conductive pattern portion CP disposed on one surface of the substrate, And a protective portion PP formed by disposing a layer 140 thereon.

The conductive pattern part CP may include the wiring pattern layer 120 and the plating layer 130. [

The protective portion PP may not be disposed on a region other than one region on the conductive pattern portion CP. Accordingly, the substrate 110 between the conductive pattern CP and the conductive pattern CP spaced apart from the conductive pattern CP may be exposed on a region other than the one region on the conductive pattern CP. The first connection part 70 and the second connection part 80 may be respectively disposed on a region other than the one region on the conductive pattern CP. In detail, the first connection part 70 and the second connection part 80 may be respectively disposed on the upper surface of the conductive pattern part CP in which the protection part PP is not disposed.

The first connection part 70 and the second connection part 80 may have different shapes. For example, the first connection part 70 may have a hexahedral shape. In detail, the cross-section of the first connection portion 70 may include a rectangular shape. More specifically, the cross section of the first connection portion 70 may include a rectangular or square shape. For example, the second connection portion 80 may include a spherical shape. The cross section of the second connection portion 80 may include a circular shape. Alternatively, the second connection portion 80 may include a partially or entirely rounded shape. For example, the cross-sectional shape of the second connection portion 80 may be a flat surface on one side and a curved surface on the other side opposite to the one side surface.

The first connection part 70 and the second connection part 80 may have different sizes. The first connection part 70 may be smaller than the second connection part 80. [

The widths of the first connection portion 70 and the second connection portion 80 may be different from each other. For example, the width D1 between both sides of one first connection portion 70 may be smaller than the width D2 between both sides of one second connection portion 80. [

The first chip C1 may be disposed on the first connection part 70. [ The first connection portion 70 may include a conductive material. The first connection part 70 includes the first chip C1 disposed on the upper surface of the first connection part 70 and the conductive pattern part CP disposed on the lower surface of the first connection part 70, Can be electrically connected.

And the second chip C2 may be disposed on the second connection unit 80. [ The second connection portion 80 may include a conductive material. The second connection part 80 is electrically connected to the conductive pattern part CP disposed on the lower surface of the second chip C2 and the second connection part 80 disposed on the upper surface of the second connection part 80, Can be electrically connected.

The first chip C1 and the second chip C2 of different types may be disposed on the same surface of the flexible circuit board 100 for a cross-sectional all-in-one chip-on-film according to the embodiment. In detail, one of the first chip C1 and the plurality of second chips C2 may be disposed on the same surface of the flexible circuit board 100 for a cross-sectional all-in-one chip-on-film according to the embodiment. Thus, the efficiency of the chip packaging process can be improved.

The first chip C1 may include a drive IC chip.

The second chip C2 may refer to a chip other than a drive IC chip. The second chip C2 may refer to various chips including a socket or a device other than a drive IC chip. For example, the second chip C2 may be at least one of a diode chip, a power IC chip, a touch sensor IC chip, a multi layer ceramic condenser (MLCC) chip, a ball grid array (BGA) chip, .

The plurality of second chips (C2) disposed on the all-in-one chip-on-film flexible circuit board (100) may include at least one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, Can be placed. For example, a plurality of MLCC chips may be disposed on a flexible circuit board 100 for an all-in-one chip-on film.

The second chip C2 may include at least two of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor. That is, a plurality of second chips C2a and C2b of different kinds may be disposed on the flexible circuit board 100 for an all-in-one chip-on-film. For example, a second chip (C2a) of any one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor and a diode chip, A power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor.

In detail, a plurality of second chips (C2a) of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor can be arranged on the all-in-one chip- And a plurality of second chips (C2b) different from any one of the diode chip, the power IC chip, the touch sensor IC chip, the MLCC chip, the BGA chip, and the chip capacitor may be disposed. For example, the MLCC chip C2a and the plurality of power IC chips C2b may be provided on the all-in-one chip-on-film flexible circuit board 100. [ For example, a plurality of MLCC chips C2a and a plurality of diode chips C2b may be formed on a flexible circuit board 100 for an all-in-one chip-on-film. For example, the flexible circuit board 100 for an all-in-one chip-on-film may include a plurality of MLCC chips C2a and a plurality of BGA chips C2b.

It is needless to say that the second chip is not limited to two types in the embodiment, and various chips other than the driving IC chip may be included in the second chip.

One end of the flexible circuit board 100 for the all-in-one chip-on-film may be connected to the display panel 30. One end of the all-in-one chip-on-film flexible circuit board 100 may be connected to the display panel 30 by an adhesive layer 50. The display panel 30 is disposed on the upper surface of the adhesive layer 50 and the flexible circuit board 100 for the all-in-one chip on film may be disposed on the lower surface of the adhesive layer 50. Accordingly, the display panel 30 and the flexible circuit board 100 for the all-in-one chip-on-film can be adhered upward and downward with the adhesive layer 50 interposed therebetween.

The other end opposite to the one end of the all-in-one chip-on-film flexible circuit board 100 may be connected to the main board 40. The other end opposite to the one end of the all-in-one chip-on-film flexible circuit board 100 may be connected to the main board 40 by an adhesive layer 50. The main board 40 is disposed on the upper surface of the adhesive layer 50 and the flexible circuit board 100 for the all-in-one chip on film may be disposed on the lower surface of the adhesive layer 50. Accordingly, the main board 40 and the flexible circuit board 100 for the all-in-one chip-on-film can be adhered up and down with the adhesive layer 50 interposed therebetween.

The adhesive layer 50 may include a conductive material. The adhesive layer 50 may be one in which the conductive particles are dispersed in the adhesive material. For example, the adhesive layer 50 may be an anisotropic conductive film (ACF).

Accordingly, the adhesive layer 50 transmits electric signals between the display panel 30, the flexible circuit board 100 for the all-in-one chip-on-film and the main board 40, You can connect.

4 to 6, a manufacturing process of a chip package including a flexible circuit board for an all-in-one chip-on-film according to the embodiment will be described.

4, a conductive pattern portion CP including a pattern pattern layer 120, a first plating layer 131 and a second plating layer 132, and a protective layer 140 are formed on one surface of a substrate 100, So that a flexible circuit board for an all-in-one chip-on film can be prepared.

At this time, the passivation layer 140 may include a first open area OA1 and a second open area OA2.

And the second plating layer 132 may be exposed in the first open area OA1. In addition, the second plating layer 132 may be exposed in the second open area OA2.

5 and 6, a first step of disposing the first chip C1 and a second step of disposing the second chip C2 on the flexible circuit board for an all-in-one chip-on-film according to the embodiment will be described do.

First, the step of disposing the first chip (C1) on the flexible circuit board for all-in-one chip-on film according to the embodiment will be described.

The first connection portion 70 may be disposed in the first open area OA1 of the flexible circuit board for an all-in-one chip-on-film according to the embodiment.

The content of tin (Sn) in the second plating layer 132a in the first open region OA1 may be 50 atomic% or more. In the first open area OA1, the second plating layer 132a may include pure tin. For example, the content of tin (Sn) in the second plating layer 132a in the first open area OA1 may be 70 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132a in the first open area OA1 may be 90 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132a in the first open area OA1 may be 95 atomic% or more. For example, the content of tin (Sn) in the second plating layer 132a in the first open area OA1 may be 98 atomic% or more. When the content of tin (Sn) in the second plating layer 132 in the first open region OA1 is less than 50 atomic%, the second plating layer 132 and the first chip C1 may be difficult to connect. When the content of tin (Sn) in the second plating layer 132 in the first open area OA1 is less than 50 at.%, The second plating layer 132 and the first The connection by the bonding of the chip C1 may be difficult.

The first connection part 70 may include gold (Au). The first connection part 70 may be a gold bump.

In order to dispose one first chip C1 on the flexible circuit board for an all-in-one chip-on-film according to the embodiment, a plurality of the first connection portions 70 may be formed on the first chip C1 and the second plating layer 132a, As shown in FIG.

The second plating layer 132 of the first open area OA1 has a tin (Sn) content of 50 atomic% or more, and thus has excellent adhesion properties to the first connection part 70 including gold (Au) can do. The chip package including the all-in-one chip-on-film flexible circuit board according to the embodiment can have excellent electrical connection between the conductive pattern and the first chip (C1) through the first connection portion (70) .

Next, the step of disposing the second chip (C2) on the flexible circuit board for all-in-one chip-on film according to the embodiment will be described.

The second connection portion 80 is disposed in the second open area OA2 of the all-in-one chip-on-film flexible circuit board according to the embodiment.

In order to arrange the second chip C2 on the flexible circuit board for an all-in-one chip-on-film according to the embodiment, only the portion corresponding to the region where the second connection portion 80 is arranged via the mask M, ). In detail, the embodiment can selectively supply heat to a region where the second connection portion 80 for connecting the second chip C2 is disposed through an optional reflow process.

In detail, the flexible circuit board for an all-in-one chip-on-film according to the embodiment can be manufactured by a selective reflow process even when the second chip C2 is disposed after the first chip C1 is mounted Partial heat supply may be possible.

That is, the fabrication process according to the embodiment can prevent heat from being exposed to the first open region OA through the mask. Thus, the second plating layer disposed in the first open area OA can be prevented from being transformed from pure tin into an alloy layer of tin and copper by heat supply. Thus, even when the first chip C1 and the second chip C2, which are different from each other, are mounted on the flexible circuit board 100 for one all-in-one chip-on film, the second plating layer 132a may be 50 atomic% or more, and the assembly of the driving IC chip may be excellent.

On the other hand, a hole of a mask may be disposed in an area corresponding to the second open area OA2. Accordingly, the plating layer exposed by heat in the second open area OA2 may be denatured as an alloy layer of tin and copper.

In detail, a part of the second plating layer 132 exposed by the heat through the hole of the mask may further undergo diffusion of tin / copper. Accordingly, the content of tin (Sn) in the second plating layer 132b in the second open region OA2 may be less than 50 atomic%. In the second open area OA2, the second plating layer 132b may be an alloy layer of copper (Cu) and tin (Sn).

The second connection portion 80 may include a metal other than Au. Accordingly, even when the second plating layer 132b located below the second connection unit 80 is not pure tin, the second connection unit 80 can be manufactured with excellent performance in assembly with the second chip C2 can do. In addition, the second connection portion 80 may include a metal other than gold (Au), thereby reducing the manufacturing cost.

For example, the second connection part 80 may be formed of at least one selected from the group consisting of Cu, Sn, Al, Zn, In, Pb, Sb, ), Silver (Ag), and nickel (Ni).

The second connection portion 80 may be a solder bump. The second connection unit 80 may be a solder ball. The solder ball can be melted at the temperature of the reflow process.

In order to dispose one second chip C2 on the flexible circuit board for an all-in-one chip-on-film according to the embodiment, a plurality of the second connecting portions 80 may be formed on the second chip C2 and the second plating layer 132b, As shown in FIG.

At the temperature of the reflow process, the second chip C2 can be bonded with the second plating layer 132b on the second open area OA2 through the second connection part 80 with good bonding.

The flexible circuit board for an all-in-one chip-on-film according to the embodiment is excellent in the connection of the first chip C1 through the first connection portion 70 in the first open region and the second connection portion 80 The connection of the second chip C2 can be excellent.

The flexible circuit board for an all-in-one chip-on-film according to the embodiment may include a plating layer having a different Sn content in the first open area OA1 and the second open area OA2, The assembly performance is excellent, and the assembling performance of the second chip (C2) can be excellent.

As in the comparative example, after the first chip is mounted on the first printed circuit board and the second chip is mounted on the second printed circuit board, the first printed circuit board having the first chip and the second chip are provided In the case of bonding a second printed circuit board to an adhesive layer, there may be no problem caused by thermal degeneration of the first chip.

However, when the first and second chips, which are different from each other, are mounted on one substrate as in the embodiment, the second plating layer is deformed by heat in the first open region of the protective layer for connecting the first chip, There is a problem that it is difficult to assemble the first chip by the first connecting portion.

In order to solve such a problem, the inventors arranged the first chip and the second chip sequentially on the flexible circuit board for all-in-one chip-on film through an optional reflow process. Accordingly, the flexible circuit board for an all-in-one chip-on-film and the chip package including the same according to the embodiment can reduce the content of tin in the second plated layer in the first open region and the content of tin in the second plated layer in the first open region, May be different. Therefore, the chip package including the flexible circuit board for an all-in-one chip-on-film according to the embodiment can provide excellent electrical connection between the first chip C1 and the second chip C2 which are different from each other.

The second plating layer including pure tin in the first open region can be stably mounted on the first chip, which is a driving IC chip, through a first connection portion including gold (Au). Also, the second plating layer including the copper and tin alloy layer in the second open region may be a diode chip, a power IC chip, a touch sensor IC chip, an MLCC A stable mounting of a second chip, which is at least one of a chip, a BGA chip, and a chip capacitor, may be possible.

Accordingly, the flexible circuit board for all-in-one chip-on-film and the chip package including the all-in-one chip-on-film according to the embodiments can be mounted on one all-in-one flexible circuit board with excellent yields of first and second chips .

In addition, since a plurality of existing printed circuit boards can be replaced by a flexible circuit board for one all-in-one chip-on-film, miniaturization and thinning of the all-in-one chip-on-film flexible circuit board for connecting the display panel and the main board have.

Therefore, the electronic device including the all-in-one chip-on-film flexible circuit board of the embodiment can easily mount various functional parts such as a camera module and an iris recognition module. Further, the electronic device including the flexible circuit board for an all-in-one chip-on film of the embodiment can expand the battery space.

In addition, the flexible circuit board for all-in-one chip-on-film can be manufactured through a roll-to-roll process, and chip mounting on the all-in-one chip-on-film flexible circuit board can be achieved through a selective reflow process, The manufacturing yield can be improved.

As described above, the first chip, the second chip, the display panel, and the main board may all be connected to the same side of the chip package including the flexible circuit board for a cross-sectional all-in-one chip-on film.

Such a flexible all-in-one chip-on-film flexible circuit board may be difficult to implement a circuit having high resolution (QHD).

2. Description of the Related Art Recently, various electronic devices having a display portion such as a smart phone, a television, a monitor, an electronic paper, and a wearable device are required to realize a high resolution display.

Accordingly, the flexible circuit board for an all-in-one chip-on film according to the embodiment can include a flexible circuit board for a three-layer all-in-one chip-on film.

A flexible circuit board for a three-layer all-in-one chip-on film can be disposed on at least three layers on a substrate in order to realize a high-resolution display.

In other words, the flexible circuit board includes at least two substrates, and the conductive pattern layer includes a conductive pattern layer disposed on an upper surface of the substrate positioned on top of the at least two substrates, a conductive pattern layer disposed on a lower surface of the substrate disposed below, A pattern layer, and a conductive pattern layer disposed between the two substrates.

A flexible circuit board for a three-layer all-in-one chip-on film according to an embodiment will be described with reference to Figs. 7, 8A, 8B, 9, and 10. Fig. The same components as those of the above-described flexible circuit board for a cross-sectional all-in-one chip-on film are given the same drawings. The thickness of each component, the material of each component, etc., are not included.

Figs. 7, 8A, 8B, and 9 are various cross-sectional views of a three-layer all-in-one chip-on-film flexible circuit board according to the embodiment centering on the mounting of the first chip. That is, Figs. 7, 8A, 8B, and 9 are views for explaining various cross-sectional structures of the second conductive pattern portion for mounting the first chip.

Referring to FIGS. 7, 8A, 8B, 9 and 10, the flexible circuit board 100 for an all-in-one chip on film according to the embodiment includes a three- Layer all-in-one chip-on film.

A flexible circuit board 100 for an all-in-one chip on film according to an embodiment includes a substrate 110 including a first substrate 111 and a second substrate 112, 111 may include a wiring pattern layer 120 disposed between the upper surface of the second substrate 112 and the first substrate 111 and the second substrate 112.

A wiring pattern layer 120 disposed on the lower surface of the first substrate 111 and a wiring pattern layer 120 disposed on the upper surface of the second substrate 112 are respectively formed with a plating layer 130 and a protective layer 140 may be disposed.

The flexible circuit board 100 includes a wiring pattern layer 120 formed on a first substrate 111 and a second substrate 111 formed on the first substrate 111 so as to cover the wiring pattern layer 120. [ The wiring pattern layer 120, the plating layer 130 and the protective layer 140 are disposed on the upper surface of the second substrate 112. Then, the lower surface of the first substrate 111 The wiring pattern layer 120, the plating layer 130, and the protective layer 140 can be disposed.

Hereinafter, the lower surface of the first substrate 111 and the upper surface of the second substrate 112 may be referred to as the upper surface and the lower surface of the substrate 110 or one surface of the substrate 110, respectively.

That is, the upper wiring pattern layer, the upper plating layer, and the upper protective layer may be disposed on one surface of the substrate 110 according to the embodiment, and the lower wiring pattern layer, the lower plating layer, Can be arranged. A central wiring pattern layer may be disposed in the substrate 110, that is, between the first substrate 111 and the second substrate 112.

The upper wiring pattern layer may include a metal material corresponding to the central wiring pattern layer and the lower wiring pattern layer. Thus, the process efficiency can be improved. However, it should be understood that the embodiments are not limited thereto and may include other conductive materials.

The thickness of the upper wiring pattern layer, the thickness of the center wiring layer, and the thickness of the lower wiring pattern layer may correspond to each other. Thus, the process efficiency can be improved. Meanwhile, since the upper wiring pattern layer and the lower wiring pattern layer are disposed on the outer surface of the substrate, they are exposed to the outside, and the central wiring pattern layer is protected by the first substrate 111 and the second substrate 112 .

Therefore, the plating layer and the protection layer may be disposed on the upper wiring pattern layer and the lower wiring pattern layer, respectively, and the plating layer and the protection layer may not be disposed on the central wiring pattern layer. At this time, an upper plating layer may be disposed on the upper wiring pattern layer, and the lower plating layer may be disposed on the lower wiring pattern layer.

On the other hand, the upper plating layer may include a metal material corresponding to the lower plating layer. Thus, the process efficiency can be improved. However, it should be understood that the embodiments are not limited thereto and may include other conductive materials.

The thickness of the upper plating layer may correspond to the thickness of the lower plating layer. Thus, the process efficiency can be improved.

The substrate 110 may include a plurality of through holes. The substrate 110 may include a plurality of through holes. The plurality of through holes of the substrate 110 may be formed individually or simultaneously by a mechanical process or a chemical process. For example, the plurality of through holes of the substrate 110 may be formed by a drilling process or an etching process. For example, the through-holes of the substrate may be formed through laser punching and desmearing processes. The desmearing step may be a step of removing the polyimide smear attached to the inner surface of the through hole. By the desmearing process, the inner surface of the polyimide substrate may have a slope similar to a straight line.

At this time, the plurality of through holes may pass through both the first substrate 111 and the second substrate 112 constituting the substrate 110, may penetrate only the first substrate 111, Only the second substrate 112 may be penetrated. Here, the through hole may be referred to as a via hole.

The wiring pattern layer 120, the plating layer 130, and the protective layer 140 may be disposed on the substrate 110. In detail, the wiring pattern layer 120, the plating layer 130, and the protective layer 140 may be sequentially arranged on the both surfaces of the substrate 110. The wiring pattern layer 120 may be disposed between the first substrate 111 and the second substrate 112 constituting the substrate 110.

The wiring pattern layer 120 may be formed by at least one of evaporation, plating, and sputtering.

For example, a wiring layer for forming a circuit can be formed by electrolytic plating after sputtering. For example, the wiring layer for forming the circuit may be a copper plated layer formed by electroless plating. Alternatively, the wiring layer may be a copper-plated layer formed by electroless plating and electrolytic plating.

Next, a patterned wiring layer can be formed on both sides of the flexible circuit board, that is, on the upper and lower surfaces of the flexible circuit board through lamination of a dry film on the wiring layer, and exposure, development and etching. Thus, the wiring pattern layer 120 can be formed.

Vias (V1, V2, V3, V4, V5) passing through the substrate 110 may be filled with a conductive material. The conductive material filled in the via hole may be a conductive material corresponding to or different from the wiring pattern layer 120. For example, the conductive material filled in the via hole may be copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), molybdenum (Mo). Gold (Au), titanium (Ti), and alloys thereof. The electrical signal of the second conductive pattern CP2 on the upper surface of the second substrate 112 is transmitted through the conductive material filled in the via hole to the third conductive pattern portion CP2 between the first substrate 111 and the second substrate (CP3) on the lower surface of the first substrate 111 and the first conductive pattern CP1 on the lower surface of the first substrate 111.

Next, a plating layer 130 may be formed on the wiring pattern layer 120 constituting the first and second conductive pattern portions CP1 and CP2.

Thereafter, the protective portion PP can be screen-printed on the first and second conductive pattern portions CP1 and CP2.

The first conductive pattern part CP1 and the second conductive pattern part CP2 may include the plating layer 130 in addition to the wiring pattern layer 120. [ However, the third conductive pattern portion CP3 may include only the wiring pattern layer 120.

Hereinafter, the relationship between the wiring pattern layer 120 constituting the first conductive pattern part CP1 and the second conductive pattern part CP2 and the plating layer 130 will be described. At this time, the wiring pattern layer of the first conductive pattern portion CP1 may be referred to as a lower wiring pattern layer, and the wiring pattern layer constituting the second conductive pattern portion CP2 may be referred to as an upper wiring pattern layer. Upper and lower

 The areas of the upper and lower wiring pattern layers 120 may correspond to or different from each other with respect to the plating layer 130. The area of the first plating layer 131 may correspond to the area of the second plating layer 132 or may be different from each other.

Referring to FIG. 7, the areas of the upper and lower wiring pattern layers 120 may correspond to the plating layer 130. The area of the first plating layer 131 may correspond to the area of the second plating layer 132.

Referring to FIG. 8, the areas of the upper and lower wiring pattern layers 120 may be different from the thickness of the plating layer 130. The area of the upper and lower wiring pattern layers 120 may correspond to the area of the first plating layer 131. The area of the first plating layer 131 may be different from the area of the second plating layer 132. For example, the area of the first plating layer 131 may be larger than the area of the second plating layer 132.

Referring to FIG. 9, the areas of the upper and lower wiring pattern layers 120 may be different from those of the plating layer 130.

10, the area of the upper wiring pattern layer 120 on the upper surface of the second substrate 112 is different from that of the plating layer 130, The area of the layer 120 may correspond to the plating layer 130.

The protective layer 140 may be disposed in direct contact with the substrate 110 or in direct contact with the wiring pattern layer 120 or in direct contact with the first plating layer 131, And may be disposed in direct contact with the second plating layer 132.

7, the first plating layer 131 is disposed on the upper and lower wiring pattern layers 120, the second plating layer 132 is formed on the first plating layer 131, The protective layer 140 may be partially disposed on the second plating layer 132.

8A and 8B, the first plating layer 131 is disposed on the upper and lower wiring pattern layers 120 and the protective layer 140 is partially formed on the first plating layer 131 . The second plating layer 132 may be disposed in a region other than the region where the protective layer 140 is disposed on the plating layer 131.

The first plating layer 131 contacting the lower surface of the protective layer 140 may be an alloy layer of copper and tin. The second plating layer 132 contacting the side surface of the protective layer 140 may include pure tin. Accordingly, it is possible to prevent the formation of a whisker from the protective layer due to the formation of the cavity between the protective layer 140 and the first plating layer 131, to increase the adhesion of the protective layer have. Therefore, the embodiment can include a two-layer plated layer, thereby providing an electronic device with high reliability.

In the case where only a single tin plating layer 131 is disposed on the upper and lower wiring pattern layers 120 and the protective layer 140 is disposed on one tin plating layer 131, The copper may be diffused in the tin plating layer 131 as the tin plating layer 131 is heated at the time of thermal curing of the tin plating layer 131. Accordingly, since the tin plating layer 131 can be an alloy layer of tin and copper, the first chip having gold bumps can not be mounted firmly. Therefore, the plating layer 130 according to the embodiment requires a first plating layer 131 and a second plating layer 132 which can increase the concentration of tin continuously as the distance from the substrate increases.

Referring to FIG. 9, the first plating layer 131 is disposed on the upper and lower wiring pattern layers 120, and the protective layer 140 is partially disposed on the first plating layer 131 . The second plating layer 132 may be disposed in a region other than the region where the protective layer 140 is disposed on the plating layer 131.

At this time, the upper and lower wiring pattern layers 120 may include a first wiring pattern layer 121 and a second wiring pattern layer 122. That is, a plurality of wiring pattern layers may be disposed on the substrate.

Although not shown in the drawing, a metal layer (not shown) for improving adhesion between the substrate 110 and the upper, lower, and central wiring pattern layers 120 is formed between the substrate 110 and the upper, And a seed layer. At this time, the metal seed layer can be formed by sputtering. The metal seed layer may comprise copper.

In other words, each of the upper, lower and central wiring pattern layers may include the first wiring pattern layer 121 and the second wiring pattern layer 122.

The first wiring pattern layer 121 and the second wiring pattern layer 122 may correspond to each other or may be formed in different processes.

The first wiring pattern layer 121 may be formed by sputtering copper to a thickness of 0.1 탆 to 0.5 탆. The first wiring pattern layer 121 may be disposed on the top, bottom, and inner surfaces of the through holes. At this time, since the thickness of the first wiring pattern layer 121 is thin, the inner surfaces of the through holes can be spaced apart from each other.

Next, the second wiring pattern layer 122 may be disposed on the first wiring pattern layer 121. In addition, the second wiring pattern layer 122 may be entirely filled in the through hole by plating.

Since the first wiring pattern layer 121 is formed by sputtering, the first wiring pattern layer 121 has an excellent adhesion to the substrate 110 or the metal seed layer. However, since the manufacturing cost is high, The second wiring pattern layer 122 by plating is formed on the second wiring pattern layer 121, thereby reducing the manufacturing cost. Since the second wiring pattern layer 122 can be disposed on the first wiring pattern layer 121 and copper can be filled in the via hole without filling the through hole of the substrate separately with the conductive material, Can be improved. In addition, it is possible to prevent formation of voids in the via hole, thereby providing a highly reliable all-in-one flexible circuit board for chip-on-film and an electronic device including the same.

Referring to FIG. 10, a plurality of protective layers 140 may be disposed on the upper surface of the second substrate 112. The protective layer may include a first protective layer 141 and a second protective layer 142.

For example, a first protective layer 141 is partially disposed on the upper surface of the second substrate 112, and the upper wiring pattern layer 120 is formed on a region other than the region where the protective layer 141 is disposed. Can be arranged.

The second passivation layer 142 may be disposed on the passivation layer 141. The second passivation layer 142 covers the first passivation layer 141 and the upper wiring pattern layer 120 and may be disposed in a region larger than the first passivation layer 141.

The protective layer 142 may be disposed on a region corresponding to the protective layer 141 while covering an upper surface of the first protective layer 141. The width of the second protective layer 142 may be greater than the protective layer 141. Accordingly, the lower surface of the second passivation layer 142 may contact the upper wiring pattern layer 120 and the first passivation layer 141. Accordingly, the second protective layer 142 can relieve stress concentration at the interface between the first passivation layer 141 and the wiring pattern layer 120. Therefore, it is possible to reduce the occurrence of a film or crack that may occur when the flexible circuit board for an all-in-one chip-on-film according to the embodiment is bent.

A plating layer 130 constituting the second conductive pattern CP2 may be disposed in an area other than the area where the second protective layer 142 is disposed. The first plating layer 131 is disposed on the upper wiring pattern layer 120 in a region other than the region where the second protective layer 142 is disposed and the first plating layer 131 is formed on the first plating layer 131 The second plating layer 132 may be disposed in order.

The lower wiring pattern layer 120 may be disposed on the lower surface of the first substrate 111. The plating layer 130 may be disposed on the lower wiring pattern layer 120. A protective layer 140 may be partially disposed on the plating layer 130.

The widths of the protective layer disposed on the lower surface of the first substrate 111 and the protective layer disposed on the upper surface of the second substrate 112 may be different from or different from each other.

Although a plurality of protective layers are disposed on only the upper surface of the second substrate 112 in the drawing, the present invention is not limited thereto, and a plurality of protective layers may be disposed on the lower surface of the first substrate 111 . It should be noted that a plurality of or only one protective layer may be disposed on the lower surface of the first substrate 111 or the upper surface of the second substrate 112.

In addition, it is a matter of course that the arrangement structure of the protective layer can be variously arranged by combining the structures of the conductive pattern part and the protective part according to at least one of the structures shown in FIGS. 7, 8A, 9,

A first chip C1 mounted on a flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment, a first chip C1 mounted on a flexible circuit board 100, The connection relationship between the panel 30 and the main board 40 will be described.

A flexible circuit board 100 for a three-layer all-in-one chip-on-film according to an embodiment includes a substrate 100 including a first substrate 111 and a second substrate 112 including through-holes; A lower wiring pattern layer 120 disposed on the lower surface of the first substrate 111; An upper wiring pattern layer 120 disposed on the upper surface of the second substrate 112; A central wiring pattern layer 120 disposed between the first substrate 111 and the second substrate 112; A first plating layer 131 disposed on the upper and lower wiring pattern layers 120; A second plating layer 132 disposed on the first plating layer 131; And a protective layer 140 partially disposed on the upper and lower wiring pattern layers.

At this time, the protective layer 140 may be disposed on the first substrate 111 and the second substrate 112, and may be the protective portion PP. The first conductive pattern portion CP1 and the second conductive pattern portion CP2 may be exposed to the outside in a region other than the protective portion PP. That is, the first and second conductive pattern portions CP1 and CP2 are electrically connected to the first chip C1 and the display panel (not shown) in an area where the protective portion is not disposed on the open region, 30 and the main board 40 electrically or indirectly.

The lead pattern portion and the test pattern portion of the flexible circuit board for a three-layer all-in-one chip-on-film according to the embodiment may not overlap with the protective portion. That is, the lead pattern portion and the test pattern portion may refer to first and second conductive pattern portions CP1 and CP2 located in an open region that is not covered by the protective layer. According to the function, the lead pattern portion and the test pattern portion Can be distinguished.

The lead pattern part may mean a conductive pattern part for connecting with the first chip, the second chip, the display panel, or the main board.

The test pattern unit may refer to a conductive circuit board for all-in-one chip-on-film and a conductive pattern unit for checking whether a product of the chip package including the same is defective or not.

The lead pattern portion can be distinguished as an inner lead pattern portion and an outer lead pattern portion depending on the position. One region of the second conductive pattern portion CP2 that is relatively close to the first chip C1 and is not overlapped by the protective layer may be represented by the inner lead pattern portion. One region of the first and second conductive pattern portions CP1 and CP2 that are relatively far from the first chip C1 and are not overlapped by the protective layer may be represented by an outer lead pattern portion.

7, 8A, 8B, 9, 11, 12A and 12B, the flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment includes a first inner lead pattern portion I1 The second inner lead pattern portion I2, the third inner lead pattern portion I3, the fourth inner lead pattern portion I4 and the fifth inner lead pattern portion I5.

The flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment includes a first outer lead pattern portion O1, a second outer lead pattern portion O2, a third outer lead pattern portion O3, And an outer lead pattern portion O4.

The flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment may include a first test pattern portion T1 and a second test pattern portion T2.

On one surface (more specifically, the upper surface of the second substrate 112) of the flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment, the first inner lead pattern portion I1, The pattern portion I2, the third inner lead pattern portion I3, the fourth inner lead pattern portion I4, the first outer lead pattern portion O1, and the second outer lead pattern portion O2, Can be disposed.

On the other surface (specifically, the lower surface of the first substrate 111) opposite to the one surface of the flexible circuit board 100 for the three-layer all-in-one chip-on-film according to the embodiment, the fifth inner lead pattern portion I5, The third outer lead pattern portion O3, the fourth outer lead pattern portion O4, the first test pattern portion T1 and the second test pattern portion T2.

The first chip C1 disposed on one surface of the flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment is connected to the first inner lead pattern portion I1 through the first connection portion 70, The second inner lead pattern portion I2, the third inner lead pattern portion I3, or the fourth inner lead pattern portion I4.

The first sub connecting portion 71, the second sub first connecting portion 72, the third sub first connecting portion 73, and the fourth sub connecting portion 71, depending on the position and / 1 &lt; / RTI &gt;

The first chip C1 disposed on one surface of the flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment is connected to the first inner lead pattern portion 100 through the first sub- (I1).

The first inner lead pattern portion I1 may transmit an electrical signal to the first outer lead pattern portion O1 adjacent to the second via hole V2 along the upper surface of the substrate 110. [ The second via hole V2 and the first outer lead pattern portion O1 may be electrically connected. That is, the first inner lead pattern portion I1 and the first outer lead pattern portion O1 may have one end and one end of the conductive pattern portion extending in one direction.

For example, the main board 40 may be connected to the first outer lead pattern portion O1 through an adhesive layer 50. [ Accordingly, a signal transmitted from the first chip can be transmitted to the main board 40 through the first inner lead pattern portion I1 and the first outer lead pattern portion O1.

The first inner lead pattern portion I1 is electrically connected to the second via hole V2 along the upper surface of the second substrate 112 and electrically connected to the second via hole V2 through the conductive material filled in the second via hole V2. An electrical signal can be transmitted along the lower surface of the first substrate 111 to the third outer lead pattern portion O3 adjacent to the second via hole V2. The second via hole V2 may be electrically connected to the third outer lead pattern part O3. Accordingly, although not shown in the drawings, it is needless to say that the main board 40 may be electrically connected to the third outer lead pattern portion O3 through the adhesive layer 50. [

The first chip C1 disposed on one surface of the flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment is connected to the second inner lead pattern portion 100 via the second sub first connection portion 72, (I2).

The second inner lead pattern portion I2 disposed on the upper surface of the substrate 110 is electrically connected to the substrate via the conductive material filled in the first via hole V1 located below the second inner lead pattern portion 12, It is possible to transmit an electrical signal to the fifth inner lead pattern portion I5 adjacent to the first via hole V1 and the first test pattern portion T1 along the lower surface of the first via hole 110. [ The first via hole V1, the first test pattern portion T1, and the fifth inner lead pattern portion I5 may be electrically connected to each other on the lower surface of the substrate.

The display panel 30 may be attached to the fifth inner lead pattern portion I5 and the fourth outer lead pattern portion 04.

The first test pattern portion T1 can confirm the failure of an electrical signal that can be transmitted through the first via hole V1. For example, the accuracy of a signal transmitted to the fifth inner lead pattern unit I5 through the first test pattern unit T1 can be confirmed. In detail, by measuring the voltage or current in the first test pattern portion (T1), it is possible to determine whether a short circuit or a short circuit occurs or a position where the conductive pattern portion located between the first chip and the display panel occurs, It is possible to improve the reliability.

The first chip C1 disposed on one surface of the flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment is connected to the third inner lead pattern portion 100 via the third sub- (I3).

The third inner lead pattern portion I3 disposed on the upper surface of the substrate 110 is electrically connected to the center via the conductive material filled in the fourth via hole V4 located below the third inner lead pattern portion I3, And is connected to the wiring pattern layer 120. The central wiring pattern layer 120 is electrically connected to the fifth inner lead pattern portion I5 and the first test pattern portion T1 adjacent to the fifth via hole V5 through the fifth via hole V5. It can transmit an electrical signal. The fifth via hole (V5), the first test pattern portion (T1), and the fifth inner lead pattern portion (I5) may be electrically connected at a lower surface of the substrate.

The wiring of the signal transmitted through the third sub first connection part 73 is a central wiring pattern layer 120 disposed between the first substrate 111 and the second substrate 112 as a whole, The fifth via hole V5 is transferred to the fifth inner lead pattern portion I5 and the first test pattern portion T1.

It is also assumed that the signals of the second sub first connection portion 72 and the third sub first connection portion 73 are transmitted to the same fifth inner lead pattern portion I5 and the first test pattern portion T1 , Which is only one embodiment. That is, the fifth inner lead pattern portion I5 and the first test pattern portion T1 may include a first part connected to the second sub first connection part 72 and a third part connected to the third sub first connection part 73 And a second part connected to the second part.

In addition, the first test pattern portion T1 can confirm the failure of an electrical signal that can be transmitted through the fifth via hole V5. For example, the accuracy of a signal transmitted to the fifth inner lead pattern unit I5 through the first test pattern unit T1 can be confirmed. In detail, by measuring the voltage or current in the first test pattern portion (T1), it is possible to determine whether a short circuit or a short circuit occurs or a position where the conductive pattern portion located between the first chip and the display panel occurs, It is possible to improve the reliability.

The first chip C1 disposed on one surface of the flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment is connected to the fourth inner lead pattern portion 100 via the fourth sub first connection portion 74, Lt; RTI ID = 0.0 &gt; I4. &Lt; / RTI &gt;

The fourth inner lead pattern portion I4 may transmit an electrical signal to the second outer lead pattern portion O2 adjacent to the third via hole V3 along the upper surface of the substrate 110. [ The third via hole (V3) and the second outer lead pattern portion (O2) may be electrically connected. That is, the fourth inner lead pattern portion I4 and the second outer lead pattern portion O2 may have one end and one end of the conductive pattern portion extending in one direction.

The fourth inner lead pattern portion I3 is electrically connected to the third via hole V3 along the upper surface of the second substrate 112 and electrically connected to the third via hole V4 through the conductive material filled in the fourth via hole V4 An electrical signal can be transmitted to the fourth outer lead pattern portion O4 and the second test pattern portion T2 adjacent to the third via hole V3 along the lower surface of the first substrate 111. [

The third via hole (V3), the fourth outer lead pattern portion (O4), and the second test pattern portion (T2) may be electrically connected at a lower surface of the substrate.

The display panel 30 may be attached to the fifth inner lead pattern portion I5 and the fourth outer lead pattern portion O4 through the adhesive layer 50 as described above.

The second test pattern portion T2 can confirm the failure of an electrical signal that can be transmitted through the third via hole V3. For example, the accuracy of a signal transmitted to the fourth outer lead pattern portion (O4) can be confirmed through the second test pattern portion (T2). In detail, by measuring the voltage or current in the second test pattern portion T2, it is possible to determine whether a short circuit or a short circuit occurs or a position where the conductive pattern portion located between the first chip and the display panel occurs, It is possible to improve the reliability.

In the flexible circuit board for a three-layer all-in-one chip-on-film according to the embodiment, the display panel 30 can be disposed on the other surface opposite to the one surface on which the first chip C1 is disposed, have. Further, by disposing the display panel on the other surface opposite to the surface on which the plurality of chips are mounted, effective heat dissipation can be achieved. Thus, the reliability of the all-in-one chip-on-film flexible circuit board according to the embodiment can be improved.

Also, in the present invention, a part of the plurality of connection parts of the first chip (C1) is transmitted through the second conductive pattern part (CP2) disposed on the upper surface of the second substrate, A signal is transmitted through the third conductive pattern part CP3 disposed between the second substrate and the other part is transmitted through the first conductive pattern part CP1 disposed on the lower surface of the first substrate , And a circuit having a high resolution (QHD) can be implemented efficiently.

Fig. 11 is a plan view of Fig. 8A, and Figs. 12A and 12B are bottom views of Fig. 8A.

11, 12A, and 12B, the flexible circuit board 100 for a three-layer all-in-one chip-on-film of the embodiment may have sprocket holes on both sides in the longitudinal direction for convenience of fabrication or processing. Therefore, the flexible circuit board 100 for an all-in-one chip-on-film can be rolled or unwound by a sprocket hole by a roll-to-roll method.

The flexible circuit board 100 for a three-layer all-in-one chip-on-film can be defined as an inner region IR and an outer region OR with reference to a cut portion indicated by a dotted line.

First and second conductive pattern portions CP1 and CP2 for connecting one chip, a second chip, a display panel, and a main board are disposed in the inner region IR of the all-in-one chip-on-film flexible circuit board 100 .

A chip package including the all-in-one chip-on-film flexible printed circuit board 100 and a chip package including the all-in-one chip-on-film flexible printed circuit board 100 are formed by cutting a portion where the sprocket holes are formed, And the like.

11, on the upper surface of the all-in-one chip-on-film flexible printed circuit board 100, through the first open area OA1 of the protective layer 140, the first conductive pattern CP2, The first inner lead pattern portion I1, the second inner lead pattern portion I2, the third inner lead pattern portion I3 and the fourth inner lead pattern portion I4 may be exposed to the outside.

In the upper surface of the flexible circuit board 100 for the three-layer all-in-one chip-on-film, the first conductive pattern CP2 is formed on the first conductive pattern CP2 through the third open area OA3 of the protective layer 140, The outer lead pattern portion O1 may be exposed to the outside.

The first inner lead pattern portion I1 and the fourth inner lead pattern portion I4 may be a conductive pattern portion connected to the chip through the first connection portion.

The end portions of the first inner lead pattern portion I1 and the end portions of the fourth inner lead pattern portion 14 may be arranged in a line. For example, the plurality of first inner lead pattern portions I1 may be spaced apart from each other in the lateral direction (x-axis direction) of the substrate, and the ends of the first inner lead pattern portion I1 may be arranged in a line . For example, the plurality of fourth inner lead pattern portions I4 may be spaced apart from each other in the lateral direction (x-axis direction) of the substrate, and the ends of the fourth inner lead pattern portion I4 may be arranged in a line . Accordingly, the bonding of the first inner lead pattern portion I1 and the fourth inner lead pattern portion I4 to the first connection portion and the first chip can be excellent.

The plurality of second via holes V2 may be spaced apart from each other in a horizontal direction (x-axis direction) of the substrate, and may be arranged in a line. The plurality of third via holes V3 may be spaced apart from each other in a horizontal direction (x-axis direction) of the substrate, and may be arranged in a line.

The ends of the first inner lead pattern portion I1 may be spaced apart from the ends of the second inner lead pattern portion I2. The ends of the third inner lead pattern portions I3 may be spaced apart from the end portions of the fourth inner lead pattern portions I4. The ends of the second inner lead pattern portions I2 may be spaced apart from the third inner lead pattern portions I3.

The second inner lead pattern portion I2 and the third inner lead pattern portion I3 may be a conductive pattern that is not bonded to the first chip. At least one end of one end and the other end of the second inner lead pattern portion 12 may not be arranged in a row. At least one end of one end and the other end of the third inner lead pattern portion I3 may not be arranged in a row.

For example, the plurality of second inner lead pattern portions I2 may be spaced apart from each other in the lateral direction (x-axis direction) of the substrate. In addition, the plurality of third inner lead pattern portions I3 may be spaced from each other in the lateral direction (x-axis direction) of the substrate.

At least one end of the one end and the other end of the second inner lead pattern part I2 is spaced apart from the end of the first inner lead pattern part I1 in the lateral direction (x-axis direction) of the substrate . At least one end of the one end and the other end of the second inner lead pattern portion I2 is spaced apart from the end of the first inner lead pattern portion I1 in the lateral direction (x-axis direction) of the substrate .

At least one end of one end of the third inner lead pattern portion I3 is spaced apart from the end of the fourth inner lead pattern portion 14 in the lateral direction (x-axis direction) of the substrate . At least one end of one end of the third inner lead pattern portion I3 and the other end portion of the third inner lead pattern portion I3 decrease in the distance from the end of the fourth inner lead pattern portion 14 toward the lateral direction of the substrate .

The plurality of first via holes V1 may be spaced apart from each other and arranged in different rows in the lateral direction (x-axis direction) of the substrate.

The length between the one end and the other end of the second inner lead pattern portion I2 may include a first set portion of the second inner lead pattern portions 12 gradually decreasing in the lateral direction (x-axis direction) have. In detail, the length between one end and the other end of the second inner lead pattern portion I2 is gradually decreased from the first length to the lateral direction (x-axis direction) of the substrate, Lt; RTI ID = 0.0 &gt; I2. &Lt; / RTI &gt; At this time, the first length may be larger than the second length. A plurality of first sets may be disposed on the substrate 110. Accordingly, on the substrate 110, the second inner lead pattern portions 12 may be gradually reduced in length from the first length to the second length. The second inner lead pattern portion I2 adjacent to the second inner lead pattern portion I2 having the second length may have a first length again. Accordingly, the first set of the second inner lead pattern portions I2 whose length is gradually reduced from the first length to the second length in the lateral direction (x-axis direction) of the substrate; And the first set portion of the second inner lead pattern portions I2 whose length is gradually increased from the first length to the second length may be repeatedly arranged. Alternatively, the first set of the second inner lead pattern portions 12 may be gradually reduced in length from the first length to the second length in the lateral direction (x-axis direction) of the substrate. And the second set of the second inner lead pattern portions I2 whose length is gradually increased from the second length to the first length can be repeatedly arranged.

The length between one end and the other end of the third inner lead pattern portion I3 may include a first set portion of the third inner lead pattern portions 13 gradually increasing in the lateral direction (x-axis direction) of the substrate have. In detail, the length between the one end and the other end of the third inner lead pattern portion I3 is gradually increased from the third length to the lateral direction (x-axis direction) of the substrate to form the third inner lead pattern portion Lt; RTI ID = 0.0 &gt; I3. &Lt; / RTI &gt; At this time, the third length may be smaller than the fourth length. A plurality of first sets may be disposed on the substrate 110. Accordingly, on the substrate 110, the third inner lead pattern portions I3 may be gradually reduced in length from the third length to the fourth length. The third inner lead pattern portion I3 adjacent to the third inner lead pattern portion I2 having the fourth length may have a third length again. Accordingly, the first set of the third inner lead pattern portions I3 whose length is gradually increased from the third length to the fourth length in the lateral direction (x-axis direction) of the substrate; And the first set portion of the third inner lead pattern portions I3 whose length is gradually reduced from the third length to the fourth length can be repeatedly arranged. Alternatively, the first set of the third inner lead pattern portions I3 may be gradually increased in length from the third length to the fourth length in the lateral direction (x-axis direction) of the substrate. And the second set portion of the third inner lead pattern portions I3 whose length is gradually reduced from the fourth length to the third length may be repeatedly arranged.

At least one end of the one end and the other end of the second inner lead pattern portion I2 is spaced apart from the end of the first inner lead pattern portion I1 in the lateral direction (x-axis direction) of the substrate .

The plurality of first inner lead pattern portions I1 may be spaced apart from each other by a first distance. The second inner lead pattern portions I2 may be located at positions facing the first inner lead pattern portions I1. In addition, one end of the second inner lead pattern portion I2 may be positioned in an area between two adjacent first inner lead pattern portions I1 which are spaced apart from each other. In the lateral direction of the substrate, the end of the first inner lead pattern portion I1 and the end of the second inner lead pattern portion I2 may be disposed opposite to each other, .

12A, the bottom surface of the all-in-one chip-on-film flexible printed circuit board 100 is covered with the first conductive pattern portion CP1 through the third open area OA3 of the protective layer 140, The fifth inner lead pattern portion I5, and the fourth outer lead pattern portion 04 may be exposed to the outside. The second inner lead pattern portion I2 may be connected to the fourth outer lead pattern portion O4 through a metal material filled in the first via hole V1.

12B, the third inner lead pattern portion I3 is electrically connected to a third conductive pattern (not shown) disposed on the upper surface of the first substrate 111 through a metal material filled in the fourth via hole V4, (CP3). The third conductive pattern part CP3 may be connected to the fourth outer lead pattern part O4 through a metal material filled in the fifth via hole V5.

A chip package including a first chip C1 and a second chip C2 is stacked on a flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment with reference to Figs. 8B and 13 to 17, Will be described in detail.

13 is a schematic plan view of a chip package including a flexible circuit board 100 for a three-layer all-in-one chip-on film according to an embodiment.

13A and 13B, the flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment may include a first chip C1 and a second chip C2 disposed on the same surface have.

The flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment may have a length in the lateral direction (x-axis direction) greater than a length in the longitudinal direction (y-axis direction). That is, the flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment may include two long sides in the lateral direction and two short sides in the longitudinal direction.

The lengths of the first chip C1 and the second chip C2 in the lateral direction (x-axis direction) may be greater than those in the longitudinal direction (y-axis direction), respectively. That is, the first chip C1 and the second chip C2 may include two long sides in the horizontal direction and two short sides in the vertical direction.

The long side of the flexible circuit board 100 for a three-layer all-in-one chip-on-film according to the embodiment can be arranged parallel to the long side of the first chip C1 and the long side of the second chip C2, The chips can be efficiently arranged on the flexible circuit board 100 for one three-layer all-in-one chip-on film.

The longitudinal length (long side) of the first chip C1 may be greater than the length (long side) of the second chip C2 in the horizontal direction. The length (short side) of the first chip C1 in the vertical direction may be smaller than the length (short side) of the second chip C2 in the vertical direction. Referring to FIG. 13A, the second chip C2 may be disposed below the first chip C1. The long side of the first chip C1 and the long side of the second chip C2 may overlap each other.

Referring to FIG. 13B, the second chip C2 may be disposed on the side of the first chip C1. The long side of the first chip C1 and the long side of the second chip C2 may not overlap with each other.

The first chip C1 is a driving IC chip and the second chip C2 is a second chip C2a of any one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, And a second chip C2b different from any one of the diode chip, the power IC chip, the touch sensor IC chip, the MLCC chip, the BGA chip, and the chip capacitor.

14 to 17, a manufacturing step of a chip package including a flexible circuit board for a three-layer all-in-one chip-on film according to an embodiment will be described.

14 is a plan view of a flexible circuit board 100 for a three-layer all-in-one chip-on film according to an embodiment.

14A and 14B, the protective layer 140 disposed on one side of the flexible circuit board 100 for a three-layer all-in-one chip-on-film according to an embodiment may include a plurality of holes. That is, the protective layer 140 may include a plurality of open regions.

The first open area OA1 of the protection layer may be exposed to be connected to the first connection part 70. [ The conductive pattern CP exposed in the first open area OA1 of the protective layer may include pure plating on the surface facing the first connection part. That is, the content of tin in the second plating layer included in the conductive pattern portion CP in the first open region OA1 of the protective layer may be 50 atomic% or more.

The second open area OA2 of the protective layer may be exposed to connect with the second connection part 80. [ The conductive pattern portion CP exposed in the second open region OA2 of the protective layer may include an alloy layer of copper and tin on the surface facing the second connection portion. That is, the content of tin in the second plating layer included in the conductive pattern portion CP in the second open region OA2 of the protective layer may be less than 50 atomic%.

The first open area OA1 may be an area for connecting the first chip. The first inner lead pattern portions I1 extending from the first outer lead pattern portion O1 located in the third open area OA3 and directed toward the inside of the first open area OA1 may be connected to each other Width. For example, the width W1 of the first outer lead pattern portion O1 may correspond to the width W2 of the first inner lead pattern portion I1. For example, the width W1 of the first outer lead pattern portion O1 may be greater than the width W2 of the first inner lead pattern portion I1. In detail, the width W1 of the first outer lead pattern part O1 may be less than 20% of the width W2 of the first inner lead pattern part I1.

The first inner lead pattern portion I1 and the fourth inner lead pattern portion I4 extending toward the inside of the first open area OA1 may have a width corresponding to each other.

The first outer lead pattern portion O1 and the second outer lead pattern portion O2 extending from the first open area OA1 toward the outer periphery of the substrate may have widths corresponding to each other. Thereby, the first chip having a fine line width, requiring a large number of first connection parts, and the second chip having a large line width and requiring a small number of second connection parts, (Not shown). At this time, the fine line width is set so that the line width of any one of the first outer lead pattern portion O1 and the second outer lead pattern portion O2 is equal to the line width of the fifth outer lead pattern portion O5 and the sixth outer lead pattern portion O6 The line width is smaller than any one of the line widths. On the other hand, when the line width of any of the outer lead pattern portion O5 and the sixth outer lead pattern portion O6 is larger than the line width of the first outer lead pattern portion O1 and the second outer lead pattern portion O2 It may mean that any one of the line widths is relatively larger than the line width of any one of the fifth outer lead pattern portion O5 and the sixth outer lead pattern portion O6.

The flexible circuit board 100 for an all-in-one chip-on-film of the embodiment may include a plurality of the second open areas OA2 for connecting second chips C2a and C2b of different kinds.

One of the second open areas OA2 may be an area for connecting one second chip C2a. The fifth outer lead pattern portion O5 extending from the sixth inner lead pattern portion I6 located in the second open region OA2 toward the outer periphery of the substrate may have a different width. For example, the width W3 of the sixth inner lead pattern portion I6 may be greater than the width W4 of the fifth outer lead pattern portion O5. In detail, the width W3 of the sixth inner lead pattern portion I6 may be 1.5 times larger than the width W4 of the fifth outer lead pattern portion O5.

And the second open area OA2 may be an area for connecting the other second chip C2b. The sixth outer lead pattern portion O6 extending from the seventh inner lead pattern portion I7 located in the second open region OA2 toward the outer periphery of the substrate may have a different width. For example, the width W5 of the seventh inner lead pattern portion I7 may be greater than the width W6 of the sixth outer lead pattern portion O6. In detail, the width W5 of the seventh inner lead pattern portion I7 may be 1.5 times larger than the width W6 of the sixth outer lead pattern portion O6.

A width W3 of the sixth inner lead pattern portion I6 exposed through the second open region and a width W5 of the seventh inner lead pattern portion I7 may be equal to a width And the width W2 of the first inner lead pattern portion I1 exposed through the first inner lead pattern portion I1. As a result, the lead pattern portion corresponding to the first and second connecting portions of various sizes / shapes can be formed, and the degree of design freedom can be improved. That is, the embodiment can include inner lead pattern portions of various sizes suitable for the first chip and the second chip of different kinds, and inner lead pattern portions of various shapes, so that an optimum chip package can be realized.

The shape of the lead pattern portion located below the first chip may be different from the shape of the lead pattern portion located below the second chip. Accordingly, the embodiment can include the lead pattern portions of different shapes, which can have excellent adhesion characteristics with the first and second chips of different kinds, respectively. Therefore, in the flexible circuit board for an all-in-one chip-on film according to the embodiment, the bonding characteristics of the first chip and the second chip can be excellent.

That is, the lead pattern portions having different shapes may be an optimal pattern design in which first and second chips of different kinds are mounted on one substrate to secure a certain bonding topology.

The shape of the first inner lead pattern portion I1 in the plane may be a rectangular stripe pattern. In detail, the shape of the first inner lead pattern portion I1 in the plane may be a rectangular stripe pattern having a uniform width and extending in one direction. For example, the widths of one end and the other end of the first inner lead pattern portion I1 may be equal to each other.

For example, the shape of the sixth inner lead pattern portion I6 or the seventh inner lead pattern portion I7 may be various shapes such as a polygonal shape, a circular shape, an elliptical shape, a hammer shape, a T shape, As shown in Fig. In detail, the shape of the sixth inner lead pattern portion I6 or the seventh inner lead pattern portion I7 in the plane is a polygonal shape having a varying width and extending in a direction different from the one direction, Shape, a T shape, a random shape, or the like. For example, at least one inner lead pattern portion of the sixth inner lead pattern portion I5 and the seventh inner lead pattern portion I7 may have different widths at one end and the other end. The width of the other end of the sixth inner lead pattern portion I6 and the seventh inner lead pattern portion I7, which is an end far from the protective layer, may be larger than the width at one end near the protective layer. It should be noted that the width of the other end of the sixth inner lead pattern portion I6 and the seventh inner lead pattern portion I7, which is an end far from the protective layer, Of course, can be small.

For example, in the case where the second chip is an MLCC chip, the inner lead pattern portion may have a T-shape like the sixth inner lead pattern portion I6 of FIG. 14B.

For example, when the second chip is a BGA chip, the inner lead pattern portion may have the same circular shape as the seventh inner lead pattern portion I7 of FIG. 14A. Alternatively, when the second chip is a BGA chip, the inner lead pattern portion may have a semicircular shape like the seventh inner lead pattern portion I7 of FIG. 14B or a rounded end shape.

The shape of the first inner lead pattern portion and the first connecting portion may be the same. For example, the top view of the first inner lead pattern portion and the first connection portion may have a rectangular shape. Here, the same shape of the first inner lead pattern portion and the first connecting portion means that the planar shape is the same polygon, and may include a different size.

The shape of the sixth inner lead pattern portion and the second connection portion may be the same or different from each other. The seventh inner lead pattern portion and the second connecting portion may have the same shape or different shapes.

14A and 15A, the planar shape of the sixth inner lead pattern portion I6 may be a polygonal shape, and the planar shape of the second connection portion may be a circular shape. The planar shape of the seventh inner lead pattern portion I7 may have a circular shape, and the second connection portion may have a circular shape.

14B and 15B, the planar shape of the sixth inner lead pattern portion I6 may be a polygonal shape, and the second connection portion may have a rectangular shape or an elliptical shape having rounded corners. The planar shape of the seventh inner lead pattern portion I7 may be a long semicircular shape, and the second connecting portion may have a circular shape.

The planar shape of the first connection part 70 may correspond to or differ from each other in the transverse length and the longitudinal length (aspect ratio). For example, the planar shape of the first connection part 70 may be a square shape having a width and a length (aspect ratio) corresponding to each other, or a rectangular shape having a width and a length (aspect ratio) different from each other.

The planar shape of the second connection portion 80 may correspond to or differ from each other in the transverse length and the longitudinal length (aspect ratio). For example, the planar shape of the second connection part 80 may be a circular shape corresponding to a transverse length and a longitudinal length (aspect ratio), or an elliptical shape having a transverse length and a longitudinal length (aspect ratio) different from each other.

One pitch, which is an interval between the adjacent first outer lead pattern portions O1, is equal to a pitch between at least one of the fifth outer lead pattern portion O5 and the sixth outer lead pattern portion O6, May be smaller than a second pitch (pitch) between the pattern portions. Here, the first interval and the second interval may mean an average spacing distance between adjacent two conductive pattern portions.

The first spacing (P1) may be less than 100 mu m. For example, the first spacing may be less than 30 占 퐉. For example, the first spacing may be between 1 [mu] m and 25 [mu] m.

The second interval P2 may be equal to or greater than 100 mu m. For example, the second spacing may be between 100 μm and 500 μm. For example, the second spacing may be between 100 μm and 300 μm.

Thus, it is possible to prevent interference of signals between the conductive pattern portions connected to the first chip and the second chip, respectively, and to improve the accuracy of the signals.

The planar area of the first inner lead pattern part I1 in the first open area OA1 may correspond to or be different from that of the first connection part 70. [

The width of the first inner lead pattern portion I1 and the width of the first connection portion 70 may be the same or less than 20%. Accordingly, the first inner lead pattern portion I1 and the first connection portion 70 can be stably mounted. Also, the adhesion characteristics between the first inner lead pattern portion I1 and the first connection portion 70 can be improved.

The planar portion of the inner lead pattern portion of any one of the sixth inner lead pattern portion I5 and the seventh inner lead pattern portion I6 in the second open area OA2 corresponds to the second connective portion 80, May be different.

For example, the width of the second connection portion 80 may be 1.5 times larger than the width of the inner lead pattern portion of any one of the sixth inner lead pattern portion I5 and the seventh inner lead pattern portion I6 . Accordingly, the width of the second connection portion 80 can be improved by improving adhesion characteristics of either the sixth inner lead pattern portion I6 or the seventh inner lead pattern portion I7 and the second connection portion 80 .

15A and 15B, the steps of arranging the first connecting portion 70 and the second connecting portion 80 on the all-in-one chip-on-film flexible circuit board 100 of the embodiment will be described.

The first connection portions 70 may be disposed on the first inner lead pattern portion I1 and the fourth inner lead pattern portion I4 exposed through the first open region OA1. For example, the first connection portion 70 may cover the upper surfaces of the first inner lead pattern portion I1 and the fourth inner lead pattern portion 14 in whole or in part.

The total number of the plurality of first inner lead pattern portions I1 spaced apart from each other and the plurality of fourth inner lead pattern portions I4 spaced apart from each other corresponds to the number of the first connecting portions 70 .

For example, referring to FIGS. 16A and 16B, the number of the plurality of first inner lead pattern portions I1 spaced apart from each other is nine, and the plurality of fourth inner lead pattern portions The number of the first inner lead pattern portions I1 is nine and the number of the first connection portions 70 is nine in the first inner lead pattern portions I1 and a plurality of the fourth inner lead pattern portions I4 ) Can be 18, which is the total sum of 9.

The second connection portion 80 may be disposed on the sixth inner lead pattern portion I6 and the seventh inner lead pattern portion I7 exposed through the second open area OA2. For example, the second connection portion 80 may cover the upper surfaces of the sixth inner lead pattern portion I6 and the seventh inner lead pattern portion I7 in whole or in part.

The number of the plurality of sixth inner lead pattern portions I6 spaced apart from each other may correspond to the number of the second connection portions 80 disposed on the seventh inner lead pattern portion I5.

For example, referring to FIGS. 16A and 16B, the number of the plurality of sixth inner lead pattern portions I6 spaced apart from each other is two, and the number of the sixth inner lead pattern portions I6 arranged on the sixth inner lead pattern portion I6 The number of the second connection portions 80 may be two.

The number of the seventh inner lead pattern portions I7 spaced apart from each other may correspond to the number of the second connection portions 80 disposed on the seventh inner lead pattern portion I7.

For example, referring to FIGS. 16A and 16B, the number of the seventh inner lead pattern portions I7 spaced apart from each other is three, and the number of the seventh inner lead pattern portions I7 arranged on the seventh inner lead pattern portion I7 The number of the second connecting portions 80 may be three.

The second connection unit 80 may be larger than the first connection unit 70. The width of the sixth inner lead pattern portion I6 or the seventh inner lead pattern portion I7 exposed through the second open region is larger than the width of the first inner lead pattern portion I1 The second connection portion 80 may be larger than the first connection portion 70. [

16A and 16B, steps for disposing the first chip C1 and the second chips C2a and C2b on the all-in-one chip-on-film flexible circuit board 100 of the embodiment will be described.

The first chip C1 may be disposed on the first connection portion 70. [

The first chip C2 may be disposed on the second connection unit 80. [

The first chip C1 and the second chip C2 may be spaced apart from each other by a predetermined distance to prevent problems such as signal interference, disconnection, and the like.

17 is a cross-sectional view of a chip package including a flexible circuit board for a three-layer all-in-one chip-on film according to Figs. 16A and 16B.

The first chip (C1) and the second chip (C2) may be arranged in different sizes on the same surface. For example, the second chip C2 may be larger than the first chip C1.

A via hole may be disposed under the first chip (C1) and the second chip (C2). That is, the substrate 110 corresponding to the first open area OA1 and the second open area OA2 may include a via hole.

The electrical signal of the second chip C2 can be transmitted from the upper surface to the lower surface of the substrate through the conductive material disposed in the sixth via hole V6. Accordingly, the embodiment can include a large number of conductive pattern portions on one substrate.

The flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment can realize a conductive pattern portion having a fine pitch in three layers, and can be suitable for an electronic device having a display portion with a high resolution.

Further, the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment is flexible, small in size, and thin in thickness, and thus can be used in various electronic devices.

For example, referring to FIG. 18, the flexible circuit board 100 for an all-in-one chip-on film according to the embodiment can be used for an edge display since the bezel can be reduced.

For example, referring to FIG. 19, the flexible circuit board 100 for an all-in-one chip-on film according to the embodiment can be included in a flexible electronic device that is bent. Accordingly, the touch device device including the same may be a flexible touch device device. Therefore, the user can bend or bend by hand. Such a flexible touch window can be applied to a wearable touch or the like.

For example, referring to FIG. 20, the flexible circuit board 100 for an all-in-one chip-on film according to the embodiment can be applied to various electronic devices to which a foldable display device is applied. 20A to 20C, the folder-type display device can fold the folder-cover window. Foldable display devices can be included in a variety of portable electronic products. In detail, the folder-type display device can be included in a mobile terminal (mobile phone), a notebook (portable computer), and the like. Accordingly, while the display area of the portable electronic product is large, it is possible to reduce the size of the device when storing or moving the portable electronic device, thereby increasing the portability. Therefore, the convenience of the user of the portable electronic device can be improved. However, the embodiment is not limited thereto, and it goes without saying that the folder-type display device can be used for various electronic products.

Referring to FIG. 20A, the foldable display device may include one folded area in the screen area. For example, the foldable display device may have a C-shape in a folded configuration. That is, the folder-type display device may have one end and the other end opposite to the end. At this time, the one end and the other end may be disposed close to each other. For example, the one end and the other end may be disposed facing each other.

Referring to FIG. 20B, the foldable display device may include two folded regions in the screen region. For example, the foldable display device may have a G shape in a folded form. That is, the foldable display device can be superposed on each other as the one end and the other end opposite to the one end are folded in the directions corresponding to each other. At this time, the one end and the other end may be spaced apart from each other. For example, the one end and the other end may be arranged parallel to each other.

Referring to FIG. 20C, the foldable display device may include two folding regions in the screen region. For example, the foldable display device may have an S-shaped configuration in a folded configuration. That is, the folder-type display device can be folded at one end and the other end opposite to the one end in different directions. At this time, the one end and the other end may be spaced apart from each other. For example, the one end and the other end may be arranged parallel to each other.

Also, although not shown in the drawings, it goes without saying that the flexible circuit board 100 for all-in-one chip-on-film according to the embodiment can be applied to rollerable displays.

Referring to FIG. 21, the flexible circuit board 100 for an all-in-one chip-on film according to the embodiment may be included in various wearable touch devices including a curved display. Therefore, the electronic device including the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment can be made slimmer, smaller, or lighter.

Referring to FIG. 22, the flexible circuit board 100 for an all-in-one chip-on-film according to the embodiment can be used in various electronic devices having a display portion such as a TV, a monitor, and a notebook.

However, the embodiment is not limited thereto, and it goes without saying that the flexible circuit board 100 for an all-in-one chip-on film according to the embodiment can be used for various electronic devices having a flat or curved display portion.

The features, structures, effects and the like described in the foregoing embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the present invention. It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments may be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

Claims (10)

A first substrate;
A second substrate disposed on the first substrate;
A first wiring pattern layer disposed on a lower surface of the first substrate; a first conductive pattern portion disposed on the first wiring pattern layer and including a plating layer including tin;
A second wiring pattern layer disposed on an upper surface of the second substrate; a second conductive pattern portion disposed on the second wiring pattern layer and including a plating layer including tin;
A third conductive pattern portion including a third wiring pattern layer disposed between the first substrate and the second substrate; And
And a protective layer partially disposed on the first and second conductive pattern portions,
The second conductive pattern portion may include:
First to fourth inner lead pattern portions disposed on a first open region of the protective layer,
And an extended pattern portion covered by the protective layer,
Wherein the first and fourth inner lead pattern portions comprise:
And an extension portion connected to the extension pattern portion,
Wherein the second inner lead pattern portion comprises:
Wherein the first conductive pattern portion is directly connected to the first conductive pattern portion via a first via passing through the first substrate and the second substrate,
The third inner lead pattern portion may include:
And is directly connected to the third conductive pattern portion through a second via penetrating the second substrate
Flexible circuit board for all - in - one chip on film. The method according to claim 1,
The second conductive pattern portion
And first and second outer lead pattern portions exposed through a second open region of the protective layer,
Wherein the first inner lead pattern portion comprises:
A second outer lead pattern portion connected to the first outer lead pattern portion through the extended pattern portion,
Wherein the second inner lead pattern portion comprises:
And the second outer lead pattern portion is connected to the second outer lead pattern portion
Flexible circuit board for all - in - one chip on film. 3. The method of claim 2,
The first conductive pattern portion may include:
Third and fourth outer lead pattern portions exposed through a third open region of the protective layer,
And first and second test pattern portions exposed through a fourth open region of the passivation layer,
Wherein the first inner lead pattern portion comprises:
The first and second substrates are connected to the third outer lead pattern portion through a third via passing through the first substrate and the second substrate,
Wherein the second inner lead pattern portion comprises:
The first and second test leads being connected to the fourth outer lead and the first test pad through the first via,
The third inner lead pattern portion may include:
The first via and the second via are connected to the fourth outer lead and the first test pad through a fourth via passing through the second via and the first substrate,
Wherein the fourth inner lead pattern portion comprises:
The first and second test patterns being connected to the fourth outer lead pattern portion and the second test pad through fifth vias passing through the first substrate and the second substrate,
Flexible circuit board for all - in - one chip on film. The method of claim 3,
The second conductive pattern portion may include:
Further comprising fifth and sixth inner lead pattern portions disposed on a fifth open region of the protective layer,
Wherein a content of tin (Sn) in a plating layer of the second conductive pattern portion in the first open region is larger than a content of tin (Sn) in a plating layer of the second conductive pattern portion in the fifth open region
Flexible circuit board for all - in - one chip on film. 5. The method of claim 4,
Wherein the plating layer includes a first plating layer disposed on the wiring pattern layer and a second plating layer disposed on the first plating layer,
Wherein a content of tin in the second plating layer in the first open region is larger than a content of tin in the second plating layer in the fifth open region
Flexible circuit board for all - in - one chip on film. 6. The method of claim 5,
In the fifth open region, the second plating layer is an alloy layer of copper (Cu) and tin (Sn)
Flexible circuit board for all - in - one chip on film. In the all-in-one chip-on-film flexible circuit board,
A first substrate;
A second substrate disposed on the first substrate;
A first wiring pattern layer disposed on a lower surface of the first substrate; a first conductive pattern portion disposed on the first wiring pattern layer and including a plating layer including tin;
A second wiring pattern layer disposed on an upper surface of the second substrate; a second conductive pattern portion disposed on the second wiring pattern layer and including a plating layer including tin;
A third conductive pattern portion including a third wiring pattern layer disposed between the first substrate and the second substrate; And
And a protective layer partially disposed on the first and second conductive pattern portions,
The second conductive pattern portion may include:
A first connection portion including first to fourth inner lead pattern portions disposed on a first open region of the protection layer;
And an extended pattern portion covered by the protective layer,
A first chip is disposed on the first connection portion on the first open region,
Wherein the first and fourth inner lead pattern portions comprise:
And an extension portion connected to the extension pattern portion,
Wherein the second inner lead pattern portion comprises:
Wherein the first conductive pattern portion is directly connected to the first conductive pattern portion via a first via passing through the first substrate and the second substrate,
The third inner lead pattern portion may include:
And is directly connected to the third conductive pattern portion through a second via penetrating the second substrate
A chip package comprising a flexible circuit board for an all-in-one chip-on film. 8. The method of claim 7,
The second conductive pattern portion may include:
And a second connection portion including fifth and sixth inner lead pattern portions disposed on a second open region of the protection layer,
And a second chip different from the first chip is disposed in the second connection portion on the second open region
A chip package comprising a flexible circuit board for an all-in-one chip-on film. 9. The method of claim 8,
The first chip is a drive IC chip,
The second chip may be at least one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor
A chip package comprising a flexible circuit board for an all-in-one chip-on film. A first substrate; A second substrate disposed on the first substrate; A first wiring pattern layer disposed on a lower surface of the first substrate; a first conductive pattern portion disposed on the first wiring pattern layer and including a plating layer including tin; A second wiring pattern layer disposed on an upper surface of the second substrate; a second conductive pattern portion disposed on the second wiring pattern layer and including a plating layer including tin; A third conductive pattern portion including a third wiring pattern layer disposed between the first substrate and the second substrate; And a protective layer partially disposed on the first and second conductive pattern portions, wherein the second conductive pattern portion includes first to fourth inner lead pattern portions disposed on a first open region of the protective layer Wherein the first and fourth inner lead pattern portions are connected to the extended pattern portion and the second inner lead pattern portion includes a first inner lead pattern portion and a second outer lead pattern portion, Wherein the second conductive pattern portion is directly connected to the first conductive pattern portion through a first via penetrating through the second substrate and the third inner lead pattern portion is directly connected to the third conductive pattern portion via a second via penetrating through the second substrate, A flexible circuit board for all-in-one chip-on film to be connected;
A display panel connected to one end of the flexible circuit board for the all-in-one chip-on film; And
And a main board connected to the other end opposite to the one end of the all-in-one chip-on-film flexible circuit board
Electronic device.

Images