KR20190024287A - Bidirectional Low Clamping Transient Voltage Suppression Device Using Schokley Diodes and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a transient voltage suppression device having a lower clamping voltage/capacitance and a higher peak pulse current in a chip scale package and a manufacturing method thereof. For example, the transient voltage suppression device includes: a substrate of a first conductive type; an epitaxial layer of a first conductive type formed on the substrate; a first buried layer of a second conductive type formed in the epitaxial layer; a pair of second buried layers of a second conductive type formed in the epitaxial layer; a third buried layer of a first conductive type formed on the first buried layer; a fourth buried layer of a second conductive type formed on the third buried layer; at least one trench source region of a first conductive type formed in the epitaxial layer between the first and second buried layers; a pair of first conductive regions of a first conductive type formed at positions corresponding to the second buried layer in the epitaxial layer; and a pair of second conductive regions of a second conductive type formed on both sides of the first buried layer in the epitaxial layer.

Description

Technical Field [0001] The present invention relates to a bidirectional low clamping transient voltage suppressing device using a choke diode structure and a manufacturing method thereof,

The present invention relates to a transient voltage suppressing element and a method of manufacturing the same.

Referring to FIG. 1, the operation principle and circuit diagram of a conventional transient voltage suppressing element are shown.

As shown in FIG. 1, a transient voltage suppressing device TVS (for example, varistor, thyristor, diode (rectifier / zener)) is connected in parallel between a power source V _G and a load R _LOAD , And one side of the transient voltage suppressing element is connected to the ground (GND).

With this arrangement, when an excessive voltage exceeding the voltage required by the load R _LOAD is input, the transient current I _TV caused by the transient voltage flows toward the ground GND via the transient voltage suppressing element TVS , by applying a low voltage is clamped to stabilize only the load (R _lOAD), the load (R _lOAD) is protected from excess voltage.

A problem to be solved by the present invention is that a Schottky diode structure of a PNPN structure is formed in a chip scale package and a PN forward diode is connected in series to the structure, a trench source region is inserted in a lower portion of the electrode Directional low clamping transient voltage suppressing element having a lower clamping voltage and capacitance (Vc) and a higher peak pulse current (Ipp) than the conventional one, thereby forming a well region on one side.

A transient voltage suppressing device according to the present invention includes: a substrate of a first conductivity type; An epitaxial layer of a first conductivity type formed on top of the substrate; A first buried layer of a second conductivity type formed in the epitaxial layer; A second buried layer of a second conductivity type formed on one side of the first buried layer, the second buried layer being formed on the epitaxial layer; A third buried layer of a first conductivity type formed on the first buried layer; A fourth buried layer of a second conductivity type formed on the third buried layer; A trench source region of a first conductivity type formed in the epitaxial layer, wherein a plurality of first trenches are formed on one side of the first buried layer and each is deposited on the first trench; A pair of first conductivity type first conductivity type regions formed on both sides of the first buried layer in the epitaxial layer; And a pair of second conductivity type second conductivity type regions formed on both sides of the first buried layer in the epitaxial layer.

And a well region of a second conductivity type formed in the epitaxial layer on one side of the trench source region, wherein the first conductivity type region and the second conductivity type region are formed in the well region.

A second trench is formed from the top of the epitaxial layer to the substrate and an insulating film is deposited on the second trench so that a region corresponding to the first buried layer, the second buried layer, the trench source region, .

The fourth buried layer is connected to one of the pair of first conductivity type regions through an electrode formed on the upper part.

The trench source region is connected to one of the pair of second conductivity type regions through an upper electrode.

The first conductive type region and the second conductive type region form a diode structure.

The first buried layer is connected to the trench source region through the substrate.

The fourth buried layer, the third buried layer, the first buried layer and the substrate form a Shockley diode structure.

And an insulating layer formed from an upper portion of the epitaxial layer and exposing portions of the fourth buried layer, the trench source region, the first conductive type region, and the second conductive type region.

Wherein the epitaxial layer comprises a first epitaxial layer on which the first and second buried layers are formed, a second epitaxial layer formed on the first epitaxial layer and on which the third buried layer is formed, And a third epitaxial layer formed on the top of the texial layer and on which the fourth buried layer is formed.

A method of fabricating a transient voltage suppressing device according to the present invention includes: preparing a substrate of a first conductivity type; Forming an epitaxial layer of a first conductivity type on the substrate; Forming a first buried layer and a second buried layer of a second conductivity type on the epitaxial layer; Forming a plurality of first trenches on one side of the first buried layer with respect to the epitaxial layer and forming trench source regions of a first conductivity type on the first trenches, respectively; Forming a third buried layer of the first conductivity type on the first buried layer with respect to the epitaxial layer; Forming a fourth buried layer of the second conductivity type on the third buried layer with respect to the epitaxial layer; And forming a first conductive type first conductive type region and a second conductive type second conductive type region on both sides of the first buried layer with respect to the epitaxial layer.

Further comprising forming a well region of a second conductivity type in the epitaxial layer on one side of the trench source region, wherein the first conductivity type well region and the second conductivity type region .

Forming a second trench from the top of the epitaxial layer to the substrate and depositing an insulating film on the second trench so that a region corresponding to the first buried layer, the second buried layer, the trench source region, .

And forming an electrode on the fourth buried layer to connect one of the pair of the first conductivity type regions to the fourth buried layer.

And forming an electrode on top of the trench source region to connect the trench source region to one of the pair of second conductivity type regions.

In the present invention, a Schottky diode structure of a PNPN structure is formed in a chip scale package, and a PN forward diode is connected in series to the structure. A trench source region is inserted into a lower portion of the electrode, Directional low clamping transient voltage suppressing element having a lower clamping voltage and capacitance (Vc) and a higher peak pulse current (Ipp) than conventional ones, and a method of manufacturing the same.

1 is a circuit diagram showing the operation principle of a general transient voltage suppressing element.
2 is a flowchart illustrating a method of manufacturing a transient voltage suppressing device according to an embodiment of the present invention.
3A to 3O are cross-sectional views sequentially illustrating a method of manufacturing a transient voltage suppressor according to an embodiment of the present invention.
4 is a diagram showing an equivalent circuit of a structure of a transient voltage suppressing element according to an embodiment of the present invention.
5 is an equivalent circuit diagram of a transient voltage suppressing element according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

Hereinafter, a method of manufacturing a transient voltage suppressing device according to an embodiment of the present invention will be described.

2 is a flowchart illustrating a method of manufacturing a transient voltage suppressing device according to an embodiment of the present invention. 3A to 3O are cross-sectional views sequentially illustrating a method of manufacturing a transient voltage suppressor according to an embodiment of the present invention.

Referring to FIG. 2, a method for fabricating a transient voltage suppressing device according to an embodiment of the present invention includes a substrate preparing step S1, a first epitaxial layer forming step S2, a first buried layer forming step S3, The second epitaxial layer forming step S5, the third buried layer forming step S6, the third epitaxial layer forming step S7, the fourth buried layer forming step S8, the trench source forming step S6, The first conductivity type region forming step S9, the trench isolation forming step S10, the well region forming step S11, the first conductivity type region forming step S12, the second conductivity type region forming step S13, A step S14, and an electrode formation step S15. Hereinafter, the steps of FIG. 2 will be described with reference to FIGS. 3A to 3O.

As shown in FIG. 3A, in the substrate preparation step S1, a substrate 110 of a first conductivity type is prepared. The substrate 110 is in the form of a plate including an upper surface and a lower surface. The substrate 110 may be, for example, an N + + type semiconductor substrate formed by implanting an impurity such as arsenic (As), phosphorus (P), or antimony (Sb), which is a Group 5 element, into the intrinsic semiconductor at high concentration. Here, the high concentration means that the concentration is relatively higher than the impurity concentration of the epitaxial layer 120 to be described later. On the other hand, the substrate 110 of the first conductivity type may be a P-type in which impurity such as gallium (Ga), indium (In), or boron (B), which is a group III element, is implanted into the intrinsic semiconductor at high concentration. However, in the present invention, it is assumed that the substrate 110 is N-type.

As shown in FIG. 3B, the first epitaxial layer 120 may be further formed in the first epitaxial layer forming step S2. For example, at a high temperature of 600 to 2,000 ° C., a gas containing SiH ₄ gas and a pentavalent element such as arsenic (As), phosphorus (P), or antimony (Sb) The N-type first epitaxial layer 120 may be deposited on the surface of the substrate 110 by flowing the first epitaxial layer 120 together.

As shown in FIG. 3C, a first buried layer 130 of a second conductivity type extending in the horizontal direction is formed on the substrate 110 in the first buried layer forming step S3. Here, the first buried layer 130 is formed to have a certain depth from the upper surface of the first epitaxial layer 120 toward the inside. In addition, the first buried layer 130 may be located at a position where a Shockley diode having a PNPN structure is to be formed, for example, approximately at the center of the substrate 110. Accordingly, the first buried layer 130 may include a P + type region in the structure of the Shockley Diode (Shockley Diode).

The first buried layer 130 may be formed by forming an insulating film (not shown) such as a silicon oxide film or a nitrogen oxide film on the upper surface of the first epitaxial layer 120 in a region other than the region where the first buried layer 130 is formed Impurity such as gallium (Ga), indium (In) or boron (B) as a Group III element can be directly ion-implanted or a thermal diffusion process can be performed to form P + type.

On the other hand, a bottom insulating film may be formed on the bottom surface of the substrate 110. The insulating film may be formed of any one selected from the group consisting of a silicon oxide film, a nitrogen oxide film, undoped polysilicon, Phospho-Silicate-Glass (PSG), Borophosphoric Silicate-Glass (BPSG) However, the present invention is not limited thereto. The insulating layer prevents auto-doping of the first conductive type substrate 110 having a high concentration.

3D, a second P type buried layer 150 may be formed outside the first buried layer 130 in the second buried layer forming step S4. Here, the second buried layer 150 may be formed only on one side of the first buried layer 130. For example, as shown in FIG. 3D, the second buried layer 150 may be formed on the left side of the first buried layer 130. Here, a trench source region to be described below is formed on the right side of the first buried layer 130.

The second buried layer 150 may be formed by directly ion-implanting a Group III element or performing a thermal diffusion process in the same manner as the first buried layer 130. In addition, the second buried layer 150 may be formed in a relatively low P-type than the first buried layer 130.

3E, a second epitaxial layer 160 may be formed on the first epitaxial layer 120 in the second epitaxial layer formation step S5. The second epitaxial layer 160 may be formed on the first buried layer 130 and the second buried layer 150 to cover the first buried layer 130 and the second buried layer 150. The second epitaxial layer 160 may be formed of a mixture of a gas such as SiH ₄ and a pentavalent element such as arsenic (As), phosphorus (P), or antimony (Sb) in the same manner as the first epitaxial layer 120 An N-type second epitaxial layer 160 may be deposited on the surface of the first epitaxial layer 120 by flowing the contained gases at a low concentration.

As shown in FIG. 3F, the N + -type third buried layer 170 is formed on the first buried layer 130 in the third buried layer forming step S6. The third buried layer 170 may be formed by directly ion implanting 5-group impurities into the second epitaxial layer 160 or by thermal diffusion. In addition, the third buried layer 170 may form an N layer in the structure of the choke diode. Here, an additional first conductive type buried layer 171 may be further formed on the second epitaxial layer 160, which is the upper portion of the second buried layer 150, in the same manner as described above. Here, the buried layer 171 may be formed at a relatively low concentration as compared with the third buried layer 170.

As shown in FIG. 3G, a third epitaxial layer 180 is formed on the second epitaxial layer 160 in the third epitaxial layer formation step S7. Like the second epitaxial layer 160, the third epitaxial layer 180 may include a gas including SiH ₄ gas and arsenic (As), phosphorus (P), or antimony (Sb) To the N + -type impurity region.

3H, a P + type fourth buried layer 190 is formed on the third buried layer 170 in the fourth buried layer forming step S8. The fourth buried layer 190 may be formed by directly implanting an impurity such as gallium (Ga), indium (In) or boron (B), which is a group III element, in the same manner as the first buried layer 130, , And P + type. Accordingly, the fourth buried layer 190, the third buried layer 170, the first buried layer 130, and the substrate 110 can sequentially form a PNPN structure. Accordingly, the structure of the Shockley diode (Shockley Diode) Can be formed. Such a Shockley diode structure can be connected in series with forward and reverse forward diodes. Therefore, it is possible to form a bidirectional transient voltage suppressing device (TVS) structure with low capacitance. Further, it is possible to form a transient voltage suppressing element having a clamping voltage and capacitance (Vc) and a high peak pulse current (Ipp) which are lower than those of the prior art. For example, the clamping voltage (Vc) is measured at 5A, which is lower than the conventional 12V (measured 1pF -> 0.5pF). As a result, the clamping voltage . ≪ / RTI > In addition, it was confirmed that the peak pulse current Ipp in the transient voltage suppressor according to the present embodiment was increased from 8A to 5A.

3I, the third epitaxial layer 180, the second epitaxial layer 160, the first epitaxial layer 120, and the substrate 110 (FIG. 3C) are formed in the trench source region forming step S9 A plurality of trenches are formed at a predetermined depth to the trenches, and the first conductive impurities are implanted into the trenches to form the trench source regions 140. [ In particular, such a trench source region 140 has a PNPN structure (i.e., a Shockley diode structure formed by the fourth buried layer 190, the third buried layer 170, the first buried layer 130, and the substrate 110) The first and second buried layers 150 and 150 are formed.

By way of example and not limitation, a number of trenches may be formed in the third epitaxial layer 180, the second epitaxial layer 160, the first epitaxial layer 120, and the substrate 110 at a certain depth, Or a laser ablation process, and impurities of the first conductivity type (for example, POCl3, H₃PO4, etc.) are deposited and diffused at a high temperature in the thus formed trench, and then the vacancies are filled with polysilicon A trench source region 140 of the first conductivity type may be formed.

More specifically, although not limiting the present invention, POCl3 doping includes predeposition, which is largely a first stage, and diffusion-process, which drives the impurities into silicon at a high temperature of 850 DEG C or higher, can do. In the line deposition process, POCl 3 is implanted into the surface of the preformed trench at a temperature of about 810 ° C. In this process, a P 2 O 5 oxide film may be formed on the surface of the trench. In the subsequent diffusion process, heat treatment is performed at a temperature of about 820 ° C. to 860 ° C. to diffuse the P of the P₂O 5 layer into the surface of the trench, ie, Si, whereby the first conductive type (ie, N type) trench source region 140 . Here, the POCl3 doping results in a doping depth of approximately 0.5 mu m, so that the remaining pores of the trench can be filled with intrinsic polysilicon.

The trench source region 140 is formed by the shading diode structure (i.e., the fourth buried layer 190, the third buried layer 180, the first buried layer 150, and the substrate 110) and the forward diode structure The second conductive type region 230 and the first conductive type region 220 on the right side) are connected in series, and current flows through the second conductive type region 230 and the first conductive type region 220 in series.

3J, a trench is formed from the upper surface of the third epitaxial layer 180 in the trench isolation forming step (S10). By filling the trench with an insulating film, the trench isolation 210 is implemented . The trench isolation 210 may include a plurality of trench isolations 210: 211 - 218 spaced from the top surface of the third epitaxial layer 180.

Specifically, the first trench isolation 211 and the second trench isolation 212 sequentially include a third epitaxial layer 180, a second epitaxial layer 160, a first epitaxial layer 120, The third buried layer 171, and the second buried layer 150 to reach the substrate 110, and may be isolated. Also, the diode structure formed in the upper third epitaxial layer 180 can be made independent.

The third trench isolation 213 and the fourth trench isolation 214 are also sequentially passed from the top through the fourth buried layer 190, the third buried layer 170 and the first buried layer 130, 110, so that these PNPN structures can be made independent of other structures while forming the above-described choke diode structure.

The fifth trench isolation 215 and the sixth trench isolation 216 may also include a third epitaxial layer 180, a second epitaxial layer 160, and a first epitaxial layer 120 sequentially from the top. To reach the substrate 110 so that the trench source region 140 is isolated from other structures.

The seventh trench isolation 217 and the eighth trench isolation 218 may also include a third epitaxial layer 180, a second epitaxial layer 160, and a first epitaxial layer 120 sequentially from the top. And may be formed so as to reach the substrate 110 and be isolated. In addition, the well region and the diode structure to be formed in the upper third epitaxial layer 180 can be made independent.

Next, as shown in FIG. 3K, a third epitaxial layer 180 surrounded / isolated by the seventh trench isolation 217 and the eighth trench isolation 218 in the well region formation step S11 is formed. So that the well region 200 of the conductive type is formed. The depth of the well region 200 may be less than the depth of the third epitaxial layer 180.

The well region 200 may be formed by directly ion-implanting a Group 3 element into the third epitaxial layer 180 or by performing a thermal diffusion process. Thus, the well region 200 has a different conductive form from that of the third epitaxial layer 180, so that a buried-schottky diode structure is not formed.

Then, as shown in FIG. 31, a third epitaxial layer 180 between the first trench isolation 211 and the second trench isolation 212 is formed in the first conductive type region forming step S12, The N + type first conductive type region 220 is formed for the well region 200 formed between the first trench isolation 217 and the eighth trench isolation 218, respectively. The first conductivity type region 220 forms a part of a forward diode structure located at the front and rear ends of the structure of the shockle diode.

As shown in FIG. 3M, the third epitaxial layer 180 between the first trench isolation 211 and the second trench isolation 212 in the second conductive type region forming step S13 Type second conductivity type region 230 are formed for the well region 200 formed between the first trench isolation 217 and the eighth trench isolation 218. The p + The second conductive type region 230 is located to correspond to the first conductive type region 220 and the structure of the diode can be completed through the structure of the conductive type regions 220 and 230.

At this time, a second conductive type region 260 having a predetermined depth from the third epitaxial layer 180 may be further formed on the outer periphery of the first trench isolation 211 and the outer periphery of the eighth trench isolation 218, respectively . This pair of second conductivity type regions 260 serves to lower the MOSFET capacitance in the transient voltage suppressor according to the embodiment of the present invention.

3N, an insulating film 240 is formed on the upper surface of the structure in the insulating film (contact) forming step S14, a via is formed in each insulating film 240, and each diode or a shockle diode A contact can be formed in the structure. The insulating layer 240 may be formed of any one selected from the group consisting of a silicon oxide layer, a nitrogen oxide layer, undoped polysilicon, phospho-silicate-glass (PSG), borophosphoric-silicate-glass (BPSG) However, the present invention is not limited thereto.

3O, the first conductive type region 220, the second conductive type region 230, and the fourth buried layer 190 (not shown) exposed through the insulating layer 240 in the electrode forming step S15 And an electrode 250 is formed on the upper surface of the trench source region 140. Here, the first conductive type region 220 (i.e., a forward diode) on the left side in the drawing is connected to the fourth buried layer 190 (i.e., a Shockley diode) through the electrode 250, and the trench source region 140 Is connected to the right second conductive region 230 (i. E., A forward diode) through an electrode 250. The electrode 250 is connected to the left second conductive region 230 and the electrode 250 is connected to the right first conductive region 220. The electrode 250 may be formed of a conductive wire, A clip or a lead frame can be connected.

The electrode 250 may be formed by sequentially sputtering or sequentially plating a selected one of molybdenum (Mo), aluminum (Al), nickel (Ni), gold (Au), and the like, It does not.

As described above, the structure of the choke diode can be formed between the forward diodes formed in the left and right regions of the drawing. Particularly, the fourth buried layer 190, the third buried layer 170, the first buried layer 130, and the substrate 110 may sequentially form a PNPN structure. Accordingly, the structure of the Shockley diode (Shockley Diode) Can be formed. In addition, the Shockley diode structure can be connected in series with left and right forward diodes. Therefore, it is possible to form a bidirectional transient voltage suppressing device (TVS) structure with low capacitance. Further, it is possible to form a transient voltage suppressing element having a clamping voltage and a capacitance (Vc) and a high peak pulse current (Ipp) which are lower than those of the prior art.

Further, in the present invention, the sharkle diode structure is connected to the forward diode through the trench source region having the substrate and trench structure, thereby further lowering the clamping voltage and capacitance, and further increasing the peak pulse current. Furthermore, the forward diode on the right side in the drawing further includes a well region, which is a different conductive type compared to the third epitaxial layer, so that the occurrence of the parasitic Shockley diode structure can be suppressed.

Hereinafter, the circuit configuration of the transient voltage suppressing device according to the embodiment of the present invention will be described in more detail.

4 is a diagram showing an equivalent circuit of a structure of a transient voltage suppressing element according to an embodiment of the present invention. 5 is an equivalent circuit diagram of a transient voltage suppressing element according to an embodiment of the present invention.

4 and 5, the transient voltage suppressor according to the exemplary embodiment of the present invention includes a PNPN (n-type PNPN) structure including a fourth buried layer 190, a third buried layer 170, a first buried layer 130, (Shockley Diode or DIAC) can be connected in series with a forward diode (PN Recti) at the front end and a forward diode (PN Recti) at the rear end.

Meanwhile, the transient voltage suppressor according to the present invention has a structure in which the above-described cross-sectional structures are opposite to each other and are electrically connected to each other when viewed in plan.

Accordingly, as shown in FIG. 5, the transient voltage suppressor has a structure in which reverse diodes are connected in parallel to the forward diodes connected in series as a whole, so that the transient voltage suppressor according to the present invention operates in both directions do.

In this way, the transient voltage suppressor according to the embodiment of the present invention can form a bidirectional transient voltage suppressing device (TVS) structure having a low capacitance, and has a lower clamping voltage, a lower capacitance Vc, A transient voltage suppressing element having a high peak pulse current Ipp can be formed.

It is to be understood that the present invention is not limited to the above-described embodiment, and that various modifications and changes may be made by those skilled in the art without departing from the spirit and scope of the present invention. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

110; Substrate 120; The first epitaxial layer
130; A first buried layer 140; Trench source region
150; A second buried layer 160; The second epitaxial layer
170; A third buried layer 180; The third epitaxial layer
190; A fourth embedding layer 200; Well region
210; Trench isolation 220; The first conductivity type region
230; A second conductivity type region 240; Insulating film
250; electrode

Claims (15)

A substrate of a first conductivity type;
An epitaxial layer of a first conductivity type formed on top of the substrate;
A first buried layer of a second conductivity type formed in the epitaxial layer;
A second buried layer of a second conductivity type formed on one side of the first buried layer, the second buried layer being formed on the epitaxial layer;
A third buried layer of a first conductivity type formed on the first buried layer;
A fourth buried layer of a second conductivity type formed on the third buried layer;
A trench source region of a first conductivity type formed in the epitaxial layer, wherein a plurality of first trenches are formed on one side of the first buried layer and each is deposited on the first trench;
A pair of first conductivity type first conductivity type regions formed on both sides of the first buried layer in the epitaxial layer; And
And a pair of second conductivity type second conductivity type regions formed on both sides of the first buried layer in the epitaxial layer. The method according to claim 1,
And a well region of a second conductivity type formed in the epitaxial layer on one side of the trench source region,
And the first conductivity type region and the second conductivity type region are formed in the well region. 3. The method of claim 2,
A second trench is formed from the top of the epitaxial layer to the substrate and an insulating film is deposited on the second trench so that a region corresponding to the first buried layer, the second buried layer, the trench source region, The transient voltage suppressing element isolating the transient voltage. The method according to claim 1,
Wherein the fourth buried layer is connected to one of the pair of first conductive regions through an electrode formed on the upper portion. The method according to claim 1,
Wherein the trench source region is connected to one of the pair of second conductivity type regions through an upper formed electrode. The method according to claim 1,
Wherein the first conductivity type region and the second conductivity type region form a diode structure. The method according to claim 1,
Wherein the first buried layer is connected to the trench source region through the substrate. The method according to claim 1,
Wherein the fourth buried layer, the third buried layer, the first buried layer and the substrate form a Shockley diode structure. The method according to claim 1,
And an insulating film formed from an upper portion of the epitaxial layer and exposing portions of the fourth buried layer, the trench source region, the first conductive type region, and the second conductive type region. The method according to claim 1,
Wherein the epitaxial layer comprises a first epitaxial layer on which the first and second buried layers are formed, a second epitaxial layer formed on the first epitaxial layer and on which the third buried layer is formed, And a third epitaxial layer formed on the top of the trench layer and on which the fourth buried layer is formed.
Preparing a substrate of a first conductivity type;
Forming an epitaxial layer of a first conductivity type on the substrate;
Forming a first buried layer and a second buried layer of a second conductivity type on the epitaxial layer;
Forming a plurality of first trenches on one side of the first buried layer with respect to the epitaxial layer and forming trench source regions of a first conductivity type on the first trenches, respectively;
Forming a third buried layer of the first conductivity type on the first buried layer with respect to the epitaxial layer;
Forming a fourth buried layer of the second conductivity type on the third buried layer with respect to the epitaxial layer; And
And forming a first conductive type first conductive type region and a second conductive type second conductive type region on both sides of the first buried layer with respect to the epitaxial layer. 12. The method of claim 11,
Forming a well region of a second conductivity type in the epitaxial layer on one side of the trench source region,
And the first conductivity type region and the second conductivity type region are formed in the well region of the second conductivity type. 13. The method of claim 12,
Forming a second trench from the top of the epitaxial layer to the substrate and depositing an insulating film on the second trench so that a region corresponding to the first buried layer, the second buried layer, the trench source region, Wherein the method further comprises the steps of: 12. The method of claim 11,
And forming an electrode on the fourth buried layer to connect one of the pair of first conductive type regions to the fourth buried layer. 12. The method of claim 11,
And forming an electrode on the trench source region to connect one of the pair of the second conductivity type regions to the trench source region.

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