KR20190019617A - Gip circuit and display device using the same - Google Patents

Abstract

The present invention provides a display device capable of forming a small size of a non-display area. The display device comprises: a display panel in which a plurality of gate lines and a plurality of data lines cross each other wherein the display panel is divided into a 1-1 region, a 1-2 region and a second region; a first gate circuit which is disposed on one side of the display panel and sequentially applies a gate signal to the gate lines arranged in the 1-1 region; a second gate circuit which is disposed on one side of the display panel and sequentially applies the gate signal to the odd-numbered gate lines among the gate lines arranged in the second region; a third gate circuit which is disposed on the other side of the display panel and sequentially applies the gate signal to the gate lines arranged in the 1-2 region; a fourth gate circuit which is disposed on the other side of the display panel and sequentially applies the gate signal to the even-numbered gate lines among the gate lines arranged in the second region; and a data driver circuit which applies a data signal to the plurality of data lines.

Description

TECHNICAL FIELD [0001] The present invention relates to a gate driver circuit and a display device using the gate driver circuit.

The present embodiments relate to a gate driver circuit and a display using the same.

BACKGROUND ART Demands for a display device for displaying an image have been increasing in various forms as an information society has developed. The demand for display devices such as a liquid crystal display device (LCD), an organic light emitting display device (OLED) Various types of flat panel display devices have appeared.

Recently, flat panel display devices have been adopted in mobile devices and widely used. The mobile device is being developed so that the entire front surface employing the display panel can display images for aesthetics or ease of use.

However, in the mobile device, the lens of the camera is installed on the front side, and the area occupied by the lens can not display the image. In addition, the gate lines are cut off due to the area occupied by the lens, so that there is a restriction in widening the area of the display area in which the image can be displayed on the display panel.

In general, when the size of the display panel is increased, there is a problem that power consumption is increased. However, because the mobile device is powered by the battery, the usage time can be determined according to the capacity of the battery. In addition, mobile devices are being developed thin and light for convenient use.

Therefore, if the size of the display panel is increased because the capacity of the battery of the mobile device can not be increased, the use time is shortened.

An object of these embodiments is to provide a gate driver circuit which can realize a small size of a non-display area in a display device and a display device using the same.

An object of these embodiments is to provide a gate driver circuit which can increase the use time and a display device using the same.

Another object of the present invention is to provide a gate driver circuit and a display device which enable image display around a mounting space of an application part such as a camera lens and a sensor.

In one aspect, the present embodiments include a display panel in which a plurality of gate lines and a plurality of data lines intersect and are divided into a 1-1 region, a 1-2 region and a second region, A first gate circuit for sequentially applying a gate signal to gate lines arranged in a first region of the display region, a second gate circuit arranged on one side of the display panel, A third gate circuit arranged on the other side of the display panel for sequentially applying a gate signal to gate lines arranged in a first-second region, a second gate circuit arranged on the other side of the display panel, A fourth gate circuit for sequentially applying a gate signal to even-numbered gate lines among the gate lines arranged in the second region, and a third gate circuit for applying a data signal to the plurality of data lines Emitter to provide a display device including the driver circuit.

In another aspect, the present embodiments provide a display panel, a first GIP (Gate In Panel) block for sequentially outputting gate signals of k (k is a natural number of 2 or more), and k gate signals sequentially, A third GIP block that sequentially outputs k gate signals when at least one of the k gate signals output from the first GIP block is input, a third GIP block that sequentially outputs k gate signals, A fourth GIP block sequentially outputting a plurality of gate signals output in synchronization with a plurality of gate signals output from the first GIP block, a fourth GIP block sequentially outputting k gate signals, 5GIP block, and k gate signals output from the fifth GIP block, the controller sequentially outputs k gate signals, To provide a display device including a first block 6GIP that intersects the k gate signal output from.

According to another aspect of the present invention, there are provided a first stage for sequentially outputting gate signals k (k is a natural number equal to or greater than 2), and a second stage for sequentially outputting k gate signals, And a third stage for sequentially outputting k gate signals when one of the k gate signals output from the first stage is input, and a third stage for sequentially outputting k gate signals, A fifth stage for sequentially outputting k gate signals and alternately outputting k gate signals output from the fourth stage, and a fifth stage for outputting k gate signals sequentially outputted from the fifth stage, And a sixth stage for sequentially outputting k gate signals when one of the signals is input Is to provide a gate driver circuit.

According to the embodiments, a gate driver capable of realizing a small size of a non-display region and a display using the gate driver are provided.

Further, according to the embodiments, a gate driver circuit capable of reducing power consumption and a display device using the same can be provided.

In addition, according to the embodiments, a gate driver circuit and a display device which enable image display around a mounting space of an application part such as a camera lens and a sensor can be provided.

Fig. 1 is a structural diagram showing an embodiment of a display device according to the present embodiments.
2 is a structural diagram showing an embodiment of a display device according to the present embodiments.
3 is a plan view showing one embodiment of a front portion of a display device according to the present embodiments.
4 is a plan view showing one embodiment of a front portion of a display device according to the present embodiments.
5 is a plan view showing one embodiment of a gate line arranged in a display device.
FIG. 6 is a conceptual view of the front area of the display device. FIG.
7 is a structural diagram showing one embodiment of a gate driver circuit employed in a display device according to the present embodiments.
Fig. 8 is a structural diagram showing one embodiment of a gate driver circuit employed in the display device according to the present embodiments.
FIG. 9 is a state transition diagram showing that the display device according to the present embodiments is changed from a low power mode to a normal mode.
10 is a conceptual diagram showing that the display device according to the present embodiments is displayed in a normal mode and a low power mode.
11 is a conceptual diagram showing an embodiment of an image displayed in a low power mode in a display device according to the present embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

Fig. 1 is a structural diagram showing an embodiment of a display device according to the present embodiments.

1, the display device 100 includes a display panel 110, a data driver circuit 120, a first gate driver circuit 130a, a second gate driver circuit 130b, and a controller 140 .

A plurality of pixels 101 may be formed in an area where a plurality of gate lines G1, G2, ..., Gn-1, Gn and a plurality of data lines D1, ..., Dm intersect with each other And each pixel 101 may include a thin film transistor (not shown) for selectively transmitting a data signal. Each pixel 101 may be a red pixel R, a green pixel G, and a blue pixel G, respectively. The red pixel R, the green pixel G, and the blue pixel G may transmit red, green, and blue light corresponding to the data signal. The display panel 110 may be a liquid crystal display panel using liquid crystal or an organic light emitting diode panel using an organic light emitting diode. However, the present invention is not limited thereto. The wiring arranged in the display panel 110 is not limited to the plurality of gate lines G1, G2, ..., Gn-1, Gn and the plurality of data lines D1, ..., Dm.

The data driver circuit 130 is connected to the plurality of data lines D1 to Dm to supply the data signals to the data lines D1 to Dm. The data driver circuit 130 may include a plurality of drive ICs (not shown) and the number of drive ICs may be determined corresponding to the resolution and / or size of the display panel 110. In addition, the data driver circuit 130 may be connected to a plurality of data lines D1, ..., Dm through a multiplexer. The data driver circuit 130 receives a video signal to generate a data signal, and may transmit a data voltage corresponding to the data signal to the data lines D1, ..., Dm.

The first gate driver circuit 130a is connected to the odd gate lines G1 to Gn-1 of the plurality of gate lines G1 to Gn to sequentially supply gate signals have. The second gate driver circuit 130b may be connected to even-numbered gate lines G2, ..., Gn among the plurality of gate lines G1, G2, ..., Gn-1, Gn to sequentially supply gate signals. The first gate driver circuit 130a and the second gate driver circuit 130b each include a plurality of stages and sequentially output gate signals at each stage.

The control unit 140 may transmit control signals to the data driver circuit 120, the first gate driver circuit 130a, and the second gate driver circuit 130b, respectively. Also, the control unit 140 can supply the video signal to the data driver circuit 120. [

Also, the control unit 140 may receive an input signal from the external device 150. The external device may be a keyboard, a mouse, or a touch panel. However, the present invention is not limited thereto. The controller 140 may cause the display panel 110 to operate in a normal mode or a low power mode in response to an input signal.

2 is a structural diagram showing an embodiment of a display device according to the present embodiments.

Referring to FIG. 2, the display device 200 may include a display panel 210, a plurality of driver ICs 220 and 230, and a control unit 240.

The display panel 210 includes a display area 211 for displaying an image at the center and non-display areas 212a and 212b disposed on both sides of the display area 211 for supplying signals to the display area 211 . The non-display areas 212a and 212b may include a first non-display area 212a and a second non-display area 212b in which a plurality of GIP blocks GIP are disposed, respectively. In the display area 211, as shown in FIG. 1, a plurality of data lines and a plurality of gate lines may be arranged so as to cross each other, and the pixels P may be disposed at intersections. A plurality of GIP blocks (GIP) connected to the odd gate lines among the plurality of gate lines are arranged in the first non-display area 212a. In the second display area 212b, even-numbered gate lines A plurality of GIP blocks (GIP) to be connected may be arranged. However, the connection of the GIP block and the gate line is not limited thereto.

The gate signals can be sequentially supplied by the GIP block GIP so that the widths of the non-display areas 212a and 212b of the display panel 210 are narrowed and the area of the display area 211 is further reduced It can be implemented largely. Also, the GIP block (GIP) may correspond to the stage described in Fig.

The plurality of driver ICs 220 and 230 may include a driver IC 220 connected to a data line to drive a data signal and a driver IC 230 connected to a GIP block GIP to drive a GIP block GIP . The number of the driver ICs 220 driving the data signal may correspond to the resolution and / or the size of the display area 211. When the GIP block arranged in the first non-display area 212a and the second non-display area 212b is driven by the driver IC driving the gate signal, the plurality of GIP blocks are sequentially driven by the gate signal to the gate line .

The control unit 240 may output a control signal for controlling the plurality of driver ICs 220 and 230. In addition, the control unit 240 may supply the video signal to the driver IC 220 driving the data line among the plurality of driver ICs 220 and 230.

In addition, the control unit 240 may receive an input signal from the external device 150. [ The external device 250 may be a keyboard, a mouse, or a touch panel. However, the present invention is not limited thereto. The control unit 240 may cause the display panel 210 to operate in a normal mode or a low power mode in response to an input signal.

3 is a plan view showing one embodiment of a front portion of a display device according to the present embodiments.

Referring to FIG. 3, a display panel 310 may be disposed on a front surface of the display device 300. At least one hole 311 arranged in one area of the front part of the display device and in which the display panel 310 is disposed and at least one application part such as a camera lens or sensor is formed on the upper part of the display panel 310 . The hole 311 disposed on the upper portion of the display panel 310 is not limited thereto. The display device 300 may include a bezel 301 disposed at an edge of the display panel 300.

The display panel 310 may be divided into a first area 310a and a second area 310b. The first region 310a may be disposed above the second region 310b and may be formed to be thinner than the second region 310b. Also, the first area 310a may be an area for displaying an image in the low power mode, and the second area 310b may be an area for displaying an image in the normal mode. The image displayed in the first area 310a can display a simple icon or the like. The icon or the like displayed in the first area 310a may not be changed in color or shape for a long time and the current flowing may be kept constant, so that the power consumption may not be significantly increased. In addition, the image displayed in the second area 310b may display a moving image or a still image including various colors, so that a large change in the current may occur. Thus, the first region 310a can be called a low power mode region and the second region 310b can be called a normal display region.

FIG. 4 is a plan view showing one embodiment of a front portion of a display device according to the present embodiments, and FIG. 5 is a plan view showing an embodiment of a gate line arranged in a display device. Fig. 6 is a conceptual view of the front area of the display device.

Referring to FIG. 4, the front portion of the display device 300 may include a display panel 310. The display panel 310 may be divided into a first area 310a and a second area 310b. The first area 310a may be an area for displaying an image in a low power mode and the second area 310b may be an area for displaying an image in a normal mode. However, the present invention is not limited thereto.

In addition, the first area 310a may have a hole 311 through which a camera lens, a sensor, or the like can protrude. However, the reason why the hole 311 is formed is not limited to this.

Alternatively, the region 310a may include a portion to which an application component such as a camera lens or a sensor may be attached.

Also, the first area 310a may be referred to as a low power mode area and the second area 310b may be referred to as a normal display mode area. The low power mode area may be an area where an image is displayed in the standby mode and the normal display mode area may be an area where the image is displayed when the normal mode is used. A plurality of gate lines arranged in the first region 310a may be referred to as a first gate line, and a plurality of gate lines arranged in the second region 310b may be referred to as a second gate line.

Since the first area 310a is overlapped with the area where the hole 311 in which the camera lens is formed is formed, the position of the first area 310a is the area where the display panel is not formed in the mobile device shown in FIG. So that the height h2 of the second area is longer than the height h1 of the second area shown in Fig. 3, so that the size of the display panel 310 can be increased in the front part have.

When the area where the hole 311 is formed is enlarged, the first gate lines disposed in the first region 310a may be cut off as shown in FIG. Accordingly, the first gate lines G11 and G12, the second gate lines G21 and G22, the third gate lines G31 and G32, and the fourth gate line G41 and G42 may be two lines, respectively . On the other hand, the second gate lines disposed in the second region 310b are not disconnected, so that the fifth gate line G5 and the sixth gate line G6 may be formed as one line.

A region of the first region 310a formed on the left side of the hole 311 with respect to the hole 311 is referred to as a 1-1 region 311a and a region formed on the right side of the hole is referred to as a 1- 2 region 312a. The first direction length L3 of the second region 310b is equal to the first direction length L1 of the first region 311a and the first direction L2 of the first and second regions 312a, The length in the second direction of the 1-1 zone 311a and the length in the second direction of the 1-2 zone 312a may correspond to each other. Here, the second direction may be perpendicular to the first direction and may be a direction corresponding to the height of the display device. An application component may exist between the first-first region 311a and the first-second region 312a. The application part may be a camera lens or a camera. However, the present invention is not limited thereto.

As described above, the plurality of gate lines are arranged so that the first gate lines drive the driving circuits G11, G21, G31 and G41 and the driving circuits G12, G22, G32 and G42 to drive the first gate line to the fourth gate line A gate driving circuit is required. The gate drive circuit may be a GIP block (GIP) shown in Fig. In order to drive the odd-numbered gate lines and the even-numbered gate lines as in driving the second gate lines, two driving circuits for driving G11, G21, G31 and G41 are required in the first area, and G12, G22, G32 and G42 It may be necessary to use two driving circuits. That is, in the first region 310a, four driver circuits may be required to drive four gate lines. However, the present invention is not limited thereto.

Two of the four driving circuits are disposed on the left and right sides of the display panel 310 and disposed in a non-display area covered by the bezel 301, and the remaining two driving circuits include holes 311 The area of the region where the light is not emitted around the hole 311 becomes large due to the driving circuit.

A first gate circuit is disposed on one side of the display panel 310 and sequentially applies gate signals to the gate lines arranged in the first area 311a of the first area 310a. A second gate circuit disposed on one side of the display panel 310 and sequentially applying a gate signal to the odd gate lines among the gate lines arranged in the second region 310b, A third gate circuit for sequentially applying a gate signal to the gate lines arranged in the first and second regions 312a of the first region 310a and a second gate region 310b arranged on the other side of the display panel 310, And a fourth gate circuit for sequentially applying a gate signal to the even-numbered gate lines among the gate lines arranged in the second gate line.

As shown in FIG. 6, a first-first area 311a, a first-second area 312a, and a second area 310b may be disposed on the front surface of the display device 300. The first area 311a and the first and second areas 312a are disposed on the upper portion of the display panel 310 and the second area 310b is formed on the lower part thereof, Can be disposed. In this case, the first gate circuit may be disposed at the left end of the 1-1 zone 311a of the display panel 310, the second gate circuit may be disposed below the first gate circuit, And may be disposed at the left end of the second region 310b. The first gate circuit and the second gate circuit may be disposed in the first area 311a and the second area 310b, respectively, adjacent to each other. The third gate circuit may be disposed at the right end of the first-second area 312a of the display panel 310, the fourth gate circuit may be disposed below the third gate circuit, 2 region 310b. The third gate circuit and the fourth gate circuit may be disposed in the first and second regions 312a and 310b, respectively, but may be disposed adjacent to each other.

The first area 311a and the second area 312a are disposed under the display device 300 and the second area 310b is disposed on the first area 311a and the second area 312a as shown in FIG. . In this case, the first gate circuit may be disposed at the left end of the first-first region 311a of the display panel 310, the second gate circuit may be disposed at the upper portion of the first gate circuit, And may be disposed at the left end of the second region 310b. The first gate circuit and the second gate circuit may be disposed in the first area 311a and the second area 310b, respectively, adjacent to each other. The third gate circuit may be disposed at the right end of the first-second area 312a of the display panel 310, the fourth gate circuit may be disposed at the upper portion of the third gate circuit, 2 region 310b. The third gate circuit and the fourth gate circuit may be disposed in the first and second regions 312a and 310b, respectively, but may be disposed adjacent to each other.

Also, the second area 310b may be disposed adjacent to both the first-first area 311a and the first-second area 312a.

As shown in FIG. 6 (a), when the 1-1 region 311a, the 1-2 region 312a, and the second region 310b are arranged, data is written in the lower direction from the upper portion of the display device The first-first region 311a, the first-second region 312a, and the second region 310b may be arranged as shown in FIG. 6 (b) , The data may be driven in a reverse manner (R) in which the data is written in the upper direction from the lower portion of the display device.

7 is a structural diagram showing one embodiment of a gate driver circuit employed in a display device according to the present embodiments.

7, the gate driver circuit 430 includes a first gate driver block 430a that can be disposed on the left side of the display panel 310 and a second gate driver block 430b that can be disposed on the right side of the display panel ). The first gate driver block 430a may be disposed on the first non-display area 212a on the left side of the display panel 211 shown in FIG. 2 and the second gate driver block 430b may be disposed on the left side of the display panel 211 And can be disposed in the second non-display area 212b on the right side. However, the present invention is not limited thereto. The first gate driver block 430a outputs odd gate signals G1, G3, G5, G7, G9 and G11 driven on the odd gate lines and the second gate driver block 430b outputs the odd gate signals G1, (G2, G4, G6, G8, G10, and G12) to be driven.

The first gate driver block 430a includes a first stage 431a for sequentially outputting the first gate signal G1 and the third gate signal G3 and a fourth stage 431b for sequentially outputting the fifth gate signal G5 and the seventh gate signal G7 A third stage 433a for outputting a ninth gate signal G9 and an eleventh gate signal G11.

The second gate driver block 430b includes a fourth stage 431b for sequentially outputting the second gate signal G2 and the fourth gate signal G4 and a fourth stage 431b for sequentially outputting the sixth gate signal G6 and the eighth gate signal G8 And a sixth stage 433b sequentially outputting the tenth gate signal G10 and the twelfth gate signal G12. The fifth stage 432b sequentially outputs the tenth gate signal G10 and the sixth gate signal G12.

However, the number of gate lines output in one stage and the number of stages included in the gate driver circuit are not limited thereto.

The first stage 431a to the third stage 433a, and the fourth stage 431b to the sixth stage 433b, respectively. Here, the clock input to the first stage 431a through the third stage 433a and the clock input to the fourth stage 431b through the sixth stage 433b may have different phases. In addition, the first stage 431a and the fourth stage 431b can receive a start signal START, respectively. The first stage 431a outputs a first gate signal G1 corresponding to the start signal START and a clock and outputs a first gate signal G1 and a third gate signal G3 corresponding to the first clock can do. The second stage 42a can output the fifth gate signal G5 corresponding to the third gate signal G3 and the clock and can output the seventh gate signal G5 corresponding to the fifth gate signal G5 and the clock. G7). The third stage 433a can output the ninth gate signal G9 in correspondence with the seventh gate signal G7 and the clock signal and the eleventh gate signal G9 corresponding to the ninth gate signal G9 and the clock. 0.0 > G11. ≪ / RTI >

The fourth stage 431b to the sixth stage 433b are connected to the second gate signal G2 and the fourth gate signal G4 in the same manner as the first stage 431a to the third stage 433b. The even-numbered gate signals can be sequentially output. The clocks input to the fourth stage 431b through the sixth stage 433b are delayed in phase relative to the clocks input to the first stage 431a through the third stage 433b so that the first gate signal G1, The second gate signal G2 may be output, the third gate signal G3 may be output, and the fourth gate signal G4 may be output. That is, an even-numbered gate signal may be generated after one odd-numbered gate signal is generated, and an odd-numbered gate signal and an even-numbered gate signal may be generated alternately. However, the present invention is not limited thereto.

The start signal START supplied to the first stage 431a and the fourth stage 431b may be a synchronized signal and may be supplied to the first stage 431a and the fourth stage 431b through different wirings, . However, the present invention is not limited thereto.

In the gate driver circuit 430, the first gate driver block 430a and the second gate driver block 430b are connected to the first switch portion SW1 for connecting the first stage 431a and the second stage 432a, And a second switch SW2 for connecting the fourth stage 431b and the fifth stage 431b. The first stage 431a and the fourth stage 431b are disposed in the first region 310a of the display panel 310 shown in FIG. 3 or 4 and the second stage 432a and the third stage 433a , And the fifth stage 432b and the sixth stage 433b may be disposed in the second region 310b.

The third gate signal G3 output from the first stage 431a may be supplied to the third stage 432a through the first switch SW1. The fourth gate signal G4 output from the fourth stage 431b may be supplied to the fifth stage 432b through the second switch SW2.

The first stage 431a to the sixth stage 433b sequentially output two gate signals, and the third gate signal G3 output from the first stage 431a is output to the first stage 431a, The fourth gate signal G4 outputted from the stage 431a and the fourth gate signal G4 outputted from the fourth stage 431b may correspond to the second gate signal outputted from the fourth stage 431b. However, the present invention is not limited thereto.

When the first switch unit SW1 and the second switch unit SW2 are turned off, the third gate signal G3 and the fourth gate signal G4 are supplied to the second stage 432a and the fifth stage The gate driver circuit 430 can output the first gate signal G1 through the fourth gate signal G4 only in the first stage 431a and the fourth stage 431b. Therefore, only the first area 310a of the display panel 310 is transferred with the gate signal, so that only the first area 310a can display the image.

When the first switch unit SW1 and the second switch unit SW2 are turned on, the third gate signal G3 and the fourth gate signal G4 are supplied to the second stage 432a and the fifth stage 432b, The gate driver circuit 430 is operated so that the first stage 431a to the sixth stage 433b are all operated so that the gate signal is transmitted to the first region 310a and the second region 310b, 310a and the second area 310b.

The first switch unit SSW1 and the second switch unit SW2 can operate in response to the enable signal Enable and the enable signal Enable can not be transmitted in the low power mode, And the second switch unit SW2 are turned off so that an image is displayed only in the first area 310a and an enable signal is transmitted in the normal mode so that the first area 310a and the second area 310b ) Can be displayed on all of the images. Therefore, the display device can reduce the power consumption in the low power mode than in the normal mode. The enable signal Enable may be output from the control unit shown in FIGS. 1 and 2. In response to the input signal, the control unit may determine whether to output the enable signal Enable.

Here, although each of the first gate driving block 430a and the second gate driving block 430b is shown as including a plurality of stages, each stage may correspond to the GIP circuit shown in Fig. 7 is a structural diagram showing one embodiment of a gate driver circuit employed in a display device according to the present embodiments.

Referring to FIG. 7, the gate driver circuit 530 may include a first gate driver block 530a disposed on the left side of the display panel and a second gate driver block 530b disposed on the right side of the display panel. The first gate driver block 530a is disposed on one side of the display panel and includes a first gate circuit and a second gate circuit respectively disposed in the 1-1 region 311a and the second region 310b in FIG. And the second gate driver block 530b is disposed on the other side of the display panel and includes a first gate circuit and a second gate arranged in the first and second regions 312a and 310b, respectively, Circuit.

The first gate driver block 530a sequentially outputs the first stage 531a and the second gate signals G2 and G4 sequentially outputting the plurality of gate signals G1 and G3, A second stage 542a for intersecting a plurality of gate signals outputted from the first stage 531a and a second gate signal G3 outputted from the first stage 531a, And a third stage 532a for sequentially outputting signals.

The second gate driver block 530b sequentially outputs the plurality of gate signals G1 and G3 and sequentially outputs the gate signals G1 and G3 to the fourth stages 542b and 542b in synchronization with the two gate signals output from the first stage 531a, A fifth stage 531b that sequentially outputs a plurality of gate signals G2 and G4 and a plurality of gate signals output from the fourth stage 542b and a fifth stage 531b that outputs a plurality of gate signals G2 and G4 output from the fifth stage 531b And sequentially outputs the two plurality of gate signals G6 and G8 and outputs the two gate signals G5 and G7 output from the third stage 532a and the two gate signals G5 and G7, And a sixth stage 532b that allows the first stage 532a to be activated.

The first stage 531a sequentially outputs the first gate signal G1 and the third gate signal G3 and the second stage 542a outputs the second gate signal G2 and the fourth gate signal G4 Can be output sequentially. The fourth stage 542b sequentially outputs the first gate signal G1 and the third gate signal G3 and the fifth stage 531b sequentially outputs the second gate signal G2 and the fourth gate signal G4 Can be sequentially output. Accordingly, the first stage 531a and the second stage 542a sequentially output the first gate signal G1 to the fourth gate signal G4, and the fourth stage 542b and the fifth stage 531b It is possible to sequentially output the first gate signal G1 to the fourth gate signal G4. The first stage 531a, the second stage 542a, the fourth stage 542b and the fifth stage 531b operate in response to the start signal START and the clocks, 4 gate signal G4 may be sequentially output.

The third gate signal G3 output from the first stage 531a may be transmitted to the third stage 532a. In addition, the fourth gate signal G4 output from the fourth stage 531b may be transmitted to the sixth stage 532b. The third stage 532a outputs the fifth gate signal G5 and the seventh gate signal G7 corresponding to the third gate signal G4 and the sixth stage 532b outputs the fourth gate signal G5 The sixth gate signal G6 and the eighth gate signal G8 can be output corresponding to the first to fourth gate signals G1 to G4.

Accordingly, the first stage 531a and the second stage 532a, the fourth stage 542b, and the fifth stage 531b sequentially output the first gate signal G1 to the fourth gate signal G4 The fifth stage and the sixth stage can drive the odd gate signal and the even gate signal alternately. Therefore, it is possible to drive the gate lines arranged in the 1-1 zone and the second zone or in the 1-2 zone and the second zone using the same gate drive circuit, and use a separate gate drive circuit for each zone .

The first gate signal G1 to the fourth gate signal G4 output from the first stage 531a and the second stage 542a are supplied to the first stage 542b and the fifth stage 531b, Can be synchronized with the gate signal (G1) to the fourth gate signal (G4). Therefore, even though the gate line is disconnected as in the first region 310a shown in FIG. 4, since the gate signal is driven on both sides of the gate line, the pixels connected to the gate line can express the image.

Here, the first stage 531a and the second stage 542a, the fourth stage 542b and the fifth stage 531b are arranged side by side, but the present invention is not limited thereto. In addition, the number of gate lines output in one stage and the number of stages included in the gate driver circuit are not limited thereto.

The gate driver circuit 530 connects the first stage 531a and the third stage 532a and connects the third gate signal G3 among the plurality of gate signals output from the first stage 531a to the third stage And a fifth stage 531b that connects the fifth stage 531b and the sixth stage 532b to each other and a fourth switch SW1 for transferring the fourth signal among the plurality of gate signals output from the fifth stage 531b to the fourth stage 531b, And a second switch SW2 for transferring the gate signal G4 to the sixth stage 532b. Here, since each stage can sequentially output two gate signals, the third gate signal G3 is the second gate signal outputted from the first stage 531a and the fourth gate signal G4 is outputted from the fifth stage 531a, And may be the second gate signal output from the second gate 531b. Accordingly, the second gate signal outputted from the first stage 531a and the second gate signal outputted from the fifth stage 531b may be transmitted to the third stage 532a and the sixth stage 532b, respectively. The connection between the first stage 531a and the third stage 532a, the connection between the fifth stage 531b and the sixth stage 532b via the first switch unit SW1 and the second switch unit SW2, It is possible to easily distinguish between the low power mode and the general mode.

The first switch unit SW1 may receive the third gate signal G3 output from the first stage 531a and may transfer the third gate signal G3 to the third stage 532a and the second switch unit SW2 may be connected to the fifth stage The fourth gate signal G4 output from the second stage 531b may be received and transferred to the sixth stage 532b.

The first stage 531a, the second stage 542a, the third stage 532a, the fourth stage 542b, the fifth stage 531b and the sixth stage 532b can receive clocks. The first stage 531a and the second stage 542a, the fourth stage 542b, and the fifth stage 531b can receive a start signal START, respectively.

The first stage 531a outputs the first gate signal G1 in correspondence with the start signal START and the clock and outputs the third gate signal G3 in correspondence with the first gate signal G1 and the clock have. The second stage 542a can output the second gate signal G2 in correspondence with the start signal START and the clock and can output the fourth gate signal G4 in response to the second gate signal G2 and the clock. Can be output. The third stage 532a may output the fifth gate signal G5 in correspondence with the third gate signal G3 and the clock and may output the seventh gate signal G5 in response to the fifth gate signal G5 and the clock. G7).

The fourth stage 542b and the fifth stage 531b of the second gate driver block 530b are formed in the same manner as the first stage 531a and the fifth stage 531b of the first gate driver block 530a Numbered gate signals such as the first gate signal G1 and the fourth gate signal G4 in the same manner as the first to fourth gate signals G1 to G4 to the third stage 532a Can be output. The clock input to the fifth stage 532b and the sixth stage 532b is delayed in phase with respect to the clock to output the first gate signal G1 and then the second gate signal G2, After the signal G3 is outputted, the fourth gate signal G4 may be outputted. That is, an even-numbered gate signal may be generated after one odd-numbered gate signal is generated, and an odd-numbered gate signal and an even-numbered gate signal may be generated alternately.

Here, the start signal START supplied to the first stage 531a, the second stage 532a, the fourth stage 542b, and the fifth stage 531b may be a synchronized signal, And may be supplied to the stage 531a, the second stage 532a, the fourth stage 542b, and the fifth stage 531b, respectively. However, the present invention is not limited thereto.

When the first switch SW1 and the second switch SW2 are turned off, the third gate signal G3 and the fourth gate signal G4 are respectively applied to the third stage 532a and the sixth stage 532b, The gate driver circuit 530 does not transfer the first gate signal G1 to the fourth gate signal G1 only to the first stage 531a and the second stage 542a and the fourth stage 542b and the fifth stage 532b, It is possible to output the signal G4. Accordingly, only the first area 310a of the display panel 310 can be displayed.

When the first switch unit SW1 and the second switch unit SW2 are turned on, the third gate signal G3 and the fourth gate signal G4 are respectively supplied to the third stage 532a and the sixth stage 532b, The gate driver circuit 530 can operate both the first stage 531a to the sixth stage 533b to display images in both the first area 310a and the second area 310b.

The first switch unit SW1 and the second switch unit SW2 operate in response to the enable signal Enable and the enable signal is not transmitted in the low power mode so that an image is displayed only in the first area 310a In the normal mode, the enable signal is transmitted to enable the first region 310a and the second region 310b to display images. Only the first region 310a can display an image in the low power mode by the operation of the first switch portion SW1 and the second switch portion SW2, so that the power consumption can be reduced in the normal mode.

The enable signal Enable may be output from the control unit shown in FIGS. 1 and 2. In response to the input signal, the control unit may determine whether to output the enable signal Enable.

Here, although each of the first gate driver block 530a and the second gate driver block 530b is shown as including a plurality of stages, each stage may correspond to the GIP circuit shown in Fig. 2

In the low power mode, the enable signal Enable can be transmitted in a low state. When the enable signal Enable is transmitted in a low state, the first switch unit SW1 and the second switch unit SW2 may be turned off. The start signal START and the first clock CLK1 are inputted to the first stage 531a and the third stage 532a in a state where the first switch unit SW1 and the second switch unit SW2 are turned off, .

In the normal mode, the enable signal Enable can be transferred to the high state. When the enable signal Enable is transmitted to the high state, the first switch unit SW1 and the second switch unit SW2 may be turned on. However, the first switch unit SW1 and the second switch unit SW2 are not necessarily turned on. When the start signal START and the first clock CLK1 are transmitted to the first stage 531a and the third stage 532a respectively in a state where the first switch unit SW1 and the second switch unit SW2 are turned on The first stage 531a and the third stage 532a can successively output the first gate signal G1 through the fourth gate signal G4 in sequence. Since the first switch unit SW1 and the second switch unit SW2 are turned on, the third gate signal G3 output from the first stage 531a and the third gate signal G2 output from the third stage 532a 4 gate signal G4 may be transmitted to the second stage 542a and the fourth stage 542b, respectively.

Therefore, the selection of the area in which the display panel is displayed for each of the low power mode and the general mode can be easily achieved by using the switch.

Here, although the gate driving block 430a and the second gate driving block 430b are shown as corresponding to FIG. 6A, they can be configured to correspond to FIG. 6B.

FIG. 9 is a state transition diagram showing that the display device according to the present embodiments is changed from a low power mode to a normal mode.

Referring to FIG. 9, the display device can be divided into a low power mode and a general mode.

The normal mode is an operation mode in which a video is normally displayed in a mobile terminal such as a smart phone or a tablet, or in a general TV, monitor, or the like, in a situation where the user has substantial viewing or action.

On the other hand, the low-power mode is an operation mode for reducing power consumption. For example, in a mobile terminal such as a smart phone or a tablet or a general TV or a monitor, Or an operation mode used to implement a screen in a state in which there is no action.

For example, during the low power mode period, in order to reduce power consumption, the area in which the image is displayed is a part of the entire area of the screen, and the image displayed in this part of the area may be an image in which simple information is represented by a small number of colors .

For example, in the normal mode, the enable signal enable for turning on the first switch unit SW1 and the second switch unit SW2 is transmitted to the first switch unit SW1 and the second switch unit SW2 shown in FIG. 8 The second switch unit SW2 can be turned on.

Thus, gate driving is performed in both the first-first region 311a, the first-second region 312a, and the second region 310b. Therefore, all subpixels disposed in the first-first region 311a, the first-second region 312a, and the second region 310b can be driven.

In the low power mode, the enable signal enable is not transmitted, so that the first switch unit SW1 and the second switch unit SW2 can be turned off.

Thus, gate driving is performed only in the 1-1 zone 311a and the 1-2 zone 312a, and gate driving is not performed in the second zone 310b. Therefore, only the subpixels arranged in the 1-1 region 311a and the 1-2th region 312a can be driven.

Meanwhile, as an example of the state transition method, there may be a case where, during the normal mode operation, a state in which there is no action of the user lapses for a certain period of time or a user input related to the entry into the low power mode , The control unit 140 does not output the enable signal enable so that the first switch unit SW1 and the second switch unit SW2 are turned off so that the low power mode can be executed.

In addition, when the user operates the switch that presses the screen while the screen of the display device is turned off, the controller 140 generates a start pulse and a clock, but does not generate an enable signal, thereby enabling the low power mode to be executed.

A switch operated by a user to operate a screen may be a switch added to an input device provided separately in the display device. The input device separately added to the display device may be a keyboard, a mouse, and a touch panel. When the user inputs a signal through the designated key or all of the keys of the keyboard, the display device can recognize the screen as a key operated switch. Also, when the pointer moves by the mouse or the button on the mouse is operated through the mouse, the display device can recognize the screen as a key operated switch. Further, when the touch panel is touched, the display device can recognize that the switch for operating the screen is operated.

In addition, when the signal is input once by the input device, it enters the low power mode, and when the input signal by the user's operation is inputted again within the predetermined time, it can enter the normal mode.

After the low power mode is executed, when the input signal indicating the entry of the normal mode is delivered by the user's operation, the controller 140 outputs the enable signal and the first switch unit SW1 and the second switch unit SW2 It can be turned on.

When the first switch portion SW1 and the second switch portion SW2 are in the turned off state, the first-first region 311a, the first-second region 312a, and the second region 310b Only the first-first area 311a and the first-second area 312a can display an image.

However, when the first switch unit SW1 and the second switch unit SW2 are turned on, the first-first area 311a, the first-second area 312a, and the second area 310b ) All can display video.

10 is a conceptual diagram showing that the display device according to the present embodiments is displayed in a normal mode and a low power mode. 11 is an exemplary diagram of an image displayed in the first-first region 311a and the first-second region 312a in the low-power mode in the display device according to the present embodiments.

Referring to FIG. 10, (a) shows that the display device operates in the normal mode, and the first-first region 311a, the first-second region 312a, and the second region 310b all display an image can do. That is, gate driving is performed in the first-first region 311a, the first-second region 312a, and the second region 310b.

(B) and (c) illustrate embodiments in which the display device operates in a low power mode, and the 1-1 zone 311a and the 1-2 zone 312a display images, but the second zone 310b do not display an image. That is, the gate driving is performed in the first-first region 311a and the first-second region 312a, and the gate driving is not performed in the second region 310b.

However, in (b), information of a single color or various colors is displayed on a general background (for example, a background having a non-black color), whereas in (c) Information is displayed. Therefore, in the case of (c) as compared with (b), the area of the region where the light is emitted is reduced, so that the power consumption can be further reduced.

For example, in the case of FIGS. 10 (b) and 10 (c), a user's actual action (such as a lock screen, a standby screen, a screen saver operation screen, etc.) in a mobile terminal such as a smart phone, a tablet, can be used to implement a screen with no action.

11, the image displayed in the first-first area 311a and the first-second area 312a includes, for example, information such as a communication state, a current time, an alarm, : Represented by numbers, letters, symbols, images, and the like) can be divided and displayed in the first-first area 311a and the first-second area 312a. However, the image or the information displayed in the 1-1 zone 311a and the 1-2 zone 312a is not limited thereto.

In addition, the images displayed in the first-first area 311a and the first-second area 312a may be monochromatic images or images of about two to four colors or images with little gray level change, The power may not be large. However, the present invention is not limited thereto.

In addition, the first-first area 311a and the first-second area 312a can display images in whole or in part. In the case of FIG. 10 (c), the background may be displayed in black, numbers and symbols may be displayed in bright gradation, and black and bright colors may be reversed.

According to the embodiments described above, a gate driver having a structure and a driving mechanism capable of realizing a small size of a non-display region and a display using the gate driver are provided.

Further, according to the embodiments, it is possible to provide a gate driver circuit having a gate driving structure and a mechanism capable of reducing power consumption, and a display device using the same.

In addition, according to the embodiments, a gate driver circuit and a display device which enable image display around a mounting space of an application part such as a camera lens and a sensor can be provided.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device
101: pixel
110: Display panel
120: Data driver circuit
130a: first gate driver circuit
130b: second gate driver circuit
140:
G1, G2, ... , Gn-1, Gn: gate line
D1, ... , Dm: data line

Claims (18)

A display panel in which a plurality of gate lines intersect with a plurality of data lines and are divided into a first 1-1 region, a 1-2 region and a second region;
A first gate circuit disposed on one side of the display panel and sequentially applying a gate signal to gate lines arranged in the 1-1 zone;
A second gate circuit which is disposed on one side of the display panel and sequentially applies a gate signal to odd-numbered gate lines among the gate lines arranged in the second area;
A third gate circuit disposed on the other side of the display panel and sequentially applying a gate signal to gate lines arranged in the first-second region;
A fourth gate circuit disposed on the other side of the display panel and sequentially applying a gate signal to even-numbered gate lines among the gate lines arranged in the second region; And
And a data driver circuit for applying a data signal to the plurality of data lines.
The method according to claim 1,
The first gate circuit
and a second stage for sequentially outputting k gate signals and alternately outputting k gate signals output from the first stage, and a second stage for sequentially outputting k gate signals and alternately outputting k gate signals output from the first stage, Including,
Wherein the second gate circuit includes a third stage for sequentially outputting k gate signals when at least one of the k gate signals output from the first stage is inputted.
3. The method of claim 2,
The third gate circuit may include a fourth stage for sequentially outputting k gate signals, and a fifth stage for sequentially outputting k gate signals and alternately outputting k gate signals output from the third stage Including,
And the fourth gate circuit includes a sixth stage for sequentially outputting k gate signals when at least one of the k gate signals output from the fifth stage is inputted.
The method according to claim 1,
A first switch unit electrically connected between the first stage and the third stage and transmitting at least one of k gate signals output from the first stage to the third stage; And
And a second switch part electrically connected between the fifth stage and the sixth stage and transmitting at least one of the k gate signals output from the fifth stage to the sixth stage.
The method according to claim 1,
Wherein each of the first stage, the second stage, the fourth stage, and the fifth stage receives a start signal.
The method of claim 3,
The first stage outputs k gate signals to k odd gate lines located in the 1-1 region,
The second stage outputs k gate signals to k even-numbered gate lines located in the 1-1 region,
The fourth stage outputs k gate signals to k odd-numbered gate lines located in the 1-2 zone,
The fifth stage outputs k gate signals to k even-numbered gate lines located in the 1-2 zone,
The third stage outputs k gate signals to k odd gate lines located in the second region,
And the sixth stage outputs k gate signals to k even-numbered gate lines located in the second region.
Display panel;
a first GIP (Gate In Panel) block for sequentially outputting gate signals of k (k is a natural number of 2 or more);
a second GIP block sequentially outputting k gate signals and crossing a plurality of gate signals output from the first GIP block;
A third IP block for sequentially outputting k gate signals when at least one of the k gate signals output from the first GIP block is input;
a fourth GIP block sequentially outputting k gate signals;
a fifth GIP block sequentially outputting k gate signals and crossing the plurality of gate signals output from the fourth GIP block; And
And a sixth GIP block for sequentially outputting a plurality of k gate signals and crossing the k gate signals output from the third IP block when at least one of the k gate signals output from the fifth GIP block is input / RTI >
8. The method of claim 7,
A first switch for connecting the first GIP block and the third GIP block and transmitting the at least one gate signal output from the first GIP block to the third GIP block; And
And a second switch for connecting the fifth GIP block to the sixth GIP block and for transmitting the at least one gate signal output from the fifth GIP block to the sixth GIP block.
8. The method of claim 7,
Wherein the first GIP block, the second GIP block, the fourth GIP block, and the fifth GIP block are each operated to receive a start signal.
8. The method of claim 7,
The first GIP (Gate In Panel) block outputs k gate signals to k odd-numbered gate lines located in the 1-1 region,
The second GIP block outputs k gate signals to k even-numbered gate lines located in the 1-1 region,
The fourth GIP block outputs k gate signals to k odd-numbered gate lines located in the 1-2 region,
The fifth GIP block outputs k gate signals to k even-numbered gate lines located in the 1-2 zone,
The third 3GPP block outputs k gate signals to k odd-numbered gate lines located in the second region,
And the sixth GIP block outputs k gate signals to k even-numbered gate lines located in the second region.
11. The method of claim 10,
Wherein the first direction length of the second region,
A first direction length of the first 1-1 region and a first direction length of the first 1-2 region,
A length in the second direction of the 1-1 zone and a length in the second direction of the 1-2 zone correspond to each other,
And at least one application part is present between the 1-1 zone and the 1-2 zone.
9. The method of claim 8,
When the low power mode signal is generated, the first switch and the second switch are turned off, and when the low power mode signal is not generated, the first switch and the second switch are turned on.
9. The method of claim 8,
When the low power mode signal is generated, the first GIP block, the second GIP block, the fourth GIP block, and the fifth GIP block output k gate signals, and the third and sixth GIP blocks output no gate signal ,
If the low power mode signal is not generated, the first GIP block, the second GIP block, the fourth GIP block, and the fifth GIP block output k gate signals, and the third and sixth GIP blocks output k gate signals. And outputs a signal.
11. The method of claim 10,
And at least one hole is formed between the first-first region and the first-second region.
a second stage for sequentially outputting k gate signals and alternately outputting k gate signals output from the first stage; a first stage for sequentially outputting gate signals of k (k is a natural number of 2 or more) And a third stage for sequentially outputting k gate signals when at least one of the k gate signals output from the first stage is input; And
a fifth stage for sequentially outputting k gate signals and alternately outputting k gate signals output from the fourth stage; and a fourth stage for sequentially outputting k gate signals, And a sixth stage for sequentially outputting k gate signals when at least one of the k gate signals is input to the gate driver circuit.
16. The method of claim 15,
A first switch unit electrically connected between the first stage and the third stage and transmitting at least one of the k gate signals output from the first stage to the third stage; And
And a second switch part electrically connected between the fifth stage and the sixth stage and transmitting at least one of the k gate signals output from the fifth stage to the sixth stage.
16. The method of claim 15,
Wherein each of the first stage, the second stage, the fourth stage, and the fifth stage receives a start signal.
16. The method of claim 15,
The first stage outputs k gate signals to k odd-numbered gate lines located in the 1-1 region,
The second stage outputs k gate signals to k even-numbered gate lines located in the 1-1 region,
The fourth stage outputs k gate signals to k odd-numbered gate lines located in the 1-2 region,
The fifth stage outputs k gate signals to k even-numbered gate lines located in the 1-2 zone,
The third stage outputs k gate signals to k odd-numbered gate lines located in the second region,
And the sixth stage outputs k gate signals to k even-numbered gate lines located in the second region.

Images