KR102392953B1 - Gip circuit and display device using the same - Google Patents

Abstract

In the present exemplary embodiments, a plurality of gate lines and a plurality of data lines intersect, and the display panel is divided into a 1-1 region, a 1-2 region and a second region, and is disposed on one side of the display panel and is disposed in the 1-1 region. A first gate circuit for sequentially applying a gate signal to the arranged gate lines, a first gate circuit for sequentially applying a gate signal to odd-numbered gate lines among gate lines arranged on one side of the display panel and arranged in a second region A second gate circuit, a third gate circuit disposed on the other side of the display panel and sequentially applying a gate signal to the gate lines disposed in the first-2 regions, disposed on the other side of the display panel and disposed in the second region An object of the present invention is to provide a display device comprising: a fourth gate circuit for sequentially applying a gate signal to even-numbered gate lines among gate lines; and a data driver circuit for applying a data signal to a plurality of data lines.

Description

Gate driver circuit and display device using same {GIP CIRCUIT AND DISPLAY DEVICE USING THE SAME}

The present embodiments relate to a gate driver circuit and a display device using the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, such as Liquid Crystal Display Device (LCD), Organic Light Emitting Display Device (OLED), etc. Several types of flat panel display devices have appeared.

Recently, a flat panel display device has been widely used in mobile devices. Mobile devices are being developed so that the entire front surface of which a display panel is employed can display an image for aesthetics or convenience of use.

However, in the mobile device, the lens of the camera is installed on the front side, and the area occupied by the lens cannot display an image. In addition, the gate line is cut off by the area occupied by the lens, and thus there is a limitation in increasing the area of the display area in which an image can be displayed on the display panel.

In general, there is a problem in that power consumption increases when the size of the display panel is increased. However, since the mobile device is supplied with power using a battery, the usage time may be determined according to the capacity of the battery. In addition, mobile devices are being developed to be thin and light for convenient use.

Accordingly, there is a problem in that the use time is shortened when the size of the display panel is increased because the capacity of the battery of the mobile device cannot be increased.

It is an object of the present embodiments to provide a gate driver circuit capable of realizing a small non-display area in a display device and a display device using the same.

It is an object of the present embodiments to provide a gate driver circuit capable of increasing use time and a display device using the same.

Another object of the present embodiments is to provide a gate driver circuit and a display device that enable image display around a mounting space of application parts such as a camera lens and a sensor.

In one aspect, the present exemplary embodiments provide a display panel in which a plurality of gate lines and a plurality of data lines intersect and are divided into a 1-1 region, a 1-2 region and a second region, and disposed at one side of the display panel, the first A first gate circuit for sequentially applying a gate signal to the gate lines arranged in the -1 region, a first gate circuit arranged at one side of the display panel and sequentially gated to odd-numbered gate lines among the gate lines arranged in the second region A second gate circuit for applying a signal, a third gate circuit disposed on the other side of the display panel and sequentially applying a gate signal to the gate lines disposed in regions 1-2, disposed on the other side of the display panel, the second gate circuit Provided is a display device comprising: a fourth gate circuit for sequentially applying a gate signal to even-numbered gate lines among gate lines arranged in two regions; and a data driver circuit for applying a data signal to a plurality of data lines will do

In another aspect, the present embodiments provide a display panel, a first gate in panel (GIP) block sequentially outputting k (k is a natural number equal to or greater than 2) gate signals, and sequentially outputting k gate signals, wherein the first GIP When receiving at least one of the k gate signals output from the second GIP block and the first GIP block that intersect the plurality of gate signals output from the block, the third GIP block sequentially outputs k gate signals, k gate signals a fourth GIP block that sequentially outputs k gate signals outputting synchronously with the plurality of gate signals output from the first GIP block, and sequentially outputs k gate signals, but intersecting the plurality of gate signals output from the fourth GIP block When receiving at least one of the 5GIP block and the k gate signals output from the 5th GIP block, the k gate signals are sequentially outputted to intersect the k gate signals output from the 3rd GIP block. It is to provide a display device including a block.

In another aspect, the present embodiments have a first stage for sequentially outputting k (k is a natural number greater than or equal to 2) gate signals, and sequentially outputting k gate signals, but k gate signals output from the first stage A first gate driver block including a second stage alternately outputting with and a third stage sequentially outputting k gate signals upon receiving one of k gate signals output from the first stage, and k A fourth stage for sequentially outputting gate signals, a fifth stage for sequentially outputting k gate signals but alternately outputting k gate signals output from the fourth stage, and k gates output from the fifth stage To provide a gate driver circuit including a second gate driver block including a sixth stage that sequentially outputs k gate signals when one of the signals is received.

According to the present embodiments, a gate driver capable of realizing a small non-display area and a display device using the same are provided.

In addition, according to the present embodiments, a gate driver circuit capable of reducing power consumption and a display device using the same can be provided.

In addition, according to the present embodiments, it is possible to provide a gate driver circuit and a display device that enable image display around a mounting space of application parts such as a camera lens and a sensor.

1 is a structural diagram illustrating an exemplary embodiment of a display device according to the present exemplary embodiment.
2 is a structural diagram illustrating an exemplary embodiment of a display device according to the present exemplary embodiment.
3 is a plan view illustrating an exemplary embodiment of a front part of a display device according to the present exemplary embodiment.
4 is a plan view illustrating an exemplary embodiment of a front part of a display device according to the present exemplary embodiment.
5 is a plan view illustrating an exemplary embodiment of a gate line disposed on a display device.
6 is a conceptual diagram in which regions of a front part of a display device are divided.
7 is a structural diagram illustrating an example of a gate driver circuit employed in the display device according to the present exemplary embodiment.
8 is a structural diagram illustrating an example of a gate driver circuit employed in a display device according to the present exemplary embodiment.
9 is a state transition diagram illustrating a change between a low power mode and a normal mode in the display device according to the present embodiments.
10 is a conceptual diagram illustrating display in a normal mode and a low power mode in the display device according to the present embodiments.
11 is a conceptual diagram illustrating an example of an image displayed in a low power mode in the display device according to the present exemplary embodiment.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It should be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a structural diagram illustrating an exemplary embodiment of a display device according to the present exemplary embodiment.

Referring to FIG. 1 , the display device 100 may include a display panel 110 , a data driver circuit 120 , a first gate driver circuit 130a , a second gate driver circuit 130b , and a controller 140 . can

In the display panel 110 , a plurality of pixels 101 may be formed in a region where the plurality of gate lines G1, G2, ..., Gn-1, Gn and the plurality of data lines D1, ..., Dm intersect. In addition, each pixel 101 may include a thin film transistor (not shown) that selectively transmits a data signal. In addition, each pixel 101 may be a red pixel (R), a green pixel (G), and a blue pixel (G). The red pixel R, the green pixel G, and the blue pixel G may transmit light in response to the data signal to display red, green, and blue colors. In addition, the display panel 110 may be a liquid crystal display panel using liquid crystal or an organic light emitting diode panel using an organic light emitting diode. However, the present invention is not limited thereto. Also, the wirings disposed on the display panel 110 are not limited to the plurality of gate lines G1, G2, ..., Gn-1, Gn and the plurality of data lines D1, ..., Dm.

The data driver circuit 130 may be connected to the plurality of data lines D1, ..., Dm to supply data signals to the data lines D1, ..., Dm. The data driver circuit 130 may include a plurality of drive ICs (not shown), and the number of drive ICs may be determined according to the resolution and/or size of the display panel 110 . Also, in the data driver circuit 130 , one output terminal may be connected to the plurality of data lines D1, ..., Dm through a mux. The data driver circuit 130 may receive an image signal, generate a data signal, and transmit a data voltage corresponding to the data signal to the data lines D1, ..., Dm.

The first gate driver circuit 130a may be connected to the odd-numbered gate lines G1, ..., Gn-1 among the plurality of gate lines G1, G2, ..., Gn-1, Gn to sequentially supply gate signals. there is. The second gate driver circuit 130b may be connected to the even-numbered gate lines G2, ..., Gn among the plurality of gate lines G1, G2, ..., Gn-1, Gn to sequentially supply gate signals. The first gate driver circuit 130a and the second gate driver circuit 130b may each include a plurality of stages, and may sequentially output a gate signal at each stage.

The controller 140 may transmit control signals to the data driver circuit 120 , the first gate driver circuit 130a , and the second gate driver circuit 130b , respectively. Also, the controller 140 may supply an image signal to the data driver circuit 120 .

Also, the controller 140 may receive an input signal from the external device 150 . The external device may be a keyboard, a mouse, or a touch panel. However, the present invention is not limited thereto. The controller 140 may cause the display panel 110 to be driven in a normal mode or a low power mode in response to an input signal.

2 is a structural diagram illustrating an exemplary embodiment of a display device according to the present exemplary embodiment.

Referring to FIG. 2 , the display device 200 may include a display panel 210 , a plurality of driver ICs 220 and 230 , and a controller 240 .

The display panel 210 includes a display area 211 that displays an image in the center and non-display areas 212a and 212b that are disposed on both sides of the display area 211 and supply a signal to the display area 211 . can The non-display areas 212a and 212b may include a first non-display area 212a and a second non-display area 212b in which a plurality of GIP blocks GIP are respectively disposed. In the display area 211 , as shown in FIG. 1 , a plurality of data lines and a plurality of gate lines may be disposed to cross each other, and pixels P may be respectively disposed at the intersections. A plurality of GIP blocks GIP connected to an odd-numbered gate line among the plurality of gate lines are disposed in the first non-display area 212a, and an even-numbered gate line and an even-numbered gate line among the plurality of gate lines are disposed in the second display area 212b. A plurality of connected GIP blocks (GIPs) may be disposed. However, the connection between the GIP block and the gate line is not limited thereto.

Since the gate signal may be sequentially supplied by the GIP block GIP, the widths of the non-display areas 212a and 212b of the display panel 210 are narrowed to increase the area of the display area 211 in a mobile device having the same size. can be greatly implemented. Also, the GIP block GIP may correspond to the stage illustrated in FIG. 1 .

The plurality of driver ICs 220 and 230 may include a driver IC 220 connected to a data line to drive a data signal, and a driver IC 230 connected to the GIP block GIP to drive the GIP block GIP. . The number of driver ICs 220 driving the data signal may correspond to the resolution and/or size of the display area 211 . When the GIP blocks disposed in the first non-display area 212a and the second non-display area 212b are driven by the driver IC for driving the gate signal, the plurality of GIP blocks are sequentially driven by the gate signal to the gate line. can make it happen

The controller 240 may output a control signal for controlling the plurality of driver ICs 220 and 230 . Also, the controller 240 may supply the image signal to the driver IC 220 for driving the data line among the plurality of driver ICs 220 and 230 .

Also, the controller 240 may receive an input signal from the external device 150 . The external device 250 may be a keyboard, a mouse, or a touch panel. However, the present invention is not limited thereto. The controller 240 may cause the display panel 210 to be driven in a normal mode or a low power mode in response to an input signal.

3 is a plan view illustrating an exemplary embodiment of a front part of a display device according to the present exemplary embodiment.

Referring to FIG. 3 , a display panel 310 may be disposed on the front portion of the display device 300 . At least one hole 311 is disposed in one area of the front part of the display device, the display panel 310 is disposed, and at least one application part such as a lens of a camera and a sensor is formed on the top of the display panel 310 . can be The hole 311 disposed on the upper portion of the display panel 310 is not limited thereto. In addition, the display device 300 may include a bezel 301 disposed on the edge of the display panel 300 .

The display panel 310 may be divided into a first area 310a and a second area 310b. The first region 310a is disposed on the second region 310b and may be formed to be thinner than the second region 310b. Also, the first area 310a may be an area displaying an image in the low power mode, and the second area 310b may be an area displaying an image in the normal mode. The image displayed in the first area 310a may display a simple icon or the like. Since the color or shape of the icons displayed in the first region 310a does not change for a long period of time, the flowing current can be kept constant, so that the power consumption is not significantly generated. In addition, the image displayed in the second region 310b may display a moving image or a still image including various colors, so that a large change in current flowing may occur. Accordingly, the first area 310a may be referred to as a low power mode area and the second area 310b may be referred to as a normal display area.

4 is a plan view illustrating an example of a front part of a display device according to the present exemplary embodiment, and FIG. 5 is a plan view illustrating an example of a gate line disposed on the display device. 6 is a conceptual diagram in which regions of the front part of the display device are divided.

Referring to FIG. 4 , the front portion of the display device 300 may include a display panel 310 . The display panel 310 may be divided into a first area 310a and a second area 310b. The first area 310a may be an area displaying an image in the low power mode, and the second area 310b may be an area displaying an image in the normal mode. However, the present invention is not limited thereto.

Also, a hole 311 through which application parts such as a camera lens and a sensor may protrude may be formed in the first region 310a. However, the reason why the hole 311 is formed is not limited thereto.

Alternatively, a portion to which application parts such as a camera lens and a sensor can be attached may exist in the region 310a.

Also, the first area 310a may be referred to as a low power mode area and the second area 310b may be referred to as a normal display mode area. The low power mode area may be an area in which an image is displayed in standby mode, and the normal display mode area may be an area in which an image is displayed in normal use. In addition, the plurality of gate lines disposed in the first region 310a may be referred to as a first gate line, and the plurality of gate lines disposed in the second region 310b may be referred to as second gate lines.

Since the first region 310a overlaps with the region where the hole 311 where the camera lens is formed is formed, the position of the first region 310a is the portion in which the display panel is not formed in the mobile device illustrated in FIG. 3 . can be formed on the , and thus the height h2 of the second region becomes longer than the height h1 of the second region shown in FIG. there is.

When the area in which the hole 311 is formed is enlarged, as shown in FIG. 5 , the first gate lines disposed in the first area 310a may be cut off. For this reason, among the first gate lines, the first gate line is divided into G11 and G12, the second gate line is divided into G21 and G22, the third gate line is G31 and G32, and the fourth gate line is G41 and G42, so that there may be two lines, respectively. . On the other hand, the second gate lines disposed in the second region 310b are not disconnected, so that the fifth gate line G5 and the sixth gate line G6 may be formed as one line.

Also, a region formed on the left side of the hole 311 with respect to the hole 311 among the first region 310a is referred to as a 1-1 region 311a, and a region formed on the right side of the hole is referred to as a 1-th region. The second region 312a may also be referred to as the second region 312a. The first direction length L3 of the second region 310b is a first direction length L1 of the 1-1 region 311a and a first direction length L2 of the 1-2 th region 312a. greater than the sum of , the second direction length of the 1-1 region 311a and the second direction length of the 1-2 th region 312a may correspond to each other. Here, the second direction may be perpendicular to the first direction and may be a direction corresponding to the height of the display device. Also, an application component may exist between the 1-1 region 311a and the 1-2 th region 312a. The application part may be a camera lens or a camera. However, the present invention is not limited thereto.

As described above, the plurality of gate lines are arranged, and the first gate lines are used to drive the first to fourth gate lines. A gate driving circuit is required. The gate driving circuit may be a GIP block (GIP) illustrated in FIG. 2 . To drive the odd gate line and the even gate line like driving the second gate line, two driving circuits for driving G11, G21, G31, G41 are required in the first region, and G12, G22, G32, G42 Two driving circuits may be needed to drive the That is, in order to drive the four gate lines in the first region 310a, four driving circuits may be required. However, the present invention is not limited thereto.

Of the four driving circuits, two driving circuits are disposed on the left and right sides of the display panel 310 and are disposed in a non-display area covered by the bezel 301 , and the remaining two driving circuits are provided in a hole 311 in which a camera lens is formed. ), there is a problem in that the area of the non-light-emitting region around the hole 311 increases due to the driving circuit.

In addition, a first gate circuit disposed on one side of the display panel 310 and sequentially applying a gate signal to the gate lines disposed in the 1-1 region 311a of the first region 310a, the display panel ( A second gate circuit disposed on one side of the 310 and sequentially applying a gate signal to odd-numbered gate lines among the gate lines disposed in the second region 310b, the second gate circuit disposed on the other side of the display panel 310 and disposed on the second side of the display panel 310 A third gate circuit for sequentially applying a gate signal to the gate lines arranged in the first-2 region 312a of the first region 310a, the second region 310a and the other side of the display panel 310 It may be divided into a fourth gate circuit that sequentially applies a gate signal to even-numbered gate lines among the gate lines disposed in the .

As shown in FIG. 6 , a 1-1 region 311a , a 1-2 th region 312a and a second region 310b may be disposed on the front portion of the display device 300 . As shown in (a) of FIG. 6 , a 1-1 region 311a and a 1-2 th region 312a are disposed on the upper portion of the display panel 310 , and a second region 310b is disposed below the display panel 310 . can be placed. In this case, the first gate circuit may be disposed at the left end of the 1-1 region 311a of the display panel 310 , and the second gate circuit may be disposed below the first gate circuit and of the display panel 310 . It may be disposed at the left end of the second region 310b. The first gate circuit and the second gate circuit are disposed in the 1-1 region 311a and the second region 310b, respectively, and may be disposed adjacent to each other. In addition, the third gate circuit may be disposed at the right end of the first-2 region 312a of the display panel 310 , and the fourth gate circuit may be disposed below the third gate circuit and may be disposed on the second side of the display panel 310 . It may be disposed at the right end of the second region 310b. The third gate circuit and the fourth gate circuit are respectively disposed in the first-2 region 312a and the second region 310b, but may be disposed adjacent to each other.

Also, as shown in (b), the 1-1 region 311a and the 1-2 th region 312a are disposed below the display device 300 and the second region 310b is disposed above the display device 300 . can be In this case, the first gate circuit may be disposed at the left end of the 1-1 region 311a of the display panel 310 , and the second gate circuit may be disposed above the first gate circuit, and It may be disposed at the left end of the second region 310b. The first gate circuit and the second gate circuit are disposed in the 1-1 region 311a and the second region 310b, respectively, and may be disposed adjacent to each other. In addition, the third gate circuit may be disposed at the right end of the first-2 region 312a of the display panel 310 , and the fourth gate circuit may be disposed on the third gate circuit and disposed on the second side of the display panel 310 . It may be disposed at the right end of the second region 310b. The third gate circuit and the fourth gate circuit are respectively disposed in the first-2 region 312a and the second region 310b, but may be disposed adjacent to each other.

Also, the second region 310b may be disposed adjacent to both the 1-1 region 311a and the 1-2 th region 312a.

As shown in (a) of FIG. 6 , when the 1-1 region 311a , the 1-2 th region 312a and the second region 310b are arranged, data is written from the top to the bottom of the display device. can be driven in the forward method F, and the 1-1 region 311a, the 1-2 region 312a, and the second region 310b are arranged as shown in FIG. In this case, the data may be driven in the reverse method (R) in which data is written from the bottom to the top of the display device.

7 is a structural diagram illustrating an example of a gate driver circuit employed in the display device according to the present exemplary embodiment.

Referring to FIG. 7 , the gate driver circuit 430 includes a first gate driver block 430a that can be disposed on the left side of the display panel 310 and a second gate driver block 430b that can be disposed on the right side of the display panel. ) may be included. The first gate driver block 430a may be disposed in the first non-display area 212a on the left side of the display panel 211 shown in FIG. 2 , and the second gate driver block 430b is the display panel 211 . It may be disposed in the right second non-display area 212b. However, the present invention is not limited thereto. The first gate driver block 430a outputs odd-numbered gate signals G1, G3, G5, G7, G9, and G11 driven to the odd-numbered gate lines, and the second gate driver block 430b is driven to the even-numbered gate lines. The driven even-numbered gate signals G2, G4, G6, G8, G10, and G12 may be output.

The first gate driver block 430a includes a first stage 431a sequentially outputting a first gate signal G1 and a third gate signal G3, a fifth gate signal G5, and a seventh gate signal G7. ) may include a second stage 432a for outputting, a third stage 433a for outputting a ninth gate signal G9 and an eleventh gate signal G11.

The second gate driver block 430b has a fourth stage 431b sequentially outputting a second gate signal G2 and a fourth gate signal G4, a sixth gate signal G6, and an eighth gate signal G8. ) may include a fifth stage 432b sequentially outputting, a sixth stage 433b sequentially outputting a tenth gate signal G10 and a twelfth gate signal G12.

However, the number of gate lines output from one stage and the number of stages included in the gate driver circuit are not limited thereto.

Clocks may be received from the first stage 431a to the third stage 433a and the fourth stage 431b to the sixth stage 433b, respectively. Here, the clock input to the first stage 431a to the third stage 433a and the clock input to the fourth stage 431b to the sixth stage 433b may have different phases. In addition, the first stage 431a and the fourth stage 431b may receive a start signal START, respectively. The first stage 431a outputs the first gate signal G1 in response to the start signal START and the clock, and outputs the third gate signal G3 in response to the first gate signal G1 and the first clock. can do. In addition, the second stage 42a may output the fifth gate signal G5 in response to the third gate signal G3 and the clock, and the seventh gate signal G5 in response to the fifth gate signal G5 and the clock. G7) can be output. In addition, the third stage 433a may output the ninth gate signal G9 in response to the seventh gate signal G7 and the clock, and the eleventh gate signal G9 in response to the ninth gate signal G9 and the clock. G11) can be output.

In addition, the fourth stage (431b) to the sixth stage (433b) is the first stage (431a) to the third stage (433b) in the same manner as the second gate signal (G2), the fourth gate signal (G4), etc. Even-numbered gate signals may be sequentially output. However, the clock input to the fourth stage 431b to the sixth stage 433b is delayed in phase from the clock input to the first stage 431a to the third stage 433b, so that the first gate signal G1 After is output, the second gate signal G2 may be output, and after the third gate signal G3 is output, the fourth gate signal G4 may be output. That is, after one odd-numbered gate signal is generated, one even-numbered gate signal may be generated, so that the odd-numbered gate signal and the even-numbered gate signal may be generated alternately. However, the present invention is not limited thereto.

Here, the start signal START supplied to the first stage 431a and the fourth stage 431b may be a synchronized signal, so that the first stage 431a and the fourth stage 431b are respectively supplied through different wires. can be However, the present invention is not limited thereto.

In addition, in the gate driver circuit 430 , the first gate driver block 430a and the second gate driver block 430b have a first switch unit SW1 connecting the first stage 431a and the second stage 432a, respectively. ) and may include a second switch unit SW2 connecting the fourth stage 431b and the fifth stage 431b. The first stage 431a and the fourth stage 431b are disposed in the first area 310a of the display panel 310 shown in FIG. 3 or 4 , and the second stage 432a and the third stage 433a ), the fifth stage 432b and the sixth stage 433b may be disposed in the second area 310b.

The third gate signal G3 output from the first stage 431a may be supplied to the third stage 432a through the first switch unit SW1. Also, the fourth gate signal G4 output from the fourth stage 431b may be supplied to the fifth stage 432b through the second switch unit SW2.

Here, the first stage 431a to the sixth stage 433b are disclosed as sequentially outputting two gate signals, respectively, so that the third gate signal G3 output from the first stage 431a is the first The second gate signal output from the stage 431a and the fourth gate signal G4 output from the fourth stage 431b may correspond to the second gate signal output from the fourth stage 431b. However, the present invention is not limited thereto.

And, when the first switch unit SW1 and the second switch unit SW2 are turned off, the third gate signal G3 and the fourth gate signal G4 are respectively transmitted to the second stage 432a and the fifth stage ( 432b), the gate driver circuit 430 can output the first gate signal G1 to the fourth gate signal G4 only from the first stage 431a and the fourth stage 431b. Accordingly, the gate signal is transmitted only to the first region 310a of the display panel 310, so that only the first region 310a can display an image.

And, when the first switch unit SW1 and the second switch unit SW2 are turned on, the third gate signal G3 and the fourth gate signal G4 are transmitted to the second stage 432a and the fifth stage 432b, respectively. is transmitted to the gate driver circuit 430, the first stage 431a to the sixth stage 433b are all operated, and the gate signal is transmitted to the first region 310a and the second region 310b to the first region ( Both 310a) and the second region 310b may display an image.

The first switch unit SSW1 and the second switch unit SW2 may each operate in response to the enable signal Enable, and in the low power mode, the enable signal Enable is not transmitted, so the first switch unit SW1 ) and the second switch unit SW2 are turned off to display an image only in the first area 310a, and in the normal mode, the enable signal Enable is transmitted to the first area 310a and the second area 310b ) can all be enabled to display images. Accordingly, the display device can reduce power consumption in the low power mode compared to the normal mode. The enable signal Enable may be output from the control unit illustrated in FIGS. 1 and 2 , and the control unit may determine whether to output the enable signal Enable in response to the input signal.

Here, the first gate driving block 430a and the second gate driving block 430b are illustrated as including a plurality of stages, respectively, but each stage may correspond to the GIP circuit illustrated in FIG. 2 . 7 is a structural diagram illustrating an example of a gate driver circuit employed in the display device according to the present exemplary embodiment.

Referring to FIG. 7 , the gate driver circuit 530 may include a first gate driver block 530a disposed on the left side of the display panel and a second gate driver block 530b disposed on the right side of the display panel. In addition, the first gate driver block 530a is disposed on one side of the display panel, and the first gate circuit and the second gate circuit are respectively disposed in the 1-1 region 311a and the second region 310b of FIG. 4 . The second gate driver block 530b is disposed on the other side of the display panel, and the first gate circuit and the second gate are respectively disposed in the 1-2 first region 312a and the second region 310b of FIG. 4 . It may be a circuit.

The first gate driver block 530a sequentially outputs a first stage 531a for sequentially outputting two plurality of gate signals G1 and G3, and sequentially outputting two plurality of gate signals G2 and G4, When the second stage 542a that crosses the plurality of gate signals output from the first stage 531a, and the second gate signal G3 output from the first stage 531a are input, the two gates A third stage 532a for sequentially outputting signals may be included.

The second gate driver block 530b sequentially outputs two plurality of gate signals G1 and G3, and a fourth stage 542b, which is synchronized with the two gate signals output from the first stage 531a, 2 A fifth stage 531b that sequentially outputs a plurality of gate signals G2 and G4 and crosses a plurality of gate signals output from the fourth stage 542b, and a fifth stage 531b that is output from Upon receiving the second gate signal G4, two gate signals G6 and G8 are sequentially output, and crosses the two gate signals G5 and G7 output from the third stage 532a. It may include a sixth stage (532b) to make it.

The first stage 531a sequentially outputs the first gate signal G1 and the third gate signal G3, and the second stage 542a outputs the second gate signal G2 and the fourth gate signal G4. It can be printed sequentially. Then, the fourth stage 542b sequentially outputs the first gate signal G1 and the third gate signal G3, and the fifth stage 531b has the second gate signal G2 and the fourth gate signal G4. ) can be output sequentially. Accordingly, the first stage 531a and the second stage 542a sequentially output the first gate signal G1 to the fourth gate signal G4, and the fourth stage 542b and the fifth stage 531b are The first gate signal G1 to the fourth gate signal G4 may be sequentially output. The first stage 531a, the second stage 542a, the fourth stage 542b, and the fifth stage 531b operate in response to the start signal START and the clocks, so that the first gate signal G1 to the first gate signal G1 The four gate signals G4 may be sequentially output.

In addition, the third gate signal G3 output from the first stage 531a may be transmitted to the third stage 532a. Also, the fourth gate signal G4 output from the fourth stage 531b may be transferred to the sixth stage 532b. And, the third stage 532a outputs the fifth gate signal G5 and the seventh gate signal G7 in response to the third gate signal G4, and the sixth stage 532b has the fourth gate signal (G4). In response to G4), the sixth gate signal G6 and the eighth gate signal G8 may be output.

Accordingly, the first stage 531a and the second stage 532a and the fourth stage 542b and the fifth stage 531b sequentially output the first gate signal G1 to the fourth gate signal G4 and The fifth stage and the sixth stage may alternately drive the odd-numbered gate signal and the even-numbered gate signal. Accordingly, the gate lines disposed in the 1-1 region and the second region or in the 1-2 region and the second region can be driven using the same gate driving circuit, and a separate gate driving circuit is used for each region. you can avoid doing it.

The first gate signal G1 to the fourth gate signal G4 output from the first stage 531a and the second stage 542a are the first gate signals G1 to the fourth gate signal G4 output from the fourth stage 542b and the fifth stage 531b. It may be synchronized with the gate signal G1 to the fourth gate signal G4. Accordingly, even when the gate line is disconnected as in the first region 310a illustrated in FIG. 4 , since gate signals are driven from both sides of the gate line, pixels connected to the gate line can display an image.

Here, the first stage (531a) and the second stage (542a), the fourth stage (542b) and the fifth stage (531b) are arranged side by side, but is not limited thereto. Also, the number of gate lines output from one stage and the number of stages included in the gate driver circuit are not limited thereto.

In addition, the gate driver circuit 530 connects the first stage 531a and the third stage 532a, and receives the third gate signal G3 from among the plurality of gate signals output from the first stage 531a. The first switch unit SW1 transferred to the stage 532a, and the fifth stage 531b and the sixth stage 532b are connected, and a fourth of the plurality of gate signals output from the fifth stage 531b A second switch unit SW2 for transferring the gate signal G4 to the sixth stage 532b may be included. Here, since each stage can sequentially output two gate signals, the third gate signal G3 is the second gate signal output from the first stage 531a, and the fourth gate signal G4 is the fifth stage It may be the second gate signal output from 531b. Accordingly, the second gate signal output from the first stage 531a and the second gate signal output from the fifth stage 531b may be transmitted to the third stage 532a and the sixth stage 532b, respectively. In addition, electrically connecting the first stage 531a and the third stage 532a, the fifth stage 531b and the sixth stage 532b through the first switch unit SW1 and the second switch unit SW2 It can be easily disconnected from the low power mode and the normal mode can be easily distinguished and operated.

The first switch unit SW1 may receive the third gate signal G3 output from the first stage 531a and transmit it to the third stage 532a, and the second switch unit SW2 may receive the third gate signal G3 outputted from the first stage 531a. The fourth gate signal G4 output from 531b may be received and transferred to the sixth stage 532b.

The first stage 531a, the second stage 542a, the third stage 532a, the fourth stage 542b, the fifth stage 531b, and the sixth stage 532b may receive clocks. In addition, the first stage 531a, the second stage 542a, the fourth stage 542b, and the fifth stage 531b may receive a start signal START, respectively.

The first stage 531a may output the first gate signal G1 in response to the start signal START and the clock and output the third gate signal G3 in response to the first gate signal G1 and the clock. there is. In addition, the second stage 542a may output the second gate signal G2 in response to the start signal START and the clock, and a fourth gate signal G4 in response to the second gate signal G2 and the clock. can be printed out. Also, the third stage 532a may output the fifth gate signal G5 in response to the third gate signal G3 and the clock, and the seventh gate signal G5 in response to the fifth gate signal G5 and the clock. G7) can be output.

The fourth stage 542b and the fifth stage 531b of the second gate driver block 530b are performed in the same manner as the first stage 531a and the fifth stage 531b of the first gate driver block 530a. Even-numbered gate signals such as the first gate signal G1 and the fourth gate signal G4 are sequentially applied to the first gate signal G1 to the fourth gate signal G4 in the same manner as the third stage 532a. can be printed out. However, the phase of the clock input to the fifth stage 532b and the sixth stage 532b is delayed from the clock, and after the first gate signal G1 is output, the second gate signal G2 is output and the third gate After the signal G3 is output, the fourth gate signal G4 may be output. That is, after one odd-numbered gate signal is generated, one even-numbered gate signal may be generated, so that the odd-numbered gate signal and the even-numbered gate signal may be generated alternately.

Here, the start signal START supplied to the first stage 531a, the second stage 532a, the fourth stage 542b and the fifth stage 531b may be a synchronized signal, so that the first The stage 531a, the second stage 532a, the fourth stage 542b, and the fifth stage 531b may be respectively supplied. However, the present invention is not limited thereto.

When the first switch unit SW1 and the second switch unit SW2 are turned off, the third gate signal G3 and the fourth gate signal G4 are the third stage 532a and the sixth stage 532b, respectively. is not transmitted to the gate driver circuit 530, only the first gate signal (G1) to the fourth gate of the first stage 531a, the second stage 542a, the fourth stage 542b, and the fifth stage 532b. A signal G4 may be output. Accordingly, only the first region 310a of the display panel 310 may display an image.

And, when the first switch unit SW1 and the second switch unit SW2 are turned on, the third gate signal G3 and the fourth gate signal G4 are the third stage 532a and the sixth stage 532b, respectively. In the gate driver circuit 530 , all of the first stage 531a to the sixth stage 533b operate, so that both the first region 310a and the second region 310b display an image.

The first switch unit SW1 and the second switch unit SW2 operate in response to the enable signal Enable, respectively, and in the low power mode, the enable signal is not transmitted so that the image is displayed only in the first region 310a. And in the normal mode, an enable signal is transmitted so that both the first region 310a and the second region 310b can display an image. Due to the operation of the first switch unit SW1 and the second switch unit SW2, only the first region 310a can display an image in the low power mode, thereby reducing power consumption compared to the normal mode.

The enable signal Enable may be output from the control unit illustrated in FIGS. 1 and 2 , and the control unit may determine whether to output the enable signal Enable in response to the input signal.

Here, the first gate driver block 530a and the second gate driver block 530b are illustrated as including a plurality of stages, respectively, but each stage may correspond to the GIP circuit illustrated in FIG. 2 .

In the low power mode, the enable signal Enable may be transmitted in a low state. When the enable signal Enable is transferred to the low state, the first switch unit SW1 and the second switch unit SW2 may be turned off. In a state in which the first switch unit SW1 and the second switch unit SW2 are turned off, the start signal START and the first clock CLK1 are input to the first stage 531a and the third stage 532a, respectively. can be

In the normal mode, an enable signal (Enable) may be transferred to a high state. When the enable signal Enable is transferred to a high state, the first switch unit SW1 and the second switch unit SW2 may be turned on. However, the turn-on of the first switch unit SW1 and the second switch unit SW2 is not limited thereto. When the first switch unit SW1 and the second switch unit SW2 are turned on, the start signal START and the first clock CLK1 are transmitted to the first stage 531a and the third stage 532a, respectively. The first stage 531a and the third stage 532a may sequentially output the first gate signal G1 to the fourth gate signal G4 in sequence. At this time, since the first switch unit SW1 and the second switch unit SW2 are turned on, the third gate signal G3 output from the first stage 531a and the third gate signal G3 output from the third stage 532a are turned on. The four gate signals G4 may be transmitted to the second stage 542a and the fourth stage 542b, respectively.

Accordingly, selection of an area in which the display panel is displayed for each low power mode and normal mode can be simply achieved by using a switch.

Here, the gate driving block 430a and the second gate driving block 430b are illustrated as being configured to correspond to (a) of FIG. 6 , but may be configured to correspond to (b) of FIG. 6 .

9 is a state transition diagram illustrating a change between a low power mode and a normal mode in the display device according to the present embodiments.

Referring to FIG. 9 , the display device may operate in a low power mode and a normal mode.

The normal mode is an operation mode in which an image is normally displayed in a situation in which a user actually watches or takes an action in a mobile terminal such as a smart phone or a tablet, or a general TV or monitor.

In contrast, the low power mode is an operation mode for reducing power consumption. For example, in a mobile terminal such as a smart phone or tablet, or a general TV or monitor, a user's actual viewing such as a lock screen, a standby screen, a screen saver operation screen, etc. However, it may be an operation mode used to implement a screen with no action.

For example, during the low power mode period, in order to reduce power consumption, the area where the image is displayed is a portion of the entire screen area, and the image displayed on this partial area may be an image expressing simple information with only a small number of colors. .

For example, in the normal mode, an enable signal capable of turning on the first switch unit SW1 and the second switch unit SW2 is transmitted, and the first switch unit SW1 shown in FIG. 8 and The second switch unit SW2 may be turned on.

Accordingly, gate driving is performed in all of the 1-1 region 311a, the 1-2 th region 312a, and the second region 310b. Accordingly, all sub-pixels disposed in the 1-1 region 311a , the 1-2 th region 312a and the second region 310b may be driven.

Also, in the low power mode, the enable signal is not transmitted, so that the first switch unit SW1 and the second switch unit SW2 may be turned off.

Accordingly, the gate driving is performed only in the 1-1 region 311a and the 1-2 th region 312a, and the gate driving is not performed in the second region 310b. Accordingly, only subpixels disposed in the 1-1 region 311a and the 1-2 th region 312a may be driven.

Meanwhile, as an example of a state transition method, a state without a user action elapses for a predetermined time or longer while operating in a normal mode, or a user input related to entering a low power mode (eg, input of a lock screen button, a power button, etc.) ), the control unit 140 does not output the enable signal (enable) so that the first switch unit SW1 and the second switch unit SW2 are turned off, so that the low power mode can be executed.

In addition, when the user operates a switch for turning on the screen while the screen of the display device is turned off, the control unit 140 generates a start pulse and a clock, but prevents an enable signal from being generated so that the low power mode is executed.

The user's manipulation of the switch for turning the screen may be a switch added to an input device separately provided in the display device. The input device separately added to the display device may be a keyboard, a mouse, and a touch panel. When the user inputs a signal through one of the designated keys or all keys of the keyboard, the display device may recognize that a switch for keying the screen has been manipulated. In addition, when the pointer is moved by the mouse through the mouse or a button on the mouse is manipulated, the display device may recognize that a switch that controls the screen has been manipulated. In addition, when the touch panel is touched, the display device may recognize that a switch for turning the screen has been operated.

In addition, if a signal is inputted by the input device once, the low power mode may be entered, and if the input signal by the user's manipulation is input again within a preset time, the normal mode may be entered.

After the low power mode is executed, when an input signal notifying the entry into the normal mode is transmitted by the user's manipulation, the control unit 140 outputs an enable signal to activate the first switch unit SW1 and the second switch unit SW2. can be turned on.

When the first switch unit SW1 and the second switch unit SW2 are turned off, the 1-1 region 311a, the 1-2 region 312a, and the second region 310b shown in FIG. 4 are turned off. ), only the 1-1 region 311a and the 1-2 th region 312a may display an image.

However, when the first switch unit SW1 and the second switch unit SW2 are turned on, the 1-1 region 311a, the 1-2 region 312a, and the second region 310b shown in FIG. 4 are turned on. ) can all display images.

10 is a conceptual diagram illustrating display in a normal mode and a low power mode in the display device according to the present embodiments. 11 is an exemplary diagram of an image displayed on the 1-1 region 311a and the 1-2 th region 312a in the low power mode in the display device according to the present embodiments.

Referring to FIG. 10 , (a) shows that the display device operates in the normal mode, and the 1-1 region 311a, the 1-2 region 312a, and the second region 310b all display images. can do. That is, gate driving is performed in all of the 1-1 region 311a , the 1-2 th region 312a , and the second region 310b.

In addition, (b) and (c) show embodiments in which the display device operates in a low power mode, wherein the 1-1 region 311a and the 1-2 th region 312a display an image, but the second region ( 310b) does not display an image. That is, the gate driving is performed in the 1-1 region 311a and the 1-2 th region 312a, and the gate driving is not performed in the second region 310b.

However, in the case of (b), information of a single color or various colors is displayed on a general background (eg, a background with a color other than black), whereas in case (c), information of a single color or a few kinds of colors is displayed on a black background. information is expressed. Therefore, compared to (b), in the case of (c), the area of the region where light is emitted is reduced, so that power consumption can be further reduced.

For example, in the case of (b) and (c) of FIG. 10, the user's actual action (such as a lock screen, a standby screen, a screen saver operation screen, etc.) It can be used to implement a screen with no action).

The images displayed in the 1-1 region 311a and the 1-2 region 312a are, for example, as shown in FIG. 11 , information such as communication status, current time, alarm, and remaining battery capacity : represented by numbers, letters, symbols, images, etc.) may be displayed separately in the 1-1 area 311a and the 1-2 area 312a, respectively. However, the image or information thereof displayed in the 1-1 region 311a and the 1-2 th region 312a is not limited thereto.

Also, the images displayed in the 1-1 region 311a and the 1-2 th region 312a may be monochromatic or images of about 2 to 4 colors or images with little change in gradation. Power may not be great. However, the present invention is not limited thereto.

Also, all or part of the 1-1 region 311a and the 1-2 th region 312a may display an image. In addition, when applied to the case of (c) of FIG. 10 , black and bright colors may be inverted by displaying the background in black and numbers, symbols, etc. in bright grayscale.

According to the present embodiments described above, it is an object to provide a gate driver having a structure and a driving mechanism capable of realizing a small non-display area, and a display device using the same.

In addition, according to the present embodiments, a gate driver circuit having a gate driving structure and mechanism capable of reducing power consumption and a display device using the same can be provided.

In addition, according to the present embodiments, it is possible to provide a gate driver circuit and a display device that enable image display around a mounting space of application parts such as a camera lens and a sensor.

The above description and the accompanying drawings are merely illustrative of the technical spirit of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine configurations within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device
101: pixel
110: display panel
120: data driver circuit
130a: first gate driver circuit
130b: second gate driver circuit
140: control unit
G1, G2,… ,Gn-1,Gn: gate line
D1,… ,Dm: data line

Claims (18)

A display panel comprising: a display panel in which a plurality of gate lines and a plurality of data lines intersect and divided into a 1-1 region, a 1-2 region, and a second region;
a first gate circuit disposed at one side of the display panel and sequentially applying a gate signal to the gate lines disposed in the 1-1 region;
a second gate circuit disposed at one side of the display panel and sequentially applying a gate signal to odd-numbered gate lines among the gate lines disposed in the second region;
a third gate circuit disposed on the other side of the display panel and sequentially applying a gate signal to the gate lines disposed in the first-2 regions;
a fourth gate circuit disposed on the other side of the display panel and sequentially applying a gate signal to even-numbered gate lines among the gate lines disposed in the second region; and
a data driver circuit for applying a data signal to the plurality of data lines;
The first gate circuit is
A first stage that receives the start signal and the clock and sequentially outputs k (k is a natural number greater than or equal to 2) gate signals;
and a second stage for sequentially outputting k gate signals by receiving the start signal and the clock, and alternately outputting k gate signals output from the first stage,
The second gate circuit is
and a third stage receiving at least one of the k gate signals output from the first stage and a clock and sequentially outputting k gate signals,
The third gate circuit is
a fourth stage receiving the start signal and the clock and sequentially outputting k gate signals;
and a fifth stage for sequentially outputting k gate signals by receiving the start signal and the clock and alternately outputting k gate signals output from the fourth stage,
The fourth gate circuit is
a sixth stage receiving at least one of the k gate signals and a clock output from the fifth stage and sequentially outputting k gate signals;
The gate line disposed in the 1-1 region and the gate line disposed in the 1-2 th region are not connected to each other.
delete delete According to claim 1,
a first switch unit electrically connected between the first stage and the third stage and transferring at least one of k gate signals output from the first stage to the third stage; and
and a second switch unit electrically connected between the fifth stage and the sixth stage and transferring at least one of k gate signals output from the fifth stage to the sixth stage.
delete According to claim 1,
The first stage outputs k gate signals to k odd-numbered gate lines located in the 1-1 region,
The second stage outputs k gate signals to k even-numbered gate lines located in the 1-1 region,
The fourth stage outputs k gate signals to the k odd-numbered gate lines located in the 1-2 regions,
the fifth stage outputs k gate signals to k even-numbered gate lines located in the region 1-2;
The third stage outputs k gate signals to k odd-numbered gate lines located in the second region,
The sixth stage is a display device that outputs k gate signals to k even-numbered gate lines located in the second region.
display panel;
a first gate in panel (GIP) block for sequentially outputting k (k is a natural number greater than or equal to 2) gate signals;
a second GIP block that sequentially outputs k gate signals and crosses the plurality of gate signals output from the first GIP block;
a third GIP block for sequentially outputting k gate signals when receiving at least one of the k gate signals output from the first GIP block;
a fourth GIP block sequentially outputting k gate signals;
a fifth GIP block that sequentially outputs k gate signals and crosses the plurality of gate signals output from the fourth GIP block; and
When receiving at least one of the k gate signals output from the 5th GIP block, a 6th GIP block that sequentially outputs a plurality of k gate signals to intersect the k gate signals output from the 3rd GIP block. and
The first GIP block receives the start signal and the clock and sequentially outputs k gate signals,
The second GIP block receives the start signal and the clock and sequentially outputs k gate signals, and alternately outputs k gate signals output from the first GIP block,
The third GIP block receives at least one of k gate signals and a clock output from the first GIP block and sequentially outputs k gate signals,
The fourth GIP block receives the start signal and the clock and sequentially outputs k gate signals,
The fifth GIP block receives the start signal and the clock to sequentially output k gate signals, and alternately outputs k gate signals output from the fourth GIP block;
The sixth GIP block receives at least one of k gate signals and a clock output from the fifth GIP block and sequentially outputs k gate signals,
A gate line connected to the first or second GIP block and a gate line connected to the fourth or fifth GIP block are not connected to each other.
8. The method of claim 7,
a first switch unit connecting the first GIP block and the third GIP block and transferring the at least one gate signal output from the first GIP block to the third GIP block; and
and a second switch unit connecting the fifth GIP block and the sixth GIP block and transferring the at least one gate signal output from the fifth GIP block to the sixth GIP block.
delete 8. The method of claim 7,
The first Gate In Panel (GIP) block outputs k gate signals to k odd-numbered gate lines located in the 1-1 region;
the second GIP block outputs k gate signals to k even-numbered gate lines located in the 1-1 region;
The fourth GIP block outputs k gate signals to k odd-numbered gate lines located in regions 1-2;
The 5th GIP block outputs k gate signals to k even-numbered gate lines located in the region 1-2;
The third GIP block outputs k gate signals to k odd-numbered gate lines located in the second region,
The sixth GIP block outputs k gate signals to k even-numbered gate lines located in the second region.
11. The method of claim 10,
The length in the first direction of the second region is,
greater than the sum of the length in the first direction of the 1-1 region and the length in the first direction of the region 1-2;
The length in the second direction of the region 1-1 and the length in the second direction of the region 1-2 correspond to each other;
A display device in which at least one application component is disposed between the 1-1 region and the 1-2 region.
9. The method of claim 8,
When the low power mode signal is generated, the first switch and the second switch are turned off, and when the low power mode signal is not generated, the first switch and the second switch are turned on.
9. The method of claim 8,
When a low power mode signal is generated, the first GIP block, the second GIP block, the fourth GIP block and the fifth GIP block output k gate signals, and the third GIP block and the sixth GIP block do not output gate signals, ,
When the low power mode signal is not generated, the first GIP block, the second GIP block, the fourth GIP block, and the fifth GIP block output k gate signals, and the third GIP block and the sixth GIP block have k gates A display device that outputs a signal.
11. The method of claim 10,
at least one hole is formed between the 1-1 region and the 1-2 th region.
A first stage for sequentially outputting k (k is a natural number greater than or equal to 2) gate signals, and a second stage for sequentially outputting k gate signals and alternately outputting k gate signals output from the first stage; , a first gate driver block including a third stage for sequentially outputting k gate signals when receiving at least one of the k gate signals output from the first stage; and
A fourth stage for sequentially outputting k gate signals, a fifth stage for sequentially outputting k gate signals and alternately outputting k gate signals output from the fourth stage, and output from the fifth stage a second gate driver block including a sixth stage for sequentially outputting k gate signals when receiving at least one of the k gate signals,
The first stage receives the start signal and the clock and sequentially outputs k (k is a natural number equal to or greater than 2) number of gate signals,
The second stage receives the start signal and the clock and sequentially outputs k gate signals, and alternately outputs k gate signals output from the first stage,
The third stage receives at least one of the k gate signals output from the first stage and a clock, and sequentially outputs k gate signals,
The fourth stage receives the start signal and the clock and sequentially outputs k gate signals,
The fifth stage receives the start signal and the clock and sequentially outputs k gate signals, and alternately outputs the k gate signals output from the fourth stage,
The sixth stage receives at least one of the k gate signals and a clock output from the fifth stage and sequentially outputs k gate signals,
The gate line connected to the first stage or the second stage and the gate line connected to the fourth stage or the fifth stage are not connected to each other.
16. The method of claim 15,
a first switch unit electrically connected between the first stage and the third stage and transferring at least one of the k gate signals output from the first stage to the third stage; and
and a second switch unit electrically connected between the fifth stage and the sixth stage and transferring at least one of the k gate signals output from the fifth stage to the sixth stage.
delete 16. The method of claim 15,
The first stage outputs k gate signals to k odd-numbered gate lines located in the 1-1 region,
the second stage outputs k gate signals to k even-numbered gate lines located in the 1-1 region;
The fourth stage outputs k gate signals to k odd-numbered gate lines located in regions 1-2,
the fifth stage outputs k gate signals to k even-numbered gate lines located in the region 1-2;
The third stage outputs k gate signals to k odd-numbered gate lines located in the second region,
The sixth stage is a gate driver circuit that outputs k gate signals to k even-numbered gate lines located in the second region.

Images