KR20190016747A - Organic light emitting display device, data management device and method for driving the organic light emitting display device - Google Patents

Abstract

Embodiments of the present invention relate to an organic light emitting diode display device capable of reducing time required for displaying an image by the organic light emitting diode display device by reducing time for loading a compensation value for sub pixels on a display panel when the organic light emitting diode display device is powered on and a driving method thereof. The organic light emitting diode display device comprises a display panel, a sensing unit, a controller, a first memory unit, and a second memory unit.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device, a data management device of the OLED display device,

The present invention relates to an organic light emitting display and a driving method thereof.

2. Description of the Related Art [0002] As an information-oriented society develops, there have been various demands for a display device for displaying images. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) And various display devices such as an organic light emitting display (OLED) device are used.

Recently, an organic light emitting diode (OLED) display device that has been well known in the art has an advantage of high response speed, contrast ratio, luminous efficiency, brightness and viewing angle by using an organic light emitting diode (OLED)

Each of the sub-pixels arranged in the organic light emitting display panel of the organic light emitting display device is basically composed of a driving transistor for driving the organic light emitting diode, a switching transistor for transmitting the data voltage to the gate node of the driving transistor, And a capacitor that serves to maintain the capacitor.

On the other hand, the driving transistors in each sub-pixel have characteristic values such as a threshold voltage and a mobility, and these characteristic values may be different for each driving transistor.

In addition, as the driving time becomes longer, the driving transistor is degraded and the characteristic value may be changed. Due to the difference in the degree of deterioration, a characteristic value deviation between the driving transistors may occur.

Since the deterioration of the organic light emitting diodes in each subpixel also progresses as the driving time increases, the characteristic values such as the threshold voltage may change, and the degree of deterioration between the organic light emitting diodes may be different. Deviations may occur.

The deviation of the characteristic value between the sub-pixels caused by the characteristic value deviation between the driving transistors and the characteristic value deviation between the organic light emitting diodes causes a luminance deviation between the sub pixels, resulting in a screen abnormal phenomenon such as a screen afterimage or a luminance unevenness of the display panel .

Thus, a technique for compensating for the deviation of characteristic values between subpixels has been developed. In the compensation method, a sensing value (Vsen) is obtained after sensing the characteristic value of the driving transistor or the organic light emitting diode of the subpixel by sensing driving the organic light emitting display device, and data to be applied to the subpixel based on the sensing value (Vsen) As shown in FIG.

However, as the resolution of the organic light emitting display increases, the number of driving transistors increases, and the time required to compensate for the characteristic value deviation between subpixels is getting longer.

The purpose of these embodiments is to reduce the time for performing the compensation of the OLED display.

It is an object of the present embodiments to provide an organic light emitting display device which is more convenient for a user by reducing a user response time until an image is displayed after a power-on signal is generated.

An object of the present invention is to reduce the time taken to load a compensation value for compensating for a characteristic value deviation between subpixels at the time of power-on, thereby reducing the time taken for the organic light emitting display to display an image.

In one aspect of the present invention, an embodiment of the present invention provides a display panel in which a plurality of subpixels are arranged, a method of measuring sensing voltage from at least one of the plurality of subpixels, A controller for receiving the sensing data, the sensing data, the sensing data, and the sensing data, and calculating a compensation value for at least one subpixel; a first memory unit and a first memory unit, And a second memory unit having a different transfer rate.

The initial compensation data can be transferred from the first memory unit to the second memory unit under the control of the controller when the power-on signal is generated.

The compensation section can read the initial compensation data in the second memory section.

The second memory unit may have a higher transmission speed than the first memory unit.

The controller may transmit the initial compensation data stored in the first memory unit to the second memory unit when the driving voltage is applied and may transmit the initial compensation data stored in the second memory unit to the compensation unit when the panel driving voltage is applied .

The compensation unit may receive the initial compensation data for the selected subpixel while receiving the sensing data for the selected one of the plurality of subpixels in the predetermined order and calculating the compensation value.

Before the initial compensation data is transferred from the first memory unit to the second memory unit, the compensation unit parameter is transferred from the first memory unit to the second memory unit, and before the compensation unit reads the initial compensation data from the second memory unit, Parameters can be read in the second memory unit.

The controller can load the pre-stored controller parameters while the initial compensation data is transferred from the first memory unit to the second memory unit after the firmware boot is performed, when the drive voltage is applied, .

When the panel driving voltage is applied, the controller can output information on the abnormality of the display panel before receiving the second memory unit rotor compensation data.

The controller performs booting of the firmware when the driving voltage is applied. When the panel driving voltage for driving the display panel is applied, the initial compensation data stored in the first memory unit is transmitted to the compensation unit through the second memory unit according to a preset flag value .

According to another aspect of the present invention, there is provided a display device including a display panel in which a plurality of sub-pixels are arranged, a driving circuit for measuring a sensing voltage from a display panel and outputting a sensing value, a controller for generating a compensation value based on the sensing data, And a second memory unit having a different transmission speed from the first memory unit and the first memory unit, which are stored in advance.

In the OLED display, when a power-on signal is generated, an image may be displayed after the ON sequence has been performed.

The initial compensation value may be transferred from the first memory unit to the second memory unit during a period during which the on sequence is performed.

The controller can read the initial compensation value from the second memory unit.

The driving circuit can measure the sensing voltage during the sensing drive period of the display panel and output a sensing value.

The controller may generate a compensation value based on the sensing value output from the driving circuit and the initial compensation value read from the second memory.

Each of the plurality of subpixels includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, a switching transistor electrically connected between the first node of the driving transistor and the data line, And a capacitor electrically connected between the electrodes.

The sensing voltage may be a voltage of a sensing line electrically connectable to a first node or a second node of the driving transistor.

When the data voltage is applied to the data line corresponding to at least one subpixel during the sensing drive period of the display panel and then the voltage of the sensing line which is the other data line is changed, Can be measured as a sensing voltage.

According to another aspect of the present invention, there is provided a memory device including a first memory unit in which initial compensation data is stored in advance, a second memory unit having a transfer rate different from that of the first memory unit, a first connection unit connected to an output end of the first memory unit, And a data bus for connection between the first connection unit and the second connection unit, and a data bus for connecting the first connection unit and the second connection unit.

According to another aspect of the present invention, in the embodiments, when the power-on signal is generated, the initial compensation data is transferred from the first memory unit to the second memory unit under the control of the controller, and the compensation unit reads the initial compensation data from the second memory unit And a driving step of driving the organic light emitting display device.

According to the embodiments described above, after the power-on signal is generated, the user response time can be reduced to provide a more convenient organic light emitting display.

According to the embodiments, it is possible to reduce the time taken to load the compensation value for compensating the characteristic value deviation between subpixels at the time of power-on, thereby reducing the time required until the organic light emitting display device displays an image.

1 is a schematic system configuration diagram of an organic light emitting display according to the present embodiments.
FIG. 2 is a view illustrating a sub-pixel structure of an OLED display according to an embodiment of the present invention. Referring to FIG.
3 is a view illustrating another example of the sub-pixel structure of the OLED display according to the present embodiments.
4 is an illustration of a compensation circuit of an organic light emitting diode display according to the present embodiments.
5 is a view for explaining a threshold voltage sensing driving method for a driving transistor of an organic light emitting display according to the present embodiments.
6 is a view for explaining a mobility sensing driving method for a driving transistor of an organic light emitting diode display according to embodiments of the present invention.
7 is a diagram showing sensing timing of the OLED display according to the present embodiments.
8 is a diagram illustrating an exemplary system implementation of an OLED display according to the present embodiments.
FIG. 9 conceptually illustrates a data transmission path between the compensation unit and the memory unit in the on-sensing process of the OLED display according to the present embodiments.
10 is a diagram specifically illustrating a data transmission path between the controller and the memory unit during the on-sensing process of the OLED display according to the present embodiments.
11 is a timing diagram illustrating an initial driving process of the organic light emitting diode display according to the exemplary embodiments of the present invention.
FIG. 12 conceptually illustrates a data transmission path between the compensation unit and the memory unit in the on-sensing process of the organic light emitting diode display according to other embodiments.
13 is a diagram illustrating a data transmission path between a controller and a memory unit in an on-sensing process of the OLED display according to another embodiment of the present invention.
FIG. 14 is a timing diagram illustrating an initial driving process of the OLED display according to another embodiment of the present invention. Referring to FIG.
15 shows a method of driving the organic light emitting display according to the present embodiments.
16 shows a method of driving an organic light emitting display according to another embodiment.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

 FIG. 1 is a schematic system configuration diagram of an organic light emitting diode display 100 according to the present embodiments.

1, the OLED display 100 according to the present embodiment includes a plurality of data lines DL and a plurality of gate lines GL, a plurality of data lines DL, An OLED display panel 110 in which a plurality of sub pixels (SP) defined by a gate line GL are arranged, a data driver 120 driving a plurality of data lines DL, A gate driver 130 for driving the gate line GL, a controller 140 for controlling the data driver 120 and the gate driver 130, and the like.

The controller 140 supplies various control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130.

The controller 140 starts scanning according to the timing implemented in each frame, switches the input image data input from the outside according to the data signal format used by the data driver 120, and outputs the converted image data , And controls the data driving at a suitable time according to the scan.

The controller 140 may be a timing controller used in a conventional display technology or a control device including a timing controller to perform other control functions. In the present invention, the controller 140 may include a compensation unit that performs a compensation process to compensate for a characteristic value deviation between subpixels.

The controller 140 may be implemented as a separate component from the data driver 120, or may be implemented as an integrated circuit together with the data driver 120.

The data driver 120 drives the plurality of data lines DL by supplying data voltages to the plurality of data lines DL. Here, the data driver 120 is also referred to as a 'source driver'.

The data driver 120 may drive a plurality of data lines including at least one source driver integrated circuit (SDIC).

Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, and the like.

Each source driver integrated circuit (SDIC) may further include an analog to digital converter (ADC), as the case may be.

The gate driver 130 sequentially supplies the scan signals to the plurality of gate lines GL to sequentially drive the plurality of gate lines GL. Here, the gate driver 130 is also referred to as a " scan driver ".

The gate driver 130 may include at least one gate driver integrated circuit (GDIC).

Each gate driver IC (GDIC) may include a shift register, a level shifter, and the like.

The gate driver 130 sequentially supplies a scan signal of an On voltage or an Off voltage to the plurality of gate lines GL under the control of the controller 140.

When a specific gate line is opened by the gate driver 130, the data driver 120 converts the image data received from the controller 140 into an analog data voltage and supplies the data voltage to a plurality of data lines DL.

1, the data driver 120 may be located only on one side (for example, on the upper side or the lower side) of the organic light emitting display panel 110, and in some cases, depending on the driving method, And may be located on both sides (e.g., upper and lower sides) of the display panel 110.

1, the gate driver 130 may be located only on one side (e.g., the left side or the right side) of the organic light emitting display panel 110, and depending on the driving method, the panel design method, And may be located on both sides (e.g., left and right sides) of the light emitting display panel 110.

The controller 140 described above is capable of outputting various kinds of signals including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the input data enable signal (DE), and the clock signal (CLK) Timing signals from the outside (e.g., the host system).

The controller 140 receives a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal, and a clock signal to control the data driver 120 and the gate driver 130, And generates various control signals and outputs them to the data driver 120 and the gate driver 130.

For example, in order to control the gate driver 130, the controller 140 generates a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal GOE Gate Output Enable), and the like.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driver 130. The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE specifies the timing information of one or more gate driver ICs.

In order to control the data driver 120, the controller 140 may further include a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE) And outputs various data control signals (DCS: Data Control Signals).

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits constituting the data driver 120. The source sampling clock SSC is a clock signal for controlling sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driver 120.

Each subpixel SP arranged in the organic light emitting display panel 110 includes an organic light emitting diode (OLED), a driving transistor for driving the organic light emitting diode (OLED) And the like.

The types and the number of the circuit elements constituting each subpixel SP can be variously determined depending on the providing function, the design method, and the like.

2 is an exemplary view of a sub-pixel structure of the OLED display 100 according to the present embodiments.

Referring to FIG. 2, in the organic light emitting diode display 100 according to the present embodiment, each of the sub-pixels SP basically includes an organic light emitting diode OLED, a driving circuit for driving the organic light emitting diode OLED A first transistor T1 for transmitting a data voltage to a first node N1 corresponding to a gate node of a driving transistor DRT and a driving transistor DRT; And a storage capacitor (Cst: Storage Capacitor) for maintaining the voltage corresponding thereto for one frame time.

The organic light emitting diode OLED may include a first electrode (e.g., an anode electrode or a cathode electrode), an organic layer, and a second electrode (e.g., a cathode electrode or an anode electrode).

A base voltage EVSS may be applied to the second electrode of the organic light emitting diode OLED.

The driving transistor DRT drives the organic light emitting diode OLED by supplying a driving current to the organic light emitting diode OLED.

The driving transistor DRT has a first node N1, a second node N2, and a third node N3.

The first node N1 of the driving transistor DRT is a node corresponding to a gate node and may be electrically connected to a source node or a drain node of the first transistor T1.

The second node N2 of the driving transistor DRT may be electrically connected to the first electrode of the organic light emitting diode OLED and may be a source node or a drain node.

The third node N3 of the driving transistor DRT may be electrically connected to a driving voltage line DVL that supplies a driving voltage EVDD as a node to which the driving voltage EVDD is applied, Node or source node.

The driving transistor DRT and the first transistor T1 may be implemented as an n-type or a p-type as illustrated in FIG.

The first transistor T1 is electrically connected between the data line DL and the first node N1 of the driving transistor DRT and receives the scan signal SCAN through the gate line have.

The first transistor T1 may be turned on by the scan signal SCAN to transfer the data voltage Vdata supplied from the data line DL to the first node N1 of the driving transistor DRT .

The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

The storage capacitor Cst is not a parasitic capacitor (for example, Cgs or Cgd) which is an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor DRT, And is an external capacitor intentionally designed outside the driving transistor DRT.

In the OLED display 100 according to the present embodiment, as the driving time of each sub-pixel SP becomes longer, the driving voltage of the organic light emitting diode OLED, the driving transistor DRT, Degradation can proceed.

Accordingly, inherent characteristic values of the circuit elements such as the organic light emitting diode (OLED) and the driving transistor (DRT) can be changed. Here, the intrinsic property value of the circuit element may include a threshold voltage of the organic light emitting diode OLED, a threshold voltage of the driving transistor DRT, a mobility of the driving transistor DRT, and the like.

A change in the characteristic value of the circuit element may cause a change in luminance of the corresponding subpixel. Therefore, the change in the characteristic value of the circuit element can be used in the same concept as the change in luminance of the subpixel.

In addition, the degree of change in the characteristic value between the circuit elements may be different depending on the degree of deterioration of each circuit element.

Such a difference in degree of characteristic value change between circuit elements may cause a deviation in characteristic value between circuit elements, resulting in luminance deviation between subpixels. Therefore, the characteristic value deviation between the circuit elements can be used in the same concept as the luminance deviation between the subpixels.

Variations in the characteristic values of the circuit elements (luminance variation of the subpixels) and characteristic deviations between the circuit elements (luminance deviation between the subpixels) cause problems such as degradation of the accuracy of luminance expressions of subpixels or occurrence of screen anomalies .

The organic light emitting diode display 100 according to the exemplary embodiments of the present invention can provide a sensing function for sensing a characteristic value for a subpixel and a compensation function for compensating a subpixel characteristic value using a sensing result.

Sensing a characteristic value for a subpixel in this specification means sensing a characteristic value or a characteristic value change of a circuit element (a driving transistor DRT, an organic light emitting diode (OLED)) in a subpixel, DRT), and organic light emitting diode (OLED)).

In this specification, the compensation of the characteristic value for the subpixel means that the characteristic value or the characteristic value change of the circuit element (drive transistor DRT, organic light emitting diode (OLED)) in the subpixel is changed to a predetermined level, The transistor DRT, and the organic light emitting diode OLED) may be reduced or eliminated.

The organic light emitting diode display 100 according to the present embodiments may include a compensation circuit including a sensing and compensation structure and a subpixel structure suitable for providing a sensing function and a compensation function.

3 is another example of the sub-pixel structure of the OLED display 100 according to the present embodiments.

The subpixel structure shown in FIG. 3 is an example of a suitable subpixel structure to provide a sensing function and a compensation function.

Referring to FIG. 3, each sub-pixel disposed in the organic light emitting display panel 110 according to the present exemplary embodiment includes an organic light emitting diode OLED, a driving transistor DRT, a first transistor T1, In addition to the storage capacitor Cst, it may further include a second transistor T2.

3, the second transistor T2 is electrically connected between the second node N2 of the driving transistor DRT and a reference voltage line RVL for supplying a reference voltage Vref And may be controlled by receiving a sensing signal SENSE, which is a kind of a scan signal, to the gate node.

By further including the second transistor T2 described above, the voltage state of the second node N2 of the driving transistor DRT in the sub-pixel SP can be effectively controlled.

The second transistor T2 is turned on by the sensing signal SENSE and applies a reference voltage Vref supplied through the reference voltage line RVL to the second node N2 of the driving transistor DRT .

Also, the second transistor T2 may be utilized as one of the voltage sensing paths for the second node N2 of the driving transistor DRT.

Meanwhile, the scan signal SCAN and the sense signal SENSE may be separate gate signals. In this case, the scan signal SCAN and the sense signal SENSE may be respectively applied to the gate node of the first transistor T1 and the gate node of the second transistor T2 through different gate lines.

In some cases, the scan signal SCAN and the sense signal SENSE may be the same gate signal. In this case, the scan signal SCAN and the sense signal SENSE may be commonly applied to the gate node of the first transistor T1 and the gate node of the second transistor T2 through the same gate line.

4 is an exemplary diagram of a compensation circuit of the OLED display 100 according to the present embodiments.

Referring to FIG. 4, the OLED display 100 according to the present embodiment includes a sensing unit 410 for generating and outputting sensing data through voltage sensing in order to determine a characteristic value for a subpixel, A compensation unit 420 for determining a characteristic value of the subpixel based on the characteristic value of the subpixel and compensating the characteristic value of the subpixel, And a memory unit 430 for storing a compensation value calculated in the memory unit 430.

The memory unit 430 receives sensing data from the sensing unit, stores the sensed data, and transmits the sensed data to the compensating unit 420. However, in some cases, the compensation unit 420 directly receives the sensing data, calculates the compensation value, and then stores the compensation value and the sensing data in the memory unit 430 together.

For example, the sensing unit 410 may include at least one analog-to-digital converter (ADC). The sensing data output from the sensing unit 410 may be, for example, a Low Voltage Differential Signaling (LVDS) data format.

Each analog-to-digital converter (ADC) may be contained within each source driver integrated circuit (SDIC) included in the data driver 120 and, in some cases, may be external to the source driver integrated circuit . ≪ / RTI >

The compensation unit 420 may be included in the controller 140 and may be provided outside the controller 140 in some cases. The compensation unit 420 may be referred to as a compensation processor.

The memory unit 430 may store preset initial compensation data and may store sensing data applied from the sensing unit 410 or compensation values calculated by the compensation unit 420. [ However, the data stored in the memory unit 430 is not limited thereto. For example, the memory unit 430 may store image data applied from a host device (not shown) while driving the display panel 110, and may transmit the stored data to the compensation unit 420. The memory unit 430 may store changed data obtained by changing the image data Data to the calculated compensation value in the compensation unit 420. [

The memory unit 430 may be included outside the controller 140 and may be included in the controller 140 in some cases.

Meanwhile, the memory unit 430 may include a plurality of memories. In particular, the memory unit 430 may include a plurality of memories of different types. As an example, the memory unit 430 may include at least one nonvolatile memory and at least one volatile memory. And the plurality of memories may have different data transfer rates. Here, the data transfer rate refers to the read speed of the memory and may include the write speed.

Referring to FIG. 4, the OLED display 100 according to the present embodiment includes an initialization switch SPRE for controlling whether a reference voltage Vref is applied to a reference voltage line RVL, And a sampling switch (SAM) for controlling connection between the sensing unit (RVL) and the sensing unit (410).

The initialization switch SPRE is connected to the second node N2 of the driving transistor DRT so that the second node N2 of the driving transistor DRT in the sub-pixel SP becomes a voltage state reflecting the characteristic value of the desired circuit element. To the voltage application state.

When the initialization switch SPRE is turned on, the reference voltage Vref is supplied to the reference voltage line RVL and is supplied to the second node N2 of the driving transistor DRT through the second transistor T2, ). ≪ / RTI >

The sampling switch (SAM) is turned on to electrically connect the reference voltage line (RVL) and the sensing unit (410).

The sampling switch SAM is turned on so that the second node N2 of the driving transistor DRT in the subpixel SP turns on when the voltage state reflects the characteristic value of the desired circuit element Respectively.

When the sampling switch SAM is turned on, the sensing unit 410 may sense the voltage of the connected reference voltage line RVL.

When the sensing unit 410 senses the voltage of the reference voltage line RVL and the second transistor T2 is turned on and the resistance component of the driving transistor DRT can be ignored, ) May correspond to the voltage of the second node N2 of the driving transistor DRT. The voltage sensed by the sensing unit 410 may be the voltage of the reference voltage line RVL, that is, the voltage of the second node N2 of the driving transistor DRT.

If a line capacitor is present on the reference voltage line RVL, the voltage sensed by the sensing portion 410 may be the voltage charged in the line capacitor on the reference voltage line RVL. Here, the reference voltage line RVL is also referred to as a sensing line.

For example, the voltage sensed by the sensing unit 410 may be a voltage value (Vdata-Vth or Vdata-? Vth, where Vdata-Vth includes the threshold voltage Vth or threshold voltage deviation Vth of the driving transistor DRT) Is a data voltage for sensing driving), or a voltage value for sensing the mobility of the driving transistor DRT.

On the other hand, the reference voltage lines RVL may be arranged one for each sub-pixel column, or one for each of two or more sub-pixel columns.

For example, when one pixel is composed of four subpixels (red subpixel, white subpixel, green subpixel, and blue subpixel), the reference voltage line RVL is divided into four subpixel columns , A white subpixel column, a green subpixel column, and a blue subpixel column).

In the following, the threshold voltage sensing drive and the mobility sensing drive for the driving transistor DRT will be briefly described.

5 is a view for explaining a threshold voltage sensing driving method for the driving transistor DRT of the OLED display 100 according to the present embodiments.

The threshold voltage sensing drive for the driving transistor DRT may proceed to a sensing process including an initialization step, a tracking step and a sampling step.

The initializing step is a step of initializing the first node N1 and the second node N2 of the driving transistor DRT.

In this initialization step, the first transistor T1 and the second transistor T2 are turned on, and the initialization switch SPRE is turned on.

Thus, the first node N1 and the second node N2 of the driving transistor DRT are initialized to the threshold voltage sensing driving data voltage Vdata and the reference voltage Vref (V1 = Vdata, V2 = Vref).

The tracking step is performed until the voltage V2 of the second node N2 of the driving transistor DRT is turned on until the voltage of the second node N2 of the driving transistor DRT becomes a threshold voltage or a voltage state reflecting the change, .

That is, the tracking step is a step of tracking the voltage of the second node N2 of the driving transistor DRT which can reflect the threshold voltage or the change.

In this tracking step, the initialization switch SPRE is turned off or the second transistor T2 is turned off, and the second node N2 of the driving transistor DRT is floated.

As a result, the voltage V2 of the second node N2 of the driving transistor DRT rises.

The voltage V2 of the second node N2 of the driving transistor DRT rises and the rising width gradually decreases and becomes saturated.

The saturated voltage of the second node N2 of the driving transistor DRT may correspond to the difference between the data voltage Vdata and the threshold voltage Vth or the difference between the data voltage Vdata and the threshold voltage deviation Vth .

When the voltage V2 of the second node N2 of the driving transistor DRT becomes saturated, the sampling step can proceed.

The sampling step is a step of measuring a threshold voltage of the driving transistor DRT or a voltage reflecting the change thereof so that the sensing unit 410 can sense the voltage of the reference voltage line RVL, And sensing the voltage of the node N2.

In this sampling step, the sampling switch SAM is turned on so that the sensing unit 410 is connected to the reference voltage line RVL to supply the voltage of the reference voltage line RVL, that is, And senses the voltage V2 of the second node N2.

The voltage Vsen sensed by the sensing unit 410 is a voltage Vdata-Vth obtained by subtracting the threshold voltage Vth from the data voltage Vdata or a voltage Vdata-Vth obtained by subtracting the threshold voltage deviation Vth from the data voltage Vdata Vdata -? Vth). Here, Vth may be a positive threshold voltage or a negative threshold voltage.

6 is a diagram for explaining a mobility sensing driving method for the driving transistor DRT of the OLED display 100 according to the present embodiments.

The mobility sensing drive for the driving transistor DRT may proceed to a sensing process including an initialization step, a tracking step and a sampling step.

The initializing step is a step of initializing the first node N1 and the second node N2 of the driving transistor DRT.

In this initialization step, the first transistor T1 and the second transistor T2 are turned on, and the initialization switch SPRE is turned on.

Accordingly, the first node N1 and the second node N2 of the driving transistor DRT are initialized to the mobility sensing driving data voltage Vdata and the reference voltage Vref, respectively (V1 = Vdata, V2 = Vref).

The tracking step is performed until the voltage V2 of the second node N2 of the driving transistor DRT reaches the voltage V2 until the voltage of the second node N2 of the driving transistor DRT becomes the voltage state reflecting the mobility or the change thereof. .

That is, the tracking step is a step of tracking the voltage of the second node N2 of the driving transistor DRT which can reflect the mobility or the change.

In this tracking step, the initialization switch SPRE is turned off or the second transistor T2 is turned off, so that the second node N2 of the driving transistor DRT is floated. At this time, the first transistor T1 is turned off, and the first node N1 of the driving transistor DRT can also be floated together.

As a result, the voltage V2 of the second node N2 of the driving transistor DRT starts to rise.

The rising speed of the voltage V2 of the second node N2 of the driving transistor DRT depends on the current capability (i.e., mobility) of the driving transistor DRT.

The voltage V2 of the second node N2 of the driving transistor DRT increases more sharply as the driving transistor DRT having a higher current capability (mobility) is.

The sampling step may proceed after the tracking step has progressed for a predetermined time period DELTA t, that is, after the voltage V2 of the second node N2 of the driving transistor DRT has risen for a predetermined constant time DELTA t.

During the tracking step, the rising speed of the voltage V2 of the second node N2 of the driving transistor DRT corresponds to the voltage variation? V for a predetermined time? T.

In the sampling step, the sampling switch SAM is turned on, and the sensing unit 410 and the reference voltage line RVL are electrically connected.

Accordingly, the sensing unit 410 senses the voltage of the reference voltage line RVL, that is, the voltage V2 of the second node N2 of the driving transistor DRT.

The voltage Vsen sensed by the sensing unit 410 is a voltage increased by the voltage change amount? V for a predetermined time? T from the initialization voltage Vref and is a voltage corresponding to the mobility.

5 and 6, the sensing unit 410 may convert the sensed voltage Vsen to a digital value for threshold voltage sensing or mobility sensing, And generates and outputs sensing data including a digital value (sensing value).

The sensing data output from the sensing unit 410 may be provided to the compensating unit 420. In some cases, the sensing data may be provided to the compensation unit 420 through the memory unit 430.

The compensating unit 420 may calculate a characteristic value (e.g., threshold voltage, mobility) of the driving transistor DRT in the corresponding subpixel or a characteristic value change of the driving transistor DRT Voltage change, and mobility change), and perform characteristic value compensation process.

Here, the change in the characteristic value of the driving transistor DRT means that the current sensing data is changed based on the previous sensing data, or the current sensing data is changed based on the initial compensation data.

Therefore, when comparing the characteristic value or the characteristic value change between the driving transistors DRT, it is possible to grasp the characteristic value deviation between the driving transistors DRT. The characteristic value deviation (i.e., sub-pixel luminance deviation) between the driving transistors DRT from the characteristic value change of the driving transistor DRT when the characteristic value change of the driving transistor DRT indicates that the current sensing data is changed based on the initial compensation data, .

Here, the initial compensation data may be initial setting data set and stored at the time of manufacturing the OLED display.

The characteristic value compensation process may include a threshold voltage compensation process for compensating the threshold voltage of the driving transistor DRT and a mobility compensation process for compensating the mobility of the driving transistor DRT.

The threshold voltage compensation process calculates a compensation value for compensating a threshold voltage or a threshold voltage deviation (threshold voltage change), stores the calculated compensation value in the memory unit 430, or stores the corresponding video data Data ). ≪ / RTI >

The mobility compensation process calculates a compensation value to compensate for mobility or mobility deviation (mobility change), stores the calculated compensation value in the memory unit 430, or stores the corresponding video data Data ). ≪ / RTI >

The compensation unit 420 may change the image data Data through the threshold voltage compensation process or the mobility compensation process and supply the changed data to the corresponding source driver integrated circuit (SDIC) in the data driver 120.

Accordingly, the source driver integrated circuit (SDIC) converts the data changed by the compensating unit 420 into a data voltage through a digital to analog converter (DAC) and supplies the data voltage to the corresponding subpixel, Compensation (threshold voltage compensation, mobility compensation) is actually performed.

By compensating for the subpixel characteristic value, luminance deviation between the subpixels is reduced or prevented, thereby improving the image quality.

In this case, if one reference voltage line RVL is arranged for each subpixel column, the sensing unit 410 applies a driving signal to each of the plurality of pixels on the gate line GL driven by the scanning signal SCAN, And senses the voltage V2 of the second node N2 of the driving transistor DRT.

For example, when one pixel is composed of four subpixels (a red subpixel, a white subpixel, a green subpixel, and a blue subpixel), the sensing unit 410 senses a gate line The voltage V2 of the second node N2 of the driving transistors DRT of a plurality of red subpixels may be received and sensed through the reference voltage line RVL in accordance with the order specified on the reference voltage line GL. Then, the voltage V2 of the second node N2 of the driving transistor DRT of the white subpixel, the green subpixel, and the blue subpixel may be sequentially applied through the reference voltage line RVL.

However, if four reference voltage lines RVL are arranged for each subpixel column corresponding to the number of subpixels constituting each pixel, the sensing unit 410 may sense the gate line GL driven by the scan signal SCAN, It is possible to sense the voltage V2 of the second node N2 of the driving transistor DRT for all the subpixels of the driving transistor DRT at a time.

That is, the sensing unit 410 may sense one gate line GL driven by the scan signal SCAN according to the number of subpixels constituting one pixel and the number of the corresponding reference voltage lines RVL. A plurality of times of sensing can be performed on the gate line GL. Therefore, the compensation unit 420 for receiving the sensing data from the sensing unit 410 and calculating the compensation value may also calculate the multiple-time compensation value for one gate line GL.

FIG. 7 is a diagram showing sensing timing of the OLED display 100 according to the present embodiments.

7, when the power-on signal is generated, the organic light emitting display 100 according to the exemplary embodiment of the present invention includes a driving transistor DRT in each sub-pixel disposed in the display panel 110, The characteristic value can be sensed. This sensing process is referred to as an " on-sensing process ".

When a power off signal is generated, before the off-sequence such as power-off occurs, the characteristic value of the driving transistor DRT in each sub-pixel arranged on the display panel 110 . This sensing process is referred to as an " off-sensing process ".

It is also possible to sense the characteristic value of the driving transistor DRT in each sub-pixel disposed on the display panel 110 at every blank time during the display driving until a power-off signal is generated after the power-on signal is generated. This sensing process is referred to as a " real-time sensing process ".

This real-time sensing process may be performed for each blank time between active times based on the vertical synchronization signal Vsync.

Since the mobility sensing of the driving transistor DRT is required only for a short time, it may be performed before the display driving starts after the power-on signal is generated, or when the display driving can not be performed after the power- .

In addition, the mobility sensing of the driving transistor DRT can be performed in real time using a short blank time even during the display driving.

That is, the mobility sensing of the driving transistor DRT may proceed to an on-sensing process before the display driving starts by generating a power-on signal, and a power-off signal is generated and the display driving is progressed (Off-Sensing Process) during the non-display period, and may proceed to the Real-time Sensing Process every short blank time during the display driving.

In contrast, since the threshold voltage sensing (Vth Sensing) of the driving transistor DRT requires the long voltage saturation time Vsat of the second node N2 of the driving transistor DRT, It takes a relatively long time compared to the mobility sensing.

In consideration of this point, the threshold voltage sensing of the driving transistor DRT must be performed utilizing a timing that does not interfere with user viewing.

Therefore, in general, the threshold voltage sensing of the driving transistor DRT can be performed while the display is not driven, that is, in a state where the user does not intend to watch, after a power off signal occurs according to user input or the like .

However, as occasion demands, the threshold voltage sensing of the driving transistor DRT may also proceed to an on-sensing process or a real-time sensing process.

FIG. 8 is a system implementation view of the OLED display 100 according to the present embodiments.

Referring to FIG. 8, each gate driver IC (GDIC) may be mounted on a film GF connected to the display panel 110 when implemented in a chip-on-film (COF) manner.

Each source driver integrated circuit (SDIC), when implemented in a chip-on-film (COF) manner, may be mounted on a film SF connected to the display panel 110.

The display device 100 includes at least one source printed circuit board (SPCB) for controlling the connection between the SDIC and other devices, And a control printed circuit board (CPCB) for mounting the devices.

At least one source printed circuit board (SPCB) may be connected to a film (SF) mounted with a source driver integrated circuit (SDIC). That is, the film SF on which the source driver integrated circuit (SDIC) is mounted is electrically connected to the display panel 110 on one side and electrically connected to the source printed circuit board SPCB on the other side.

The control printed circuit board CPCB is provided with a controller 140 for controlling operations of the data driver 120 and the gate driver 130 and the like and a controller 140 for controlling operations of the display panel 110, the data driver 120, and the gate driver 130, A power management IC (PMIC) 830 for controlling various voltages or currents to be supplied or supplied with various voltages or currents may be mounted.

Here, the controller 140 includes the compensation unit 420, and may further include a timing controller used in a conventional display technology.

The memory unit 430 may be mounted on the control printed circuit board (CPCB). When the memory unit 430 includes a plurality of memories of different types, each memory may be separately mounted on a control printed circuit board (CPCB) and electrically connected to the controller 140.

8 illustrates the first and second memory units 810 and 820 including memories of different types. For convenience of explanation, the first memory unit 810 and the second memory unit 820 are referred to as 1 Each having a memory. However, the first and second memory units 810 and 820 may have a plurality of memories, respectively.

At least one memory included in the first memory unit 810 may be a NAND flash memory as a nonvolatile memory and at least one memory included in the second memory unit 820 may be a DDR SDRAM rate synchronous dynamic random access memory).

In addition, a memory other than the first and second memory units 810 and 820 may be mounted on the control PCB (CPCB). For example, at least one of a ROM (Read-Only Memory) and a programmable ROM (Electrically Erasable Programmable Read-Only Memory: EEPROM) may be further mounted on the control printed circuit board (CPCB).

On the other hand, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be connected in circuit through at least one connecting member.

Here, the connecting member may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like.

At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated into one printed circuit board.

The display apparatus 100 may further include a set board 840 electrically connected to a control printed circuit board (CPCB).

The set board 840 may be referred to as a power board.

The set board 840 may include a main power management circuit 850 (M-PMC) for managing the overall power of the OLED display 100.

The power management integrated circuit 830 is a circuit for managing power to the display module including the display panel 110 and the drive circuits 120, 130, and 140 and the like. The main power management circuit 850 is a circuit for managing the overall power including the display module and can be interlocked with the power management integrated circuit 830.

For example, the main power management circuit 850 can supply the driving voltage VDD, the panel driving voltage EVDD, and the like to the control printed circuit board CPCB. The controller 140 on the control printed circuit board CPCB may be driven by receiving the driving voltage VDD and the power management integrated circuit 830 may supply the panel driving voltage EVDD to the display panel 110 .

FIG. 9 conceptually illustrates a data transmission path between the compensation unit 420 and the memory unit 430 during the on-sensing process of the OLED display 100 according to the present embodiments.

7, when the power-on signal is generated, the OLED display 100 performs an on-sensing process to sense a characteristic value of the driving transistor DRT in each sub-pixel disposed on the display panel 110, can do.

9, in performing the on-sensing process, the compensation unit 420 receives the initial compensation data (ICD) stored in the first memory unit 810 in advance. The initial compensation data (ICD) is data used as a reference value for compensating the sensing data output from the sensing unit 410. The initial compensation data (ICD) may include at least one of the initial setting data set and stored at the time of manufacturing the OLED display 100 and the data stored at the time of executing the previous off-sensing process. Also, the initial compensation data (ICD) may be data on a compensation value for directly compensating the characteristic value of each subpixel included in the display panel 110, or may be data on a reference value for generating a compensation value.

The compensation unit 420 may receive initial compensation data (ICD) from the first memory unit 810 in a predetermined compensation unit. For example, the compensation unit 420 may receive initial compensation data (ICDn) for subpixels included in each gate line GLn at one time. That is, when the organic light emitting display 100 is in the UHD resolution (3840 X 2160 pixels), the compensation unit 420 may receive 2160 times initial compensation data (ICD1 to ICD2160) in units of gate lines (GL).

At this time, the compensation unit 420 senses the characteristic value of the driving transistor DRT in each of the plurality of sub-pixels on the gate line GLn to which the current scan signal is applied through the reference voltage line RVL, 8) corresponding to each of the plurality of respective subpixels on the next gate line GLn + 1 while calculating the compensation value CPVn using the previously applied corresponding initial compensation data ICDn from the initial compensation data ICDn +1).

(ICDn + 1) for each of a plurality of respective subpixels on the next selected gate line GLn + 1, while performing the sensing and compensation value operation for the currently selected gate line GLn . This is to reduce the increase in the time of the on-sensing process due to the time that the initial compensation data (ICD) is transferred from the first memory unit 810 to the compensation unit 420. [

In the present invention, the first memory unit 810 and the second memory unit 820 are memories having different data transfer rates. Here, the data transfer speed of the second memory unit 820 is different from that of the first memory unit 810, Is faster than the data transmission rate of < RTI ID = 0.0 >

As described above, the first memory unit 810 may be a non-volatile memory, and the second memory 820 may be a volatile memory. In the case where the second memory unit 820 is a volatile memory, when the power of the OLED display 100 is turned off, the stored data is lost. Therefore, the compensating unit 420 performs the on- (CPD) by receiving the initial compensation data (ICD) stored in the first memory unit 810 whose data transfer rate is slower than that of the first memory unit 810.

The compensation unit 420 stores the calculated compensation value CPVn in the second memory unit 820 and then performs a characteristic value compensation process using the compensation value CPVn stored in the second memory unit 820 . At this time, the compensation unit 420 may store the compensation value CPVn in the second memory unit 820. The compensating unit 420 may transmit the sensing data SDn to the second memory unit 820 and store the sensing data SDn.

Since the compensation value CPVn is stored in the second memory unit 820 after the on-sensing process is completed, the compensation unit 420 compensates for the compensation value CPVn in the second memory unit 810, (820). That is, the real time sensing process time for compensating the characteristic values of the driving transistors DRT in each sub-pixel disposed in the display panel 110 at every blank time in the display driving can be reduced.

10 is a diagram specifically showing a data transmission path between the controller 140 and the memory unit 430 during the on-sensing process of the organic light emitting diode display 100 according to the present embodiments. FIG. FIG. 3 is a timing chart showing an initial driving process of the organic light emitting display according to the examples.

Referring to FIG. 10, the controller 140 may include an MCU 1010, a compensation unit 420, first and second connection units PDC1 and PDC2, and a data bus 1020. FIG.

The first connection unit PDC1 can convert data transferred between the controller 140 and the first memory unit 810 under the control of the MCU 1010 and control the data transfer path. The second connection unit PDC2 can convert data transferred between the controller 140 and the second memory unit 820 under the control of the MCU 1010 and control the data transfer path. The first and second connection units PDC1 and PDC2 control the data communication between the controller 140 and the first memory unit 810 and the second memory unit 820 under the control of the MCU 1010. [

The data bus 1020 provides a data transmission path between the first and second connection parts PDC1 and PDC2 and the MCU 1010 is connected to the compensation part 420 and the first and second connection parts PDC1 and PDC2, The bus 1020 can be controlled.

Here, the connection part for transferring data between the first and second memory parts 810 and 820 and the data bus 1020 is divided into the first and second connection parts PDC1 and PDC2, 810 and 820 are different types of memories.

For example, when the first memory unit 810 is implemented as at least one NAND flash memory, the first connection unit PDC1 receives initial compensation data (ICD) in units of a predetermined page of the NAND flash memory, It may transmit the applied initial compensation data ICD to the compensating unit 420 in units corresponding to the predetermined compensation unit, here the gate line GL. Here, the page size of the NAND flash memory (for example, 512B to 16KB) can be set variously.

If the first memory unit 810 includes a plurality of first memories, the first connection unit PDC1 may perform parallel data transmission / reception with the plurality of first memories. That is, a plurality of first memories can simultaneously perform data transfer with the first connection unit PDC1.

Also, the second memory unit 820 may include a plurality of second memories capable of relatively high-speed data transmission as compared with the first memory. The second connection unit PDC2 may perform data transmission / reception in parallel with the plurality of second memories.

On the other hand, as shown in FIG. 10, the data bus 1020 may be configured to transmit or receive data to the compensator 420 in different paths corresponding to the first and second connection portions PDC1 and PDC2, respectively .

On the other hand, the control printed circuit board (CPCB) or the controller 140 may further include a separate memory. Further, a timing controller may be further included.

11, when the power-on signal is generated, the organic light emitting diode display 100 according to the present exemplary embodiment includes a main power management circuit 850, The driving voltage VDD is applied to the control printed circuit board CPCB from the controller circuit board CPCB to start the controller booting period CBP for activating the components of the control printed circuit board CPCB.

The controller 140, the power management integrated circuit 830 and the first and second memory units 810 and 820 on the control printed circuit board CPCB in the controller booting period CBP respond to the applied driving voltage VDD .

The controller 140 to which the driving voltage VDD is applied starts the controller booting period CBP. The controller boot interval (CBP) may include a firmware boot interval (FWP) and a boot setting interval (BCP).

In the firmware boot interval FWP, the MCU 1010 of the controller 140 may load the pre-designated firmware to perform firmware boot (FW boot). After the firmware boot interval FWP, the MCU 1010 may load controller parameters stored in advance in the boot setting interval BCP for the components in the controller 140. That is, the component in the controller 140 according to the set value specified by the controller parameter.

At this time, the firmware and controller parameters may be stored in a non-volatile memory or the like separately provided in the control printed circuit board (CPCB) or the controller 140. [

For example, the firmware and controller parameters may be pre-stored in a controller 140 or a ROM or EEPROM mounted on a control printed circuit board (CPCB).

The controller boot interval (CBP) may further include a set margin interval (SMP). That is, the controller 140 does not apply the panel drive voltage EVDD to the display panel 110 immediately after completing the firmware boot operation and the setting value application operation, and outputs the panel drive voltage EVDD after the set margin interval SMP, It is possible to control the power management integrated circuit 830 to be applied to the display panel 110. [ The Set Margin Period (SMP) is not necessarily a time for the Controller Boot Interval (CBP), but is the time period specified for the subsequent addition of various initial operations of the controller.

Here, for example, the firmware boot interval (FWP) and the boot setting interval (BCP) may take 141 ms and 184 ms, respectively. Assuming that the set margin interval (SMP) is set to 500 ms, the controller boot interval (CBP) takes a total of 825 ms.

After the controller booting period CBP, the controller 140 controls the power management integrated circuit 830 so that the panel driving voltage EVDD applied from the main power management circuit 850 is applied to the display panel 110 Start the panel sensing interval (PSP).

The controller 140 senses the characteristic value of the driving transistor DRT in each sub pixel disposed on the display panel 110 immediately after the panel driving voltage EVDD is applied to the display panel 110 in the panel sensing period PSP And may be configured to perform an on-sensing process. However, as shown in FIG. 11, the bunt sensing process may be performed on the display panel 110 before performing the on-sensing process.

Burnt sensing is a process of detecting a burst phenomenon in which a display panel is burned due to a reason such as a power failure being normally supplied to a crack or a panel of a panel, and it is a process of outputting an error detection signal indicating information on abnormality of the panel. The error detection signal is output to the main power management circuit 850 to prevent the panel bunting phenomenon.

For example, the controller 140 or the power management integrated circuit 410 may display the threshold voltage and / or the mobility of the driving transistor DRT in each sub-pixel SP, On the basis of the sensing result of the current by the turn-on level gate voltage (VGH) and / or the turn-off level gate voltage (VGL) applied to the panel (110) 850). ≪ / RTI > The main power management circuit 850 can interrupt the supply of the power source EVDD to be applied to the display panel 110 when the error detection signal is applied. It is possible to prevent a panel bunting phenomenon in which the display panel 110 is burnt by the interruption of the power supply.

The reason for performing the bunt sensing process before the on-sensing process is that the bunt phenomenon can be further intensified by the on-sensing process. In this example, it is assumed that the burst sensing interval (BSP) required for the burst sensing process is 442 ms.

After performing the bunt sensing process, the compensation unit 420 of the controller 140 performs an on-sensing process. As described above, in the on-sensing process, the compensating unit 420 compensates the sensing data SDn sensing characteristic values of the driving transistor DRT for a plurality of sub-pixels on the selected gate line GLn among the plurality of gate lines, . CPVn for the sensing data SDn using the previously transmitted initial compensation data ICDn from the first memory unit 810 and supplies the calculated compensation value CPVn to the data bus 1020. [ To the second connection unit PDC2.

If one reference voltage line RVL is arranged for each subpixel column and one pixel is composed of four subpixels (red subpixel, white subpixel, green subpixel, and blue subpixel) As shown in the figure, the compensator 420 has to perform four sensing and data transfer processes corresponding to the number of subpixels for the selected gate line GLn.

That is, the compensation value calculation process is performed four times for each of the selected gate lines GLn. In order to calculate the compensation value CPVn for all the subpixels of the selected gate line GLn when the time SSP for applying the sensing data SDn to each subpixel and calculating the compensation value CPVn is 400 mu sec, The time (ST) required is SSP * 4 = 1600 sec.

The second connection unit PDC2 receiving the compensation value CPVn for the selected gate line GLn transfers the transferred compensation value CPVn to the second memory unit 820 and stores the compensation value CPVn. However, data transfer between the second connection unit PDC2 and the second memory unit 820 is not included in the time of the on-sensing process because it is a separate operation from the compensation unit 420. [

On the other hand, when the first memory unit 810 has two first memories, each of the two first memories has a data transfer rate of up to 215 MB / sec, and initial compensation data corresponding to the next gate line GLn + The time RT1 required for the compensating unit 420 to receive the initial compensation data ICDn + 1 from the first memory unit 810 is approximately 3000 μsec, assuming that the data amount of the ICDn + ICDn + 1 is 128 KB.

That is, the time RT1 required for the compensation unit 420 to read the initial compensation data ICDn + 1 from the first memory unit 810 indicates that the compensation unit 420 determines the time Is longer than the time (ST) required for calculating the compensation value (CPVn) for the subpixel. However, the compensating unit 420 may select the sub-pixel of the next selected gate line GLn + 1 from the first memory unit 810 while calculating the compensation value CPVn for the plurality of subpixels on the selected gate line GLn. And receives initial compensation data (ICDn + 1) for the pixel. That is, the time RT1 required to receive the initial compensation data ICDn + 1 is overlapped with the time ST for calculating the compensation value CPVn. Therefore, the time for performing the on-sensing process (OSP) can be greatly reduced.

Here, the compensation unit 420 may receive the initial compensation data ICD1 for the first gate line GL1 before the on-sensing process period, the set margin period SMP, or the bunt sensing period BSP. Further, although not shown, the first memory unit 810 may further store a compensation unit parameter for applying the preset value to the compensation unit 420, and the compensation unit parameter may also be stored in the setting margin interval (SMP) And may be transmitted from the first memory unit 810 to the compensation unit 420 in the interval BSP.

12 conceptually illustrates a data transmission path between the compensation unit 420 and the memory unit 430 in performing the on-sensing process of the organic light emitting diode display 100 according to other embodiments.

9, the compensating unit 420 may compare the data transfer path between the compensating unit 420 and the memory unit 430 according to FIG. 12 from the first memory unit 810 to the gate line GL unit 12, the entire initial compensation data ICD is transferred from the first memory unit 810 to the second memory unit 820 under the control of the memory control unit 1210 . The initial compensation data ICD stored in the second memory unit 820 is transferred to the compensation unit 420 in a predetermined compensation unit (a unit corresponding to the gate line GL in this case).

Here, the memory control unit 1210 may be included in the MCU 1310 shown in FIG. 13 below.

12 shows that the initial compensation data ICD is directly transferred from the first memory unit 810 to the second memory unit 820 in order to explain the concept of the data transmission path, The initial compensation data (ICD) to be transmitted may be configured to be transmitted to the second memory unit 820 through the controller 140 as shown in FIG.

In the on-sensing process described with reference to FIGS. 9 to 11, while the compensating unit 420 senses the characteristic value of the driving transistor DRT with respect to the subpixel of the gate line GLn and calculates the compensation value CPVn, By allowing the initial compensation data (ICDn + 1) corresponding to the line GLn + 1 to be transmitted, the time to perform the on-sensing process is reduced. That is, after the power-on signal is generated, the time until the first image is displayed on the display panel 110 is reduced. Here, the operation performed until the first image is displayed on the display panel 110 after the power-on signal is generated is referred to as an on sequence, and the time required for the on sequence is determined by the user response of the OLED display 100 Time is called.

The time RT1 at which the initial compensation data ICDn + 1 is transferred from the first memory unit 810 to the compensation unit 420 is obtained by the compensation unit 420 sensing the characteristic value of the driving transistor DRT, CPVn) is calculated. Therefore, the compensation unit 420 must wait for the waiting time (WT = RT - ST) until the initial compensation data (ICDn + 1) is transmitted after calculating the compensation value.

In particular, if one pixel is composed of three subpixels (red subpixel, green subpixel, and blue subpixel), the time ST for calculating the compensation value CPVn becomes shorter, WT) becomes longer.

The waiting time WT is an unnecessary time in the operation of the compensator 420 and increases the length of the on-sensing process interval OSP by accumulating the number of gate lines GLn (resolution) of the display panel 110 . Therefore, the waiting time (WT) should be removed as much as possible in the on-sensing process period (OSP).

12, the entire initial compensation data (ICD) stored in the first memory unit 810 is transferred to the second memory unit 820 and stored. The compensation unit 420 is configured to receive the initial compensation data ICDn from the second memory unit 820 having a higher data transfer rate than the first memory unit 810 in a predetermined compensation unit.

The period ST during which the compensation unit 420 performs the sensing and compensation value operation for a plurality of subpixels on the selected gate line GLn is the same as in FIG. Therefore, during the time ST for calculating the sensing and compensation values, the compensating unit 420 compensates the initial compensation data for the subpixel of the next selected gate line GLn + 1 from the second memory unit 820, (ICDn + 1). (RT2 < ST) is shorter than the time (ST2) for calculating the compensation value, the time RT2 for applying the initial compensation data (ICDn + 1) to the next selected gate line GLn + Can be removed.

Assuming that the second memory unit 820 is composed of at least one DDR SDRAM as described above, the compensating unit 420 compensates the initial compensation of the unit corresponding to the gate line GL from the second memory unit 820 The time RT2 for receiving the data ICDn may be shorter than the time SSP for sensing and compensating for one subpixel (red subpixel in Fig. 14) (RT2 < SSP).

However, the entire initial compensation data transfer time (ICDT) for transferring the entire initial compensation data (ICD) from the first memory unit 810 to the second memory unit 820 may further occur. However, if the added total initial compensation data transfer time (ICDT) is shorter than the waiting time WT * gate line GLn number (resolution) in FIG. 11, the on-sensing process interval OSP can be reduced as a result . That is, after the power-on signal is generated, the image can be displayed faster.

A control boot interval CBP or a burst sensing interval BSP may be used as a starting point for transmitting the initial compensation data ICD from the first memory unit 810 to the second memory unit 820, ), The on-sensing process interval (OSP) can be further reduced.

13 is a diagram specifically illustrating a data transmission path between the controller 140 and the memory unit 430 during the on-sensing process of the organic light emitting diode display 100 according to the other embodiments. FIG. FIG. 5 is a timing chart showing an initial driving process of the organic light emitting diode display 100 according to the examples.

13, the configuration of the control printed circuit board (CPCB) or the controller 140 is the same as that shown in Fig. 10, and thus will not be described here.

13, the first memory unit 810 is controlled by the memory control unit 1210 in accordance with the data transfer path between the controller 140 and the memory unit 430, The entire initial compensation data ICD is transmitted without transmitting the initial compensation data ICDn in units corresponding to the gate line GL to the first connection portion PDC1. Here, the memory controller 1210 is assumed to be included in the MCU 1310 and is not shown separately.

On the other hand, under the control of the MCU 1310, the first connection part PDC1 transfers the applied initial compensation data ICD to the second connection part PDC2 via the data bus 1020, and the second connection part PDC2 And transfers the initial compensation data (ICD) back to the second memory 820 for storage.

14, the first memory unit 810 initializes the initial compensation data ICD to the second memory unit 820 via the controller 140 in the boot setting period (BCP) after the firmware booting period FWP It begins to transmit. This is because the time for transmitting the initial compensation data ICD from the first memory unit 810 to the second memory unit 820 is overlapped with the control boot interval CBP and the bunt sensing interval BSP , And to reduce the on-sensing process interval (OSP).

If the compensation parameter LParam for initial setting of the compensation unit 420 is further stored in the first memory unit 810, the compensating unit parameter LParam is supplied to the compensation unit 420 before the initial compensation data ICD, Lt; / RTI &gt;

11, the initial compensation data ICDn is transferred in units corresponding to the gate lines. And the compensation part parameter (LParam) may be transmitted to the set margin section (SMP) or the bunt sensing section (BSP). Therefore, the compensating unit parameter LParam is not separately shown because the transmission time does not affect the length of the on-sensing process interval (OSP).

However, in the embodiment of FIG. 14 in which the entire initial compensation data ICDn is transmitted, the transmission time LPT of the compensating part parameter LParam transmitted prior to the initial compensation data ICDn is shorter than the length of the on- . &Lt; / RTI &gt; Therefore, it is preferable that the time of the compensation part parameter (LParam) is considered together, and in FIG. 14, it is explicitly indicated that the compensation part parameter (LParam) is transferred to the second memory part (820) before the initial compensation data Respectively.

However, the data amount of the compensation parameter (LParam) is generally very small compared to the total initial compensation data (ICDn). For example, the data amount of the compensation sub-parameter (LParam) may have a data amount of 12 times the initial compensation data (ICDn) for the subpixel of the specific gate line GLn. Considering the UHD resolution with the number of gate lines GL of the display panel 110 of 2160, the amount of data of the compensating part parameter LParam does not greatly affect the length of the on-sensing processing part OSP.

The compensation section parameter LParam is transmitted when 184 ms is required in the boot setting interval BCP, the setting margin interval SMP is set to 500 ms, and the burst sensing interval BSP is 442 ms, as described in FIG. The compensating subparameter LParam is transferred to the second memory 820 at the beginning of the boot setting interval BCP if the compensating subparameter transmission time LPT is approximately 7.3 ms.

Meanwhile, the first memory 810 transmits the compensation initial parameter (LParam) according to the control of the memory controller 1210, and then continuously transmits the initial compensation data (ICDn) to the second memory 820.

Unlike in FIG. 11, in which the initial compensation data ICDn for a subpixel of a specific gate line GLn is transferred to the compensation unit 420, in FIG. 14, the first memory unit 810 stores the entire initial compensation data ICDn, To the second memory unit 820, so that the entire initial compensation data transmission interval (ICDT) is not short.

14, the total initial compensation data transfer time (ICDT) may be longer than the sum of the boot setting interval (BCP), the set margin interval (SMP), and the burst sensing interval (BSP). BCP + SMP + BSP))

In this case, after the entire initial compensation data ICD is stored in the second memory unit 820, the compensation unit 420 reads the initial compensation data ICDn (ICDn) for the specific gate line GLn from the second memory unit 820, ), The time until the panel driving is delayed.

In particular, when the lengths of the set margin section (SMP) and the bun sensing section (BSP) are shortened or omitted, the panel initialization delay time due to the entire initial compensation data transmission time (ICDT) becomes larger.

In order to reduce the panel drive delay, the compensating unit 420 firstly supplies the initial compensation data ICD to the second memory unit 820 while the entire initial compensation data ICD is transferred from the first memory unit 810 to the second memory unit 820 May be configured to receive the stored initial compensation data (ICD) and perform the on-sensing process.

As described above, the compensating unit parameter LParam can be transferred to the second memory unit 820 at the beginning of the boot setting period (BCP), and subsequently the entire initial compensation data (ICD) Lt; RTI ID = 0.0 &gt; 820 &lt; / RTI &gt; Therefore, some initial compensation data (ICD) is already stored at the time when the boot setting period (BCP) ends and the compensating unit 420 receives the initial compensation data (ICD) stored in the second memory unit 820, - The sensing process can be started.

The initial compensation data ICD transmitted from the first memory unit 810 is transferred to the second memory unit 820 and the initial compensation data ICD already stored in the second memory unit 820 is re- An error may occur due to overlapping of paths on the data bus 1020 in the controller 140 or an initial compensation data ICDn for a specific gate line GLn may be supplied to the compensating unit 420 It may happen that the transmission can not be performed. Also, it may happen that the compensation value CPVn calculated in the compensation unit 420 can not be stored in the second memory unit 820. [

14, the MCU 1310 of the controller 140 receives the initial compensation data ICDn for the specific gate line GLn transmitted from the second memory unit 820 on the data bus 1020 The data transmission path to the compensation unit 420 is controlled to be transmitted through the path corresponding to the first connection unit PDC1 instead of the path corresponding to the second connection unit PDC2, Delay can be prevented.

14, the compensating unit 420 selects the next selected gate line GLn + 1 from the second memory unit 820 while calculating the compensation value CPVn for the plurality of subpixels on the selected gate line GLn, (ICDn + 1) for the subpixel of the subpixel. That is, the time (RT2) required to receive the initial compensation data (ICDn + 1) is overlapped with the time (ST) for calculating the compensation value (CPVn). Therefore, the time for performing the on-sensing process (OSP) can be reduced.

In Fig. 14, the second connection portion PDC2 is shown as a single component for convenience of explanation. However, the second connection unit PDC2 is generally configured to enable parallel data communication with a plurality of second memories provided in the second memory unit 820. [ The initial compensation data ICD and the initial compensation data ICDn for the specific gate line GLn and the compensation value CPVn calculated by the compensator 420 are simultaneously input and output to the second connection part PDC2, There is no failure in data transmission.

The second memory unit 820 receives the initial compensation data ICDn for the specific gate line GLn by the compensation unit 420 while receiving the entire initial compensation data ICD from the first memory unit 810, , And receives and stores the compensation value CPVn calculated by the compensation unit 420. [

In this case, when the compensation value CPVn calculated in the compensation unit 420 and the initial compensation data ICDn for the specific gate line GLn are set to be stored in the same second memory in the second memory unit 820, A storage time WRT may be added to the on-sensing process interval OSP.

However, since the data amount of the compensation value CPVn is very small, the influence of the compensation value storage time WRT on the on-sensing process interval OSP is negligible. Also, when the compensation value CPVn and the initial compensation data ICDn are stored in a second memory different from each other, the compensation value storage time WRT does not affect the on-sensing process interval OSP.

As a result, the entire initial compensation data transfer time (ICDT) does not affect the on-sensing process interval (OSP) and panel drive delay does not occur. Accordingly, it is possible to reduce the on-sensing process interval (OSP) and to output the image by driving the panel within a short time after the power-on signal is applied to the OLED display 100, have.

In other words, according to the generation of the power-on signal, the initial compensation data ICD stored in the first memory unit 810 is supplied to the first connection unit PDC1, the data bus 1020 and the second connection unit PDC2 via the first connection unit PDC1, 2 memory unit 820 and the initial compensation data ICDn stored in the second memory unit 820 is output to the compensation unit 420. [

While the compensation unit 420 calculates the compensation value CPVn for the plurality of subpixels on the selected gate line GLn, the compensation unit 420 selects the next selected gate line GLn + 1 from the first memory unit 810, The first embodiment for receiving the initial compensation data ICDn + 1 for the subpixel and the entire initial compensation data ICD stored in the first memory 810 are transferred to and stored in the second memory 820, The compensation unit 420 has separately described the second embodiment in which the initial compensation data ICDn + 1 for the subpixel of the next selected gate line GLn + 1 is read from the second memory unit 820 .

However, the organic light emitting diode display according to the present invention can be configured to use both the first and second embodiments. For example, the firmware loaded into the MCUs 1010 and 1310 including the memory control unit 1210 may be stored with a flag such that either the first embodiment or the second embodiment is selected. If the flag stored in the firmware is a first value, the MCUs 1010 and 1310 may perform an on-sensing process according to the second embodiment. If the flag is a second value, the MCUs 1010 and 1310 may perform an on-sensing process according to the first embodiment.

And even if the flag is not stored, one of the first embodiment or the second embodiment can be preset to be selected. For example, by default, the on-sensing process according to the second embodiment can be set to be performed.

15 shows a method of driving the organic light emitting display according to the present embodiments.

The driving method of the organic light emitting display shown in FIG. 15 will be described with reference to an initial driving process of the organic light emitting display shown in FIG. 11. First, a power on signal is generated (S150). When the driving voltage VDD is applied from the main power management circuit 850 to the control printed circuit board CPCB in response to the generated power-on signal, the MCU (not shown) of the controller 140 of the control printed circuit board CPCB 1010 loads the previously stored firmware and performs FW boot (S151).

The MCU 1010 that has completed the firmware boot (FW Boot) performs a boot setting operation to apply a setting value according to a predetermined controller parameter to a component in the controller 140 (S152).

Thereafter, the MCU 1010 determines whether the panel driving voltage EVDD is applied through the power management integrated circuit 830 mounted on the control printed circuit board CPCB (S153).

If it is determined that the panel driving voltage EVDD is applied, the compensating unit 420 of the controller 140 selects the gate line GLn to be compensated among the plurality of gate lines GL of the display panel 110 And receives initial compensation data ICDn corresponding to the selected gate line GLn from the first memory unit 810 (S154).

At this time, the compensating unit 420 may first receive the compensating unit parameter LParam for applying the set value to the compensating unit 420 before the panel driving voltage EVDD is applied. Also, in the case of the initial compensation data ICD1 corresponding to the gate line (for example, GL1) to be initially selected, it may be received before the panel drive voltage EVDD is applied.

The compensation unit 420 calculates the compensation value CPVn for the subpixel of the selected gate line GLn using the sensing data applied from the sensing unit 410 and the applied initial compensation data ICDn, From the first memory unit 810, initial compensation data (ICDn + 1) corresponding to the selected gate line GLn + 1 (S155). That is, the length of the on-sensing process interval (OSP) is reduced by simultaneously performing the compensation value (CPVn) operation and the next initial compensation data (ICDn + 1) reception.

The compensation unit 420 determines whether the compensation value (CPVn) calculation for all the subpixels of the display panel 110 is completed. That is, the on-sensing process is completed (S166).

If it is determined that the on-sensing process is not completed, the compensation unit 420 receives initial compensation data corresponding to the next selected gate line from the first memory unit 810 (S155). However, if it is determined that the on-sensing process is completed, the display panel is driven (S157).

16 shows a method of driving an organic light emitting display according to another embodiment.

The driving method of the organic light emitting display shown in FIG. 16 will be described with reference to an initial driving process of the organic light emitting display shown in FIG. 14. Referring to FIG. 15, a power on signal is first generated (S160). When the driving voltage VDD is applied from the main power management circuit 850 to the control printed circuit board CPCB in response to the generated power-on signal, the MCU 1310 loads the previously stored firmware And performs firmware boot (FW Boot) (S161).

The MCU 1310 which has completed the firmware boot (FW Boot) performs a boot setting operation to apply a set value according to a predetermined controller parameter to a component in the controller 140. However, unlike FIG. 15, the boot setting operation is performed in the embodiment of FIG. 16, and the entire initial compensation data (ICD) stored in the first memory unit 810 under the control of the MCU 1310 is supplied to the second memory unit 820 (S162). At this time, the first memory unit 810 first transmits the compensation parameter (LParam) to the second memory unit 820 before the entire initial compensation data (ICD), and then transmits the entire initial compensation data (ICD) .

The MCU 1010 controls the power consumption of the panel 1010 through the power management integrated circuit 830 mounted on the control printed circuit board CPCB even if the entire initial compensation data ICD is transferred to the second memory unit 820, It is determined whether or not the drive voltage EVDD is applied (S163).

When it is determined that the panel driving voltage EVDD is applied, the compensating unit 420 of the controller 140 selects the gate line GLn to be compensated among the plurality of gate lines GL of the display panel 110 And receives initial compensation data ICDn corresponding to the selected gate line GLn from the second memory unit 820 (S164).

The compensation unit 420 may first receive the compensation parameter LParam for applying the preset value to the compensation unit 420 from the second memory unit 820 before the panel drive voltage EVDD is applied have. Also, in the case of the initial compensation data ICD1 corresponding to the gate line (for example, GL1) to be initially selected, it may be received before the panel drive voltage EVDD is applied.

The compensation unit 420 compensates the compensation value for the subpixel of the selected gate line GLn by using the sensing data applied from the sensing unit 410 and the initial compensation data ICDn received from the second memory unit 820 And simultaneously receives the initial compensation data ICDn + 1 corresponding to the next selected gate line GLn + 1 from the second memory unit 820 at step S165.

The compensation unit 420 determines whether the compensation value (CPVn) calculation for all the subpixels of the display panel 110 is completed. That is, the on-sensing process is completed (S166).

If it is determined that the on-sensing process is not completed, the compensation unit 420 receives again the initial compensation data corresponding to the next selected gate line from the second memory unit 820 (S165) Is determined to be completed, the display panel is driven (S167).

The driving method of the OLED display 100 according to FIG. 16 is different from that of FIG. 15 in that the process of transmitting the entire initial compensation data ICD stored in the first memory unit 810 to the second memory unit 820 is added However, due to the difference in data transmission speed between the first memory unit 810 and the second memory unit 820, the time of the entire on-sensing process interval (OSP) can be reduced.

Also, the added process is overlapped with the boot setting step, thereby minimizing the time increase of the on-sensing process interval (OSP) due to the added process. In addition, the compensation unit 420 may be provided in the second memory unit 820 in a state where some initial compensation data (ICD) is stored before the entire initial compensation data (ICD) is stored in the second memory unit 820 Since the compensation value calculation can be performed using the stored initial compensation data ICD, the on-sensing process interval &lt; RTI ID = 0.0 &gt; (OSP) time can be prevented from occurring.

As a result, the compensation unit 420 can receive the initial compensation data ICDn from the second memory unit 820 capable of high-speed data transfer, thereby reducing the time of the on-sensing process interval OSP, It is possible to advance the driving time of the motor 110. That is, the user responsiveness of the OLED display 100 can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: organic light emitting diode display 410:
110: display panel 420:
120: Data driver 430: Memory part
130: Gate driver 810: First memory part
140: controller 820: second memory unit

Claims (17)

A display panel on which a plurality of subpixels are arranged;
A sensing unit for measuring a sensing voltage from the display panel and outputting sensing data for at least one of the plurality of subpixels;
A compensation unit receiving the initial compensation data and the sensing data and calculating a compensation value for the at least one subpixel;
A first memory unit for storing the initial compensation data in advance; And
And a second memory unit having a transmission rate different from that of the first memory unit,
When a power-on signal is generated,
The initial compensation data is transferred from the first memory unit to the second memory unit under the control of the controller,
And the compensation unit reads the initial compensation data from the second memory unit. The method according to claim 1,
Wherein the second memory unit comprises:
Wherein the first memory unit has a higher transmission speed than the first memory unit. The method according to claim 1,
The controller comprising:
When the driving voltage is applied, transfers the entire initial compensation data stored in the first memory unit to the second memory unit,
And transmits the initial compensation data stored in the second memory unit to the compensation unit when a panel driving voltage is applied. The method of claim 3,
Wherein the compensation unit comprises:
And receives the initial compensation data for the selected subpixel while receiving the sensing data for a selected one of the plurality of subpixels according to a predetermined order and calculating the compensation value. 5. The method of claim 4,
Before the initial compensation data is transferred from the first memory unit to the second memory unit,
The compensating sub-parameter is transferred from the first memory unit to the second memory unit,
Wherein the compensation unit, before reading the initial compensation data from the second memory unit,
And the compensating unit parameter is read out from the second memory unit. The method of claim 3,
The controller comprising:
Wherein the initialization data is loaded from the first memory unit to the second memory unit after the booting of the firmware is performed when the drive voltage is applied, Organic light emitting display. The method of claim 3,
The controller comprising:
When the panel driving voltage is applied, before receiving the compensation data in the second memory unit rotor,
And outputs information about an abnormality of the display panel. The method according to claim 1,
The controller comprising:
When the driving voltage is applied, the firmware is booted,
When a panel driving voltage for driving the display panel is applied,
And the initial compensation data stored in the first memory unit is transferred to the compensation unit without passing through the second memory unit according to a preset flag value. The method according to claim 1,
The controller
A first connection unit for controlling data transfer between the first memory unit and the controller;
A second connection unit for controlling data transfer between the second memory unit and the controller;
A data bus that is a data transmission path inside the controller; And
And an MCU controlling the compensation unit, the first and second connection units, and the data bus. The method according to claim 1,
The controller
And transmits the computed compensation value to the second memory unit and stores the compensation value. A display panel on which a plurality of subpixels are arranged;
A driving circuit for measuring a sensing voltage from the display panel and outputting a sensing value;
A controller for generating a compensation value based on the sensing value;
A first memory unit for storing an initial compensation value in advance; And
And a second memory unit having a transmission rate different from that of the first memory unit,
When a power-on signal is generated, an image is displayed after the on sequence has been performed,
During the on sequence,
The initial compensation value is transferred from the first memory unit to the second memory unit,
The controller reads the initial compensation value from the second memory,
Wherein the driving circuit measures a sensing voltage during a sensing drive period of the display panel to output a sensing value,
Wherein the controller generates a compensation value based on the sensing value output from the driving circuit and the initial compensation value read from the second memory. 12. The method of claim 11,
Each of the plurality of sub-
An organic light emitting diode,
A driving transistor for driving the organic light emitting diode,
A switching transistor electrically connected between the first node of the driving transistor and the data line,
And a capacitor electrically connected between a first node and a second node of the driving transistor,
The sensing voltage,
Wherein the voltage of the sensing line is electrically connected to the first node or the second node of the driving transistor. 12. The method of claim 11,
During the sensing drive period of the display panel,
A data voltage is applied to a data line corresponding to at least one subpixel,
Thereafter, when the voltage of the sensing line, which is a signal line different from the data line, is varied,
Wherein the driving circuit measures the voltage of the sensing line as the sensing voltage. A first memory unit for storing initial compensation data in advance;
A second memory unit having a transfer rate different from that of the first memory unit;
A first connection unit connected to an output end of the first memory unit;
A second connection unit connected to an output end of the second memory unit; And
And a data bus for connection between the first connection part and the second connection part,
As the power-on signal is generated,
Initial compensation data stored in advance in the first memory unit is transferred to the second memory unit via the first connection unit, the data bus, and the second connection unit,
And the initial compensation data is output to the compensation processor in the second memory unit. A sensing unit for measuring a sensing voltage from the display panel and outputting sensing data for at least one subpixel among the plurality of subpixels, receiving initial compensation data and the sensing data, And a compensation unit for calculating a compensation value for the at least one subpixel, a first memory unit storing the initial compensation data in advance, and a second memory unit having a transfer rate different from that of the first memory unit A driving method of an organic light emitting display device,
When the power-on signal is generated, transferring the initial compensation data from the first memory unit to the second memory unit under the control of the controller; And
And the compensation unit reads the initial compensation data from the second memory unit. 16. The method of claim 15,
Wherein the step of transmitting to the second memory unit comprises:
Wherein the initial compensation data stored in the first memory unit is transmitted to the second memory unit when a driving voltage is applied. 16. The method of claim 15,
The step of reading comprises:
And when the panel driving voltage is applied, the initial compensation data stored in the second memory unit is transferred to the compensation unit.

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