KR20190004952A - Solar cell and method for manufacturing the same - Google Patents

Abstract

According to an embodiment of the present invention, a solar cell capable of increasing productivity comprises: a semiconductor substrate; a first conductive region positioned on the semiconductor substrate and formed of a first compound layer of metal and nonmetal to selectively extract a first carrier; a first insulating film positioned on the first conductive region and having a first opening; and a first electrode penetrating the first opening to be electrically connected to the first conductive region.

Description

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell and a manufacturing method thereof, and more particularly, to a solar cell including a semiconductor substrate and a compound layer and a manufacturing method thereof.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. However, solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize a solar cell, it is required to overcome a low efficiency and a low productivity, and a solar cell capable of maximizing the efficiency and productivity of the solar cell is required.

For example, in a conventional solar cell manufactured by doping a semiconductor substrate with a dopant, the doping process and the like are very complicated, and the interfacial characteristics of the semiconductor substrate are degraded, resulting in poor passivation characteristics. To prevent this, a solar cell using a compound layer as a conductive type region has been proposed. In general, such a solar cell includes a transparent conductive film for reducing horizontal resistance and preventing reflection. However, such a transparent conductive film is expensive in terms of material cost and process cost, and has a problem of deteriorating various characteristics and efficiency of a solar cell.

The present invention is to provide a solar cell having excellent characteristics and efficiency, a beautiful appearance, and improved productivity, and a method of manufacturing the same.

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A first conductive type region formed on the semiconductor substrate and composed of a first compound layer of a metal and a non-metal to selectively extract a first carrier; A first insulating layer located above the first conductive type region and having a first opening; And a first electrode electrically connected to the first conductive type region through the first opening.

A method of manufacturing a solar cell according to an embodiment of the present invention includes: forming a first conductive type region on a semiconductor substrate, the first conductive type region including a first compound layer of a metal and a non-metal and selectively extracting a first carrier; Forming a first insulating layer over the first conductive type region and having a first opening; And forming a first electrode electrically connected to the first conductive type region through the first opening.

According to this embodiment, in the solar cell having the conductive type region composed of the compound layer, the insulating film through which the electrode penetrates is applied as the anti-reflection film and the transparent conductive film is removed, thereby effectively preventing the problems caused by the transparent conductive film can do. That is, it is possible to prevent problems such as free carrier absorption, improve the characteristics and efficiency of the solar cell, freely change the color of the solar cell, and reduce the manufacturing cost. Therefore, the characteristics and efficiency of the solar cell can be improved, the appearance can be improved, and the manufacturing productivity of the solar cell can be improved.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.
2 is a front plan view of the solar cell shown in FIG.
FIG. 3A is a band diagram of a semiconductor substrate, a second passivation layer, and a second conductive type region in a solar cell according to an embodiment of the present invention. FIG. 3B is a band diagram of a semiconductor substrate, , A first passivation layer, and a first conductive type region.
4 is a graph showing the resistance of the conductive type region of the solar cell according to Examples 1 and 2 and Comparative Examples 1 and 2 measured.
5 is a cross-sectional view of a solar cell according to a modification of the present invention.
6A to 6E are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
7 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, the terms "first "," second ", and the like are used for distinguishing each other, and the present invention is not limited to these terms.

Hereinafter, a solar cell and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.

1, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10, conductive regions 20 and 30 located on the semiconductor substrate 10 and composed of metal and non-metal compound layers, An insulating film 22 and 32 disposed on the conductive regions 20 and 30 and having openings 22a and 32a and an insulating film 22 electrically connected to the conductive regions 20 and 30 through the openings 22a and 32a, And electrodes 42, By the way, the terms of the conductive type regions 20 and 30 can be used not only in the case of including a dopant but also in the case of selectively extracting a carrier having a constant polarity. In practice, the conductive regions 20 and 30 composed of the compound described above do not include a dopant, but refer to a case where a carrier is selectively extracted.

At this time, the conductive regions 20 and 30 include the first conductive type region 20 and the second conductive type region 30, and the electrodes 42 and 44 are electrically connected to the first conductive type region 20 And a second electrode (44) electrically connected to the second conductive type region (30), wherein the insulating film (22) comprises a first electrode (42) And a second insulating layer 32 located on the insulating layer 22 and the second conductive type region 30. The solar cell 100 may further include a passivation layer 52, 54.

The semiconductor substrate 10 may include a base region 110 having a first or second conductivity type including a first or a second conductivity type dopant at a relatively low doping concentration. The base region 110 may be comprised of a single crystalline semiconductor (e.g., a single single crystal or polycrystalline semiconductor, such as single crystal or polycrystalline silicon, particularly monocrystalline silicon) comprising an n-type or p-type dopant. The base region 110 having a high degree of crystallinity and having few defects or the solar cell 100 based on the semiconductor substrate 10 has excellent electrical characteristics. In this embodiment, the semiconductor substrate 10 may include only the base region 110 having no doping region formed by additional doping or the like. As a result, the passivation property of the semiconductor substrate 10 due to the doped region can be prevented from deteriorating.

For example, in this embodiment, the base region 110 may be doped with an n-type dopant to have an n-type. If the base region 10 has the n-type conductivity, at least one of the first conductive type region 20 and the second conductive type region 30 can be easily formed and can be formed into a compound layer easily obtainable. Specific materials of the first conductivity type region 20 and the second conductivity type region 30 will be described later in detail.

An anti-reflection structure capable of minimizing reflection can be formed on the front surface and the rear surface of the semiconductor substrate 10. For example, a texturing structure having a concavo-convex shape in the form of a pyramid or the like may be provided as an antireflection structure. The texturing structure formed in the semiconductor substrate 10 may have a certain shape (e.g., a pyramid shape) having an outer surface formed along a specific crystal plane (e.g., (111) plane) of the semiconductor. If the surface roughness of the semiconductor substrate 10 is increased due to the unevenness formed on the front surface of the semiconductor substrate 10 by such texturing, the reflectance of light incident into the semiconductor substrate 10 can be reduced to minimize optical loss. However, the present invention is not limited thereto, and an antireflection structure may be formed on only one side of the semiconductor substrate 10, or an antireflection structure may not be formed on the front and rear surfaces of the semiconductor substrate 10.

The first passivation layer 52 may be formed on the front surface of the semiconductor substrate 10 (e.g., in contact with the first passivation layer 52). The first passivation layer 52 can improve the passivation property on the surface of the semiconductor substrate 10. [ And the first passivation layer 52 may act as a kind of barrier in electrons and holes. More specifically, the first passivation layer 52 prevents the second carrier from passing therethrough, and when the first carrier has a certain energy or more after being accumulated at a portion adjacent to the first passivation layer 52, the first passivation layer 52). At this time, the first carrier having energy above a certain level can easily pass through the first passivation layer 52 by the tunneling effect.

The first passivation layer 52 may be formed entirely on the front surface of the semiconductor substrate 10. Accordingly, it can be easily formed without additional patterning while having excellent passivation characteristics. And the first passivation layer 52 may be an undoped film that does not include a dopant.

The first passivation layer 52 may include, for example, an oxide, a nitride, a semiconductor, a conductive polymer, or the like. For example, the first passivation layer 52 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, intrinsic amorphous semiconductor, intrinsic polycrystalline semiconductor, and the like. In particular, the first passivation layer 52 may be comprised of a silicon oxide layer comprising silicon oxide. This is because the silicon oxide layer is a film which has excellent passivation characteristics and is susceptible to tunneling of the carrier. Such a silicon oxide layer may be formed by thermal oxidation or chemical oxidation. Alternatively, the first passivation layer 52 may comprise an intrinsic amorphous silicon (i-a-Si) layer. Then, since the first passivation layer 52 has similar characteristics including the same semiconductor material as the semiconductor substrate 10, the passivation characteristics can be improved more effectively. However, the present invention is not limited thereto. Accordingly, the first passivation layer 52 may be composed of an intrinsic amorphous silicon carbide (i-a-SiCx) layer or an intrinsic amorphous silicon oxide (i-a-SiOx) layer. According to this, although the effect due to the wide energy band gap can be improved, the passivation characteristic may be somewhat lower than in the case of including an intrinsic amorphous silicon (i-a-Si) layer.

The first conductive type region 20 is positioned (e.g., in contact) on the first passivation layer 52. At this time, the first conductive type region 20 may be formed entirely on the first passivation layer 52. Accordingly, the area of the first conductivity type region 20 having a sufficient area contributes to the photoelectric conversion can be maximized. However, the first passivation layer 52 is not an essential layer, and the first conductive type region 20 may be located in contact with the semiconductor substrate 10 without the first passivation layer 52.

In this embodiment, the first conductivity type region 20 is composed of a metal and a nonmetal compound and is composed of a first compound layer (for example, a first metal oxide layer) for extracting and collecting a first carrier. The first conductivity type region 20 may selectively extract and collect the first carrier and transmit the first carrier to the first electrode 42. This will be described in more detail later.

The thickness of the first passivation layer 52 may be equal to, less than, or greater than the thickness of the first conductivity type region 20. In this embodiment, the first conductive type region 20 may be formed of a first compound layer having an amorphous structure, and the amorphous structure may be formed and maintained when the amorphous structure has a thin thickness. Accordingly, the thickness of the first passivation layer 52 is not necessarily limited to the thickness of the first conductivity type region 20 because the first conductivity type region 20 has a thin thickness in this embodiment . For example, when the thickness of the first conductive type region 20 is minimized so that the first conductive type region 20 has a more stable amorphous structure, the thickness of the first conductive type region 20 may be equal to or greater than the thickness of the first passivation type layer 52 It can be smaller. As another example, when the thickness of the first passivation layer 52 is reduced to maximize the tunneling effect through the first passivation layer 52, the thickness of the first passivation layer 52 may be less than the thickness of the first passivation layer 52. [ May be less than the thickness.

Alternatively, the thickness of the first passivation layer 52 may be 10 nm or less, and the thickness of the first conductivity type region 20 may be 30 nm or less (for example, 10 nm or less). If the thickness of the first passivation layer 52 exceeds 10 nm, the tunneling does not smoothly occur and the solar cell 100 may not operate smoothly. If the thickness of the first conductivity type region 20 exceeds 30 nm, it may be difficult to have an amorphous structure and the carrier may not flow smoothly due to low electrical conductivity. At this time, if the first conductivity type region 20 has a thickness of 10 nm or less, the amorphous structure can be stably maintained.

For example, the first passivation layer 52 may have a thickness of 5 nm or less (more specifically, 2 nm or less, for example, 0.5 nm to 2 nm) in order to sufficiently realize the tunneling effect. If the thickness of the first passivation layer 52 is less than 0.5 nm, it may be difficult to form the first passivation layer 52 of desired quality. The first conductivity type region 20 may have a thickness of 1.5 nm or more (for example, 1.5 nm to 5 nm) so as to stably extract and collect the first carrier. However, the present invention is not limited thereto, and the thickness of the first passivation layer 52 and / or the first conductivity type region 20 may have various values.

A first insulating film 22 is formed on the first conductive type region 20. The first insulating layer 22 may include a first opening 22a through which the first electrode 42 passes. The first insulating film 22 will be described later in more detail after the first conductive type region 20 is described later.

The first electrode 42 is formed on the first conductive type region 20 and electrically connected to the first conductive type region 20 through the first opening 22a. For example, the first electrode 42 is formed only of an electrode layer having a pattern (that is, the first metal electrode layer 422), and an electrode layer having a pattern (i.e., the first metal electrode layer 422) (Not shown). So that light can be incident on a portion where the first electrode 42 is not formed.

At this time, the first metal electrode layer 422 constituting the first electrode 42 may be formed of a material having excellent electric conductivity. Thus, characteristics such as carrier collection efficiency and resistance reduction can be further improved. For example, the first metal electrode layer 422 may be composed of opaque or low-transparency metal having excellent electrical conductivity. Since the first metal electrode layer 422 is opaque or low in transparency, it may interfere with the incidence of light, so that the shading loss can be minimized. Accordingly, the first electrode 42 does not have a transparent electrode layer which is formed on the first conductive type region 20 as a whole. Accordingly, the structure of the first electrode 42 can be simplified.

The planar shape of the first electrode 42 or the first metal electrode layer 422 having a pattern will be described later in more detail with reference to FIG.

In this embodiment, the first electrode 42 may be formed after forming the first opening 22a. Therefore, no fire-through is required through the first insulating film 22 when the first electrode 42 is formed. The first electrode 42 is coated with a low temperature firing paste which can be fired by firing at a low temperature (400 占 폚 or less, more specifically 350 占 폚 or less, for example, 300 占 폚 or less, for example, 250 占 폚 or less) (For example, printing), and then heat-treated. Various materials known as low-temperature firing pastes can be used.

Hereinafter, an example of the planar shape of the first electrode 42 will be described in detail with reference to Figs. 1 and 2. Fig. 2 is a front plan view of the solar cell 100 shown in Fig.

Referring to FIG. 2, the first electrode 42 or the first metal electrode layer 422 may include a plurality of finger electrodes 42a spaced apart from each other with a predetermined pitch. Although the finger electrodes 42a are parallel to each other and parallel to the edge of the semiconductor substrate 10, the present invention is not limited thereto. The first electrode 42 may include a bus bar electrode 42b formed in a direction crossing (for example, orthogonal to) the finger electrodes 42a and connecting the finger electrodes 42a. Only one bus bar electrode 42b may be provided or a plurality of bus bar electrodes 42b may be provided with a larger pitch than the pitch of the finger electrodes 42a as shown in FIG. At this time, the width of the bus bar electrode 42b may be larger than the width of the finger electrode 42a, but the present invention is not limited thereto. Therefore, the width of the bus bar electrode 42b may be equal to or smaller than the width of the finger electrode 42a.

Referring again to FIG. 1, a second passivation layer 54 may be positioned (e.g., in contact) on the backside of the semiconductor substrate 10 and a second conductive type region 30 may be formed on the second passivation layer 54, (For example, contact). However, the second passivation layer 54 is not an essential layer, and the second conductive type region 30 may be located in contact with the semiconductor substrate 10 without the second passivation layer 54. And the second electrode 44 electrically connected to the second conductivity type region 30 may be positioned (e.g., in contact). The second electrode 44 may be composed of a second metal electrode layer 442.

In the present embodiment, the second conductivity type region 30 is formed by a second compound layer (for example, a second metal oxide, for example, a metal oxide), which is composed of a metal and a nonmetal compound and selectively extracts and collects a second carrier having an opposite polarity to the first carrier Layer). The second conductivity type region 30 may serve to selectively extract and collect the second carrier and to transfer the second carrier to the second electrode 44. This will be described in more detail later.

The second passivation layer 54 can improve the passivation property on the surface of the semiconductor substrate 10. [ When the second carrier has a certain energy or more after being accumulated in the portion adjacent to the second passivation layer 54, the second passivation layer 54 is not allowed to pass through the second passivation layer 54, Allowing them to pass. At this time, the second carrier having energy above a certain level can easily pass through the second passivation layer 54 by the tunneling effect.

The second insulating layer 32 having the second opening 32a is located on the second conductive type region 30 and the second metal electrode layer 442 of the second electrode 44 is disposed on the second opening 32a. (E. G., Contact) to the second conductivity type region 30 through the first conductive type region 30. For example, the second metal electrode layer 442 may have a predetermined pattern similar to the first metal electrode layer 422.

Except for the difference described above, except for the second passivation layer 54, the second conductivity type region 30, and the second electrode 44 are located on the backside of the semiconductor substrate 10, The first electrode 52, the first conductivity type region 20, and the first electrode 42, the description thereof can be applied as it is. At this time, the first passivation layer 52 and the second passivation layer 54 may have the same thickness, shape, material, or the like, and may have different thicknesses, shapes, and materials. The first metal electrode layer 422 and the second metal electrode layer 442 of the first electrode 42 may have the same shape and / or material and may have different shapes and / or materials. For example, the width, pitch, etc. of the finger electrode 42a and the bus bar electrode 42b of the first electrode 42 may be the same as the width, pitch, etc. of the finger electrode and the bus bar electrode of the second electrode 44 And can be different. Alternatively, the planar shapes of the first electrode 42 and the second electrode 44 may be different from each other, or the lamination structure of the first electrode 42 and the second electrode 44 may be different from each other. Various other variations are possible.

As described above, the first conductive type region 20 and the second conductive type region 30 have a work function in consideration of the electron affinity of the semiconductor substrate 10, And a first or second compound layer containing a compound capable of selectively extracting and collecting a second carrier (electron or hole). Accordingly, the first conductive type region 20 and the second conductive type region 30 do not contain a semiconductor material as such, and the dopant (i.e., the n type or the p type) And the like). However, in some cases, the first and second conductivity type regions 20 and 30 may further include inevitable impurities, hydrogen, or the like, or may include some dopants.

At this time, the first or second compound layer may have an amorphous structure. This is because if the compound layer or the metal oxide layer has a crystalline structure, the passivation property is significantly lowered and the efficiency of the solar cell 100 is greatly lowered. The exact reason for this is not known, but it can be confirmed experimentally. Although it is not clear, when the crystal structure is abundantly included, the optical absorption is greatly increased to cause the current loss, and the surface roughness of the compound layer (for example, the metal oxide layer) increases.

For example, at least the portion adjacent to the first or second passivation layer 52, 54 in the first conductive type region 20 and the second conductive type region 30 may be formed in such a manner that an amorphous portion having an amorphous structure has a crystalline structure And an amorphous portion formed wider than the crystalline portion. Particularly, in the case where at least the portion adjacent to the first or second passivation layer 52 or 54 in the first conductivity type region 20 and the second conductivity type region 30 has an amorphous structure as a whole, have. However, the present invention is not limited thereto.

The first and second conductivity type regions 20 and 30 composed of the first or second compound layer can prevent the recombination due to the dopant that may occur when the doped region is formed in the semiconductor substrate 10, have. In addition, the loss due to light absorption can be reduced as compared with the doped region or the doped film, and the short circuit current density can be improved. Thus, the efficiency of the solar cell 100 can be improved. Further, it can be manufactured by omitting a dopant doping process, a dopant activating process, and the like. In particular, since a high temperature process is not required, a process can be performed at a low temperature, thereby simplifying a manufacturing process and reducing a manufacturing cost. Therefore, the productivity of the solar cell 100 can be improved.

The first conductive type region 20 and the second conductive type region 30 will be described in more detail with reference to FIG.

3 (a) is a band diagram of the semiconductor substrate 10, the second passivation layer 54 and the second conductivity type region 30 in the solar cell 100 according to the embodiment of the present invention, and FIG. 3 (b) A band diagram of the semiconductor substrate 10, the first passivation layer 52, and the first conductivity type region 20 in the solar cell 100 according to the embodiment of the present invention. Here, as described above, the semiconductor substrate 10 may be configured as an n-type base region 110. [

Hereinafter, the first conductive type region 20 extracts holes and the second conductive type region 30 extracts electrons. The first conductivity type region 20 functions as an emitter region by extracting holes of opposite polarity from electrons which are the majority carriers of the n type base region 110 and the second conductivity type region 30 functions as an n- (Back electric field region) by extracting electrons which are majority carriers of the base region 110 of the light emitting element. According to this, the first conductivity type region 20, which is located on the front side of the semiconductor substrate 10 and functions as an emitter region for substantially photoelectric conversion, can effectively extract and collect holes having a relatively low moving speed. However, the present invention is not limited thereto. The second conductive type region 30 which is located on the rear surface of the semiconductor substrate 10 and is composed of the front electric field region for extracting electrons and the first conductive type region 20 located on the front surface of the semiconductor substrate 10, And an emitter region for extracting the holes.

More specifically, the first compound layer constituting the first conductive type region 20 capable of selectively extracting and collecting holes has a Fermi level lower than the fermi level of the semiconductor substrate 10, It is possible to have a work function capable of obtaining a high open-circuit voltage and a low resistance while preventing mal-synthesis of the work function based on the electron affinity of 4.5 eV of the substrate 10. For example, the work function of the first conductivity type region 20 may be 5.0 eV or more. If the above-mentioned work function is less than 5.0 eV, it may be difficult to selectively collect only holes except electrons.

When the first conductive type region 20 composed of the first compound layer having such a Fermi level and the work function is bonded to the semiconductor substrate 10 with the first passivation layer 52 interposed therebetween, The Fermi level of the semiconductor substrate 10 and the first conductivity type region 20 are aligned and bonded so as to have the same value. 3 (b), the holes in the electrical current path in the semiconductor substrate 10 can easily move as the current flows through the first conductive type region 20 when passing through the first passivation layer 52 . On the other hand, electrons in the semiconductor substrate 10 do not pass through the first passivation layer 52.

The second compound layer of the second conductive type region 30 capable of selectively collecting electrons has a Fermi level higher than the Fermi level of the semiconductor substrate 10 and has an electron affinity of 4.5 eV It is possible to have a work function capable of obtaining a high open-circuit voltage and a low resistance while preventing a malfunction of the work function. For example, the work function of the second conductivity type region 30 may be 4.5 eV or less. If the above-mentioned work function exceeds 4.5 eV, it may be difficult to selectively collect electrons.

When the second conductive type region 30 composed of the metal compound layer having the Fermi level and the work function is bonded to the semiconductor substrate 10 with the second passivation layer 54 therebetween, The Fermi level of the semiconductor substrate 10 and the second conductivity type region 30 are aligned and bonded so as to have the same value. Electrons in the conduction band in the semiconductor substrate 10 can easily move to the conduction band of the second conduction type region 30 when passing through the second passivation layer 54. [ On the other hand, holes in the semiconductor substrate 10 do not pass through the second passivation layer 54.

As the first compound layer that can be used as the first conductive type region 20 and the second compound layer that can be used as the second conductive type region 30, diffusion using oxygen vacancy A possible n-type oxide layer may be used. For example, each of the first compound layer and the second compound layer may be composed of a transition metal oxide. Here, the transition metal oxide having a work function of at least a certain level (for example, 5.0 eV or more as described above) in the n-type oxide layer constitutes the first compound layer and the work function of the n- (For example, 4.5 eV or more as described above) can constitute the second compound layer. By way of reference, the first and second compound layers are differentiated from a transparent conductive oxide in that they do not include indium, tin, and the like, and / or do not contain a substitutional dopant.

As one example, the first compound layer that can be used as the first conductive type region 20 includes a molybdenum oxide layer composed of molybdenum oxide (for example, MoO ₂ , MoO ₃ ), tungsten oxide (for example, WO ₃ ) A vanadium oxide layer composed of vanadium oxide (for example, V ₂ O ₅ ), a nickel oxide layer composed of nickel oxide (for example, NiO), copper containing copper oxide (for example, CuO) An oxide layer, a cobalt oxide layer containing cobalt oxide (for example, Co ₃ O ₄ ), a rhenium oxide layer composed of rhenium oxide, and the like. In particular, if the first conductive type region 20 includes a molybdenum oxide layer or a tungsten oxide layer, the effect of selectively collecting holes may be excellent.

As a second compound layer that can be used as the second conductivity type region 30, for example, the first compound 31 suitable for selectively extracting a second carrier (e.g., an electron) may be titanium oxide (For example, TiO ₂ and TiO ₂ ), a zinc oxide layer composed of zinc oxide (for example, ZnO), a niobium oxide layer composed of niobium oxide (for example, Nb ₂ O ₅ ), a vanadium oxide (For example, V ₂ O ₃ ), a cobalt oxide layer including a cobalt oxide (for example, CoO), a chromium oxide including chromium oxide (for example, Cr ₂ O ₃ ) Layer and the like. In particular, if the second conductivity type region 30 includes a titanium oxide layer, the effect of selectively collecting electrons can be excellent.

The work function of the metal oxide layer may be changed to some extent by the composition of the metal oxide, the crystal structure, etc. Therefore, the same material may be used as the first conductivity type region 20 depending on the work function, Type region 30 as shown in FIG.

For example, the energy bandgap of the first conductive type region 20 or the second conductive type region 30 is 2.8 eV or more (for example, 3.0 eV or more), more specifically 2.8 eV to 5 eV, 22, and 32, respectively. Within this range, the first or second conductivity type region 20, 30 can effectively extract and collect carriers selectively in this energy band gap.

In this embodiment, the first insulating layer 22 made of an insulating material or a dielectric material is positioned (for example, contact) on the first conductive type region 20 composed of the first compound layer (for example, a metal oxide layer) do. At this time, the first conductive type region 20 composed of the first compound layer has a resistance higher than that of the semiconductor layer which has been used as a conductive type region and has a higher transmittance than that. Accordingly, in this embodiment, the amount of light incident on the solar cell 100 can be increased while maintaining the electrical characteristics of the solar cell 100 by the first conductivity type region 20.

The first insulating layer 22 may include various insulating materials, for example, an insulating material having characteristics that can be easily removed by a laser. For example, the first insulating film 22 may be a single film or a laminated film including at least one of a silicon nitride film, a silicon oxide film, a silicon carbide nitride film, and a silicon carbide film. For example, in the case of a silicon nitride film, a silicon carbide nitride film, or a silicon carbide film, it can be easily removed by heat with a laser. Accordingly, the first insulating film 22 may be composed of a single film made of a silicon nitride film, a silicon carbide nitride film, a silicon carbide film, or a laminated film including one of these films. Alternatively, the first insulating film 22 may be composed of a silicon oxide film and a laminated film including at least one of a silicon nitride film, a silicon carbide nitride film, and a silicon carbide film. However, the present invention is not limited thereto, and the first insulating film 22 may further include various other materials, or may further include another layer.

At this time, the first insulating film 22 may not contain hydrogen. Since the first conductive type region 20 is formed of the first compound layer that does not include the semiconductor material and the dopant, the first insulating film 22 does not need to passivate the first compound layer with hydrogen. Accordingly, since hydrogen is not intentionally added to the first insulating film 22, hydrogen is not contained in the first insulating film 22 to a concentration that does not contain hydrogen or hydrogen passivation is possible. Accordingly, the first insulating film 22 can be formed in a simple process and a low-temperature process. In the process of forming the first insulating film 22, the crystal structure of the first conductive type region 20 can be maintained unchanged have.

On the other hand, the insulating film located on the first conductive type region formed of the semiconductor layer must include hydrogen for hydrogen passivation. Since the insulating film containing hydrogen is formed by a high temperature process (for example, a temperature exceeding 400 DEG C) Can be complicated and the process cost can be increased. When an insulating film containing hydrogen is formed on the first conductive type region 20 composed of the first compound layer, the crystal structure of the first conductive type region 20 is changed and the first carrier is extracted by applying a high- It can be difficult.

For example, the first conductive layer 20 may be formed of a compound layer (e.g., an oxide layer), a first insulating layer 22 formed of an insulating material or a dielectric material may be in direct contact with the first electrode 42 or The first metal electrode layer 422 can directly contact the first conductive type region 20. [ In addition, the first insulating layer 22 may form an outer surface at the front surface of the solar cell 100, and another layer may not be located on the first insulating layer 22. However, the present invention is not limited thereto, and another layer may be located between the first conductive type region 20 and the first insulating film 22, or another layer may be located on the first insulating film 22. [

A transparent conductive film made of a transparent conductive oxide is formed adjacent to the first insulating film 22 and the first conductive type region 20, that is, adjacent to the first insulating film 22 and the first conductive type region 20, And the solar cell 100 may not include a transparent conductive film. The transparent conductive film refers to a film containing a dopant metal for increasing the conductivity, such as an indium-based oxide, a zinc-based oxide, or a tin-based oxide. For example, the transparent conductive film may be formed of indium-tin oxide (ITO), indium-tungsten oxide (IWO), indium-cerium oxide (ICO) oxide, aluminum-zinc oxide (AZO), tin oxide, or the like.

The solar cell 100 having the first insulating film 22 without the transparent conductive film as in the present embodiment may have characteristics similar to those of the conventional solar cell having the transparent conductive film. This will be described in detail with reference to FIG.

4 is a graph showing the resistance of the conductive type region of the solar cell according to Examples 1 and 2 and Comparative Examples 1 and 2 measured. In Examples 1 and 2 and Comparative Example 2, the conductive type region was composed of a molybdenum oxide layer, and the conductive type region had thicknesses of 5 nm, 8 nm, and 1 nm, respectively. In Comparative Example 1, the conductive type region is formed of an amorphous silicon layer.

Referring to FIG. 4, Comparative Example 2 in which the thickness of the conductive type region is insufficient has a very high resistance as compared with Comparative Example 1, while Examples 1 and 2 in which the conductive type region has a thickness of 1.5 nm to 30 nm have the 1. ≪ / RTI > Accordingly, if the conductive type region has a certain thickness, it can have a resistance similar to that of the amorphous silicon layer. Accordingly, it can be seen that high efficiency can be achieved without a transparent conductive film such as a solar cell including an amorphous silicon layer, if the conductive type region has a certain thickness as in this embodiment.

Accordingly, in this embodiment, the first conductive film is removed and the first insulating film 22 is formed, so that the electrical characteristics are not deteriorated. Since the material cost and the process cost of the first insulating film 22 are lower than that of the transparent conductive film, the cost can be reduced according to the present embodiment. When the transparent conductive film is used, it is difficult for the solar cell 100 to have a hue (for example, a dark blue or black color) in consideration of aesthetic appearance due to its bright hue. If the first insulating film 22 is used, By adjusting the thickness, various colors can be realized. When a transparent conductive film is applied, free carrier absorption occurs and the current can be reduced. According to the present embodiment, this problem can also be prevented. In addition, when the transparent conductive film is located on both sides of the semiconductor substrate 10, the transparent conductive films positioned on both sides may be connected to each other, or the transparent conductive film and the conductive type region that should not be connected to each other may be connected to each other. This problem can also be avoided. As a result, the efficiency and the beauty of the solar cell 100 can be improved and the manufacturing cost can be reduced.

In this embodiment, the first insulating film 22 may serve as an anti-reflection film for preventing radiation from the front surface of the semiconductor substrate 10. The thickness of the first insulating film 22 may be greater than the thickness of the first conductive type region 20 and the first passivation layer 52 since the first insulating film 22 must have a sufficient thickness to prevent reflection have. For example, the thickness of the first insulating film 22 may be 60 nm to 100 nm. The antireflection effect can be exhibited within such a range. However, the present invention is not limited thereto.

A second insulating layer 32 having a second opening 32a is positioned (for example, in contact) on the second conductive type region 30 and a second electrode 32 having a pattern is formed through the second opening 32a. 44) or the second metal electrode layer 442 may be electrically connected (e.g., contacted) to the second conductivity type region 30. The second insulating layer 32 and the second electrode 44 or the second metal electrode layer 442 and the second conductive type region 30 are covered with the first insulating layer 22 and the first electrode 42 ) Or the first metal electrode layer 422 and the first conductivity type region 20 can be applied as they are, so that the description thereof will be omitted.

In the above description and drawings, the first and second metal electrode layers 422 and 442 of the solar cell 100 have a certain pattern, so that the solar cell 100 can enter the front and rear surfaces of the semiconductor substrate 10 And has a bi-facial structure. Accordingly, the amount of light used in the solar cell 100 can be increased to contribute to the efficiency improvement of the solar cell 100. However, the present invention is not limited to this. As shown in FIG. 5, the second metal 44 composed of the second metal electrode layer 442 may be formed entirely in contact with the second conductivity type region 30. Other variations are possible. In addition, the second conductive type region 20, the first conductive type region 30, and the first and second electrodes 42 and 44 may be disposed together on one surface. This example will be described again later with reference to Fig.

When light is incident on the solar cell 100 according to this embodiment, electrons and holes are generated by photoelectric conversion, and one of the generated holes and electrons is tunneled through the first passivation layer 52 to form the first conductivity type region 20 and then transferred to the second electrode 44 after the second passivation layer 54 is tunneled to the second conductivity type region 30 after the first passivation layer 54 is transferred to the first electrode 42. [ The holes and electrons transferred to the first and second electrodes 42 and 44 move to an external circuit or another solar cell 100. Thereby generating electrical energy.

Since the first conductive type region 20 and the second conductive type region 30 are formed on the semiconductor substrate 10 with the first or second passivation layer 52 and 54 interposed therebetween, It consists of separate layers. As a result, the loss due to the recombination can be minimized as compared with the case where the doped region formed by doping the semiconductor substrate 10 with the dopant is used as the conductive type region. In particular, the first conductive type region 20 and the second conductive type region 30 are composed of a first or a second compound layer that does not include a semiconductor material and a dopant, so that loss due to light absorption Can be reduced. Accordingly, the open-circuit voltage and the short-circuit current density of the solar cell 100 can be improved to improve the efficiency. Further, it can be manufactured by omitting a dopant doping process, a dopant activating process, and the like. In particular, since a high temperature process is not required, a process can be performed at a low temperature, thereby simplifying a manufacturing process and reducing a manufacturing cost. Therefore, the productivity of the solar cell 100 can be improved.

In particular, in the solar cell 100 having the conductive regions 20 and 30 composed of compound layers, the insulating films 22 and 23 (particularly, the first insulating film 22) through which the electrodes 42 and 44 pass are reflected It is possible to effectively prevent a problem that may be caused by the transparent conductive film by applying it as a protection film and removing the transparent conductive film. That is, it is possible to prevent problems such as free carrier absorption, improve the characteristics and efficiency of the solar cell 100, change the color of the solar cell 100 freely, and reduce manufacturing cost. Accordingly, the characteristics and efficiency of the solar cell 100 can be improved, the appearance can be improved, and the manufacturing productivity of the solar cell 100 can be improved.

In the above description, the first and second conductivity type regions 20 and 30 are all composed of compound layers, and the first and second electrodes 42 and 44 are formed without forming a transparent conductive film on both sides of the semiconductor substrate 10 The first and second insulating films 22 and 32 are illustrated. However, the present invention is not limited thereto. Therefore, one of the first and second conductivity type regions 20 and 30 may be composed of the above-described first or second compound layer, and / or a transparent conductive film is formed on at least one of both surfaces of the semiconductor substrate 10 The insulating films 22 and 32 having the openings 22a and 32a can be applied. Various other variations are possible.

Hereinafter, a method of manufacturing the solar cell 100 according to the present embodiment will be described in detail.

Hereinafter, a manufacturing method of the solar cell 100 according to the embodiment of the present invention will be described in detail with reference to FIGS. 6A to 6E. 6A to 6E are cross-sectional views illustrating a method of manufacturing a solar cell 100 according to an embodiment of the present invention.

The first and second passivation layers 52 and 54 are formed on the front surface and the rear surface of the semiconductor substrate 10, respectively, as shown in FIG. 6A. For example, the first passivation layer 52 positioned on the front surface of the semiconductor substrate 10 and the second passivation layer 54 positioned on the rear surface of the semiconductor substrate 10 may be formed at the same time. This can simplify the manufacturing process. However, the present invention is not limited thereto, and the first passivation layer 52 and the second passivation layer 54 may be formed in different processes.

The first and second passivation layers 52 and 54 may be formed by thermal growth, deposition (e.g., chemical vapor deposition (PECVD), atomic layer deposition (ALD)), chemical oxidation, However, the present invention is not limited thereto, and the first and second passivation layers 52 and 54 may be formed by various methods.

At this time, the front surface and / or the rear surface of the semiconductor substrate 10 may be textured to have an anti-reflection structure. Wet or dry texturing may be used for texturing the surface of the semiconductor substrate 10. [ The wet texturing can be performed by immersing the semiconductor substrate 10 in the texturing solution, and has a short process time. In dry texturing, the surface of the semiconductor substrate 10 is cut by using a diamond grill or a laser, so that irregularities can be formed uniformly, but the processing time is long and damage to the semiconductor substrate 10 may occur. Alternatively, the semiconductor substrate 10 may be textured by reactive ion etching (RIE) or the like. As described above, the semiconductor substrate 10 can be textured in various ways in the present invention.

The semiconductor substrate 10 may perform a cleaning process before forming the first and second passivation layers 52 and 54. In the cleaning process, the surface of the semiconductor substrate 10 is hydrogen-terminated The passivation characteristic can be improved.

6B, a first conductive type region 20 is formed on the first passivation layer 52 and a second conductive type region 30 is formed on the second passivation layer 54. Next, as shown in FIG. In this embodiment, each of the first conductive type region 20 and the second conductive type region 30 (hereinafter referred to as the conductive type regions 20 and 30) composed of the first or second compound layer has an amorphous structure.

In this embodiment, the conductive regions 20 and 30 may be formed by an atomic layer deposition process or a physical vapor deposition process. In particular, by using the atomic layer deposition process, thin and uniform conductive regions 20 and 30 can be formed on the semiconductor substrate 10 having an antireflective structure, and the mass productivity is also excellent. In the atomic layer deposition process, the composition of the second conductivity type regions 20 and 30 can be easily controlled by adjusting the amount of the material to be provided. By using such an atomic layer deposition process, thin and uniform conductive regions 20 and 30 can be formed on the semiconductor substrate 10 having an antireflective structure, and the mass productivity is also excellent.

For example, in the atomic layer deposition process, a first reaction material containing a metal and a second reaction material including a nonmetal may be used together. At this time, when the base metal contains oxygen, the second reactant may be an oxidizing agent, for example, the oxidizing agent may be oxygen gas (O ₂ ), ozone (O ₃ ), water (H ₂ O) . By reference, plasma can have very strong oxidizing power, including oxygen radicals. As the first reaction material, various materials or precursors including metals may be used.

More specifically, in the atomic layer deposition process, by repeating the process of alternately injecting the first reactant and / or the second reactant and purge them therebetween, the conductive regions 20 and 30 ) Is deposited. Since the deposition is performed in the atomic layer deposition process, the crystal structure of the conductive regions 20 and 30 can be easily controlled by controlling the process temperature, so that the desired amorphous structure (particularly, the amorphous structure The conductive regions 20 and 30 can be easily formed.

More specifically, if the process temperature of the atomic layer deposition process or the physical vapor deposition process is high, the binary metal oxide is bonded to the passivation layer 52, 54 or the existing formed layer with sufficient energy to have a crystalline structure, Can have an amorphous structure.

The process temperature of the atomic layer deposition process may be 400 캜 or lower (for example, 250 캜 or lower). This is because the conductive regions 20 and 30 can form an amorphous portion within this range. And the process temperature of the atomic layer deposition process may be 100 DEG C or higher (e.g., 150 DEG C or higher). If the process temperature is less than 100 캜, the conductivity type regions 20 and 30 may have porosity and the characteristics of extracting and delivering a desired carrier may be degraded. However, the present invention is not limited thereto.

Although the first and second conductivity type regions 20 and 30 are all the binary metal oxide layers in the above description and drawings, any one of the first and second conductivity type regions 20 and 30 may be a semiconductor A doped region formed on the substrate 10, or a semiconductor layer formed separately from the semiconductor substrate 10. At this time, the passivation layers 52 and 54 corresponding to the conductive regions 20 and 30 without the binary metal oxide layer may or may not be provided. At this time, the doped region may be formed on the semiconductor substrate 10 by a doping process such as ion implantation, thermal diffusion, or laser doping, and the semiconductor layer may be formed by a method such as deposition. The doping of the semiconductor layer may be performed together with the deposition of the semiconductor layer or may be performed by a separate doping process after the deposition of the semiconductor layer. Various other methods may also be used.

Can be performed in an in-situ process in which the process of forming the passivation layers 52 and 54 and the process of forming the conductive regions 20 and 30 in this embodiment are continuously performed in the same equipment have. That is, the passivation layers 52 and 54 can be formed by atomic vapor deposition or thermal oxidation in an atomic layer deposition apparatus. As a result, the conductive type regions 20 and 30 are formed in a state where the passivation layers 52 and 54 are not exposed to the atmosphere. Therefore, the thickness, characteristics, etc. of the passivation layers 52 and 54 It is possible to prevent change. In addition, the process can be simplified.

Subsequently, as shown in FIGS. 6C and 6D, a first insulating film 22 having a first opening 22a is formed on the first conductive type region 20, and a second insulating film 22 is formed on the second conductive type region 30 A second insulating film 32 having a second opening 32a is formed. 6C, after the first insulating film 22 and the second insulating film 32 are formed as a whole, the first and second openings 22a and 32a can be formed as shown in FIG. 6D have. This will be explained in more detail.

The first insulating film 22 is entirely formed on the first conductive type region 20 and the second insulating film 32 is formed on the second conductive type region 30 as a whole.

At this time, the insulating films 22 and 32 may be formed by a chemical vapor deposition (CVD) process or a sputtering process. Chemical vapor deposition can be formed by plasma-enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). The insulating films 22 and 32 may be formed in a different process from the conductive regions 20 and 30. In particular, the insulating films 22 and 32 may be formed at a rate lower than the forming rate of the conductive regions 20 and 30 It can be big. According to this, the conductive regions 20 and 30 are formed by an atomic layer deposition process or the like so as to have desired characteristics, and the insulating films 22 and 32 having a relatively large thickness are formed by using a process Thereby reducing the processing time.

Accordingly, in this embodiment, the step of forming the insulating films 22 and 32 can be performed at a process temperature of 400 ° C or less (more specifically, 300 ° C or less, for example, 250 ° C or less). Particularly, in the present embodiment, since the insulating films 22 and 32 do not need to contain hydrogen, the process of forming the insulating films 22 and 32 is performed in an atmosphere containing no hydrogen and can be formed at a low process temperature.

6D, a first opening 22a is formed in the first insulating film 22 and a second opening 32a is formed in the second insulating film 32. Next, as shown in FIG.

In this embodiment, the openings 22a and 32a may be formed by a laser ablation process for irradiating the laser 200 to the corresponding positions. When the laser 200 is irradiated, the conductive regions 20 and 30 are not removed, and only the corresponding portions of the insulating films 22 and 32 can be selectively removed. Although a clear reason for this has not been elucidated, a layer made of an oxide (especially a metal oxide) is not easily removed by heat by a laser, while a layer made of nitride, carbide, etc. is easily removed by a laser. Accordingly, the conductive regions 20 and 30 made of a metal oxide or the like by the laser are not easily removed by the laser, and the insulating films 22 and 32 can be selectively removed. More specifically, if a silicon nitride film, a silicon carbide film, a silicon carbide nitride film, or the like is included, it can be easily removed by a laser, and these single films can be used as the insulating films 22 and 32, or a lamination film including another film Can be used as the insulating films 22 and 32. When the insulating films 22 and 32 include a silicon oxide film, a laminated film stacked together with a silicon nitride film, a silicon carbide film, a silicon carbide nitride film, or the like may be used.

At this time, even if the conductive regions 20 and 30 are exposed to the laser 200, the crystal structure does not change due to recombination or the like. The change in the crystal structure due to the laser is caused by the fact that the dopant absorbs light and serves as a catalyst when the conductive regions 20 and 30 include a dopant. Therefore, the conductivity type regions 20 and 30 ) Does not contain a dopant, no change in crystal structure or the like occurs. Accordingly, by using the laser 200, the openings 22a and 32a can be formed without damaging or changing the characteristics of the conductive regions 20 and 30. On the other hand, when the openings 22a and 32a are formed by etching or the like, a separate mask or mask layer is required, and the conductive regions 20 and 30 made of the compound layer may be damaged or the characteristics may be changed.

As the laser 200, a laser having various wavelengths which can remove a part of the insulating films 22 and 32 can be used. For example, the laser 200 may be an ultraviolet laser, a green laser, an infrared laser, or the like. In addition, the laser 200 may be a pulsed wave laser having an output for a certain period of time in a pulse waveform and no output for a certain period of time. According to this, the laser 200 provides sufficient energy to the insulating films 22 and 32 in a short time, and the openings 22a and 32a can be stably formed. For example, the pulse of the laser 200 may be a short pulse, or may have a pulse width of a picosecond to nanosecond level. The energy required to form the openings 22a and 32a in the pulse width of the laser 200 can be sufficiently provided. However, the present invention is not limited thereto. Accordingly, the laser 200 may have a pulse width different from that described above, or may be a continuous wave laser having a constant and continuous output.

The first and second passivation layers 52 and 54 are formed first and then the first and second conductivity type regions 20 and 30 are formed and then the first and second The insulating films 22 and 32 are formed, but the present invention is not limited thereto. The order of the first passivation layer 52, the first conductive type region 20, the first insulating film 22, the second passivation layer 54, the second conductive type region 30 and the second insulating film 32, or The second passivation layer 52, the first conductive type region 20 and the second insulating film 32 in this order from the side of the second passivation layer 54, the second conductive type region 30, the second insulating film 32, the first passivation layer 52, . Various other sequences are possible. The process of forming the first and second openings 22a and 32a may also be performed in various orders.

6E, the first electrode 42 and the second opening 32a, which penetrate through the first opening 22a and are connected (for example, in contact with) the first conductivity type region 20, And the second electrode 44 is electrically connected to the second conductive type region 30 (for example, contact).

The second electrode 44 including the first metal electrode layer 422 and the second metal electrode layer 442 may be formed by plating, printing, or the like. For example, the first metal electrode layer 422 and the second metal electrode layer 442 may be formed by printing a low-temperature printing paste and then drying or firing it. At this time, the first metal electrode layer 422 and the second metal electrode layer 442 may be formed in the same process, thereby simplifying the manufacturing process. However, the present invention is not limited thereto, and the first and second metal electrode layers 422 and 442 can be formed by various methods.

Accordingly, in the present embodiment, the step of forming the first and / or second electrodes 42 and 44 is performed at a temperature of 400 占 폚 or lower (more specifically, 350 占 폚 or lower, for example, 300 占 폚 or lower, ) ≪ / RTI >

Accordingly, the step of forming the conductive regions 20 and 30 and all the steps thereafter are performed at a temperature of 400 캜 or lower (more specifically, 350 캜 or lower, for example, 300 캜 or lower, for example, 250 캜 or lower) Lt; / RTI > By this temperature, the amorphous structure or amorphous portion of the conductive type regions 20 and 30 can be retained in the final structure without being crystallized.

In the above description and drawings, the first and second insulating films 22 and 32 are all provided without the transparent conductive film, and the first and second electrodes 42 and 44 penetrate the first and second openings 22a and 32a . However, if any one of the first and second insulating films 22 and 32 is not formed and the corresponding first or second electrode 42 or 44 is formed of the first or second conductive type region 20 or 30 and the first Or between the second metal electrode layers 422 and 442. [ Various other variations are possible.

According to this embodiment, since the transparent conductive film is not formed, the solar cell 100 can be manufactured with a simple process and a low manufacturing cost. In addition, the manufacturing process of the solar cell 100 may be performed at a temperature of 400 ° C or lower (more specifically, 350 ° C or lower, for example, 300 ° C or lower, for example, 250 ° C or lower). Thus, the manufacturing cost can be reduced and the productivity can be improved. Accordingly, the solar cell 100 having excellent characteristics and efficiency can be manufactured with high productivity.

Hereinafter, a solar cell according to another embodiment of the present invention will be described in detail. Detailed descriptions will be omitted for the same or extremely similar parts as those described above, and only different parts will be described in detail. It is also within the scope of the present invention to combine the above-described embodiments or variations thereof with the following embodiments or modifications thereof.

7 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

Referring to FIG. 7, a passivation layer 56 is disposed on the rear surface of the semiconductor substrate 10, and a first conductive type region 20 and a second conductive type region 50 are formed on the same plane on the passivation layer 56, The insulating film 34 having the first and second openings 34a and 34b is positioned and contacted with the first and second openings 34a and 34b while covering the first and second openings 34a and 34b, 34b for electrically connecting (e.g., contacting) the first and second conductivity type regions 20, 30 to the first and second conductivity type regions 20, 30, respectively. A front electric field area (or a front electric field forming layer) 60 is disposed on the entire surface of the semiconductor substrate 10, and the anti-reflection film 24 may be disposed thereon.

At this time, an anti-reflection structure may be formed on the front surface of the semiconductor substrate 10, and a rear surface of the semiconductor substrate 10 may be a mirror polished surface. This is because the characteristics of the passivation layer 56 can greatly change the carrier transport characteristics and the like. However, the present invention is not limited thereto, and an anti-reflection structure may be formed on the rear surface of the semiconductor substrate 10.

In this embodiment, the first conductive type region 20 and the second conductive type region 30 may be positioned (for example, in contact with each other) on the passivation layer 56 and in contact with each other. Since the first conductive type region 20 and the second conductive type region 30 do not contain a semiconductor material and a dopant, a problem such as a short circuit does not occur even if the side faces are in contact with each other. However, the present invention is not limited thereto. Thus, as a variant, a barrier region may be located between the first and second conductive regions 20 and 30 on the passivation layer 56 to prevent them from contacting. The barrier region may be composed of an empty space, or may be composed of an intrinsic semiconductor layer, a compound such as an oxide, or the like.

The insulating layer 34 may be formed entirely excepting the first and second openings 34a and 34b while covering the first and second conductive regions 20 and 30 together. The first and second metal electrode layers 422 and 442 of the first and second electrodes 42 and 44 pass through the first and second openings 34a and 34b to form the first and second conductive regions 20 , 30), respectively.

The first and second conductivity type regions 20 and 30 and the first and second metal electrode layers 422 and 442 may have various shapes. For example, the first and second conductive type regions 20 and 30 and the first and second metal electrode layers 422 and 442 may have a strip shape extending in a straight line along one direction. At this time, they may be alternately located in a direction intersecting the longitudinal direction of the first and second conductive type regions 20 and 30, and may be alternately arranged in a direction intersecting the longitudinal direction of the first and second metal electrode layers 422 and 4420 They can be alternately located. At this time, the width of the first conductivity type region 20 can be made larger than the width of the second conductivity type region 30, thereby sufficiently securing the area of the first conductivity type region 20 serving as the emitter region.

As for the passivation layer 56, the description of the first or second passivation layer 52, 54 of the above-described embodiment can be applied as it is. The first conductive type region 20 and the second conductive type region 30 of the first embodiment except for the positions and shapes of the first conductive type region 20 and the second conductive type region 30 The description of the conductive type region 20 and the second conductive type region 30 can be applied as it is. As for the insulating film 34, the description of the first or second insulating film 22, 32 of the above-described embodiment can be applied as it is. The first electrode 42 and the second electrode 44 are the same as those of the first electrode 42 and the second electrode 44 except for the positions and shapes of the first electrode 42 and the second electrode 44. [ The description of the two electrodes 44 may be applied as it is.

The front electric field area 60 positioned (e.g., in contact with) the front surface of the semiconductor substrate 10 may be a film having a fixed electric charge or a compound layer capable of selectively collecting electrons or holes as described above (for example, A metal oxide layer, more specifically, a binary metal oxide layer). For example, the front field region 60 may be an aluminum oxide layer comprising aluminum oxide with a fixed charge. Alternatively, the front electric field region 60 may include a molybdenum oxide layer, a tungsten oxide layer, a vanadium oxide layer, a nickel oxide layer, a rhenium oxide layer, a titanium oxide layer, a zinc oxide layer, and a niobium oxide layer capable of selectively extracting and collecting electrons or holes An oxide layer or the like. Or the front electric field area 60 may be a layer including a plurality of the above-mentioned layers. This front electric field area 60 is composed of an oxide layer and can effectively passivate the front surface of the semiconductor substrate 10.

At this time, the front electric field area 60 is formed of the same layer as one of the metal compound layers constituting the first conductive type area 20, the second conductive type area 30 and the front electric field area 60, It may be simplified. For example, the front electric field region 60 and the second conductive type region 30 may be formed of a titanium oxide layer.

The front electric field area 60 may include a fixed electric charge in a state where it is not connected to the external circuit or the electrodes 42 and 44 connected to other solar cells 100 or may selectively collect electrons or holes, 10 having a constant second conductivity type region that prevents recombination in the vicinity of the front surface. In this case, the semiconductor substrate 10 does not have a separate doping region but consists only of the base region 110, thereby minimizing defects in the semiconductor substrate 10. [

At this time, the thickness of the front electric field area 60 may be equal to or less than the thickness of the first conductive type region 20 and the second conductive type region 30. This is because the front electric field area 60 is not a layer for transferring the carrier to the outside and may have a relatively small thickness. For example, the thickness of the front electric field area 60 may be 1 nm to 10 nm. It is possible to sufficiently realize the effect of the front electric field area 60 in this thickness. However, the present invention is not limited to the thickness of the front electric field area 60.

An antireflection film 24 for reducing the reflectance of light can be positioned (for example, on the front surface of the semiconductor substrate 10 or on the front electric field area 60). The antireflection film 24 may be formed of various materials. In one example, the antireflection film 24 may include at least one of a silicon nitride film, a silicon oxide film, a silicon carbide nitride film, and a silicon carbide film. The antireflection film 24 may be formed in the same process as the insulation film 34 and have the same material as the insulation film 34. [ This can simplify the manufacturing process. However, the present invention is not limited thereto, and the antireflection film 24 may be formed in a process different from that of the insulation film 34, or may be composed of other materials.

The front electric field area 60, and the antireflection film 24 may be formed entirely on the front surface of the semiconductor substrate 10. Thus, the manufacturing process can be simplified and the role of each layer can be sufficiently exhibited.

A doped region of the same conductivity type as the base region 110 may be doped to the entire surface of the semiconductor substrate 10 at a high concentration to form a doped region And this doped region may be used as the front electric field region 60. [ In this case, the antireflection film 24 or the like may be positioned on the doped region constituting the front electric field area 60. Various other variations are possible.

In the unit solar cell 100 according to the present embodiment, the first and second electrodes 42 and 44 (particularly, the first and second metal electrode layers 422 and 442) are all located on the rear side of the semiconductor substrate 10 So that there is no part for blocking the light on the front side, so that the light loss can be minimized. Particularly, in this embodiment, since at least one of the first conductive type region 20 and the second conductive type region 30 is formed of a compound layer, the first and second electrodes 42 and 44 2 metal electrode layers 422 and 442 may be formed to be wide. In this case, the rear electrode structure can be applied to prevent the problem caused by the shading loss.

6A, the passivation layer 56 is formed on the rear surface of the semiconductor substrate 10, and the passivation layer 56 is formed on the passivation layer 56 by a process shown in FIG. The insulating film 34 and the antireflection film 24 are formed by the process shown in FIG. 6C and the insulating film 34 is formed by the process shown in FIG. The first and second openings 32a and 34a are formed in the first and second electrodes 42 and 44 and the first and second electrodes 42 and 44 are formed by the process shown in FIG. The front electric field area 60 may be formed by various processes before the process of forming the antireflection film 24. The solar cell 100 according to the present embodiment can be manufactured by various other methods.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
10: semiconductor substrate
20: first conductivity type region
22: First insulating film
22a: a first opening
30: second conductivity type region
32: second insulating film
32a: a second opening
34: Insulating film
34a: a first opening
34b: a second opening
42: first electrode
44: Second electrode

Claims (20)

A semiconductor substrate;
A first conductive type region formed on the semiconductor substrate and composed of a first compound layer of a metal and a non-metal to selectively extract a first carrier;
A first insulating layer located above the first conductive type region and having a first opening; And
A first electrode electrically connected to the first conductivity type region through the first opening,
≪ / RTI > The method according to claim 1,
Wherein the first electrode includes a metal electrode layer or an electrode layer having a pattern that is in direct contact with the first conductivity type region. The method according to claim 1,
And the first insulating film is formed in contact with the first conductive type region. The method according to claim 1,
Wherein the first insulating film comprises at least one of a silicon nitride film, a silicon oxide film, a silicon carbide nitride film, and a silicon carbide film. The method according to claim 1,
Wherein the first insulating film does not contain hydrogen. The method according to claim 1,
Wherein a thickness of the first insulating film is larger than a thickness of the first conductive type region. The method according to claim 1,
Wherein the first insulating film has a thickness of 60 nm to 100 nm,
And the thickness of the first conductivity type region is 30 nm or less. The method according to claim 1,
Wherein the transparent conductive film is not disposed around the first conductive type region and the first insulating film. The method according to claim 1,
Further comprising a passivation layer disposed between the conductive region and the semiconductor substrate,
Wherein a thickness of the insulating film is larger than a thickness of the passivation layer. The method according to claim 1,
A second conductive type region located on the semiconductor substrate and comprising a second compound layer of a metal and a non-metal to selectively extract a second carrier;
A second insulating layer located above the second conductive type region and having a second opening; And
And a second electrode electrically connected to the second conductivity type region through the second opening,
Further comprising:
The first conductive type region is located on one side of the semiconductor substrate and the second conductive type region is located on the other side of the semiconductor substrate, or
Wherein the first conductivity type region and the second conductivity type region are located on the same side of the semiconductor substrate. Forming a first conductive type region on the semiconductor substrate, the first conductive type region comprising a first compound layer of a metal and a nonmetal and selectively extracting a first carrier;
Forming a first insulating layer over the first conductive type region and having a first opening; And
Forming a first electrode through the first opening and electrically connected to the first conductive type region;
Wherein the method comprises the steps of: 12. The method of claim 11,
The forming of the first insulating layer may include:
Forming the first insulating film on the first conductive type region as a whole; And
Removing a portion of the first insulating film corresponding to the first opening to form the first opening;
Wherein the method comprises the steps of: 13. The method of claim 12,
Wherein the forming of the first opening is performed by a laser ablation process of irradiating a laser beam to a portion corresponding to the first opening. 14. The method of claim 13,
And a portion of the first insulating film corresponding to the first opening is selectively removed by the laser ablation process. 13. The method of claim 12,
Wherein the step of forming the first insulating film as a whole is performed at a process temperature of 400 DEG C or less. 13. The method of claim 12,
Wherein the step of forming the first insulating film as a whole is performed in an atmosphere containing no hydrogen. 13. The method of claim 12,
Wherein the step of forming the first insulating film as a whole is performed by a chemical vapor deposition (CVD) process or a sputtering process. 13. The method of claim 12,
Wherein a thickness of the first insulating film is larger than a thickness of the first conductive type region,
Wherein the forming rate of the first insulating film in the step of forming the first insulating film as a whole is larger than the forming rate of the first conductive type region in the step of forming the first conductive type region. 13. The method of claim 12,
Wherein the forming of the first conductivity type region is performed by an atomic layer deposition process. 12. The method of claim 11,
Wherein the forming of the first electrode is performed by a printing process using a low temperature firing paste.

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