KR20170039472A - Solar cell - Google Patents

Solar cell Download PDF

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Publication number
KR20170039472A
KR20170039472A KR1020150138657A KR20150138657A KR20170039472A KR 20170039472 A KR20170039472 A KR 20170039472A KR 1020150138657 A KR1020150138657 A KR 1020150138657A KR 20150138657 A KR20150138657 A KR 20150138657A KR 20170039472 A KR20170039472 A KR 20170039472A
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KR
South Korea
Prior art keywords
type region
layer
conductivity type
semiconductor substrate
conductive type
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Application number
KR1020150138657A
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Korean (ko)
Inventor
정일형
심승환
김진아
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엘지전자 주식회사
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Application filed by 엘지전자 주식회사 filed Critical 엘지전자 주식회사
Priority to KR1020150138657A priority Critical patent/KR20170039472A/en
Priority to US15/071,923 priority patent/US10566483B2/en
Priority to JP2016053859A priority patent/JP6505627B2/en
Priority to EP17185839.2A priority patent/EP3261133B1/en
Priority to EP16160828.6A priority patent/EP3070750B1/en
Priority to EP16191774.5A priority patent/EP3151289A1/en
Priority to US15/282,482 priority patent/US20170098722A1/en
Priority to JP2016195586A priority patent/JP2017069567A/en
Publication of KR20170039472A publication Critical patent/KR20170039472A/en
Priority to JP2017087299A priority patent/JP6522684B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • H01L31/022475—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers composed of indium tin oxide [ITO]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • H01L31/022483—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers composed of zinc oxide [ZnO]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Abstract

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate including a semiconductor material; a tunneling layer located on one side of the semiconductor substrate; a first conductive type region and a second conductive type region which are located on the tunneling layer and have opposite conductivity types; and an electrode including a first electrode electrically connected to the first conductive type region and a second electrode electrically connected to the second conductive type region. At least one among the first conductivity type region and the second conductivity type region is composed of a metal compound layer. Accordingly, the present invention can improve the efficiency and productivity of the solar cell.

Description

Solar cell {SOLAR CELL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell, and more particularly, to a solar cell having a rear electrode structure.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. However, solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize a solar cell, it is required to overcome a low efficiency and a low productivity, and a solar cell capable of maximizing the efficiency and productivity of the solar cell is required.

The present invention provides a solar cell having excellent efficiency and high productivity.

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate including a semiconductor material; A tunneling layer located on one side of the semiconductor substrate; A first conductive type region and a second conductive type region which are located on the tunneling layer and have opposite conductivity types; And an electrode including a first electrode electrically connected to the first conductive type region and a second electrode electrically connected to the second conductive type region. At least one of the first conductivity type region and the second conductivity type region is composed of a metal compound layer.

In the solar cell according to the present invention, since the conductive type region does not include the semiconductor material and the dopant, the problem caused by the recombination can be minimized and the passivation effect can be improved. And the fabrication process of the conductive type region can be simplified. Thus, efficiency and productivity of the solar cell can be improved.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.
2 is a partial rear plan view of the solar cell shown in Fig.
3 is a band diagram of a semiconductor substrate, a tunneling layer, and a first conductive type region in a solar cell according to an embodiment of the present invention.
4 is a band diagram of a semiconductor substrate, a tunneling layer, and a second conductivity type region in a solar cell according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, the expressions "first "," second "and the like are used only for distinguishing each other, and the present invention is not limited thereto.

Hereinafter, a solar cell according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of a solar cell according to an embodiment of the present invention, and FIG. 2 is a partial rear plan view of the solar cell shown in FIG. The second electrodes 422 and 442 of the first and second electrodes 42 and 44 are not shown in FIG. 2 for the sake of simplicity.

1 and 2, a solar cell 100 according to an embodiment of the present invention includes a semiconductor substrate 10 including a semiconductor material, a tunneling layer (not shown) formed on one surface of the semiconductor substrate 10 Layer 20 and a first conductive type region 32 and a second conductive type region 34 located on the tunneling layer 20 and a first conductive type region 32 and a second conductive type region 34, The first electrode 42 and the second electrode 44 are connected to the first electrode 42 and the second electrode 44, respectively. At this time, in the present embodiment, at least one of the first conductivity type region 32 and the second conductivity type region 34 is composed of a metal compound layer (for example, a metal oxide layer). The solar cell 100 may further include a front electric field generating layer 30, a transparent conductive film 24, an anti-reflection film 26, and the like. This will be explained in more detail.

The semiconductor substrate 10 may include an n-type or p-type base region 110 containing an n-type or p-type dopant at a relatively low doping concentration. The base region 110 may be formed of a crystalline semiconductor material including a second conductive dopant. In one example, the base region 110 may be composed of a single crystal or a polycrystalline semiconductor (e.g., single crystal or polycrystalline silicon) including a second conductive type dopant. In particular, base region 110 may be comprised of a single crystal semiconductor (e.g., a single crystal semiconductor wafer, more specifically a semiconductor silicon wafer) comprising an n-type or p-type dopant. The electrical characteristics are excellent based on the base region 110 or the semiconductor substrate 10 having high crystallinity and few defects.

For example, if the base region 110 has an n-type, the p-type (n-type) semiconductor layer forming a junction with the base region 110 and forming a carrier by photoelectric conversion It is possible to increase the photoelectric conversion area by forming the first conductivity type region 32 of the first conductivity type. In this case, the first conductivity type region 32 having a large area can effectively collect holes having a relatively low moving speed, thereby contributing to the improvement of photoelectric conversion efficiency. In addition, when the base region 110 is n-type, the metal compound composing the first and second conductivity type regions 32 and 34 can be easily formed and can be formed of a material. Concrete materials of the first and second conductivity type regions 32 and 34 will be described later in detail.

In the present embodiment, the other surface (hereinafter referred to as "front surface") of the semiconductor substrate 10 may be textured to have irregularities such as pyramids. The texturing structure formed on the semiconductor substrate 10 may have a certain shape (e.g., a pyramid shape) having an outer surface formed along a specific crystal plane of the semiconductor. If the surface roughness of the semiconductor substrate 10 is increased by forming concavities and convexities on the front surface of the semiconductor substrate 10 by such texturing, the reflectance of light incident through the front surface of the semiconductor substrate 10 can be reduced. Accordingly, the amount of light reaching the pn junction formed by the base region 110 and the first conductivity type region 32 can be increased, and the light loss can be minimized.

The rear surface of the semiconductor substrate 10 may be made of a relatively smooth and flat surface having a surface roughness lower than that of the front surface by mirror polishing or the like. When the first and second conductivity type regions 32 and 34 are formed together on the rear side of the semiconductor substrate 10 as in the present embodiment, the characteristics of the solar cell 100 This can vary greatly. As a result, unevenness due to texturing is not formed on the rear surface of the semiconductor substrate 10, so that passivation characteristics can be improved and the characteristics of the solar cell 100 can be improved. However, the present invention is not limited thereto, and it is also possible to form concavities and convexities by texturing on the rear surface of the semiconductor substrate 10 according to circumstances. Various other variations are possible.

A tunneling layer 20 may be formed on the rear surface of the semiconductor substrate 10. For example, the tunneling layer 20 may be formed in contact with the rear surface of the semiconductor substrate 10 to simplify the structure and improve the tunneling effect. However, the present invention is not limited thereto.

The tunneling layer 20 acts as a kind of barrier to electrons and holes to prevent the minority carriers from passing therethrough and to prevent the majority carriers from being accumulated in the portion adjacent to the tunneling layer 20, so that only the majority carriers can pass through the tunneling layer 20. At this time, a plurality of carriers having energy above a certain level can easily pass through the tunneling layer 20 by the tunneling effect. The tunneling layer 20 may also serve as a diffusion barrier to prevent the dopants of the conductive regions 32 and 34 from diffusing into the semiconductor substrate 10. [ The tunneling layer 20 may include various materials through which a plurality of carriers can be tunneled. For example, the tunneling layer 20 may include an oxide, a nitride, a semiconductor, a conductive polymer, and the like. For example, the tunneling layer 20 may comprise silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, and the like. In particular, the tunneling layer 20 may be comprised of a silicon oxide layer comprising silicon oxide. This is because the silicon oxide layer is a film which has excellent passivation characteristics and is susceptible to tunneling of the carrier. Such a silicon oxide layer may be formed by thermal oxidation or chemical oxidation.

The thickness of the tunneling layer 20 may be thin so as to sufficiently realize the tunneling effect. In one example, the thickness of the tunneling layer 20 may be 5 nm or less (more specifically, 2 nm or less, for example, 0.5 nm to 2 nm). When the thickness of the tunneling layer 20 is greater than 5 nm, the solar cell 100 may not operate because the tunneling does not smoothly occur. If the thickness of the tunneling layer 20 is less than 0.5 nm, May be difficult to form. In order to further improve the tunneling effect, the thickness of the tunneling layer 20 may be 2 nm or less (more specifically, 0.5 nm to 2 nm). However, the present invention is not limited thereto, and the thickness of the tunneling layer 20 may have various values.

The tunneling layer 20 may be formed entirely on the rear surface of the semiconductor substrate 10. As a result, the passivation characteristics of the semiconductor substrate 10 can be improved and formed by a simple process without patterning.

The first and second conductivity type regions 32 and 34 may be located on the tunneling layer 20. The first and second conductivity type regions 32 and 34 may be formed in contact with the tunneling layer 20 to simplify the structure and maximize the tunneling effect. However, the present invention is not limited thereto.

In the present embodiment, the first conductivity type region 32 and the second conductivity type region 34 are metal compound layers composed of a metal compound and do not have an n-type or p-type dopant. For example, the first conductive type region 32 and the second conductive type region 34 may be a metal oxide layer including a metal oxide. If the first conductive type region 32 and the second conductive type region 34 are formed of a metal oxide layer, the first conductive type region 32 and the second conductive type region 34 can be easily manufactured, have excellent chemical stability, and can further improve the passivation effect. On the other hand, if the first conductivity type region 32 or the second conductivity type region 34 is composed of a sulfide or the like, the chemical stability may be low.

The first conductive type region 32 and the second conductive type region 34 are formed of a metal capable of selectively collecting electrons or holes in consideration of the energy band between the semiconductor substrate 10 and the tunneling layer 20, Compounds. Accordingly, the first conductivity type region 32 and the second conductivity type region 34 do not include a semiconductor material, or a material that acts as a dopant in the semiconductor material. This will be described in more detail with reference to FIGS. 3 and 4. FIG.

3 is a diagram showing band diagrams of the semiconductor substrate 10, the tunneling layer 20, and the first conductivity type region 32 in the solar cell 100 according to the embodiment of the present invention. 4 is a diagram showing band diagrams of the semiconductor substrate 10, the tunneling layer 20, and the second conductivity type region 34 in the solar cell 100 according to the embodiment of the present invention. At this time, the semiconductor substrate 10 is of the n-type will be described as an example.

The metal compound layer of the first conductive type region 32 capable of selectively collecting holes has a Fermi level lower than the fermi level of the semiconductor substrate 10 and has a work function of the semiconductor substrate 10 function can have a larger work function. For example, the work function of the semiconductor substrate 10 can be about 3.7 eV, and the work function of the first conductivity type region 32 can be greater than 3.8 eV. More specifically, the work function of the first conductivity type region 32 may be 7 eV or less (for example, 3.8 eV to 7 eV). If the work function of the first conductivity type region 32 exceeds 7 eV, it may be difficult to selectively collect holes. If the above-mentioned energy band gap is less than 3.8 eV, it may be difficult to selectively collect only holes except electrons.

When the first conductive type region 32 composed of the metal compound layer having the Fermi level and the work function is bonded to the semiconductor substrate 10 with the tunneling layer 20 therebetween, 10 and the first conductivity type region 32 have the same Fermi level. 3, the holes in the electrical current path in the semiconductor substrate 10 can easily move according to the electrical conductivity of the second conductivity type region 34 when the electrons pass through the tunneling layer 20. On the other hand, electrons in the semiconductor substrate 10 do not pass through the tunneling layer 20.

For example, the metal compound layer that can be used for the first conductive type region 32 as described above includes a molybdenum oxide layer composed of molybdenum oxide, a tungsten oxide layer composed of tungsten oxide (e.g., WO 3 ), a vanadium oxide And the like. In particular, if the first conductive type region 32 includes a molybdenum oxide layer or a tungsten oxide layer, the effect of selectively collecting holes may be excellent.

The metal compound layer of the second conductivity type region 34 capable of selectively collecting electrons has a Fermi level higher than the Fermi level of the semiconductor substrate 10 and has a work function smaller than the work function of the semiconductor substrate 10 . For example, the work function of the semiconductor substrate 10 can be about 3.7 eV, and the work function of the second conductivity type region 34 can be 0.1 eV to 3.6 eV. More specifically, the energy band gap between the conduction band of the second conductivity type region 34 and the conduction band of the semiconductor substrate 10 may be 1 eV or less (for example, 0.1 eV to 1 eV). If the energy band gap described above exceeds 1 eV, it may be difficult to selectively collect electrons. If the energy band gap is less than 0.1 eV, the energy band gap may be small and it may be difficult to selectively collect only electrons except the holes.

When the second conductive type region 34 composed of the metal compound layer having the Fermi level and the work function is bonded to the semiconductor substrate 10 with the tunneling layer 20 interposed therebetween, ) And the second conductivity type region 34 have the same Fermi level. 4, electrons in the conduction band in the semiconductor substrate 10 can easily move to the conduction band of the second conduction type region 34 when passing through the tunneling layer 20. On the other hand, holes in the semiconductor substrate 10 do not pass through the tunneling layer 20.

For example, the metal compound layer that can be used for the second conductivity type region 34 as described above includes a titanium oxide layer composed of titanium oxide (for example, TiO 2 ), a titanium oxide layer composed of zinc oxide (for example, ZnO) A zinc oxide layer, and the like. In particular, if the second conductivity type region 34 includes a titanium oxide layer, the effect of selectively collecting electrons can be excellent.

The first conductivity type region 32, which collects holes selectively and transfers the holes to the first electrode 42, constitutes an emitter region. The second conductivity type region 34, which collects electrons selectively and transfers the electrons to the second electrode 44, forms a back surface field region.

At this time, the thicknesses of the first conductivity type region 32 and the second conductivity type region 34 may be 1 nm to 100 nm, respectively. Since the first conductive type region 32 and the second conductive type region 34 are metal compound layers that do not include a dopant, the resistance may be increased when the thickness is increased. In consideration of this, the thicknesses of the first conductivity type region 32 and the second conductivity type region 34 are set to 100 nm or less. If the thicknesses of the first conductivity type region 32 and the second conductivity type region 34 are less than 1 nm, the first or second conductivity type regions 32 and 34 may not have a sufficient role. However, the present invention is not limited to the thicknesses of the first and second conductivity type regions 32 and 34.

The first and second conductivity type regions 32 and 34 may be formed by various methods. For example, by vapor deposition, printing, or the like.

Since the first conductive type region 32 and the second conductive type region 34 do not include a dopant, problems such as short-circuiting do not occur even if the side faces are in contact with each other. However, the present invention is not limited thereto. Thus, as a variant, a barrier region may be located between the first and second conductivity type regions 32 and 34 on the tunneling layer 20 to prevent them from contacting. The barrier region may be formed as an empty space, or may have a variety of structures such as an intrinsic semiconductor layer or a structure in which a compound such as an oxide is located.

As such, if the first and second conductivity type regions 32 and 34 do not contain a semiconductor material and a dopant, recombination caused by the dopant can be minimized. The first and second conductivity type regions 32 and 34 made of a metal compound (for example, a metal oxide) serve as a passivation layer, so that the passivation effect can be improved. In addition, various processes such as a process for depositing a semiconductor layer made of a semiconductor material, a process for doping, a process for activating annealing, and the like can be omitted, and a high temperature process can be omitted. The productivity of the solar cell 100 can be improved and the characteristics of the semiconductor substrate 10 can be kept excellent.

In the above description and drawings, it is exemplified that the first and second conductivity type regions 32 and 34 are all made of a metal compound layer not containing a dopant. However, the present invention is not limited to this, and it is also possible that only one of the first and second conductivity type regions 32 and 34 is composed of a metal compound layer that does not include a dopant. Various other variations are possible.

Here, a plurality of carriers (i.e., holes) different from the majority carriers of the base region 110 are collected than the area of the second conductivity type region 34 that collects the same carriers (i.e. electrons) as the majority carriers of the base region 110 The area of the first conductivity type region 32 can be made wider. As a result, the first conductive type region 32 functioning as the emitter region can be formed with a sufficient area. By the first conductive type region 32 formed to be wide, it is possible to effectively collect holes having a relatively slow moving speed. The planar structure of the first conductive type region 32 and the second conductive type region 34 will be described later in more detail with reference to FIG.

Electrodes 42 and 44 located on the rear surface of the semiconductor substrate 10 include a first electrode 42 electrically and physically connected to the first conductivity type region 32 and a second electrode 42 electrically connected to the second conductivity type region 34 And a second electrode 44 electrically and physically connected.

The first electrode 42 may include a first electrode layer 421 and a second electrode layer 422 which are sequentially stacked on the first conductive type region 32.

Here, the first electrode layer 421 may be formed in a relatively large area (for example, in contact) over the first conductivity type region 32. When the first electrode layer 421 is formed on the first conductivity type region 32 as described above, the carrier can easily reach the second electrode layer 422 through the first electrode layer 421, . In particular, in this embodiment, since the first conductive type region 32 is undoped and composed of a metal compound layer that does not include a dopant, the resistance may be lowered. Therefore, the first electrode layer 421 may be provided to effectively reduce the resistance will be.

Since the first electrode layer 421 is formed over the first conductive type region 32 as described above, the first electrode layer 421 can be formed of a light-transmitting material (transparent material). That is, the first electrode layer 421 is made of a transparent conductive material so that the carrier can be easily moved while allowing transmission of light. Accordingly, even if the first electrode layer 421 is formed over the first conductivity type region 32 in a wide area, the transmission of light is not blocked. For example, the first electrode layer 421 may include indium tin oxide (ITO), carbon nano tube (CNT), and the like. However, the present invention is not limited thereto and may include the first electrode layer 421 and various other materials.

A second electrode layer 422 may be formed on the first electrode layer 421. For example, the second electrode layer 422 may be formed in contact with the first electrode layer 421 to simplify the structure of the first electrode 42. However, the present invention is not limited to this, and various modifications such as the existence of a separate layer between the first electrode layer 421 and the second electrode layer 422 are possible.

The second electrode layer 422 located on the first electrode layer 421 may be formed of a material having a higher electrical conductivity than the first electrode layer 421. Thus, characteristics such as carrier collection efficiency and resistance reduction by the second electrode layer 422 can be further improved. For example, the second electrode layer 422 may be made of opaque metal having a good electrical conductivity or a metal having a lower transparency than the first electrode layer 421.

As such, the second electrode layer 422 may be opaque or have a low transparency and may interfere with the incidence of light, so that it may have a certain pattern so as to minimize shading loss. The second electrode layer 422 has a smaller area than the first electrode layer 421. Thus, light can be incident on a portion where the second electrode layer 422 is not formed. The planar shape of the second electrode layer 422 will be described later in more detail with reference to FIG.

The first and second electrode layers 421 and 422 of the first electrode 42 may be formed by various methods such as vapor deposition, sputtering, and printing.

The second electrode 44 may include a first electrode layer 441 and a second electrode layer 442 that are sequentially stacked on the second conductive type region 34. The role, material, shape, etc. of the first and second electrode layers 441 and 442 of the second electrode 44 are the same as those of the second electrode 44 except that the second electrode 44 is located on the second conductivity type region 34. [ Material, shape, etc. of the first and second electrode layers 421 and 422 of the first electrode 42 can be applied as they are.

A rear passivation film, an antireflection film, a reflection film, and the like are formed on the first and second conductive type regions 32 and 34 and / or the first electrode layers 421 and 441 on the rear surface of the semiconductor substrate 10 An insulating film may be additionally formed.

1 and 2, the first conductive type region 32 and the second conductive type region 34 and the second electrode layers 422 and 442 of the first and second electrodes 42 and 44, Will be described in detail.

1 and 2, in the present embodiment, the first conductive type region 32 and the second conductive type region 34 are formed to be long in a stripe shape, and alternate with each other in the direction crossing the longitudinal direction Respectively. Although not shown, a plurality of first conductive regions 32 spaced apart from each other may be connected to each other at one edge, and a plurality of second conductive regions 34 separated from each other may be connected to each other at the other edge. However, the present invention is not limited thereto.

At this time, the area of the first conductivity type region 32 may be larger than the area of the second conductivity type region 34. In one example, the areas of the first conductivity type region 32 and the second conductivity type region 34 can be adjusted by varying their widths. That is, the width W1 of the first conductivity type region 32 may be greater than the width W2 of the second conductivity type region 34. [

The second electrode layer 422 of the first electrode 42 is formed in a stripe shape corresponding to the first conductivity type region 32 and the second electrode layer 442 of the second electrode 44 is formed of a second conductive type And may be formed in a stripe shape corresponding to the region 34. [ The first electrode layer 421 of the first electrode 42 is formed in a stripe shape having a wider area than the second electrode layer 422 and the first electrode layer 421 of the first electrode 42 is formed in a stripe shape, The electrode layer 441 may be formed in a stripe shape having a larger area than the second electrode layer 442. Although not shown in the figure, the first electrodes 42 may be connected to each other at one edge, and the second electrodes 44 may be connected to each other at the other edge. However, the present invention is not limited thereto.

Referring again to FIG. 1, the front electro-depositing layer 30 may be positioned on the front surface of the semiconductor substrate 10. For example, the front field-generating layer 30 may be formed in contact with the entire surface of the semiconductor substrate 10 to simplify the structure and maximize the effect of forming the electric field region. However, the present invention is not limited thereto.

The front electroluminescence layer 30 may be composed of a film having a fixed charge or a metal compound layer capable of selectively collecting electrons or holes as described above. For example, the front electro-depositing layer 30 may be an aluminum oxide layer comprising aluminum oxide with a fixed charge. Alternatively, the front electro-forming layer 30 may be composed of a molybdenum oxide layer, a tungsten oxide layer, a vanadium oxide layer, a titanium oxide layer, or a zinc oxide layer capable of selectively collecting electrons or holes. Or the front electroplating layer 30 may be a layer including a plurality of the above-described layers.

At this time, the front electroplating layer 30 may be formed of the same layer as one of the metal compound layers constituting the first or second conductivity type regions 32 and 34, thereby simplifying the manufacturing process. For example, the front electro-depositing layer 30 and the second conductivity type region 34 may be formed of a titanium oxide layer.

The front electric field generating layer 30 may include a fixed charge in a state where it is not connected to the external circuit or the electrodes 42 and 44 connected to the other solar cells 100 or may selectively collect electrons or holes, It is possible to exhibit the effect of having a constant electric field region preventing the recombination in the vicinity of the front surface of the substrate 10. In this case, the semiconductor substrate 10 does not have a separate doping region but consists only of the base region 110, thereby minimizing defects in the semiconductor substrate 10. [

The front electro-depositing layer 30 may be composed of a compound (e.g., oxide) to effectively passivate the entire surface of the semiconductor substrate 10. [

At this time, the thickness of the front electro-forming layer 30 may be equal to or less than the thickness of the first or second conductivity type regions 32 and 34. This is because the front field-effect forming layer 30 is not a layer for transferring the carriers to the outside and may have a relatively small thickness. For example, the thickness of the front electro-forming layer 30 may be 1 nm to 10 nm. It is possible to sufficiently realize the effect of the front electric field generating layer 30 in this thickness. However, the present invention is not limited to the thickness of the front electrode layer 30.

As another modification, a doped region of a conductive type such as the base region 110 is doped to the entire surface of the semiconductor substrate 10 at a high concentration to form a doped region without forming the front electric field generating layer 30, It can also be used as an electric field area.

The transparent conductive film 24 can be positioned (for example, in contact) on the front surface of the semiconductor substrate 10 or on the front electro-forming layer 30. The transparent conductive film 24 is a floating electrode that is not connected to an external circuit or other solar cell 100. Such a floating electrode can prevent unnecessary ions and the like from gathering on the surface side of the semiconductor substrate 10. [ Accordingly, it is possible to prevent degradation caused by ions or the like (for example, a potential induced degradation (PID)) in a solar cell module in a high temperature and high humidity environment.

For example, the transparent conductive film 24 may include indium tin oxide (ITO), carbon nano tube (CNT), and the like. However, the present invention is not limited thereto, and the transparent conductive film 24 may include various other materials.

The transparent conductive film 24 is not an indispensable film, and the transparent conductive film 24 may not be provided.

The antireflection film 26 can be positioned (for example, in contact) on the front surface of the semiconductor substrate 10 or on the transparent conductive film 24.

The antireflection film 26 reduces the reflectance of light incident on the front surface of the semiconductor substrate 10. The amount of light reaching the pn junction formed at the interface between the base region 110 and the first conductive type region 32 can be increased. Accordingly, the short circuit current Isc of the solar cell 100 can be increased.

The antireflection film 26 may be formed of various materials. For example, the antireflection film 26 may be formed of any one selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a silicon carbide film, MgF 2 , ZnS, TiO 2, and CeO 2 A single film or a multilayer film structure in which two or more films are combined. In one example, the antireflection film 26 may be a silicon nitride film.

The front electro-film forming layer 30, the transparent conductive film 24, and the anti-reflection film 26 may be formed entirely on the entire surface of the semiconductor substrate 10. Here, the term " formed as a whole " includes not only completely formed physically but also includes cases where there are inevitably some exclusion parts. Thus, the manufacturing process can be simplified and the role of each layer can be sufficiently exhibited.

When light is incident on the solar cell 100 according to the present embodiment, electrons and holes are generated by photoelectric conversion, and the generated holes and electrons are tunneled through the tunneling layer 20 to form the first conductivity type regions 32 and And is transferred to the first and second electrodes 42 and 44 after moving to the second conductivity type region 34. The holes and electrons transferred to the first and second electrodes 42 and 44 move to an external circuit or another solar cell 100. Thereby generating electrical energy.

In the solar cell 100 having the rear electrode structure in which the electrodes 42 and 44 are formed on the rear surface of the semiconductor substrate 10 and electrodes are not formed on the front surface of the semiconductor substrate 10 as in the present embodiment, The shading loss can be minimized at the front of the display device. Thus, the efficiency of the solar cell 100 can be improved. However, the present invention is not limited thereto. Particularly, in this embodiment, since at least one of the first and second conductivity type regions 32 and 34 is formed of the metal compound layer, the second electrode layers 422 and 442 of the electrodes 42 and 44, Can be widely formed. In this case, the rear electrode structure can be applied to prevent the problem caused by the shading loss.

Since the first and second conductive regions 32 and 34 are formed on the semiconductor substrate 10 with the tunneling layer 20 interposed therebetween, the first and second conductive type regions 32 and 34 are formed of different layers from the semiconductor substrate 10. As a result, the loss due to the recombination can be minimized as compared with the case where the doped region formed by doping the semiconductor substrate 10 with the dopant is used as the conductive type region.

At this time, since the first and second conductivity type regions 32 and 34 do not include a semiconductor material and a dopant, problems caused by recombination can be minimized and the passivation effect can be improved. And the manufacturing process of the first and second conductivity type regions 32 and 34 can be simplified. Thus, efficiency and productivity of the solar cell 100 can be improved.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
10: semiconductor substrate
110: Base area
20: Tunneling layer
30: front field-
32: first conductivity type region
34: second conductivity type region
42: first electrode
44: Second electrode

Claims (20)

1. A semiconductor device comprising: a semiconductor substrate comprising a semiconductor material;
A tunneling layer located on one side of the semiconductor substrate;
A first conductive type region and a second conductive type region which are located on the tunneling layer and have opposite conductivity types; And
A first electrode electrically connected to the first conductivity type region, and a second electrode electrically connected to the second conductivity type region,
/ RTI >
Wherein at least one of the first conductive type region and the second conductive type region is composed of a metal compound layer. The method according to claim 1,
Wherein at least one of the first conductive type region and the second conductive type region is composed of a metal oxide layer. The method according to claim 1,
Wherein at least one of the first conductive type region and the second conductive type region does not include the semiconductor material and the material that acts as a dopant in the semiconductor material. The method according to claim 1,
Wherein the semiconductor substrate comprises silicon as the semiconductor material having an n-type conductivity. 5. The method of claim 4,
Wherein the first conductivity type region is composed of a metal compound layer,
The Fermi level of the first conductivity type region is lower than the Fermi level of the semiconductor substrate,
Wherein a work function of the first conductivity type region is larger than a work function of the semiconductor substrate. 6. The method of claim 5,
And a work function of the first conductivity type region is 7 eV or less. 5. The method of claim 4,
Wherein the first conductive type region comprises a molybdenum oxide layer, a tungsten oxide layer, or a vanadium oxide layer. 5. The method of claim 4,
The second conductivity type region is composed of a metal compound layer,
The Fermi level of the second conductivity type region is higher than the Fermi level of the semiconductor substrate,
Wherein a work function of the second conductivity type region is smaller than a work function of the semiconductor substrate. 9. The method of claim 8,
Wherein the energy band gap between the conduction band of the second conductivity type region and the conduction band of the semiconductor substrate is 1 eV or less. 5. The method of claim 4,
And the second conductivity type region is composed of a titanium oxide layer or a zinc oxide layer. 5. The method of claim 4,
Wherein the first conductivity type region and the second conductivity type region are each composed of a metal compound layer,
Wherein the first conductivity type region comprises a molybdenum oxide layer, a tungsten oxide layer, or a vanadium oxide layer,
And the second conductivity type region is composed of a titanium oxide layer or a zinc oxide layer. The method according to claim 1,
Wherein at least one of the first conductive type region and the second conductive type region has a thickness of 1 nm to 100 nm. The method according to claim 1,
The electrode connected to at least one of the first conductive type region and the second conductive type region includes a first electrode layer including a transparent conductive material and a second electrode layer formed on the first electrode layer and having a pattern Solar cells. The method according to claim 1,
And a front electric field generating layer disposed on the other surface of the semiconductor substrate and composed of a layer containing a fixed charge or containing a metal compound. 15. The method of claim 14,
Wherein the front dielectric constant layer comprises at least one of an aluminum oxide layer, a molybdenum oxide layer, a tungsten oxide layer, a vanadium oxide layer, a titanium oxide layer, and a zinc oxide layer. 15. The method of claim 14,
Wherein the metal compound layer in the at least one of the first conductive type region and the second conductive type region is made of the same material as the layer including the metal compound in the front electric field generating layer. 15. The method of claim 14,
Wherein a thickness of the front electro-film forming layer is equal to or smaller than at least one of the first conductive type region and the second conductive type region. 15. The method of claim 14,
And the thickness of the front electric field generating layer is 1 nm to 10 nm. The method according to claim 1,
Wherein at least one of a transparent conductive film including a transparent conductive material and an anti-reflection film for preventing reflection is formed on the front surface of the semiconductor substrate. The method according to claim 1,
Wherein the semiconductor substrate comprises only a base region and does not have a doped region.
KR1020150138657A 2015-03-17 2015-10-01 Solar cell KR20170039472A (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
KR1020150138657A KR20170039472A (en) 2015-10-01 2015-10-01 Solar cell
US15/071,923 US10566483B2 (en) 2015-03-17 2016-03-16 Solar cell
JP2016053859A JP6505627B2 (en) 2015-03-17 2016-03-17 Solar cell
EP17185839.2A EP3261133B1 (en) 2015-03-17 2016-03-17 Solar cell
EP16160828.6A EP3070750B1 (en) 2015-03-17 2016-03-17 Solar cell
EP16191774.5A EP3151289A1 (en) 2015-10-01 2016-09-30 Solar cell
US15/282,482 US20170098722A1 (en) 2015-10-01 2016-09-30 Solar cell
JP2016195586A JP2017069567A (en) 2015-10-01 2016-10-03 Solar cell
JP2017087299A JP6522684B2 (en) 2015-03-17 2017-04-26 Solar cell

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