KR20180104250A - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a three-dimensional semiconductor memory device using a photoresist pattern with enhanced resistance to a trimming process. More specifically, the method comprises the following steps: forming a stacked structure including insulating films and sacrificial films alternately and repeatedly stacked on a substrate; forming a first photoresist pattern on the stacked structure; and etching one end of the stacked structure with the first photoresist pattern as a mask to form the end in a step shape. The first photoresist pattern contains a copolymer including units of first to third chemical formulas.

Description

[0001] The present invention relates to a method for manufacturing semiconductor devices,

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a three-dimensional semiconductor memory device.

It is required to increase the degree of integration of semiconductor devices in order to meet the excellent performance and low price required by consumers. In the case of a semiconductor memory device, the degree of integration is an important factor in determining the price of the product, and therefore, an increased degree of integration is required in particular. In the case of a conventional two-dimensional or planar semiconductor memory device, the degree of integration is largely determined by the area occupied by the unit memory cell, and thus is greatly influenced by the level of the fine pattern formation technique. However, the integration of the two-dimensional semiconductor memory device is increasing, but is still limited, because of the need for expensive equipment to miniaturize the pattern.

In order to overcome these limitations, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass-produce a three-dimensional semiconductor memory device, a process technology capable of reducing the manufacturing cost per bit of the two-dimensional semiconductor memory device and realizing a reliable product characteristic is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device using a photoresist pattern having enhanced tolerance to a trimming process.

According to the concept of the present invention, a method of manufacturing a semiconductor device includes forming a laminated structure including insulating films and sacrificial films alternately and repeatedly stacked on a substrate; Forming a first photoresist pattern on the laminated structure; And etching the one end of the laminated structure with the first photoresist pattern as a mask to form the one end in a stepped shape. The first photoresist pattern may contain a copolymer comprising units of the following general formulas (1) and (3).

[Chemical Formula 1]

(2)

In Formula 1 and Formula 2, wherein R ₁ and R ₂ each independently is a hydrocarbon group having 1 to 20 carbon atoms substituted with hydrogen, a hydrocarbon, or a -OR ₁₁ group having 1 to 20 carbon atoms, wherein R ₁₁ is C1-C10 alkyl Wherein p is an integer from 1 to 10, and q is an integer from 1 to 10, and the copolymer is selected from the group consisting of: < RTI ID = 0.0 >Lt; RTI ID = 0.0 > 100,000. ≪ / RTI >

The copolymer may further include a unit represented by the following formula (3).

(3)

In Formula 3, R ₃ is independently hydrogen, a hydrocarbon having 1 to 20 carbon atoms, or a hydrocarbon having 1 to 20 carbon atoms substituted with -OR ₁₁ , and R ₁₁ is selected from the group consisting of C 1 -C 10 alkyl, C 2 -C 10 alkenyl , C2-C10 alkynyl, C6-C10 aryl or C3-C10 cycloalkyl, and r may be an integer from 1 to 10.

The copolymer may be a random copolymer in which the units are randomly polymerized.

The first photoresist pattern may further contain a radiation-sensitive acid generator, and the radiation-sensitive acid generator may be an onium salt compound having a fluoroalkylsulfonic acid ion having 1 to 10 carbon atoms as an anion.

The forming of the one end in the stepped shape may include repeating the cycle by making the following steps one cycle. Etching at least one of the insulating films exposed by the first photoresist pattern using the first photoresist pattern as a mask; Etching at least one of the sacrificial layers under the at least one insulating layer; And trimming the first photoresist pattern to reduce its width and height.

Trimming the first photoresist pattern comprises: reducing the width by a first length; And reducing the height by a second length. The second length may be greater than the first length and less than 1.5 times the first length.

The cycle may be repeated until the insulating film and the sacrificial layer at the lowermost layer of the laminated structure are etched.

Wherein one end of the laminated structure includes a first contact region adjacent to the cell array region and a second contact region spaced apart from the cell array region via the first contact region, Forming a second photoresist pattern containing the copolymer on the laminate structure; forming a second photoresist pattern on the laminate structure; And etching the second contact region using the second photoresist pattern as a mask to form the second contact region in a stepped shape.

Wherein one end of the laminated structure includes a first contact region adjacent to the cell array region and a second contact region spaced apart from the cell array region via the first contact region, The first photoresist pattern is formed in a stepped shape, the method comprising: forming a lower film and a second photoresist pattern on the laminated structure; Etching the lower film using the second photoresist pattern as a mask to form a lower pattern; And etching the second contact region using the lower pattern as a mask to form the second contact region in a stepped shape.

The lower film may include a novolac-based organic polymer, and the second photoresist pattern may include a polymer containing silicon.

Forming channel holes through the cell array region of the stacked structure to expose the substrate; And sequentially forming, in each of the channel holes, a gate insulating film and a channel film covering the inner wall thereof.

The manufacturing method may further include selectively removing the sacrificial layers to form recessed regions between the insulating films; And forming gate electrodes LSL, WL1, WL2, USL filling the recessed regions.

The shape of one end of each of the gate electrodes LSL, WL1, WL2, and USL corresponds to the step shape in the form of one end of the sacrificial films, and the manufacturing method includes the step of passing through at least one end of the insulating films, And forming a contact electrically connected to the one end of the at least one gate electrode (LSL, WL1, WL2, USL).

According to another aspect of the present invention, a method of manufacturing a semiconductor device includes: preparing a photoresist composition; Forming a photoresist pattern on the film to be etched on the substrate using the photoresist composition; And etching the etch target film using the photoresist pattern as an etch mask. The preparation of the photoresist composition comprises subjecting a mixture containing substituted or unsubstituted 4-hydroxystyrene and substituted acrylate to a polymerization reaction to form a copolymer, The weight ratio of 4-hydroxystyrene to acrylate in the mixture may be from 95: 5 to 60:40.

The copolymer has a weight average molecular weight of 1,000 to 100,000 and includes units of the following general formulas (1) and (2), and optionally may include units of the following general formula (3).

[Chemical Formula 1]

(2)

(3)

Wherein R ₁ to R ₃ are each independently hydrogen, a hydrocarbon having 1 to 20 carbon atoms, or a hydrocarbon having 1 to 20 carbon atoms substituted with -OR ₁₁ , and R ₁₁ is selected from the group consisting of C 1 -C 10 alkyl , P is an integer from 1 to 10, q is an integer from 1 to 10, and r is an integer from 1 to 10, and R < 2 >Lt; / RTI >

The manufacturing method may further include trimming the photoresist pattern to reduce its width by a first length and reducing its height by a second length. The second length may be greater than the first length and less than 1.5 times the first length.

The manufacturing method may further include repeating the etching step and the trimming step to form one end of the etching target film in a stepped shape.

A method of manufacturing a semiconductor device according to the present invention can form a three-dimensional memory device having a stepped structure by using a photoresist pattern having enhanced resistance to vertical etching in a trimming process. As a result, a large number of step structures can be formed through a single photoresist process, thereby simplifying the process.

1 is a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to embodiments of the present invention.
2 is a plan view of a three-dimensional semiconductor memory device according to embodiments of the present invention.
FIG. 3 is a cross-sectional view of a semiconductor memory device according to embodiments of the present invention, taken along the line I-I 'of FIG. 2. Referring to FIG.
FIGS. 4 to 22 are cross-sectional views taken along line I-I 'of FIG. 2, illustrating a method of manufacturing a three-dimensional semiconductor memory device according to embodiments of the present invention.
FIGS. 23 to 26 are cross-sectional views taken along line I-I 'of FIG. 2, illustrating a method of manufacturing a three-dimensional semiconductor memory device according to embodiments of the present invention.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be embodied in various forms and various modifications may be made. It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

In this specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thickness of the components is exaggerated for an effective description of the technical content. The same reference numerals denote the same elements throughout the specification.

Embodiments described herein will be described with reference to cross-sectional views and / or plan views that are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention. Although the terms first, second, third, etc. in the various embodiments of the present disclosure are used to describe various components, these components should not be limited by these terms. These terms have only been used to distinguish one component from another. The embodiments described and exemplified herein also include their complementary embodiments.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms "comprises" and / or "comprising" used in the specification do not exclude the presence or addition of one or more other elements.

1 is a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 1, a cell array of a three-dimensional semiconductor memory device according to embodiments of the present invention includes a common source line CS, a plurality of bit lines BL, And a plurality of cell strings CSTR disposed between the plurality of cell strings BL.

The common source line CS may be an electrically conductive thin film disposed on the substrate or an impurity region formed in the substrate. In the present embodiments, the common source line CS may be conductive patterns (e.g., metal lines) spaced from the substrate and disposed on the substrate. The bit lines BL may be conductive patterns (e.g., metal lines) spaced from the substrate and disposed on the substrate. In the present embodiments, the bit lines BL may be vertically spaced apart from the common source line CS. The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR may be connected in parallel. The cell strings CSTR may be connected in common to the common source line CS. That is, a plurality of the cell strings CSTR may be disposed between the plurality of bit lines BL and the common source line CS. According to one embodiment, the common source lines CS are provided in plural and can be two-dimensionally arranged. Here, electrically the same voltage may be applied to the common source lines CS, or each of the common source lines CS may be electrically controlled.

Each of the cell strings CSTR includes a ground selection transistor GST connected to the common source line CS, a string selection transistor SST connected to the bit line BL, And a plurality of memory cell transistors MCT arranged between the memory cells GST and SST. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CS may be connected in common to the sources of the ground selection transistors GST. In addition, a lower select line LSL, a plurality of word lines WL0-WL5 and an upper select line USL, which are disposed between the common source line CS and the bit lines BL, May be used as the gate electrodes of the selection transistor GST, the memory cell transistors MCT and the string selection transistor SST, respectively. In addition, each of the memory cell transistors MCT may include a data storage element.

2 is a plan view of a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 3 is a cross-sectional view of a semiconductor memory device according to embodiments of the present invention, taken along the line I-I 'of FIG. 2. Referring to FIG.

A substrate 100 may be provided. The substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may include common source regions (CSL) doped with impurities. The common source regions CSL may have a line shape extending in a second direction D2 parallel to the upper surface of the substrate 100. [ The common source regions CSL may be arranged along a first direction D1 that intersects the second direction D2.

The first stacking structures ST1 and the second stacking structures ST2 in which the insulating films 110 and the gate electrodes LSL, WL1, WL2, and USL are alternately and repeatedly stacked on the substrate 100, Can be arranged. The second lamination structures ST2 may be disposed on the first lamination structures ST1, respectively. Each of the stacking structures ST1 and ST2 may have a line shape extending in the second direction D2 from a plan viewpoint. Each of the stacked structures ST1 and ST2 may be arranged along the first direction D1.

The common source regions CSL may be disposed on the substrate 100 between the stacked structures ST1 and ST2. A lower insulating layer 105 may be disposed between the substrate 100 and the first stacked structures ST1. The lower insulating layer 105 may include, for example, a high dielectric constant layer such as a silicon nitride layer, an aluminum oxide layer, or a hafnium oxide layer. The lower insulating layer 105 may have a thickness smaller than that of the insulating layers 110.

The gate electrodes LSL, WL1, WL2 and USL may be stacked in a third direction D3 perpendicular to the first direction D1 and the second direction D2. The gate electrodes LSL, WL1, WL2 and USL may be vertically separated from each other by the insulating films 110 disposed between the gate electrodes LSL, WL1, WL2 and USL. For example, the gate electrodes LSL and WL1 of each of the first lamination structures ST1 may include a lower selection line LSL and first word lines WL1. The gate electrodes WL2 and USL of each of the second lamination structures ST2 may include an upper select line USL and second word lines WL2. In one example, the gate electrodes LSL, WL1, WL2, USL may comprise doped silicon, metal (e.g., tungsten), metal nitride, metal silicides, or combinations thereof. The insulating films 110 may include a silicon oxide film.

The lower selection line LSL may be the lowest gate electrode among the gate electrodes LSL and WL1 of the first lamination structures ST1. The lower selection line LSL may be used as the gate electrode of the ground selection transistor GST described above with reference to FIG. The upper select line USL may be the uppermost gate electrode among the gate electrodes WL2 and USL of the second stacked structures ST2. The upper selection line USL may be used as a gate electrode of the string selection transistor SST described above with reference to FIG. The first and second word lines WL1 and WL2 may be used as gate electrodes of the memory cell transistors MCT described with reference to FIG.

Each of the stacked structures ST1 and ST2 may include a cell array region CAR, a first contact region CTR1, and a second contact region CTR2. The first and second contact regions CTR1 and CTR2 may be disposed at at least one end of the stacked structure ST1 and ST2. The first contact region CTR1 may be a region of one end of the first lamination structure ST1 and the second contact region CTR2 may be a region of a first end of the second lamination structure ST2. have. For example, the second contact region CTR2 may be adjacent to the cell array region CAR. The first contact region CTR1 may be spaced apart from the cell array region CAR via the second contact region CTR2.

Each of the stacked structures ST1 and ST2 is electrically connected to the first and second contact regions CTR1 and CTR2 for electrical connection between the gate electrodes LSL, WL1, WL2 and USL and the peripheral logic structure, CTR2). ≪ / RTI > That is, the vertical height of the first and second contact regions CTR1 and CTR2 may gradually increase as the cell array region CAR is adjacent to the first and second contact regions CTR1 and CTR2. In other words, the stacked structures ST1 and ST2 may have a sloped profile in the first and second contact regions CTR1 and CTR2.

As the gate electrodes LSL and WL1 of the first contact region CTR1 are away from the upper surface of the substrate 100 in the third direction D3, their planar area can be reduced. Therefore, the area of the lower selection line LSL in the lowest layer among the gate electrodes LSL and WL1 may be the largest. As the gate electrodes WL2 and USL of the second contact region CTR2 are away from the upper surface of the substrate 100 in the third direction D3, their planar area can be reduced. Therefore, the area of the upper select line USL in the uppermost layer among the gate electrodes WL2 and USL may be the smallest.

A first interlayer insulating layer 180 may be disposed on the entire surface of the substrate 100 to cover the stacked structures ST1 and ST2. The first interlayer insulating layer 180 has a planarized upper surface and may cover the first and second contact regions CTR1 and CTR2. A second interlayer insulating film 190 may be disposed on the first interlayer insulating film 180.

A plurality of channel holes CH passing through the cell array region CAR of the stacked structures ST1 and ST2 may be disposed. A plurality of channel films 135 may extend toward the substrate 100 along the inner walls of the channel holes CH. The channel layers 135 may be electrically connected to the substrate 100. That is, the channel films 135 may be in direct contact with the upper surface of the substrate 100. The channel films 135 may be arranged along the second direction D2 from a plan viewpoint. For example, the channel films 135 may be arranged in one direction along the second direction D2. As another example, the channel films 135 may be arranged in a zigzag manner along the second direction D2.

In one example, the channel films 135 may be in the form of an opened pipe or macaroni at the top and bottom. As another example, the channel films 135 may be in the form of a closed pipe or macaroni at the bottom.

The channel films 135 may be in an unselected state or may be doped with an impurity having the same conductivity type as the substrate 100. The channel layers 135 may include a semiconductor material having a polycrystalline structure or a single crystal structure. As an example, the channel films 135 may comprise silicon. The inside of the channel films 135 may be filled with a buried insulating pattern 150. For example, the buried insulation pattern 150 may include a silicon oxide layer.

Gate insulating films 145 may be interposed between the stacked structures ST1 and ST2 and the channel films 135. [ That is, each of the gate insulating films 145 may directly cover the inner wall of the channel hole CH. The gate insulating films 145 may extend along the third direction D3. The gate insulating films 145 may be formed in a pipe shape or a macaroni shape with open upper and lower ends.

Each of the gate insulating films 145 may include one thin film or a plurality of thin films. In one embodiment, the gate insulating layer 145 may include a tunnel insulating layer and a charge storage layer of a charge trap type flash memory transistor. The tunnel insulating film may be one of materials having a band gap larger than that of the charge storage film. For example, the tunnel insulating film may be one of high-k films such as an aluminum oxide film and a hafnium oxide film. The charge storage film may be one of an insulating film rich in trap sites such as a silicon nitride film, a floating gate electrode, or an insulating film including conductive nano dots. The tunnel insulating layer may contact the channel layer 135 directly. On the other hand, although not shown, a blocking insulating film may be interposed between each of the gate electrodes LSL, WL1, WL2, and USL and the charge storage film. The blocking insulating layer may extend between each of the gate electrodes LSL, WL1, WL2, and USL and the insulating layer 110. The blocking insulating layer may be one of materials having a smaller band gap than the tunnel insulating layer and a band gap larger than that of the charge storage layer. For example, the blocking insulating film may be one of high-k films such as an aluminum oxide film and a hafnium oxide film.

In another embodiment, the gate insulating layer 145 may include the tunnel insulating layer, the charge storage layer, and the blocking insulating layer. The tunnel insulating layer may directly contact the channel layer 135, and the blocking insulating layer may directly contact the gate electrodes LSL, WL1, WL2, and USL. The charge storage film may be interposed between the tunnel insulating film and the blocking insulating film. At this time, the gate electrodes LSL, WL1, WL2, and USL may be in direct contact with the insulating films 110. [

The buried insulating film 170 can fill the trenches TR between the adjacent stacked structures ST1 and ST2. The buried insulating layer 170 may include a silicon oxide layer.

An upper portion of each of the channel films 135 may include a drain region DR. Conductive pads 160 that are in contact with the drain regions DR of the channel films 135 may be disposed. The second interlayer insulating layer 190 may cover the conductive pads 160. And bit line contact plugs electrically connected to the conductive pads 160 through the second interlayer insulating film 190 may be disposed. The bit lines BL may be disposed on the bit line contact plugs. Each of the bit lines BL may be electrically connected to the plurality of conductive pads 160 through a plurality of the bit line plugs BPLG. The bit lines BL may be in the form of a line extending in the first direction D1.

A wiring structure for electrically connecting the gate electrodes LSL, WL1, WL2, USL and the peripheral logic structure may be disposed on the first and second contact regions CTR1 and CTR2.

Specifically, the first contact plug CTL1 is formed on the first contact plug CTL1 through the first and second interlayer insulating films 180 and 190 and is connected to one ends of the gate electrodes LSL and WL1, (PLG1) may be disposed. The second contact plug CTR2 is connected to one end of each of the gate electrodes WL2 and USL through the first and second interlayer insulating films 180 and 190, (PLG2) may be disposed. The vertical lengths of the first and second contact plugs PLG1 and PLG2 can be reduced as they are adjacent to the cell array region CAR. The upper surfaces of the first and second contact plugs PLG1 and PLG2 may be coplanar.

In addition, first connection lines CL1 electrically connected to the first contact plugs PLG1 may be disposed on the second interlayer insulating film 190 of the first contact region CTR1. Second connection lines CL2 electrically connected to the second contact plugs PLG2 may be disposed on the second interlayer insulating layer 190 of the second contact region CTR2.

FIGS. 4 to 22 are cross-sectional views taken along line I-I 'of FIG. 2, illustrating a method of manufacturing a three-dimensional semiconductor memory device according to embodiments of the present invention.

2 and 4, stacked structures ST1 and ST2 may be formed by alternately and repeatedly depositing sacrificial layers HL1 and HL2 and insulating layers 110 on a substrate 100 . Specifically, the stacked structures ST1 and ST2 may include a first stacked structure ST1 on the substrate 100 and a second stacked structure ST2 on the first stacked structure ST1. The first stack structure ST1 may include first sacrificial layers HL1 and the second stack structure ST2 may include second sacrificial layers HL2.

For example, the sacrificial layers HL1 and HL2 may be formed to have the same thickness. As another example, the sacrificial layers (HL1, HL2) of the lowermost layer and the uppermost layer of the sacrificial films (HL1, HL2) may be formed thicker than the sacrificial films (HL1, HL2) located therebetween. The insulating films 110 may have the same thickness or a part of the insulating films 110 may have different thicknesses.

The sacrificial films HL1 and HL2 and the insulating films 110 may be formed by thermal CVD, plasma enhanced chemical vapor deposition, physical CVD, or atomic layer deposition Atomic layer deposition (ALD) process. The sacrificial films HL1 and HL2 may be formed of a silicon nitride film, a silicon oxynitride film, or a silicon film. The sacrificial films HL1 and HL2 may include a polycrystalline structure or a single crystal structure. The insulating films 110 may be formed of a silicon oxide film.

In addition, a lower insulating layer 105 may be formed between the substrate 100 and the first stacked structure ST1. The lower insulating layer 105 may be formed of a material having a high selectivity to the sacrificial layers (HL1, HL2) and the insulating layers (110). For example, the lower insulating layer 105 may include a high-k dielectric layer such as a silicon nitride layer, an aluminum oxide layer, or a hafnium oxide layer. The lower insulating layer 105 may be formed to have a thickness smaller than that of the sacrificial layers (HL1, HL2) and the insulating layers (110).

Referring to FIGS. 2 and 5, channel holes CH may be formed to expose the substrate 100 through the stacked structures ST1 and ST2. The channel holes CH may be arranged like the channel films 135 described above with reference to Figs. 2 and 3.

The formation of the channel holes CH may be performed by forming a mask pattern having openings defining regions in which the channel holes CH are to be formed on the stacked structures ST1 and ST2, And etching the stacked structures ST1 and ST2 with a mask. Thereafter, the mask patterns can be removed. Meanwhile, during the etching process, the upper surface of the substrate 100 may be over-etched. Accordingly, the upper surface of the substrate 100 can be recessed.

2 and 6, a gate insulating layer 145 and a channel layer 135 may be formed to sequentially cover the inner wall of each of the channel holes CH. For example, the gate insulating layer 145 may include a tunnel insulating layer and a charge storage layer. As another example, the gate insulating layer 145 may further include a blocking insulating layer. At this time, the blocking insulating layer may be interposed between the sacrificial layers (HL1, HL2) and the charge storage layer. The gate insulating layer 145 and the channel layer 135 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD), respectively. Then, a buried insulation pattern 150 filling the respective channel holes CH may be formed.

Referring to FIGS. 2 and 7, a first photoresist pattern PR1 may be formed on the second stack structure ST2. The first photoresist pattern PR1 may be formed on the cell array region CAR where the channel films 135 are located and on the second contact region CTR2 adjacent to the cell array region CAR. have. The first photoresist pattern PR1 may expose a first contact region CTR1 spaced apart from the cell array region CAR via the second contact region CTR2.

Specifically, the first photoresist pattern PR1 is formed by preparing a photoresist composition, applying the photoresist composition on the entire surface of the substrate 100 to form a photoresist film, And exposing and developing the resist film to form the first photoresist pattern PR1.

The preparation of the photoresist composition may comprise subjecting a mixture containing substituted or unsubstituted 4-hydroxystyrene and acrylate to a polymerization reaction to synthesize a copolymer. have. 4-hydroxystyrene or acrylate may be substituted with a hydrocarbon described later. Here, before the polymerization reaction, the weight ratio of 4-hydroxystyrene to acrylate in the mixture may be 95: 5 to 60:40. More specifically, the weight ratio of 4-hydroxystyrene: acrylate in the mixture may be from 90:10 to 80:20.

The synthesized copolymer may include units represented by the following general formulas (1) and (2). The synthesized copolymer may further include a unit represented by the following formula (3).

[Chemical Formula 1]

(2)

(3)

In the above Chemical Formulas 1 to 3, each of R ₁ to R ₃ independently represents hydrogen, or a substituted or unsubstituted hydrocarbon group having 1 to 20 carbon atoms. The hydrocarbons may be selected from the group consisting of alkyl, alkenyl, alkynyl, cycloalkyl, cycloalkyl substituted with alkyl, aryl, aralkyl and alkaryl. The hydrocarbons may be substituted with -OR < ₁₁ >. Wherein R ₁₁ is C 1 -C 10 alkyl, C 2 -C 10 alkenyl, C 2 -C 10 alkynyl, C 6 -C 10 aryl or C 3 -C 10 cycloalkyl. In one example, the hydrocarbon may be substituted with alkoxy. The hydrocarbon may be an alkyl ether group having at least one alkyl ether group or an alkyleneoxy group. The alkyl ether group may be selected from the group consisting of ethoxy, propoxy and butoxy. P may be an integer of 1 to 10, q may be an integer of 1 to 10, and r may be an integer of 1 to 10. (Q / (p + q + r)) may be 0.5 to 0.2, and the fraction of r (p / (r / (p + q + r)) may be 0.2 to 0.4. The copolymer may have a weight average molecular weight of 1,000 to 100,000.

For example, the copolymer may include a polymer having the following formula (5).

[Chemical Formula 5]

The ratio of P: q: r in the above formula (5) is 55: 15: 30. The copolymer of formula (5) has a weight average molecular weight (Mw) of 15,000. The copolymer of formula (5) may be prepared by free radical polymerization, but is not limited thereto. As another example, the copolymer may be prepared by anionic polymerization.

The preparation of the photoresist composition includes mixing the synthesized copolymer with an organic solvent in a radiation-sensitive acid-generating compound, and a tertiary aliphatic amine compound (trialkanolamine) .

The radiation-sensitive acid generator may be a compound dissociated by irradiation with an actinic ray to generate an acid. The radiation-sensitive acid generator may be an onium salt compound having a fluoroalkyl sulfonic acid ion having 1 to 10 carbon atoms as an anion. For example, the radiation-sensitive acid generator may be at least one selected from the group consisting of diphenyliodonium trifluoromethane sulfonate and diphenyliodonium trifluoromethanesulfonate and nonafluorobutanesulfonate, bis (4-tert-butylphenyl) Fluoromethane sulfonate and bis (4-tert-butylphenyl) iodonium trifluoromethanesulfonate and nonafluorobutanesulfonate.

The tertiary aliphatic amine compound can improve the cross-sectional profile of the photoresist pattern after exposure to an actinic ray and improve its stability. For example, the tertiary aliphatic amine compound may be selected from the group consisting of trimethylamine, triethylamine, tri-n-propylamine, triisopropylamine, tri-n-butylamine, triisobutylamine, tri- Amines, triethanolamines, tributanolamines, or combinations thereof.

In the photoresist composition, the radiation-sensitive acid generator may be 1 to 10 parts by weight based on 100 parts by weight of the copolymer, and the tertiary aliphatic amine compound may be 0.01 to 1 part by weight.

In order to improve the performance of the photoresist film, an auxiliary resin, a plasticizer, a stabilizer, a colorant, a surfactant, and the like may further be added to the photoresist composition.

Referring to FIGS. 2 and 8, the insulating film 110 on the uppermost layer of the second contact region CTR2 and the second sacrificial layer HL2 on the uppermost layer of the second contact region CTR2 are etched using the first photoresist pattern PR1 as an etching mask. And can be sequentially etched. The etched insulating layer 110 and the etched second sacrificial layer HL2 may expose the other insulating layer 110 and the second sacrificial layer HL2 under the etched insulating layer 110 and the etched second sacrificial layer HL2.

Referring to FIGS. 2 and 9, a trimming process may be performed on the first photoresist pattern PR1. That is, an isotropic etching process may be performed on the first photoresist pattern PR1. Thus, the width and height of the first photoresist pattern PR1 can be reduced. Specifically, during the trimming process, the width of the first photoresist pattern PR1 may be reduced by a first length T1 and the height may be reduced by a second length T2.

The trimming process may be performed using an etchant capable of selectively removing the first photoresist pattern PR1. The length of the first photoresist pattern PR1 may be greater than the length of the first photoresist pattern PR1 where the width of the first photoresist pattern PR1 is reduced. This is because the area of the top surface of the first photoresist pattern PR1 is larger than the surface area of the sidewalls of the first photoresist pattern PR1.

On the other hand, when the photoresist composition according to the embodiments of the present invention is used, the decrease in the height of the first photoresist pattern PR1 can be minimized. In particular, the reduced second length T2 during the trimming process may be greater than the first length T1 and less than 1.5 times the first length T1. If the ranges of p, q, and r are out of the ranges of the above-mentioned Formulas 1 to 3, the second length T2 may be larger than 1.5 times the first length T1.

The steps described above with reference to FIGS. 8 and 9 may constitute one cycle for forming the sidewalls of the second contact region CTR2 in a stepped structure. That is, the cycle is performed using at least one of the insulating films 110 exposed by the first photoresist pattern PR1 and at least one of the second sacrificial films PR1, Etching the first photoresist pattern PR1, and trimming the first photoresist pattern PR1 to reduce its width and height. The repetition of the cycle will be described below.

Referring to FIGS. 2 and 10, the uppermost insulating layer 110 may be etched using the first photoresist pattern PR1 reduced in size by an etching mask. At the same time, the lower insulating layer 110 exposed by the uppermost insulating layer 110 and the second sacrificial layer HL2 may be etched together. Then, the uppermost second sacrificial layer HL2 may be etched using the first photoresist pattern PR1 as an etch mask. At the same time, the underlying second sacrificial film HL2 exposed by the second sacrificial layer HL2 of the uppermost layer can be etched together. The etched insulating films 110 and the etched second sacrificial films HL2 may expose the other insulating film 110 and the other second sacrificial film HL2 under the etched insulating films 110 and the etched second sacrificial films HL2.

Referring to FIGS. 2 and 11, the trimming process may be performed again on the first photoresist pattern PR1. During the trimming process, the width of the first photoresist pattern PR1 may be reduced by the first length T1 and the height may be reduced by the second length T2. This confirms that the cycle is repeated once more.

Referring to FIGS. 2 and 12, the cycle may be repeated until the insulation layer 110 and the second sacrificial layer HL2 in the lowermost layer of the second contact region CTR2 are etched. As a result, a part of the upper surface of the insulating film 110 on the uppermost layer of the first contact region CTR1 can be exposed.

Through the repetition of the cycle using the first photoresist pattern PR1, one end of the second stacked structure ST2 (i.e., the second contact region CTR2) may have a stepped structure. In addition, the size of the first photoresist pattern PR1 can be very small due to the repeated trimming process.

Referring to FIGS. 2 and 13, after removing the first photoresist pattern PR1, a photoresist film PL covering the stacked structures ST1 and ST2 may be formed. The photoresist film PL may be formed by applying the above-described photoresist composition on the entire surface of the substrate 100. The photoresist film PL may be formed to have a uniform thickness, and thus may be inclined on the second contact region CTR2.

Referring to FIGS. 2 and 14, a second photoresist pattern PR2 may be formed by exposing and developing the photoresist film PL. The second photoresist pattern PR2 may be formed on the cell array region CAR, the second contact region CTR2, and the first contact region CTR1. The second photoresist pattern PR2 may expose the insulating films 110 and the first sacrificial films HL1 outside the first contact region CTR1.

2 and 15, the insulating film 110 on the uppermost layer of the first contact region CTR1 and the first sacrificial layer HL1 on the uppermost layer of the first contact region CTR1 are etched using the second photoresist pattern PR2 as an etching mask, And can be sequentially etched. The etched insulating layer 110 and the etched first sacrificial layer HL1 may expose the other insulating layer 110 and the first sacrificial layer HL1 below them.

Referring to FIGS. 2 and 16, a trimming process may be performed on the second photoresist pattern PR2. During the trimming process, the width of the second photoresist pattern PR2 may be reduced by a first length T1 and the height may be reduced by a second length T2.

That is, the steps described above with reference to Figs. 15 and 16 may be the same as the one cycle described above with reference to Figs. 8 and 9. The cycle may then be repeated.

Referring to FIGS. 2 and 17, the uppermost insulating layer 110 may be etched using the second photoresist pattern PR2 reduced in size by an etching mask. At the same time, the uppermost insulating film 110 and the underlying insulating film 110 exposed by the first sacrificial film HL1 can be etched together. Then, the uppermost first sacrificial layer HL1 may be etched using the second photoresist pattern PR2 as an etch mask. At the same time, the underlying first sacrificial layer HL1 exposed by the first sacrificial layer HL1 of the uppermost layer may be etched together.

Referring to FIGS. 2 and 18, the trimming process may be performed again on the second photoresist pattern PR2. This confirms that the cycle is repeated once more.

Referring to FIGS. 2 and 19, the cycle can be repeated until the insulating film 110 and the first sacrificial layer HL1 in the lowermost layer of the first contact region CTR1 are etched. Thus, a part of the upper surface of the lower insulating film 105 can be exposed. Through the repetition of the cycle using the second photoresist pattern PR2, one end of the first stacked structure ST1 (i.e., the first contact region CTR1) may have a stepped structure. In addition, due to the repeated trimming process, the size of the second photoresist pattern PR2 can be very small.

2 and 20, after removing the second photoresist pattern PR2, a first interlayer insulating film 180 may be formed on the substrate 100 to cover the stacked structures ST1 and ST2. have. The first interlayer insulating layer 180 may be formed to cover the first and second contact regions CTR1 and CTR2. The first interlayer insulating film 180 may be planarized to expose the upper surface of the second laminated structure ST2.

The stacked structures ST1 and ST2 may be patterned to form trenches TR exposing the substrate 100 between adjacent channel holes CH. Specifically, forming the trenches TR may include forming mask patterns defining a planar position on which the trenches TR are to be formed on the stacked structures ST1 and ST2, And etching the stacked structures ST1 and ST2 with an etch mask.

The trenches TR may be formed to expose the sacrificial layers HL1 and HL2 and the sidewalls of the insulating films 110. [ In the vertical depth, the trenches TR may be formed to expose the sidewalls of the lower insulating layer 105. Also, although not shown, the trenches TR may have different widths depending on the vertical distance from the substrate 100 by an anisotropic etching process.

As the trenches TR are formed, the stacked structures ST1 and ST2 can be divided into a plurality of stacked structures ST1 and ST2. Each of the stacked structures ST1 and ST2 may have a line shape extending in the second direction D2. One of the stacked structures ST1 and ST2 may be penetrated by a plurality of the channel films 135. [

Referring to FIGS. 2 and 21, recessed regions 155 may be formed by selectively removing the sacrificial layers HL1 and HL2 exposed by the trenches TR. The recessed regions 155 may correspond to areas where the sacrificial layers HL1 and HL2 are removed. When the sacrificial films HL1 and HL2 include a silicon nitride film or a silicon oxynitride film, the removal process of the sacrificial films HL1 and HL2 may be performed using an etching solution containing phosphoric acid. Portions of the sidewalls of the gate insulating layer 145 may be exposed by the recessed regions 155.

Referring to FIGS. 2 and 22, gate electrodes LSL, WL1, WL2, and USL filling the recessed regions 155 may be formed. The formation of the gate electrodes LSL, WL1, WL2 and USL may be performed by forming a conductive film filling the recessed regions 155, And removing the membrane.

After the gate electrodes LSL, WL1, WL2, and USL are formed, common source regions CSL may be formed in the substrate 100. FIG. The common source regions CSL may be formed through an ion implantation process and may be formed in the substrate 100 exposed by the trenches TR. The common source regions CSL may form a PN junction with the substrate 100. Then, drain regions DR may be respectively formed on the channel films 135 through an ion implantation process.

If the gate insulating layer 145 includes the tunnel insulating layer and the charge storage layer, the blocking layer 155 may be formed by filling a portion of the recessed regions 155 before forming the gate electrodes LSL, WL1, WL2, and USL. An insulating film (not shown) may be additionally formed. Then, the gate electrodes LSL, WL1, WL2, and USL that completely fill the recessed regions 155 may be formed on the blocking insulating film.

Referring again to FIGS. 2 and 3, a buried insulating film 170 filling the trenches TR may be formed. The buried insulating layer 170 may include a silicon oxide layer.

And conductive pads 160 that are in contact with the upper surfaces of the channel films 135 may be formed. A second interlayer insulating layer 190 may be formed to cover the buried insulating layer 170, the conductive pads 160, and the first interlayer insulating layer 180. Bit line plugs (BPLG) that penetrate the second interlayer insulating layer 190 and are in contact with the conductive pads 160 may be formed.

On the other hand, first contact plugs PLG1 may be formed through the second interlayer insulating film 190 and connected to the gate electrodes LSL and WL1 of the first contact region CTR1, respectively. Second contact plugs PLG2 may be formed through the second interlayer insulating film 190 and connected to the gate electrodes WL2 and USL of the second contact region CTR2, respectively.

On the second interlayer insulating film 190, bit lines BL extending in a first direction D1 may be formed. Each of the bit lines BL may connect a plurality of the bit line plugs BPLG to each other. In addition, first and second connection lines CL1 and CL2 that are in contact with the first and second contact plugs PLG1 and PLG2 may be formed on the second interlayer insulating layer 190, respectively.

PHS-based photoresist patterns according to embodiments of the present invention may be resistant to vertical etching in the trimming process. As a result, a large number of step structures can be formed through a single photoresist process, thereby simplifying the process.

FIGS. 23 to 26 are cross-sectional views taken along line I-I 'of FIG. 2, illustrating a method of manufacturing a three-dimensional semiconductor memory device according to embodiments of the present invention. In the present embodiment, the detailed description of the technical features overlapping with the semiconductor device manufacturing method described above with reference to FIGS. 4 to 22 will be omitted, and the differences will be described in detail.

Referring to FIGS. 2 and 23, the lower film ULa and the third photoresist pattern PR3 may be formed on the resultant structure of FIG. The lower film ULa may be formed to cover the entire surface of the second laminated structure ST2. The third photoresist pattern PR3 may be formed on the cell array region CAR and the first and second contact regions CTR1 and CTR2.

Specifically, forming the lower film ULa may include coating an organic composition on the second laminated structure ST2 after removing the remaining first photoresist pattern PR1. The organic composition may include an organic polymer based on novolac. The organic composition may further comprise a crosslinking agent comprising a compound of the following formula (4).

[Chemical Formula 4]

Wherein at least two of R ₄ OOC (CX ₂ ) _n -, R ₅ - and R ₆ OOC (CX ₂ ) _m - can be different acid or ester groups and R ₄ , R ₅ , R ₆ and X May each independently be hydrogen or a non-hydrogen substituent. Wherein said non-hydrogen substituent is selected from substituted or unsubstituted C1-10 alkyl, substituted or unsubstituted C2-10 alkenyl or C2-10 alkynyl (e.g., allyl, etc.), substituted or unsubstituted C1-10 alkanoyl , Substituted or unsubstituted C1-10 alkoxy (e.g., methoxy, propoxy, butoxy, etc.), epoxy, substituted or unsubstituted C1-10 alkylthio, substituted or unsubstituted C1-10 alkylsulfinyl, Substituted or unsubstituted C6-io aryl (e.g., phenyl, naphthyl, etc.), substituted or unsubstituted C1-8 alkylsulfonyl, substituted or unsubstituted carboxy, substituted or unsubstituted -COO- Or a substituted or unsubstituted 5- to 10-membered heteroalicyclic or heteroaryl group (e.g., methylphthalimide, N-methyl-1,8-phthalimide, etc.). n and m may be the same or different and each may be an integer greater than zero.

Furthermore, the organic composition may further comprise a solvent, an acid (or an acid generator).

The solvent may include at least one of, for example, oxybutyric acid esters, glycol ethers, ethers having a hydroxy group, esters, dibasic esters, propylene carbonates, and gamma-butyrolactones .

The acid may be selected from, for example, p-toluenesulfonic acid, dodecylbenzenesulfonic acid, oxalic acid, phthalic acid, phosphoric acid, camphorsulfonic acid, 2,4,6-trimethylbenzenesulfonic acid, triisonaphthalenesulfonic acid, 2-fluorobenzenesulfonic acid, 2-nitrobenzenesulfonic acid, 3-chlorobenzenesulfonic acid, 3-bromobenzenesulfonic acid, 2-fluorocapryl sulfonic acid, Sulfonic acid, 1-naphthol-5-sulfonic acid, and 2-methoxy-4-hydroxy-5-benzoylbenzenesulfonic acid.

The acid generator may be a photoacid generator or a thermal acid generator. Examples of the photoacid generator include onium salt, nitrobenzyl, sulfonic acid ester, diazomethane, glyoxime, N-hydroxyimide sulfonic acid ester, and halotriazine Or the like. The thermal acid generator may promote or enhance the crosslinking reaction during the curing of the first lower film ULa1. For example, the thermal acid generator may be selected from the group consisting of cyclohexyl p-toluene sulfonate, methyl p-toluene sulfonate, cyclohexyl 2,4,6-triisopropylbenzene sulfonate, 2-nitrobenzyl tosylate, tris , 3-dibromopropyl) -1,3,5-triazine-2,4,6-trione, alkyl esters and salts of organic sulfonic acids, triethylamine salts of dodecylbenzene sulfonic acid, p - < / RTI > ammonium salt of toluene sulfonic acid.

In addition, the organic composition may further comprise a surfactant, a leveling agent, a dye compound, and the like.

The third photoresist pattern PR3 is formed by preparing a photoresist composition, applying the photoresist composition on the entire surface of the substrate 100 to form a photoresist film, and exposing the photoresist film to light And developing the third photoresist pattern PR3 to form the third photoresist pattern PR3.

Here, the photoresist composition may contain silicon, unlike the photoresist composition described above with reference to FIG. Specifically, the photoresist composition comprises a polymer having a siloxane backbone of the _{(backbone) (R 7 SiO 3/2} ) l (R 8 SiO 3/2) m (R 9 SiO 3/2) n compound formula . In the above formulas, each of R ₇ to R ₉ independently represents hydrogen, or a substituted or unsubstituted hydrocarbon group having 1 to 20 carbon atoms. Wherein l is an integer of 1 to 10, m is an integer of 1 to 10, and n may be an integer of 1 to 10. The polymer compound may have a weight average molecular weight of 1,000 to 100,000. Finally, the silicon in the third photoresist pattern PR3 may be 10 wt% to 40 wt%.

More specifically, the inside of the polymer compound _{(R 7 SiO 3/2)} l units, wherein (R ₈ SiO _{3/2) m} and the unit _{(R 9 SiO 3/2)} n units of formula (6) to independently Lt; / RTI > units.

[Chemical Formula 6]

Wherein R ₁₀ is selected from the group consisting of hydrogen, C 1 -C 10 alkyl, C 1 -C 10 alkenyl, C 1 -C 10 alkynyl, C 6 -C 10 aryl, adamantyl, C 1 -C 5 alkyl-adamantyl, or C2-C6 < / RTI > lactone. And t may be an integer of 1 to 10.

For example, the polymer compound may include a polymer represented by the following formula (7).

(7)

The ratio of 1: m: n in the above formula (7) is 40: 30: 30. The polymer of formula (7) has a weight average molecular weight (Mw) of 20,000.

In addition, the photoresist composition may further include a radiation-sensitive acid-generating compound, an auxiliary resin, a plasticizer, a stabilizer, a colorant, a surfactant, and the like.

Referring to FIGS. 2 and 24, the lower pattern UL may be formed by anisotropically etching the lower film ULa using the third photoresist pattern PR3 as an etching mask. The lower pattern UL may expose the insulating films 110 and the first sacrificial films HL1 outside the first contact region CTR1. During the etching process for forming the lower pattern UL, the third photoresist pattern PR3 may be all removed. During the anisotropic etching process, the etching selectivity ratio of the third photoresist pattern PR3: the lower film ULa may be 1: 2 to 1:30.

Since the third photoresist pattern PR3 and the lower film ULa have a high etch selectivity ratio with respect to each other, the thickness of the third photoresist pattern PR3 is smaller than the thickness of the lower film ULa The lower pattern UL can be formed even if it is very small compared to the thickness. Further, by the thin third photoresist pattern PR3, the sidewall of the lower pattern UL can have a nearly vertical cross-sectional profile.

2 and 25, the insulating film 110 on the uppermost layer of the first contact region CTR1 and the first sacrificial layer HL1 on the uppermost layer are sequentially etched using the lower pattern UL as an etching mask, can do. The etched insulating layer 110 and the etched first sacrificial layer HL1 may expose the other insulating layer 110 and the first sacrificial layer HL1 below them.

Referring to FIGS. 2 and 26, a trimming process may be performed on the lower pattern UL. During the trimming process, the width of the lower pattern UL may be reduced by a third length T3 and the height may be reduced by a fourth length T4.

The trimming process may be performed using an etchant capable of selectively removing the lower pattern (UL). On the other hand, when the novolak-based organic polymer membrane according to the embodiments of the present invention is used, the height of the lower pattern UL can be minimized. In particular, the reduced fourth length T4 during the trimming process may be greater than the third length T3 and less than 1.5 times the third length T3. This may be similar to the trimming process result of the first photoresist pattern PR1 described above with reference to FIG.

The steps described above with reference to FIGS. 25 and 26 may constitute one cycle for forming the sidewalls of the first contact region CTR1 in a stepped structure. Then, the cycle can be repeated until the insulating film 110 and the first sacrificial layer HL1 in the lowermost layer of the first contact region CTR1 are etched. Thereafter, the same process as described above with reference to Figs. 20 to 22 can be performed.

When the combined process of the photoresist pattern and the lower film according to the present embodiment is used, the scattering of the lower pattern (UL) can be improved by using a photoresist pattern having a small thickness. Therefore, even in the stepped structure of the second contact region CTR2, the lower pattern UL having a cross-sectional profile close to perpendicular to the correct position can be formed.

Claims (10)

Forming a stacked structure including insulating films and sacrificial films alternately and repeatedly stacked on a substrate;
Forming a first photoresist pattern on the laminated structure; And
Etching the one end of the laminated structure with the first photoresist pattern as a mask to form the one end in a stepped shape,
Wherein the first photoresist pattern comprises a copolymer comprising units of the following formulas (1) and (2):
[Chemical Formula 1]

(2)

In Formula 1 and Formula 2, R ₁ and R ₂ are each independently hydrogen, a hydrocarbon having 1 to 20 carbon atoms, or a hydrocarbon having 1 to 20 carbon atoms substituted with -OR ₁₁ ,
Wherein R ₁₁ is C 1 -C 10 alkyl, C 2 -C 10 alkenyl, C 2 -C 10 alkynyl, C 6 -C 10 aryl or C 3 -C 10 cycloalkyl,
P is an integer of 1 to 10, and q is an integer of 1 to 10,
The copolymer has a weight average molecular weight of 1,000 to 100,000.
The method according to claim 1,
Wherein the copolymer is a random copolymer wherein the units are randomly polymerized.
The method according to claim 1,
Wherein the first photoresist pattern further contains a radiation-sensitive acid generator,
Wherein the radiation-sensitive acid generator is an onium salt compound having a fluoroalkylsulfonic acid ion having 1 to 10 carbon atoms as an anion.
The method according to claim 1,
Forming the one end in the step shape includes repeating the cycle by making the following steps one cycle:
Etching at least one of the insulating films exposed by the first photoresist pattern using the first photoresist pattern as a mask;
Etching at least one of the sacrificial layers under the at least one insulating layer; And
Trimming the first photoresist pattern to reduce its width and height.
5. The method of claim 4,
Trimming the first photoresist pattern comprises:
Reducing the width by a first length; And
And reducing the height by a second length,
Wherein the second length is greater than the first length and less than 1.5 times the first length.
5. The method of claim 4,
Wherein the cycle is repeated until the insulating film and the sacrificial layer at the lowermost layer of the laminated structure are etched.
The method according to claim 1,
Wherein one end of the laminated structure includes a first contact region adjacent to the cell array region and a second contact region spaced apart from the cell array region through the first contact region,
Wherein the first contact region is formed in a stepped shape by the first photoresist pattern,
The method comprises:
Forming a second photoresist pattern containing the copolymer on the laminated structure; And
And etching the second contact region using the second photoresist pattern as a mask to form the second contact region in a stepped shape.
The method according to claim 1,
Wherein one end of the laminated structure includes a first contact region adjacent to the cell array region and a second contact region spaced apart from the cell array region through the first contact region,
Wherein the first contact region is formed in a stepped shape by the first photoresist pattern,
The method comprises:
Forming a lower film and a second photoresist pattern on the laminated structure;
Etching the lower film using the second photoresist pattern as a mask to form a lower pattern; And
Etching the second contact region using the lower pattern as a mask to form the second contact region in a stepped shape,
The lower layer includes a novolac-based organic polymer,
Wherein the second photoresist pattern comprises a polymer containing silicon.
The method according to claim 1,
Forming channel holes through the cell array region of the stacked structure to expose the substrate; And
Further comprising sequentially forming, in each of the channel holes, a gate insulating film and a channel film covering the inner wall thereof.
The method according to claim 1,
Wherein the copolymer further comprises a unit represented by the following formula (3): < EMI ID =
(3)

In Formula 3, R ₃ is hydrogen, a hydrocarbon having 1 to 20 carbon atoms, or a hydrocarbon having 1 to 20 carbon atoms substituted with -OR ₁₁ ,
Wherein R ₁₁ is C 1 -C 10 alkyl, C 2 -C 10 alkenyl, C 2 -C 10 alkynyl, C 6 -C 10 aryl or C 3 -C 10 cycloalkyl,
And r is an integer of 1 to 10.

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