CN108573860B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN108573860B
CN108573860B CN201710142850.9A CN201710142850A CN108573860B CN 108573860 B CN108573860 B CN 108573860B CN 201710142850 A CN201710142850 A CN 201710142850A CN 108573860 B CN108573860 B CN 108573860B
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Prior art keywords
layer
pattern
contact region
chemical formula
etching
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CN108573860A (en
Inventor
洪锡九
姜美荣
李孝圣
赵庆容
金宝螺
金惠智
赵先觉
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Embodiments of the inventive concept provide a method for manufacturing a semiconductor device. The method comprises the following steps: a stacked structure is formed by alternately and repeatedly stacking an insulating layer and a sacrificial layer on a substrate, sequentially forming a first lower layer and a first photoresist pattern on the stacked structure, and etching the first lower layer using the first photoresist pattern as an etching mask to form a first lower pattern. A first portion of the stacked structure is etched using the first lower pattern as an etch mask to form a stepped structure. The first lower layer includes a novolac-based organic polymer, and the first photoresist pattern includes a polymer including silicon.

Description

Method for manufacturing semiconductor device
Technical Field
Exemplary embodiments of the inventive concept relate to semiconductor devices, and more particularly, to methods for manufacturing semiconductor devices.
Background
Semiconductor devices have been highly integrated and can provide high performance and low cost. The integration density of a semiconductor device may affect the cost of the semiconductor device. The integration density of a two-dimensional (2D) or planar memory device may be primarily determined by the area occupied by the unit memory cells. Therefore, the integration density of the 2D memory device may be affected by a technique of forming the fine pattern. However, since relatively expensive equipment can be used to form the fine pattern, the manufacturing capability of the relatively high-density 2D memory device may be limited.
Three-dimensional (3D) semiconductor devices including memory cells arranged in three dimensions have been developed to improve integration density. However, the fabrication of 3D semiconductor memory devices may be relatively expensive and more complex than 2D semiconductor memories.
Disclosure of Invention
Exemplary embodiments of the inventive concept may provide a method of manufacturing a semiconductor device using a dual layer process of a photoresist (photoresist) pattern and a lower layer (underlayer).
According to an exemplary embodiment of the inventive concept, a method for manufacturing a semiconductor device includes: a stacked structure is formed by alternately and repeatedly stacking an insulating layer and a sacrificial layer on a substrate, a first lower layer and a first photoresist pattern are sequentially formed on the stacked structure, and the first lower layer is etched using the first photoresist pattern as an etching mask to form a first lower pattern. A first portion of the stacked structure is etched using the first lower pattern as an etch mask to form a stepped structure. The first lower layer includes a novolac-based organic polymer, and the first photoresist pattern includes a polymer including silicon.
In some exemplary embodiments of the inventive concept, the polymer including silicon may include a unit represented by the following chemical formula 5.
[ chemical formula 5]
Wherein "R 10 "represents hydrogen, a C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, adamantyl, C1-C5 alkyl-adamantyl, or C2-C6 lactone group, and" t "is an integer from 1 to 10. The polymer comprising silicon may have a weight average molecular weight of 1,000 to 100,000.
In some exemplary embodiments of the inventive concept, the content of silicon in the first photoresist pattern may be in the range of 10 wt% to 40 wt%.
In some exemplary embodiments of the inventive concept, the first lower layer may include a crosslinking agent including a compound represented by the following chemical formula 1.
[ chemical formula 1]
In chemical formula 1, R 4 OOC(CX 2 ) n -、R 5 -and R 6 OOC(CX 2 ) m At least two of them being different acids or different ester groups, "R 4 ”、“R 5 ”、“R 6 "and" X "each independently represent a hydrogen or non-hydrogen substituent, and" n "and" m "are each integers greater than 0. The non-hydrogen substituent may be a substituted or unsubstituted C1-C10 alkyl group, a substituted or unsubstituted C2-C10 alkenyl group or a C2-C10 alkynyl group, a substituted or unsubstituted C1-C10 alkanoyl group, a substituted or unsubstituted C1-C10 alkoxy group, an epoxy group, a substituted or unsubstituted C1-C10 alkylthio group, a substituted or unsubstituted C1-C10 alkylsulfinyl group, a substituted or unsubstituted C1-C10 alkylsulfonyl group, a substituted or unsubstituted carboxyl group, a substituted or unsubstituted-COO- (C1-C8 alkyl) group, a substituted or unsubstituted C6-C12 aryl group, or a substituted or unsubstituted 5-to 10 membered heteroalicyclic group or heteroaryl group.
In some exemplary embodiments of the inventive concept, the formation of the stepped structure may include repeating the process cycle. The process cycle may include: etching at least one of the insulating layers exposed by the first lower pattern using the first lower pattern as an etching mask; etching at least one of the sacrificial layers under at least one of the insulating layers; and trimming the first lower pattern to reduce the width and height of the first lower pattern.
In some exemplary embodiments of the inventive concept, the trimming of the first lower pattern may include reducing the width by a first length and reducing the height by a second length. The second length may be greater than the first length and less than 1.5 times the first length.
In some exemplary embodiments of the inventive concept, the process cycle may be repeated until the lowermost insulating layer and the lowermost sacrificial layer of the stack structure are etched.
In some exemplary embodiments of the inventive concept, a substrate may include a cell array region, a second contact region adjacent (neighboring) the cell array region, and a first contact region spaced apart from the cell array region, wherein the second contact region is disposed between the cell array region and the first contact region. An etched first portion of the stacked structure may be disposed in the second contact region. The method for manufacturing the semiconductor device may include: forming a second lower pattern including a novolac-based organic polymer on the stacked structure, and etching the stacked structure in the first contact region using the second lower pattern as an etching mask to form a stepped structure in the first contact region.
In some exemplary embodiments of the inventive concept, a substrate may include a cell array region, a second contact region adjacent to the cell array region, and a first contact region spaced apart from the cell array region, wherein the second contact region is disposed between the cell array region and the first contact region. An etched first portion of the stacked structure may be disposed in the second contact region. The method for manufacturing the semiconductor device may include: forming a second photoresist pattern on the stacked structure, and etching the stacked structure in the first contact region using the second photoresist pattern as an etching mask to form a stepped structure in the first contact region. The second photoresist pattern may include a copolymer including a plurality of units represented by the following chemical formulas 2 and 3 and optionally a plurality of units represented by the following chemical formula 4.
[ chemical formula 2]
[ chemical formula 3]
[ chemical formula 4]
In chemical formulas 2 to 4, "R 7 ”、“R 8 "and" R 9 "each independently represents hydrogen, a C1-C20 hydrocarbyl group, or a group consisting of" -O-R 11 "C1-C20 hydrocarbyl group substituted with a group represented by" R 11 "can be C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, or C3-C10 cycloalkyl, "p" is an integer from 1 to 10, "q" is an integer from 1 to 10, and "r" is an integer from 1 to 10. The copolymer may have a weight average molecular weight of 1,000 to 100,000.
In some exemplary embodiments of the inventive concept, the method may include: a channel hole penetrating the stacked structure to expose the substrate is formed, and a gate insulating layer and a channel layer sequentially stacked on respective inner sidewalls of the channel hole are formed.
In some exemplary embodiments of the inventive concept, the method may include: the sacrificial layer is selectively removed to form a recess region between the insulating layers, and gate electrodes filling the recess region are respectively formed.
In some exemplary embodiments of the inventive concept, an end portion of the gate electrode may correspond to a stepped structure of an end portion of the sacrificial layer. A method for manufacturing a semiconductor device may include forming a contact plug (plug) penetrating an end portion of at least one of the insulating layers. The contact plug may be electrically connected to an end of at least one of the gate electrodes.
According to an exemplary embodiment of the inventive concept, a method for manufacturing a semiconductor device includes: forming a stacked structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate, forming an organic polymer layer on the stacked structure, and forming a photoresist layer including silicon on the organic polymer layer. The method comprises the following steps: the photoresist layer is exposed and developed to form a photoresist pattern, the organic polymer layer is etched using the photoresist pattern as an etch mask to form an organic polymer pattern, and the stacked structure is etched using the organic polymer pattern as an etch mask to form a stepped structure. The thickness of the organic polymer layer is in the range of 10 to 30 times the thickness of the photoresist layer.
In some exemplary embodiments of the inventive concept, the photoresist layer may include a polymer having a unit represented by chemical formula 5 below.
[ chemical formula 5]
Wherein "R 10 "represents hydrogen, a C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, adamantyl, C1-C5 alkyl-adamantyl, or C2-C6 lactone group, and" t "is an integer from 1 to 10. The polymer may have a weight average molecular weight of 1,000 to 100,000.
In some exemplary embodiments of the inventive concept, the organic polymer layer may include a novolac-based polymer.
According to an exemplary embodiment of the inventive concept, a method for manufacturing a semiconductor device includes: forming an organic polymer layer on an etching target layer disposed on a substrate; forming a photoresist layer comprising silicon on the organic polymer layer, wherein the photoresist layer comprises a polymer having a unit represented by the following chemical formula 5,
[ chemical formula 5]
Wherein "R 10 "represents hydrogen, a C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, adamantyl, C1-C5 alkyl-adamantyl, or C2-C6 lactone group, and" t "is an integer from 1 to 10, the polymer having a weight average molecular weight of from 1,000 to 100,000; and etching the organic polymer layer using the photoresist layer as an etching mask to form an organic polymer pattern; and etching the etch target layer using the organic polymer pattern as an etch mask to form a stepped structure.
In some exemplary embodiments of the inventive concept, the thickness of the organic polymer layer ranges from 10 to 30 times the thickness of the photoresist layer.
In some exemplary embodiments of the inventive concept, the organic polymer layer includes a novolac-based polymer.
In some exemplary embodiments of the inventive concept, the polymer layer includes a crosslinking agent including a compound represented by the following chemical formula 1,
[ chemical formula 1]
Wherein R is 4 OOC(CX 2 ) n -、R 5 -, and R 6 OOC(CX 2 ) m At least two of them being different acids or different ester groups, "R 4 ”、“R 5 ”、“R 6 "and" X "each independently represent a hydrogen or non-hydrogen substituent, and" n "and" m "are each integers greater than 0.
Drawings
The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
fig. 1 is a schematic circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to some exemplary embodiments of the inventive concept.
Fig. 2 is a plan view illustrating a 3D semiconductor memory device according to some exemplary embodiments of the inventive concept.
Fig. 3 is a cross-sectional view taken along line I-I' of fig. 2 illustrating a 3D semiconductor memory device according to some exemplary embodiments of the inventive concept.
Fig. 4 to 23 are cross-sectional views taken along line I-I' of fig. 2 illustrating methods for manufacturing a 3D semiconductor memory device according to some exemplary embodiments of the inventive concept.
Fig. 24 to 26 are cross-sectional views taken along line I-I' of fig. 2 illustrating methods for manufacturing a 3D semiconductor memory device according to some exemplary embodiments of the inventive concept.
Detailed Description
Exemplary embodiments of the inventive concept will now be described in more detail with reference to the accompanying drawings in which exemplary embodiments are shown. However, the exemplary embodiments of the inventive concept may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the drawings, exemplary embodiments of the inventive concept are not limited to the specific examples provided herein, and components, layers, or regions illustrated in the drawings may be exaggerated for clarity of description.
In the description and in the drawings, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. Throughout the specification and drawings, identical reference numbers or identical drawing indicators may identify identical elements.
Exemplary embodiments of the inventive concept may be described with reference to cross-sectional and/or plan views as exemplary figures. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments of the inventive concept should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. It will be understood that, although the terms first, second, and third may be used herein to describe various elements, these elements should not be limited by these terms. Exemplary embodiments of the inventive concepts illustrated and described herein may include their complementary counterparts (counterparts).
Fig. 1 is a schematic circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to some exemplary embodiments of the inventive concept.
Referring to fig. 1, a cell array of a 3D semiconductor memory device according to some exemplary embodiments of the inventive concept may include a common source line CS, a plurality of bit lines BL, and a plurality of Cell Strings (CSTRs) connected between the common source line CS and the bit lines BL.
The common source line CS may be a conductive layer disposed on the substrate or a dopant region formed in the substrate. In some exemplary embodiments of the inventive concept, the common source line CS may include a conductive pattern (e.g., a metal line) vertically spaced apart from the substrate. The bit line BL may include a conductive pattern (e.g., a metal line vertically spaced apart from the substrate). In some exemplary embodiments of the inventive concept, the bit line BL may cross the common source line CS and may be vertically spaced apart from the common source line CS. The bit lines BL may be two-dimensionally arranged. A plurality of cell strings CSTRs may be connected in parallel to each bit line BL. The cell string CSTR may be commonly connected to the common source line CS. A plurality of cell strings CSTR may be disposed between the common source line CS and the plurality of bit lines BL. In some exemplary embodiments of the inventive concept, the common source line CS may include a plurality of common source lines CS arranged in two dimensions. In some exemplary embodiments of the inventive concept, the same voltage may be applied to a plurality of common source lines CS. In some exemplary embodiments of the inventive concept, the common source lines CS may be electrically controlled independently of each other.
The cell strings CSTRs may each include a ground (ground) selection transistor GST connected to the common source line CS, a string selection transistor SST connected to the bit line BL, and a plurality of memory cell transistors MCT disposed between the ground and the string selection transistors GST and SST. The ground selection transistor GST, the memory cell transistor MCT, and the string selection transistor SST may be connected in series with each other.
The common source line CS may be commonly connected to the sources of the ground selection transistors GST. The lower selection line LSL, the plurality of word lines WL0 to WL3, and the upper selection line USL, which may be disposed between the common source line CS and the bit line BL, may serve as gates of the ground selection transistor GST, the memory cell transistor MCT, and the string selection transistor SST, respectively. The memory cell transistors MCT may each comprise a data storage element.
Fig. 2 is a plan view illustrating a 3D semiconductor memory device according to some exemplary embodiments of the inventive concept. Fig. 3 is a cross-sectional view taken along line I-I' of fig. 2 illustrating a 3D semiconductor memory device according to some exemplary embodiments of the inventive concept.
Referring to fig. 2 and 3, the 3d semiconductor memory device may include a substrate 100. The substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may include a common source region CSL doped with a dopant. In some exemplary embodiments of the inventive concept, the common source regions CSL may each have a line shape extending in a second direction D2 parallel to the upper surface of the substrate 100. The common source regions CSL may be arranged along a first direction D1 crossing the second direction D2.
The stack structure ST may be disposed on the substrate 100. The stack structures ST may each include an insulating layer 110 and gate electrodes LSL, WL1, WL2, and USL, which may be alternately and repeatedly stacked on the substrate 100. The respective lower portions of the stack structures ST may be referred to as first stack structures ST1, and the respective upper portions of the stack structures ST may be referred to as second stack structures ST2. The second stack structure ST2 may be disposed on the first stack structure ST 1. The stacked structures ST may each have a line shape extending in the second direction D2, and may be arranged along the first direction D1 when viewed from a plan view.
The common source regions CSL may each be disposed in the substrate 100 between the stack structures ST adjacent to each other. The lower insulating layer 105 may be disposed between the substrate 100 and the first stack structure ST 1. In some exemplary embodiments of the inventive concept, the lower insulating layer 105 may include a silicon oxide layer and/or a high-k dielectric layer (e.g., a silicon nitride layer, an aluminum oxide layer, or a hafnium oxide layer). The lower insulating layer 105 may be thinner than the insulating layer 110.
The gate electrodes LSL, WL1, WL2, and USL may be stacked along a third direction D3 perpendicular to the first and second directions D1 and D2. The gate electrodes LSL, WL1, WL2, and USL may be vertically spaced apart from each other. The gate electrodes LSL, WL1, WL2, and USL may be separated from each other by an insulating layer 110 disposed between the gate electrodes LSL, WL1, WL2, and USL. In some exemplary embodiments of the inventive concept, the gate electrodes LSL and WL1 of the first stack structure ST1, respectively, may include a lower select line LSL and a first word line WL1. The gate electrodes WL2 and USL of the second stack structure ST2 may include a second word line WL2 and an upper select line USL, respectively. For example, the gate electrodes LSL, WL1, WL2, and USL may include doped silicon, metal (e.g., tungsten), metal nitride, metal silicide, or any combination thereof. For example, the insulating layers 110 may each include a silicon oxide layer.
The lower select line LSL may be the lowermost one of the gate electrodes LSL and WL1 in each of the first stack structures ST 1. The lower select line LSL may serve as a gate electrode of the ground select transistor GST. The upper selection line USL may be an uppermost one of the gate electrodes WL2 and USL in each of the second stack structures ST 2. The upper select line USL may serve as a gate electrode of the string select transistor SST. The first and second word lines WL1 and WL2 may serve as gate electrodes of the memory cell transistors MCT.
The substrate 100 may include a cell array region CAR, a first contact region CTR1, and a second contact region CTR2. At least one end of the stack structure ST may be disposed on the substrate 100 of the first and second contact regions CTR1 and CTR2. One end of the first stack structure ST1 may be disposed on the substrate 100 of the first contact region CTR1, and one end of the second stack structure ST2 may be disposed on the substrate 100 of the second contact region CTR2. In some exemplary embodiments of the inventive concept, the second contact region CTR2 may be adjacent to the cell array region CAR. The first contact region CTR1 may be spaced apart from the cell array region CAR when viewed from a plan view, with the second contact region CTR2 disposed between the first contact region CTR1 and the cell array region CAR. The first stack structure ST1 may extend from the cell array region CAR into the first contact region CTR1 through the second contact region CTR2, and the second stack structure ST2 may extend from the cell array region CAR into the second contact region CTR2.
In order to electrically connect the gate electrodes LSL, WL1, WL2, and USL to the peripheral logic structure, the stack structures ST may each have a stepped structure on the substrate 100 of the first and second contact regions CTR1 and CT 2. The vertical height of the stepped structure of the first and second contact regions CTR1 and CTR2 may increase with decreasing distance from the cell array region CAR. The stack structure ST may have an inclined (beveled) profile on the substrate 100 of the first and second contact regions CTR1 and CTR 2.
The planar areas of the gate electrodes LSL and WL1 on the substrate 100 of the first contact region CTR1 may sequentially decrease as the distance from the upper surface of the substrate 100 in the third direction D3 increases. Accordingly, the lower selection line LSL corresponding to the lowermost one of the gate electrodes LSL and WL1 may have the largest planar area. The planar areas of the gate electrodes WL2 and USL on the substrate 100 of the second contact region CTR2 may sequentially decrease as the distance from the upper surface of the substrate 100 in the third direction D3 increases. Accordingly, the upper selection line USL corresponding to the uppermost one of the gate electrodes WL2 and USL may have the smallest planar area.
The first interlayer insulating layer 180 may be disposed on the substrate 100 and may cover at least a portion of each stack structure ST. The first interlayer insulating layer 180 may have a planarized upper surface, and may cover the stepped structure of the stack structure ST on the substrate 100 of the first and second contact regions CTR1 and CTR 2. The second interlayer insulating layer 190 may be disposed on the first interlayer insulating layer 180 and the stacked structure ST.
The plurality of channel holes CH may penetrate the stacked structure ST disposed on the substrate 100 of the cell array region CAR. The channel layer 135 may extend toward the substrate 100 along respective inner sidewalls of the channel holes CH. The channel layer 135 may be electrically connected to the substrate 100. In some exemplary embodiments of the inventive concept, the channel layer 135 may be in direct contact with the upper surface of the substrate 100. The respective channel layers 135 passing through the stack structure ST may be arranged along the second direction D2 when viewed from a plan view. In some exemplary embodiments of the inventive concept, the respective channel layers 135 of the stack structure ST may be arranged in a line along the second direction D2. In some exemplary embodiments of the inventive concept, the respective channel layers 135 of the stacked structures ST may be arranged in a zigzag manner along the second direction D2.
In some exemplary embodiments of the inventive concept, the channel layer 135 may have a tube or macaroni shape having an open bottom end and an open top end. In some exemplary embodiments of the inventive concept, the channel layer 135 may have a tube or macaroni shape having a closed bottom end.
Channel layer 135 may be undoped or may be doped with a dopant having the same conductivity type as substrate 100. The channel layer 135 may include a semiconductor material having a polycrystalline structure or a single crystal structure. For example, channel layer 135 may include silicon. The inner space surrounded by the channel layer 135 may be filled with the filling insulation pattern 150. For example, the filling insulating pattern 150 may include silicon oxide.
The gate insulating layer 145 may be disposed between the stack structure ST and each channel layer 135. The gate insulating layer 145 may directly cover the inner sidewalls of the channel hole CH. The gate insulating layer 145 may extend in the third direction D3. The gate insulating layer 145 may have a tube or a macaroni shape whose top and bottom ends are open.
The gate insulating layer 145 may include a single layer or multiple layers. In some exemplary embodiments of the inventive concept, the gate insulating layer 145 may include a charge storage layer and a tunnel (tunnel) insulating layer of a charge trap type flash memory transistor. The tunnel insulating layer may include a material having a band gap greater than that of the charge storage layer. For example, the tunnel insulating layer may include at least one of a silicon oxide layer or a high-k dielectric layer (e.g., an aluminum oxide layer or a hafnium oxide layer). The charge storage layer may include at least one of an insulating layer rich in capture sites (e.g., a silicon nitride layer), a floating gate electrode, or an insulating layer including conductive nanodots. The tunnel insulating layer may be in direct contact with the channel layer 135. A blocking insulating layer may be disposed between the charge storage layer and each of the gate electrodes LSL, WL1, WL2, and USL. The blocking insulating layer may extend between the insulating layer 110 and each of the gate electrodes LSL, WL1, WL2, and USL. The blocking insulating layer may include a material having a band gap smaller than that of the tunnel insulating layer and larger than that of the charge storage layer. For example, the barrier insulating layer may include a high-k dielectric layer (e.g., an aluminum oxide layer or a hafnium oxide layer).
In some exemplary embodiments of the inventive concept, the gate insulating layer 145 may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. The tunnel insulating layer may be in direct contact with the channel layer 135, and the blocking insulating layer may be in direct contact with the gate electrodes LSL, WL1, WL2, and USL. The charge storage layer may be disposed between the tunnel insulating layer and the blocking insulating layer. In this case, the gate electrodes LSL, WL1, WL2, and USL may be in direct contact with the insulating layer 110.
The filling insulating layer 170 may fill the trench TR between the stacked structures ST. The fill insulating layer 170 may include a silicon oxide layer.
The respective top portions of the channel layers 135 may include drain regions DR. Conductive pads (lands) 160 may be in contact with respective drain regions DR of the channel layer 135. The second interlayer insulating layer 190 may cover the conductive pad 160. The plurality of bit line plugs BPLG may penetrate the second interlayer insulating layer 190 and may be electrically connected to the conductive pads 160, respectively. The bit line BL may be disposed on the bit line plug BPLG. The bit lines BL may each have a line shape extending in the first direction D1. The bit lines BL may each be electrically connected to the conductive pads 160 arranged in the first direction D1 through the bit line plugs BPLG.
An interconnection structure electrically connecting the gate electrodes LSL, WL1, WL2, and USL to the peripheral logic structure may be disposed on the stack structure ST disposed on the substrate 100 of the first and second contact regions CTR1 and CTR 2.
The first contact plug PLG1 may penetrate the second and first interlayer insulating layers 190 and 180, and may be connected to ends of the gate electrodes LSL and WL1 disposed on the substrate 100 of the first contact region CTR1, respectively. The second contact plug PLG2 may penetrate the second and first interlayer insulating layers 190 and 180, and may be connected to ends of the gate electrodes WL2 and USL disposed on the substrate 100 of the second contact region CTR2, respectively. The vertical lengths of the first and second contact plugs PLG1 and PLG2 may sequentially decrease as the distance from the cell array region CAR decreases. The upper surfaces of the first and second contact plugs PLG1 and PLG2 may be substantially coplanar with each other.
The first connection line CL1 may be disposed on the second interlayer insulating layer 190 of the first contact region CTR1, and may be electrically connected to the first contact plug PLG1. The second connection line CL2 may be disposed on the second interlayer insulating layer 190 of the second contact region CTR2, and may be electrically connected to the second contact plug PLG2.
Fig. 4 through 23 are cross-sectional views taken along line I-I' of fig. 2 illustrating a method for manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept.
Referring to fig. 2 and 4, sacrificial layers HL1 and HL2 and an insulating layer 110 may be alternately and repeatedly deposited on the substrate 100 to form a stacked structure ST. The stack structure ST may include a first stack structure ST1 disposed on the substrate 100 and a second stack structure ST2 disposed on the first stack structure ST 1. The first stack structure ST1 may include a first sacrificial layer HL1, and the second stack structure ST2 may include a second sacrificial layer HL2.
In some exemplary embodiments of the inventive concept, the sacrificial layers HL1 and HL2 may have substantially the same thickness. In some exemplary embodiments of the inventive concept, the lowermost one and the uppermost one of the sacrificial layers HL1 and HL2 may be thicker than other sacrificial layers disposed between the lowermost and uppermost sacrificial layers HL1 and HL 2. The insulating layers 110 may have substantially the same thickness, or the thickness of one or more of the insulating layers 110 may be different than the thickness of other insulating layers of the insulating layer 110.
The sacrificial layers HL1 and HL2 and the insulating layer 110 may be deposited using the following: thermal chemical vapor deposition (thermal CVD) methods, plasma-enhanced CVD methods, physical CVD methods, and/or Atomic Layer Deposition (ALD) methods. For example, the sacrificial layers HL1 and HL2 may each include a silicon nitride layer, a silicon oxynitride layer, or a silicon layer. In some exemplary embodiments of the inventive concept, the sacrificial layers HL1 and HL2 may include a polycrystalline structure or a monocrystalline structure. For example, the insulating layers 110 may each include a silicon oxide layer.
The lower insulating layer 105 may be formed between the substrate 100 and the first stack structure ST 1. The lower insulating layer 105 may include a material having etching selectivity to the sacrificial layers HL1 and HL 2. In some exemplary embodiments of the inventive concept, the lower insulating layer 105 may include a silicon oxide layer and/or a high-k dielectric layer (e.g., a silicon nitride layer, an aluminum oxide layer, or a hafnium oxide layer). The lower insulating layer 105 may be thinner than the sacrificial layers HL1 and HL2 and the insulating layer 110.
Referring to fig. 2 and 5, a channel hole CH may be formed to penetrate the stacked structure ST. The channel hole CH may expose the substrate 100. The channel holes CH may be arranged in the same manner as the channel layer 135 when viewed from a plan view.
The forming of the channel hole CH may include: a mask pattern having an opening is formed on the stack structure ST, and the stack structure ST is etched using the mask pattern as an etching mask. The opening of the mask pattern may define a region in which the channel hole CH is to be formed. The mask pattern may be removed after the channel hole CH is formed. The upper surface of the substrate 100 under the channel hole CH may be recessed by overetching the stack structure ST.
Referring to fig. 2 and 6, a gate insulating layer 145 and a channel layer 135 may be formed to sequentially cover respective inner sidewalls of the channel holes CH. In some exemplary embodiments of the inventive concept, the gate insulating layer 145 may include a tunnel insulating layer and a charge storage layer. In some exemplary embodiments of the inventive concept, the gate insulating layer 145 may further include a blocking insulating layer. A blocking insulating layer may be formed between the charge storage layer and the sacrificial layers HL1 and HL 2. The gate insulating layer 145 and the channel layer 135 may each be formed using an ALD method or a CVD method. The filling insulating pattern 150 may be formed to completely fill each of the channel holes CH.
Referring to fig. 2 and 7, a first lower layer ULa1 and a first photoresist pattern PR1 may be sequentially formed on the second stack structure ST 2. The first lower layer ULa1 may cover substantially the entire upper surface of the second stack structure ST 2. The first photoresist pattern PR1 may be formed on the first lower layer ULa1 of the cell array region CAR and the second contact region CTR2 adjacent to the cell array region CAR. The first photoresist pattern PR1 does not need to overlap the stack structure ST disposed on the substrate 100 of the first contact region CTR1 spaced apart from the cell array region CAR, wherein the second contact region CTR2 is disposed between the cell array region CAR and the first contact region CTR 1.
Forming the first lower layer ULa1 may include depositing an organic composition on the upper surface of the second stack structure ST 2. The first lower layer ULa1 may have a first thickness TH1. The organic composition may comprise a novolac-based organic polymer. The organic composition may include a crosslinking agent including a compound represented by the following chemical formula 1.
[ chemical formula 1]
In chemical formula 1, R 4 OOC(CX 2 ) n -、R 5 -, and R 6 OOC(CX 2 ) m At least two of them being different acids or different ester groups, and "R 4 ”、“R 5 ”、“R 6 "and" X "each independently represent a hydrogen or non-hydrogen substituent. The non-hydrogen substituent may be a substituted or unsubstituted C1-C10 alkyl group, a substituted or unsubstituted C2-C10 alkenyl group (e.g., allyl) or a C2-C10 alkynyl group, a substituted or unsubstituted C1-C10 alkanoyl group, a substituted or unsubstituted C1-C10 alkoxy group (e.g., methoxy, propoxy or butoxy), an epoxy group, a substituted or unsubstituted C1-C10 alkylthio group Substituted C1-C10 alkylsulfinyl, substituted or unsubstituted C1-C10 alkylsulfonyl, substituted or unsubstituted carboxyl, substituted or unsubstituted-COO-C1-8 alkyl, substituted or unsubstituted C6-C12 aryl (e.g., phenyl or naphthyl), or a substituted or unsubstituted 5-to 10-membered heteroalicyclic or heteroaryl group (e.g., methylphthalimide or N-methyl-1, 8-naphthalimide). In chemical formula 1, "n" and "m" may be equal to or different from each other, and each of "n" and "m" may be an integer greater than 0.
The organic composition may include a solvent and an acid (or acid generator).
For example, the solvent may include at least one of the following: hydroxybutyrate, glycol ethers, ethers with hydroxyl groups, esters, dibasic esters, propylene carbonate or gamma-butyrolactone.
For example, the acid may include at least one of the following: p-toluenesulfonic acid, dodecylbenzenesulfonic acid, oxalic acid, phthalic acid, phosphoric acid, camphorsulfonic acid, 2,4, 6-trimethylbenzenesulfonic acid, triisonaphthalenesulfonic acid, 5-nitro-o-toluenesulfonic acid, 5-sulfosalicylic acid, 2, 5-dimethylbenzenesulfonic acid, 2-nitrobenzenesulfonic acid, 3-chlorobenzenesulfonic acid, 3-bromobenzenesulfonic acid, 2-fluorooctylsulfonic acid, 1-naphthol-5-sulfonic acid or 2-methoxy-4-hydroxy-5-benzoylbenzenesulfonic acid.
The acid generator may be a photoacid generator or a thermal acid generator. For example, the photoacid generator may includeAt least one of a salt, nitrobenzyl (compound), sulfonate, diazomethane, glyoxime, N-hydroxyimide sulfonate or halotriazine. When the first lower layer ULa1 is hardened, the thermal acid generator may accelerate or increase the crosslinking reaction. For example, the thermal acid generator may include cyclohexyl p-toluenesulfonate, methyl p-toluenesulfonate, cyclohexyl 2,4, 6-triisopropylbenzenesulfonate, 2-nitrobenzyl toluene sulfonate, tris (2, 3-dibromopropyl) -1,3, 5-triazine-2, 4, 6-trione, alkyl esters of organic sulfonic acids and salts thereof, triethylamine salts of dodecylbenzenesulfonic acid, or ammonium salts of p-toluenesulfonic acid.
The organic composition may include a surfactant, a leveling agent, and/or a dye compound.
Forming the first photoresist pattern PR1 may include: preparing a photoresist composition, applying the photoresist composition to substantially the entire upper surface of the substrate 100 to form a photoresist layer, and performing an exposure process and a development process on the photoresist layer to form a first photoresist pattern PR1.
The photoresist composition can include silicon. In some exemplary embodiments of the inventive concept, the photoresist composition may include a photoresist composition having a siloxane as a backbone and represented by the formula (R 1 SiO 3/2 ) l (R 2 SiO 3/2 ) m (R 3 SiO 3/2 ) n Represented by the formula wherein "R 1 ”、“R 2 "and" R 3 "each independently represents hydrogen, a substituted or unsubstituted hydrocarbon group having a carbon number of 1 to 20," l "is an integer of 1 to 10," m "is an integer of 1 to 10, and" n "is an integer of 1 to 10. The polymer compound may have a weight average molecular weight of 1,000 to 100,000. In the first photoresist pattern PR1, the content of silicon may be in a range of 10 wt% to 40 wt%.
In the polymer compound (R 1 SiO 3/2 ) l Units, (R) 2 SiO 3/2 ) m Unit, and (R) 3 SiO 3/2 ) n The unit may be independently represented by the following chemical formula 5.
[ chemical formula 5]
In chemical formula 5, "R 10 "may represent hydrogen, C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, adamantyl, C1-C5 alkyl-adamantyl, or C2-C6 lactone groups. "t" is an integer of 1 to 10.
For example, the polymer compound may include the following polymer represented by the following chemical formula 6. In chemical formula 6, the ratio of l to m to n is 40:30:30. The polymer of chemical formula 6 may have a weight average molecular weight (Mw) of 20,000.
[ chemical formula 6]
In some exemplary embodiments of the inventive concept, the photoresist composition may include one or more of the following: radiation-sensitive acid generating compounds, auxiliary resins, plasticizers, stabilizers, colorants, and surfactants.
The first photoresist pattern PR1 may have a second thickness TH2. In some exemplary embodiments of the inventive concept, the first thickness TH1 may be in a range of about 10 to about 30 times the second thickness TH2.
Referring to fig. 2 and 8, the first lower layer ULa1 may be anisotropically etched using the first photoresist pattern PR1 as an etching mask to form a first lower pattern UL1. Accordingly, the first lower pattern UL1 may expose the stack structure ST of the first contact region CTR 1.
In some exemplary embodiments of the inventive concept, the first photoresist pattern PR1 may be completely removed during the anisotropic etching process for forming the first lower pattern UL1. During the anisotropic etching process, a ratio of an etching rate of the first photoresist pattern PR1 to an etching rate of the first lower layer ULa1 may be in a range of 1:2 to 1:30. The second thickness TH2 may be adjusted in consideration of an etching rate ratio, and thus the first photoresist pattern PR1 may be completely removed during the anisotropic etching process. In the case where a portion of the first photoresist pattern PR1 remains after the anisotropic etching process, an additional process may be performed to remove the remaining portion of the first photoresist pattern PR1.
Due to a large difference between etching rates of the first photoresist pattern PR1 and the first lower layer ULa1 according to some exemplary embodiments of the inventive concept, the first lower layer UL1 may be stably formed even though the second thickness TH2 of the first photoresist pattern PR1 is smaller than the first thickness TH1 of the first lower layer ULa 1. The angle between the upper surface of the substrate 100 and the sidewall of the first lower pattern UL1 may be about 90 degrees.
Referring to fig. 2 and 9, the uppermost insulating layer 110 and the uppermost second sacrificial layer HL2 of the second stack structure ST2 may be sequentially etched using the first lower pattern UL1 as an etching mask. The etched insulating layer 110 and the etched second sacrificial layer HL2 may expose the other insulating layer 110 and the other second sacrificial layer HL2 disposed under the uppermost insulating layer 110.
Referring to fig. 2 and 10, a trimming process may be performed on the first lower pattern UL 1. For example, the first lower pattern UL1 may be subjected to an isotropic etching process. Accordingly, the width and height of the first lower pattern UL1 may be reduced. In some exemplary embodiments of the inventive concept, during the trimming process, the width of the first lower pattern UL1 may be reduced by a first length T1, and the height of the first lower pattern UL1 may be reduced by a second length T2.
The trimming process may be performed using an etching solution capable of selectively etching the first lower pattern UL 1. When the trimming process includes a wet etching process, the reduced length of the height of the first lower pattern UL1 may be greater than the reduced length of the width of the first lower pattern UL 1. This is because: the area of the exposed upper surface of the first lower pattern UL1 may be greater than the area of the exposed sidewall of the first lower pattern UL 1.
However, since the first lower pattern UL1 according to some exemplary embodiments of the inventive concept may be formed using a novolac-based organic polymer, a reduction in height of the first lower pattern UL1 may be reduced or eliminated. In some exemplary embodiments of the inventive concept, the second length T2 reduced during the trimming process may be greater than the first length T1, and may be less than 1.5 times the first length T1.
The process described with reference to fig. 9 and 10 may constitute one process cycle for forming the stepped structure of the second stack structure ST2 disposed on the substrate 100 of the second contact region CTR 2. The process cycle may include: the at least one insulating layer 110 and the at least one second sacrificial layer HL2 are etched using the first lower pattern UL1 as an etching mask, and the first lower pattern UL1 is trimmed to reduce the width and height of the first lower pattern UL 1. The process cycle may be repeated. Repeated execution of the process cycle will be described in more detail below.
Referring to fig. 2 and 11, the uppermost insulating layer 110 may be etched using the first lower pattern UL1, the size of which has been reduced once, as an etching mask. Substantially simultaneously, the insulating layer 110 exposed by and disposed under the uppermost insulating layer 110 and the uppermost second sacrificial layer HL2 may be etched together with the uppermost insulating layer 110. Subsequently, the uppermost second sacrificial layer HL2 may be etched using the first lower pattern UL1 as an etching mask. Substantially simultaneously, the second sacrificial layer HL2 exposed by and disposed under the uppermost second sacrificial layer HL2 may be etched together with the uppermost second sacrificial layer HL2. The etched insulating layer 110 and the etched second sacrificial layer HL2 may expose the other insulating layer 110 and the other second sacrificial layer HL2 disposed thereunder.
Referring to fig. 2 and 12, the trimming process may be performed again on the first lower pattern UL 1. During the trimming process, the width of the first lower pattern UL1 may be reduced by a first length T1, and the height of the first lower pattern UL1 may be reduced by a second length T2. Thus, the process cycle may be repeated once more.
Referring to fig. 2 and 13, the process cycle may be repeated until the lowermost insulating layer 110 and the lowermost second sacrificial layer HL2 of the second stack structure ST2 disposed on the substrate 100 of the second contact region CTR2 are etched. Accordingly, the uppermost insulating layer 110 of the first stack structure ST1 on the substrate 100 of the first contact region CTR1 may be exposed.
The end of the second stack structure ST2 disposed on the substrate 100 of the second contact region CTR2 may have a stepped structure formed by repeatedly performing a process cycle using the first lower pattern UL 1. When the end portion of the second stack structure ST2 disposed on the substrate 100 of the second contact region CTR2 has a stepped structure, the size of the first lower pattern UL1 may become relatively small through repeated trimming processes.
Referring to fig. 2 and 14, the first lower pattern UL1 remaining on the stack structure ST may be removed, and then, a second lower layer ULa2 covering the stack structure ST may be formed. The second lower layer ULa2 may be formed by coating substantially the entire upper surface of the stack structure ST with the above-described organic composition. The second lower layer ULa2 may have a substantially uniform thickness, and thus the second lower layer ULa2 of the second contact region CTR2 may have an inclined upper surface. The second lower layer ULa2 may have a third thickness TH3.
The second photoresist pattern PR2 may be formed on the second lower layer ULa2. The second photoresist pattern PR2 may be formed on the cell array region CAR, the second contact region CTR2, and the second lower layer ULa2 of the first contact region CTR 1. The second photoresist pattern PR2 may be formed using a photoresist composition including silicon. The second photoresist pattern PR2 may have a fourth thickness TH4. In some exemplary embodiments of the inventive concept, the third thickness TH3 may be in the range of 10 to 30 times the fourth thickness TH4.
Referring to fig. 2 and 15, the second lower layer ULa2 may be anisotropically etched using the second photoresist pattern PR2 as an etching mask to form a second lower pattern UL2. The second lower pattern UL2 may expose the insulating layer 110 and the first sacrificial layer HL1 outside the cell array region CAR and the first and second contact regions CTR1 and CTR 2. During the anisotropic etching process for forming the second lower pattern UL2, the second photoresist pattern PR2 may be completely removed.
Referring to fig. 2 and 16, the uppermost insulating layer 110 and the uppermost first sacrificial layer HL1 of the first stack structure ST1 of the first contact region CTR1 may be sequentially etched using the second lower pattern UL2 as an etching mask. The etched insulating layer 110 and the etched first sacrificial layer HL1 of the first stack structure ST1 may expose the other insulating layer 110 and the other first sacrificial layer HL1 disposed under the uppermost insulating layer 110.
Referring to fig. 2 and 17, a trimming process may be performed on the second lower pattern UL2. During the trimming process, the width of the second lower pattern UL2 may be reduced by a first length T1, and the height of the second lower pattern UL2 may be reduced by a second length T2.
The process described with reference to fig. 16 and 17 may be substantially the same as one process cycle described with reference to fig. 9 and 10. The process cycle may be repeated. Repeated execution of the process cycle will be described in more detail below.
Referring to fig. 2 and 18, the uppermost insulating layer 110 of the first stack structure ST1 may be etched using the second lower pattern UL2, which is reduced in size once, as an etching mask. Substantially simultaneously, the insulating layer 110 exposed by and disposed under the uppermost insulating layer 110 and the uppermost first sacrificial layer HL1 may also be etched. Subsequently, the uppermost first sacrificial layer HL1 may be etched using the second lower pattern UL2 as an etching mask. Substantially simultaneously, the first sacrificial layer HL1 exposed by and disposed under the uppermost first sacrificial layer HL1 may also be etched.
Referring to fig. 2 and 19, the trimming process may be performed again on the second lower pattern UL 2. Thus, the process cycle may be performed again.
Referring to fig. 2 and 20, the process cycle of the second lower pattern UL2 may be repeated until the lowermost insulating layer 110 and the lowermost first sacrificial layer HL1 of the first stack structure ST1 of the first contact region CTR1 are etched. Accordingly, a portion of the upper surface of the lower insulating layer 105 may be exposed. The end of the first stack structure ST1 disposed on the substrate 100 of the first contact region CTR1 may have a stepped structure formed by repeatedly performing a process cycle using the second lower pattern UL 2. When the end portion of the first stack structure ST1 disposed on the substrate 100 of the first contact region CTR1 has a stepped structure, the size of the second lower pattern UL2 may become relatively small after the repeated trimming process.
Referring to fig. 2 and 21, the remaining second lower pattern UL2 may be removed, and a first interlayer insulating layer 180 covering the stack structure ST may be formed on the substrate 100. The first interlayer insulating layer 180 may cover the stepped structure of the first and second stack structures ST1 and ST2 disposed on the substrate 100 of the first and second contact regions CTR1 and CTR 2. The first interlayer insulating layer 180 may be planarized to expose an upper surface of the second stack structure ST2 of the cell array region CAR.
The stack structure ST of the cell array region CAR may be patterned to form a trench TR exposing the substrate 100. The trench TR may be laterally spaced apart from the channel hole CH. In some exemplary embodiments of the inventive concept, the forming of the trench TR may include: a mask pattern defining a planar position of the trench TR is formed on the stack structure ST, and the stack structure ST is etched using the mask pattern as an etching mask.
The trench TR may expose sidewalls of the sacrificial layers HL1 and HL2 and sidewalls of the insulating layer 110. The trench TR may be formed to expose sidewalls of the lower insulating layer 105. The width of the trench TR may vary according to a vertical distance from the substrate 100.
The stack structure ST may be divided into a plurality of sub-stack structures ST by the trench TR. The sub-stack structures ST may each have a linear shape extending in the second direction D2. The plurality of channel layers 135 may penetrate each sub-stack structure ST.
Referring to fig. 2 and 22, the sacrificial layers HL1 and HL2 exposed by the trench TR may be selectively removed to form the recess region 155. The recess region 155 may correspond to a void region formed by removing the sacrificial layers HL1 and HL 2. In the case where the sacrificial layers HL1 and HL2 include a silicon nitride layer or a silicon oxynitride layer, the removal process of the sacrificial layers HL1 and HL2 may be performed using an etching solution including phosphoric acid. Portions of the sidewalls of the gate insulating layer 145 may be respectively exposed through the recess regions 155.
Referring to fig. 2 and 23, gate electrodes LSL, WL1, WL2, and USL may be formed to fill the recess regions 155, respectively. In some exemplary embodiments of the inventive concept, the formation of the gate electrodes LSL, WL1, WL2, and USL may include: a conductive layer filling the recess region 155 is formed on the substrate 100, and the conductive layer formed outside the recess region 155 is removed.
After forming the gate electrodes LSL, WL1, WL2, and USL, a common source region CSL may be formed in the substrate 100. The common source region CSL may be formed using an ion implantation process, and may be formed in the substrate 100 under the trench TR. The common source region CSL and the substrate 100 may form a PN junction. The drain region DR may be formed in a top portion of the channel layer 135 by an ion implantation process.
When the gate insulating layer 145 includes a tunnel insulating layer and a charge storage layer, a blocking insulating layer may be conformally formed on the inner surface of the recess region 155 before forming the gate electrodes LSL, WL1, WL2, and USL. The gate electrodes LSL, WL1, WL2, and USL may be formed to fill the recess region 155 in which the blocking insulating layer is formed.
Referring again to fig. 2 and 3, a filling insulation layer 170 may be formed to fill the trench TR. The fill insulating layer 170 may include a silicon oxide layer.
Conductive pads 160 may be formed on the channel layers 135, respectively. The conductive pads 160 may be respectively in contact with upper surfaces of the channel layers 135. A second interlayer insulating layer 190 may be formed to cover the filling-up insulating layer 170, the conductive pad 160, and the first interlayer insulating layer 180. The bit line plug BPLG may be formed to penetrate the second interlayer insulating layer 190. The bit line plugs BPLG may be respectively contacted with the conductive pads 160.
The first contact plug PLG1 may be formed to penetrate the second and first interlayer insulating layers 190 and 180. The first contact plug PLG1 may be connected to the gate electrodes LSL and WL1 of the first contact region CTR1, respectively. The second contact plug PLG2 may be formed to penetrate the second and first interlayer insulating layers 190 and 180. The second contact plug PLG2 may be connected to the gate electrodes WL2 and USL of the second contact region CTR2, respectively.
A bit line BL extending in the first direction D1 may be formed on the second interlayer insulating layer 190. The bit lines BL may each be connected to a plurality of bit line plugs BPLG arranged in the first direction D1. First and second connection lines CL1 and CL2 connected to the first and second contact plugs PLG1 and PLG2, respectively, may be formed on the second interlayer insulating layer 190.
According to some exemplary embodiments of the inventive concept, a bilayer process of a photoresist pattern and a lower layer may be used to increase the distribution and profile uniformity (coherence) of the lower pattern. Since the lower pattern may be relatively thick, a stepped pattern having a plurality of steps may be formed using one photolithography process. Therefore, the process of manufacturing the semiconductor device can be effectively managed and strongly simplified.
Fig. 24 to 26 are cross-sectional views taken along line I-I' of fig. 2 illustrating methods for manufacturing a 3D semiconductor memory device according to some exemplary embodiments of the inventive concept. The description of the same technical features as those described above with reference to fig. 4 to 23 may be omitted or briefly mentioned.
Referring to fig. 2, 6 and 24, a third photoresist pattern PR3 may be formed on the resultant structure of fig. 6. The first lower layer ULa1 may be omitted, and the third photoresist pattern PR3 may be directly disposed on the upper surface of the second stack structure ST2 and may cover the upper surface of the second stack structure ST 2. The third photoresist pattern PR3 may be formed on the stack structure ST of the cell array region CAR and the second contact region CTR 2. The third photoresist pattern PR3 may expose the stack structure ST of the first contact region CTR 1.
Forming the third photoresist pattern PR3 may include: preparing a photoresist composition, applying the photoresist composition to the entire upper surface of the substrate 100 to form a photoresist layer, and performing an exposure process and a development process on the photoresist layer to form a third photoresist pattern PR3.
The photoresist composition according to an exemplary embodiment of the inventive concept may include an organic polymer based on poly (4-hydroxystyrene) (PHS). Preparing the photoresist composition can include polymerizing a mixture comprising a substituted or unsubstituted 4-hydroxystyrene and a substituted acrylate to synthesize a copolymer. The 4-hydroxystyrene and acrylate may be substituted with hydrocarbyl groups as described in detail below. Here, the weight ratio of 4-hydroxystyrene to acrylate prior to polymerization may range from 95:5 to 60:40. For example, the weight ratio of 4-hydroxystyrene to acrylate in the mixture may be in the range of 90:10 to 80:20.
The synthesized copolymer may include units represented by the following chemical formulas 2 and 3 and optionally units represented by the following chemical formula 4.
[ chemical formula 2]
[ chemical formula 3]
[ chemical formula 4]
In chemical formulas 2 to 4, "R 7 ”、“R 8 "and" R 9 "each independently represents hydrogen or a substituted or unsubstituted having 1 to 20 A hydrocarbon group having a carbon number of (C). The hydrocarbyl group may be selected from alkyl, alkenyl, alkynyl, cycloalkyl, alkyl substituted cycloalkyl, aryl, aralkyl, and alkaryl groups. The hydrocarbon group may be represented by "-O-R 11 "R" represents a substituent of a group 11 "can be C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, or C3-C10 cycloalkyl. The hydrocarbyl group may be an alkyl ether having one or more alkyl ether groups or alkylene oxide groups. The alkyl ether groups may be selected from ethoxy, propoxy and butoxy groups. In chemical formulas 2 to 4, "p" is an integer of 1 to 10, "q" is an integer of 1 to 10, and "r" is an integer of 1 to 10. The ratio p/(p+q+r) may be in the range of 0.4 to 0.6, the ratio q/(p+q+r) may be in the range of 0.5 to 0.2, and the ratio r/(p+q+r) may be in the range of 0.2 to 0.4. The copolymer may have a weight average molecular weight of 1,000 to 100,000.
For example, the copolymer may include the following polymer represented by the following chemical formula 7. In chemical formula 7, the ratio of p to q to r is 55:15:30. The copolymer of chemical formula 7 may have a weight average molecular weight (Mw) of 15,000. The copolymer of chemical formula 7 may be manufactured by radical polymerization, but is not limited thereto. The copolymer may be polymerized by anionic polymerization.
[ chemical formula 7]
Preparing the photoresist composition can include mixing the synthesized copolymer with a radiation-sensitive acid generating compound and a trialkanolamine in an organic solvent.
The radiation-sensitive acid generating compound may be dissociated by irradiation with activating (activating) light, thereby generating an acid. The radiation-sensitive acid generating compound may include a compound comprising a fluoro-alkyl-sulfonate ion having a carbon number of 1 to 10 as a negative ionA salt compound. For example, the radiation-sensitive acid generating compound may include diphenyliodo->Triflate and nonafluorobutylsulfonate, or may include bis (4-tert-butylphenyl) iodo +.>Triflate and nonafluorobutylsulfonate.
Trialkanolamines can increase the cross-sectional profile uniformity and stability of the photoresist pattern after exposure processes using activating light. For example, the trialkanolamine may include trimethylamine, triethylamine, tri-n-propylamine, triisopropylamine, tri-n-butylamine, triisobutylamine, tri-t-butylamine, tripentylamine, triethanolamine, tributylamine, or any combination thereof.
In the photoresist composition, the radiation-sensitive acid generating compound may be in the range of 1 to 10 parts by weight, and the trialkanolamine may be in the range of 0.01 to 1 part by weight, for 100 parts by weight of the copolymer.
In some exemplary embodiments of the inventive concept, to increase the performance of the photoresist layer, a secondary resin, a plasticizer, a stabilizer, a colorant, and a surfactant may be added to the photoresist composition.
Referring to fig. 2 and 25, the uppermost insulating layer 110 and the uppermost second sacrificial layer HL2 of the second stack structure ST2 of the second contact region CTR2 may be sequentially etched using the third photoresist pattern PR3 as an etching mask. The etched insulating layer 110 and the etched second sacrificial layer HL2 may expose the other insulating layer 110 and the other second sacrificial layer HL2 disposed under the uppermost insulating layer 110.
Referring to fig. 2 and 26, a trimming process may be performed on the third photoresist pattern PR 3. The third photoresist pattern PR3 may be subjected to an isotropic etching process. Accordingly, the width and height of the third photoresist pattern PR3 may be reduced. In some embodiments, during the trimming process, the width of the third photoresist pattern PR3 may be reduced by a third length T3, and the height of the third photoresist pattern PR3 may be reduced by a fourth length T4.
The trimming process may be performed using an etching solution capable of selectively etching the third photoresist pattern PR 3. Since the third photoresist pattern PR3 may be formed using the PHS-based photoresist composition according to some exemplary embodiments of the inventive concept, the reduction in height of the third photoresist pattern PR3 may be reduced or eliminated. In some exemplary embodiments of the inventive concept, the fourth length T4 may be greater than the third length T3 and may be less than 1.5 times the third length T3. This may be similar to the result of the trimming process of the first lower pattern UL1 described with reference to fig. 10.
The process described with reference to fig. 25 and 26 may constitute one process cycle for forming the second stack structure ST2 of the second contact region CTR2 into a stepped structure. The process cycle may be repeated until the lowermost insulating layer 110 and the lowermost second sacrificial layer HL2 of the second stack structure ST2 of the second contact region CTR2 are etched. The processes described with reference to fig. 14 to 23 may be performed after the lowermost insulating layer 110 and the lowermost second sacrificial layer HL2 of the second stack structure ST2 of the second contact region CTR2 are etched.
According to an exemplary embodiment of the inventive concept, the stepped structure of the second contact region CTR2 may be formed using the PHS-based photoresist pattern PR3 without an additional lower layer. Therefore, the process of manufacturing the semiconductor device can be effectively simplified. However, when the stepped structure of the first contact region CTR1 is formed, a dual layer process of the photoresist pattern and the lower layer may be performed. This is because: the dual layer process may reduce or prevent inconsistencies or errors in the pattern that may be caused by the stepped structure of the second contact region CTR 2.
According to some exemplary embodiments of the inventive concept, a bilayer process using a photoresist pattern and a lower layer may increase distribution and profile uniformity of the lower pattern. A relatively thick lower pattern may be formed using an organic polymer layer having a relatively high etching selectivity to the photoresist pattern. Accordingly, a stepped structure having a plurality of steps may be formed using one photolithography process, thereby simplifying a process of manufacturing the 3D semiconductor memory device.
While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept.

Claims (14)

1. A method for manufacturing a semiconductor device, the method comprising:
forming a stacked structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate;
sequentially forming a first lower layer and a first photoresist pattern on the stacked structure;
etching the first lower layer using the first photoresist pattern as an etch mask to form a first lower pattern; and
a first portion of the stacked structure is etched using the first lower pattern as an etch mask to form a stepped structure,
wherein the first lower layer comprises a novolak-based organic polymer, and
wherein the first photoresist pattern comprises a polymer comprising silicon,
wherein the silicon-containing polymer includes a unit represented by the following chemical formula 5:
[ chemical formula 5]
Wherein "R 10 "represents hydrogen, a C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, adamantyl, C1-C5 alkyl-adamantyl, or C2-C6 lactone group, and" t "is an integer from 1 to 10, and
Wherein the silicon-containing polymer has a weight average molecular weight of 1,000 to 100,000,
wherein forming the stepped structure comprises repeating the process cycle,
wherein the process cycle comprises:
etching at least one of the insulating layers exposed by the first lower pattern using the first lower pattern as an etching mask;
etching at least one of the sacrificial layers under at least one of the insulating layers; and
the first lower pattern is trimmed to reduce the width and height of the first lower pattern.
2. The method of claim 1, wherein the content of silicon in the first photoresist pattern is in a range of 10 wt% to 40 wt%.
3. The method of claim 1, wherein the first lower layer further comprises a crosslinking agent comprising a compound represented by the following chemical formula 1,
[ chemical formula 1]
Wherein R is 4 OOC(CX 2 ) n -、R 5 -and R 6 OOC(CX 2 ) m At least two of them being different acids or different ester groups, "R 4 ”、“R 5 ”、“R 6 "and" X "each independently represent a hydrogen or non-hydrogen substituent, and" n "and" m "are each integers greater than 0, and
wherein the non-hydrogen substituent is a substituted or unsubstituted C1-C10 alkyl, substituted or unsubstituted C2-C10 alkenyl or C2-C10 alkynyl, substituted or unsubstituted C1-C10 alkanoyl, substituted or unsubstituted C1-C10 alkoxy, epoxy, substituted or unsubstituted C1-C10 alkylthio, substituted or unsubstituted C1-C10 alkylsulfinyl, substituted or unsubstituted C1-C10 alkylsulfonyl, substituted or unsubstituted carboxyl, substituted or unsubstituted-COO- (C1-C8 alkyl), substituted or unsubstituted C6-C12 aryl, or substituted or unsubstituted 5-to 10 membered heteroalicyclic or heteroaryl group.
4. The method of claim 1, the trimming of the first lower pattern comprising:
reducing the width by a first length, and
the height is reduced by a second length,
wherein the second length is greater than the first length and less than 1.5 times the first length.
5. The method of claim 1, wherein a process cycle is repeated until a lowermost insulating layer and a lowermost sacrificial layer of the stacked structure are etched.
6. The method of claim 1, wherein the substrate comprises a cell array region, a second contact region adjacent to the cell array region, and a first contact region spaced apart from the cell array region, wherein the second contact region is disposed between the cell array region and the first contact region,
wherein an etched first portion of the stacked structure is disposed in the second contact region,
the method for manufacturing a semiconductor device further includes:
forming a second lower pattern comprising a novolac-based organic polymer on the stacked structure; and
the stacked structure in the first contact region is etched using the second lower pattern as an etch mask to form a stepped structure in the first contact region.
7. The method of claim 1, wherein the substrate comprises a cell array region, a second contact region adjacent to the cell array region, and a first contact region spaced apart from the cell array region, wherein the second contact region is disposed between the cell array region and the first contact region,
wherein an etched first portion of the stacked structure is disposed in the second contact region,
the method for manufacturing a semiconductor device further includes:
forming a second photoresist pattern on the stacked structure; and
the stacked structure in the first contact region is etched using the second photoresist pattern as an etch mask to form a stepped structure in the first contact region,
wherein the second photoresist pattern includes a copolymer including a plurality of units represented by the following chemical formulas 2 and 3 and optionally a plurality of units represented by the following chemical formula 4,
[ chemical formula 2]
[ chemical formula 3]
[ chemical formula 4]
Wherein "R 7 ”、“R 8 "and" R 9 "each independently represents hydrogen, a C1-C20 hydrocarbyl group, or a group consisting of" -O-R 11 "C1-C20 hydrocarbyl group substituted with a group represented by" R 11 "is C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, or C3-C10 cycloalkyl," p "is an integer from 1 to 10," q "is an integer from 1 to 10, and" r "is an integer from 1 to 10, and
Wherein the copolymer has a weight average molecular weight of 1,000 to 100,000.
8. The method of claim 1, further comprising:
forming a channel hole penetrating the stacked structure to expose the substrate; and
a gate insulating layer and a channel layer sequentially stacked on respective inner sidewalls of the channel holes are formed.
9. The method of claim 1, further comprising:
selectively removing the sacrificial layer to form a recess region between the insulating layers; and
and respectively forming gate electrodes filling the recessed areas.
10. The method of claim 9, wherein an end of the gate electrode corresponds to a stepped structure of an end of the sacrificial layer,
the method for manufacturing a semiconductor device further includes:
a contact plug penetrating an end portion of at least one of the insulating layers is formed, wherein the contact plug is electrically connected to an end portion of at least one of the gate electrodes.
11. A method for manufacturing a semiconductor device, the method comprising:
forming a stacked structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate;
forming an organic polymer layer on the stacked structure;
forming a photoresist layer comprising silicon on the organic polymer layer;
Exposing and developing the photoresist layer to form a photoresist pattern;
etching the organic polymer layer using the photoresist pattern as an etching mask to form an organic polymer pattern; and
the stacked structure is etched using the organic polymer pattern as an etch mask to form a stepped structure,
wherein the thickness of the organic polymer layer is 10 to 30 times the thickness of the photoresist layer,
wherein the photoresist layer comprises a polymer having a unit represented by chemical formula 5 below,
[ chemical formula 5]
Wherein "R 10 "represents hydrogen, a C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, adamantyl, C1-C5 alkyl-adamantyl, or C2-C6 lactone group, and" t "is an integer from 1 to 10, and
wherein the polymer has a weight average molecular weight of 1,000 to 100,000,
wherein the organic polymer layer comprises a novolac-based polymer,
wherein forming the stepped structure comprises repeating the process cycle,
wherein the process cycle comprises:
etching at least one of the insulating layers exposed by the first lower pattern using the first lower pattern as an etching mask;
etching at least one of the sacrificial layers under at least one of the insulating layers; and
The first lower pattern is trimmed to reduce the width and height of the first lower pattern.
12. A method for manufacturing a semiconductor device, the method comprising:
forming an organic polymer layer on an etching target layer disposed on a substrate;
a photoresist layer comprising silicon is formed on the organic polymer layer,
wherein the photoresist layer includes a polymer having a unit represented by chemical formula 5 below,
[ chemical formula 5]
Wherein "R 10 "represents hydrogen, a C1-C10 alkyl, C1-C10 alkenyl, C1-C10 alkynyl, C6-C10 aryl, adamantyl, C1-C5 alkyl-adamantyl, or C2-C6 lactone group, and" t "is an integer from 1 to 10, and
wherein the polymer has a weight average molecular weight of 1,000 to 100,000; and
etching the organic polymer layer using the photoresist layer as an etching mask to form an organic polymer pattern; and
the etch target layer is etched using the organic polymer pattern as an etch mask to form a stepped structure,
wherein the organic polymer layer comprises a novolac-based polymer,
wherein forming the stepped structure comprises repeating the process cycle,
wherein the process cycle comprises:
etching at least one of the insulating layers exposed by the first lower pattern using the first lower pattern as an etching mask;
Etching at least one of the sacrificial layers under at least one of the insulating layers; and
the first lower pattern is trimmed to reduce the width and height of the first lower pattern.
13. The method of claim 12, wherein the thickness of the organic polymer layer ranges from 10 to 30 times the thickness of the photoresist layer.
14. The method of claim 12, wherein the polymer layer includes a crosslinking agent including a compound represented by the following chemical formula 1,
[ chemical formula 1]
Wherein R is 4 OOC(CX 2 ) n -、R 5 -, and R 6 OOC(CX 2 ) m At least two of them being different acids or different ester groups, "R 4 ”、“R 5 ”、“R 6 "and" X "each independently represent a hydrogen or non-hydrogen substituent, and" n "and" m "are each integers greater than 0.
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