CN110379810A - Semiconductor structure and its manufacturing method - Google Patents
Semiconductor structure and its manufacturing method Download PDFInfo
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- CN110379810A CN110379810A CN201810328457.3A CN201810328457A CN110379810A CN 110379810 A CN110379810 A CN 110379810A CN 201810328457 A CN201810328457 A CN 201810328457A CN 110379810 A CN110379810 A CN 110379810A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
A kind of semiconductor structure, including substrate, secondary virtual architecture, secondary array structure, cubical array storage unit, the first conductive structure and the second conductive structure.Substrate includes virtual region and array region, the adjacent virtual region of array region.Secondary virtual architecture is arranged on virtual region and is separated from each other by multiple first channels, and the first channel extends along a first direction.Secondary array structure is disposed on the substrate and passes through multiple second channels and is separated from each other, and the second channel extends along second direction.These storage units include multiple storage unit groups, are separately positioned in time array structure.First conductive structure and the second conductive structure are respectively arranged in the first channel and the second channel.Each first conductive structure extends along a first direction.Each second conductive structure extends along second direction.First direction is different with second direction.
Description
Technical field
This exposure is related to a kind of semiconductor structure and its manufacturing method.This exposure is in particular to a kind of including storage unit
Semiconductor structure and its manufacturing method.
Background technique
In order to reduce volume, reduce weight, increase power density and improve portability etc. reason, three-dimensional has been developed
(3-D) semiconductor structure.In addition, the element and space in semiconductor device are constantly contracted by.This may cause some ask
Topic.For example, in the technique of 3-D storage device, may in order to storage unit and/or other elements construction and being formed has height
The stacking of depth-to-width ratio.Such stacking may be bent or collapse because of its high-aspect-ratio.Therefore, it is desirable to for semiconductor junction
Structure and its manufacturing method have a variety of different improvement.
Summary of the invention
This exposure is about semiconductor structure and its manufacturing method, especially with regard to the semiconductor structure including storage unit
And its manufacturing method.
According to some embodiments, semiconductor structure includes substrate, secondary virtual architecture, secondary array structure, cubical array storage
Unit, the first conductive structure and the second conductive structure.Substrate includes virtual region and array region, the adjacent virtual area of array region
Domain.Secondary virtual architecture is arranged on virtual region and is separated from each other by multiple first channels, and the first channel is along a first direction
Extend.Secondary array structure is arranged on array region and is separated from each other by multiple second channels, and the second channel is along second party
To extension.These storage units include multiple storage unit groups, are separately positioned in time array structure.First conductive structure and
Two conductive structures are respectively arranged in the first channel and the second channel.Each first conductive structure extends along a first direction.Respectively
A second conductive structure extends along second direction.First direction is different with second direction.
According to some embodiments, a kind of manufacturing method of semiconductor structure includes the following steps.Firstly, providing a starting knot
Structure.Initial structure includes a substrate and the preliminary array structure that is formed on substrate.Substrate is including a virtual region and for a moment
Column region.Preliminary array structure includes a stacking and multiple active structures across stacking.Each packet of these active structures
An accumulation layer between including a channel layer and being formed in channel layer and stack.Secondly, first in preliminary array structure is predetermined
Channel location forms multiple first channels extended along a first direction, will be located in the preliminary array structure on virtual region and divide
From at multiple secondary virtual architectures.The second predetermined channel position formation in preliminary array structure extends more along second direction
A second channel will be separated into multiple secondary array structures in the preliminary array structure being located on array region.Then, in the first ditch
Multiple first conductive structures and multiple second conductive structures are respectively formed in road and in the second channel.Each first conductive structure edge
First direction extend, each second conductive structure extends along second direction, and first direction is different with second direction.
More preferably understand to have to the above-mentioned and other aspect of the present invention, hereafter spy enumerates embodiment, and cooperates appended attached
Detailed description are as follows for figure:
Detailed description of the invention
Figure 1A~1C is painted a kind of semiconductor structure according to the embodiment.
Fig. 2A~9C is painted a kind of manufacturing method of semiconductor structure according to the embodiment.
[symbol description]
102: substrate
104: buried layer
108,208: stacking
110: conductive layer
112: dielectric layer with high dielectric constant
114: Conductive Core
116: insulating layer
118,218: hard mask layer
120,120a, 120b: active structure
122: channel layer
124: accumulation layer
126: insulating materials
128: conductive connection pads
130: storage unit
132: interlayer dielectric layer
140a: secondary virtual architecture
140b: secondary array structure
154: conductive central portion
156: insulating liner
158: conductor wire
171: the first channels
172: the second channels
181: the first conductive structures
182: the second conductive structures
210: sacrificial layer
212: dielectric layer with high dielectric constant
216: insulating layer
232: interlayer dielectric layer
242: photoresist layer
251: the first predetermined channel positions
252: the second predetermined channel positions
254: conductive central portion
256: insulating liner
271: the first openings
272: the second openings
1811: conductive fill part
1812: dielectric layer with high dielectric constant
1821: conductive central portion
1822: insulating liner
Aa: virtual region
Ab: array region
Specific embodiment
A variety of different embodiments are described in detail below in conjunction with appended attached drawing.Appended attached drawing is served only for
Describe and explain purpose, rather than limitation purpose.For the sake of clarity, element may and be painted not according to actual ratio.This
Outside, some elements and/or component symbol may be omitted from attached drawing.It is contemplated that the element and feature in an embodiment,
It can be advantageously included in another embodiment, without further elucidated above.
A kind of semiconductor structure according to the embodiment, including substrate, secondary virtual architecture, secondary array structure, cubical array are deposited
Storage unit, the first conductive structure and the second conductive structure.Substrate includes virtual region and array region, and array region is adjacent virtual
Region.Secondary virtual architecture is arranged on virtual region and is separated from each other by multiple first channels, and the first channel is along first party
To extension.Secondary array structure is disposed on the substrate and passes through multiple second channels and is separated from each other, and the second channel is along second direction
Extend.These storage units include multiple storage unit groups, are separately positioned in time array structure.First conductive structure and second
Conductive structure is respectively arranged in the first channel and the second channel.Each first conductive structure extends along a first direction.It is each
Second conductive structure extends along second direction.First direction is different with second direction.
Figure 1A~1C is please referred to, such semiconductor structure is shown.In appended accompanying drawing, in order to make it easy to understand, half
Conductor structure is depicted as 3-D vertical channel and non-(NAND) storage organization.
The semiconductor structure includes a substrate 102.Substrate 102 may include formed therein and/or structure thereon and
Element etc..For example, substrate 102 may include the buried layer 104 being disposed thereon.Substrate 102 includes a virtual region Aa and one
Array region Ab.Virtual region Aa abuts array region Ab.
The semiconductor structure includes multiple secondary virtual architecture 140a and multiple secondary array structure 140b.Secondary virtual architecture
140a is arranged on the virtual region Aa of substrate 102.Secondary array structure 140b is arranged on the array region Ab of substrate 102.This
A little times virtual architecture 140a is separated from each other by multiple first channels 171.Each first channel 171 extends along a first direction.
These secondary array structure 140b are separated from each other by multiple second channels 172.Each second channel 172 prolongs along second direction
It stretches.First direction is different with second direction.
The extending direction for not having virtual region or a channel with virtual region but virtual region one and array area
In the identical comparative example of the extending direction of the channel in domain, after carrying out a thermal process, it may be led towards the stress of array region
Cause the structure bending of array region.In this application, since the first channel 171 is along the extension side for being different from the second channel 172
To direction extend, after carrying out a thermal process, the stress towards array region Ab can be by the first channel 171 virtual
Discharge and balance in the Aa of region, can be avoided stress of the high accumulation between virtual region Aa and array region Ab, can have compared with
The physical structure of few stress influence semiconductor structure is able to solve the bending problem of the structure on array region (e.g.
The bending of common source line).
In the present embodiment, first direction can be the X-axis side in attached drawing perpendicular to second direction, such as first direction
To second direction can be the Y direction in attached drawing.In other embodiments, first direction can be not orthogonal to second direction.Figure
The exemplary a part for being painted virtual region Aa and array region Ab of 1A to 1C can have more virtual architecture 140a and more
Secondary array structure 140b setting on substrate 102.
In the present embodiment, each first channel 171 and the second channel 172 are strip structure.In other embodiments, respectively
A first channel 171 and the second channel 172 can have other kinds of shape.
According to some embodiments, semiconductor structure may include a stacking 108 and one or more active junctions across stacking 108
Structure 120.Active structure 120 includes the first active structure 120a and the second active structure 120b, the first active structure 120a and the
Two active structure 120b are separately positioned on virtual region Aa and array region Ab.Although Figure 1B is painted each storage unit groups packet
The example (that is to say the first active structure 120a and the second active structure 120b) of the active structure 120 of two column is included, embodiment is simultaneously
It is not only restricted to this.Stacking 108 includes the multiple conductive layers 110 and multiple insulating layers 116 being alternately stacked.In some embodiments,
Each conductive layer 110 includes two dielectric layer with high dielectric constant 112 and the Conductive Core 114 being disposed there between, extremely such as Figure 1B
Shown in 1C.In such an example, Conductive Core 114 can be formed by a metal material.Two dielectric layer with high dielectric constant 112 can
It is connected to each other.In some other embodiments, each conductive layer 110 can be made of simple layer.In such an example, conductive
Sandwich layer 114 can be formed by DOPOS doped polycrystalline silicon.In some embodiments, stacking 108 further includes a hard mask layer 118, and setting is being led
In electric layer 110 and insulating layer 116.According to some embodiments, each active structure 120 is formed as column kenel.Such
In example, each active structure 120 may include a channel layer 122 and channel layer 122 be arranged in and stacks the storage between 108
Layer 124.In some embodiments, each active structure 120 further includes an insulating materials 126, is filled by 122 shapes of channel layer
At space.In some embodiments, array structure 140 further includes one or more conductive connection pads 128 each time, is respectively coupled to
One or more active structures 120.In some embodiments, array structure 140b further includes an interlayer dielectric layer 132 each time, if
It sets and is stacking on 108.According to some embodiments, secondary array structure 140b can have high-aspect-ratio.
The semiconductor structure includes multiple first conductive structures 181 and multiple second conductive structures 182.First conductive knot
Structure 181 and the second conductive structure 182 are separately positioned in the first channel 171 and the second channel 172.Each first conductive structure
181 (X-direction in attached drawing) extensions along a first direction.Each second conductive structure 182 is along the second direction (Y in attached drawing
Direction) extend.Each first conductive structure 181 is including a conductive fill part 1811 and around the one of conductive fill part 1811
Dielectric layer with high dielectric constant 1812.Each second conductive structure 182 is including a conductive central portion 1821 and around conductive central
One insulating liner 1822 of part 1821.
The semiconductor structure includes the cubical array that multiple storage units 130 are constituted.These storage units 130 include
Multiple storage unit groups (not indicated in attached drawing) are separately positioned in time array structure 140b.More specifically, setting exists
The storage unit 130 of storage unit groups in each of secondary array structure 140b can pass through the conductive layer 110 of stacking 108
Intersection point between one or more described active structures 120 defines.According to some embodiments, the stacking of secondary array structure 140b
108 conductive layer 110 can be configured for wordline, and the conductive connection pads 128 of secondary array structure 140b can be configured for bit line, lead
Electric center portion 1821 can be configured for common source line.
According to some embodiments, the distribution of active structure 120 and quantity in virtual region Aa and array region Ab
It is different.First active structure 120a can have the first density in virtual region Aa, and the second active structure 120b is in array region
There can be the second density in Ab.First density is smaller than the second density.
Illustrate a kind of manufacturing method of semiconductor structure according to the embodiment now.It includes the following steps.Firstly, providing
One initial structure.Initial structure includes a substrate and the preliminary array structure that is formed on substrate.Substrate includes a virtual region
And a burst of column region.Preliminary array structure includes a stacking and multiple active structures across stacking.These active structures it is every
One include a channel layer and be formed in channel layer and stack between an accumulation layer.Secondly, in preliminary array structure
One predetermined channel position forms multiple first channels extended along a first direction, will be located at the preliminary array junctions on virtual region
Multiple secondary virtual architectures are separated into structure.The second predetermined channel position in preliminary array structure is formed prolongs along second direction
Multiple second channels stretched will be separated into multiple secondary array structures in the preliminary array structure being located on array region.Then, exist
Multiple first conductive structures and multiple second conductive structures are respectively formed in first channel and in the second channel.Each first is conductive
Structure extends along a first direction, and each second conductive structure extends along second direction, and first direction and second direction are
It is different.
A~9C referring to figure 2. shows such method.In order to make it easy to understand, the method is depicted as using use
The technique of sacrificial layer forms semiconductor structure as shown in figs. 1 a to 1 c, wherein the sacrificial layer will be led in the next steps
Electric layer replaces.It is respectively the line B-B and line C-C being taken from the attached drawing as indicated by " A " with attached drawing indicated by " B " and " C "
Sectional view.
As shown in Fig. 2A~2B, a substrate 102 is provided.Substrate 102 may include a virtual region Aa and a burst of column region Ab.
Array region Ab is adjacent to virtual region Aa.Substrate 102 may include formed therein and/or structure thereon and element etc..
For example, substrate 102 may include the buried layer 104 being disposed thereon, as shown in Figure 2 B.Buried layer 104 can be formed of oxide.In base
One is formed on plate 102 stacks 208.Stacking 208 includes the multiple sacrificial layers 210 and multiple insulating layers 216 being alternately stacked.Sacrificial layer
210 can be formed by silicon nitride (SiN).Insulating layer 216 can be formed of oxide.In some embodiments, as shown in Fig. 2A~2B,
Stacking 208 further includes a hard mask layer 218, is formed on sacrificial layer 210 and insulating layer 216, is used to compensate membrane stress and keeps away
Exempt to stack and collapses or be bent.
As shown in Fig. 3 A~3B, formed across the multiple active structures 120 for stacking 208.Active structure 120 includes setting respectively
Set the first active structure 120a and the second active structure 120b in virtual region Aa and array region Ab.More specifically, exist
In some embodiments, it can be formed across the multiple holes for stacking 208.Multiple accumulation layers can be accordingly formed on the side wall of hole
124.Accumulation layer 124 can have multilayered structure, such as ONO (oxide/nitride/oxide) or ONONO (oxide/nitridation
Object/oxide/nitride/oxide) etc..Multiple channel layers 122 can be accordingly formed in accumulation layer 124.Channel layer 122
Also it may be formed on the bottom of hole.Channel layer 122 can be formed by polysilicon.One insulating materials 126 can be filled into hole
In remaining space.In some embodiments, multiple conductive connection pads 128 are formed on the insulating materials 126 in hole.Conductive connection pads
128 are respectively coupled to the channel layer 122 of corresponding active structure 120, especially active structure 120.Then, 208 can stacked
With an interlayer dielectric layer 232 is formed on active structure 120.
In this way, described in just being formed " initial structure ".This initial structure includes a substrate 102 and is formed in substrate 102
On a preliminary array structure, wherein preliminary array structure includes the multiple secondary virtual architecture 140a that will be separated in the next steps
And multiple secondary array structure 140b.Preliminary array structure includes a stacking 208 and multiple active structures 120 across stacking 208.
Each active structure 120 includes a channel layer 122 and is formed in channel layer 122 and stacks the accumulation layer 124 between 208.?
In some embodiments, preliminary array structure further includes multiple conductive connection pads 128, is respectively coupled to active structure 120.Some implementations
In example, preliminary array structure further includes an interlayer dielectric layer 232, is formed in stacking 208.
As shown in Fig. 4 A~4B, a photoresist layer 242 is formed on interlayer dielectric layer 232.Photoresist layer 242 includes being used for
Define the aperture of the first predetermined channel position 251 and the second predetermined channel position 252.First predetermined channel position 251 corresponds to
First channel 171, the first channel 171 are configured to the preliminary array structure on virtual region Aa being separated into multiple secondary virtual architectures
140a.Second predetermined channel position 252 corresponds to the second channel 172, and the second channel 172 is configured to will be first on array region Ab
Step array structure is separated into multiple secondary array structure 140b.
It is predetermined in the first predetermined channel position 251 and second respectively e.g. by etch process as shown in Fig. 5 A~5C
Channel location 252 forms multiple first openings 271 and multiple second openings 272.272 exposure of first opening 271 and the second opening
Buried layer 104.Then, photoresist layer 242 is removed.
As shown in figs. 6 a-6 c, sacrificial layer 210 is removed via the first opening 271 and the second opening 272, e.g. by making
With hot phosphoric acid (H3PO4) an etch process.
As figs. 7 a to 7 c, the upper side and lower side of insulating layer 216, first opening 271 with second be open 272 in and
Multiple dielectric layer with high dielectric constant 212 are formed on the top of interlayer dielectric layer 232.For example, can in the structure of Fig. 6 A~6C with
Conformal mode forms a high-k dielectric materials, as figs. 7 a to 7 c.This high-k dielectric materials can be oxygen
Change aluminium (Al2O3) etc..
As figs. 8 a to 8 c, a conductive material is filled into the remainder for removing space caused by sacrificial layer 210
In.Conductive material can be tungsten (W).108 are stacked as shown in 1A~1C figure in this way, just be formed.In addition, and removing this
The unwanted part of high-k dielectric materials.Also that is, by high-k dielectric materials position first opening 271 in layer
Between dielectric layer 232 top on part remove.Then, it is accordingly formed in the second opening 272 using an insulating materials more
A insulating liner 1822.For example, insulating materials can be monoxide material.
As shown in Fig. 9 A~9C, conductive material is filled into the first opening 271 and the second opening 272.In this way, just
Conductive central portion 1821 is formed, is completely cut off by insulating liner 1822 and conductive layer 110.Conductive material can be tungsten (W).From
And the first conductive structure 181 for respectively including a dielectric layer with high dielectric constant 1812 and a conductive fill part 1811 is formed in
In first predetermined channel position 251.Respectively include the second conductive knot of an insulating liner 1822 and a conductive central portion 1821
Structure 182 is formed in the second predetermined channel position 252.In this way, each first conductive structure 181 (example along a first direction
X-direction in attached drawing in this way) extend, each second conductive structure 182 prolongs along second direction (Y-direction e.g. in attached drawing)
It stretches.
Later, other techniques for being typically used for manufacture semiconductor structure can be carried out, seem back segment (BEOL) technique.For example,
In BEOL technique, wordline is defined using conductive layer 110 of the configuration on array region Ab, using configuration on array region Ab
Conductive connection pads 128 define bit line, using conductive central portion 1821 define common source line, and pass through wordline and channel layer
Intersection point between 122 defines storage unit 130.During BEOL, contact can be formed above array region Ab, and in void
Contact can not be formed on quasi- region Aa.
In the methods described above, due to forming the first channel in virtual region, and the extending direction of the first channel is different
There is the extending direction of the second channel in array region the stress in the stacking of high-aspect-ratio can be released by the first channel
It puts, less stress can influence the structure on array region, so as to the inclination for avoiding these from stacking, and can prevent element
Bending.Furthermore, additionally it is possible to the position deviation of the contact formed in BEOL technique caused by avoiding by the inclination that stacks
(dislocation).Although example above-mentioned is to describe to use 3-D vertical channel NAND storage organization and use to use sacrificial layer
Method, embodiment is not limited to this.The concept described herein, being applicable to other wherein and will form has advanced width
The manufacturing method of the semiconductor structure of the stacking of ratio and pass through semiconductor structure manufactured by these methods.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in protection of the invention
Within the scope of.
Claims (10)
1. a kind of semiconductor structure, comprising:
One substrate, wherein the substrate includes a virtual region and a burst of column region, the adjacent virtual region of the array region；
Multiple secondary virtual architectures are arranged on the virtual region and are separated from each other by multiple first channels, respectively first channel
Extend along a first direction；
Multiple secondary array structures are arranged on the array region and are separated from each other by multiple second channels, respectively second channel
Extend along a second direction；
The cubical array that multiple storage units are constituted, wherein these storage units include multiple storage unit groups, are respectively set
In these secondary array structures；And
Multiple first conductive structures and multiple second conductive structures are respectively arranged in these first channels and these second channels,
Wherein respectively first conductive structure extends along the first direction, and respectively second conductive structure extends along the second direction, should
First direction and the second direction are different.
2. semiconductor structure as described in claim 1, wherein the first direction is perpendicular to the second direction.
3. semiconductor structure as described in claim 1, further includes:
Multiple first active structures, are configured on the virtual region；And
Multiple second active structures, are configured on the array region；Wherein these first active structures have in the virtual region
There is one first density, these second active structures have one second density in the array region, and first density is less than this
Second density.
4. semiconductor structure as described in claim 1, wherein respectively first active structure includes a conductive fill part and one
Dielectric layer with high dielectric constant, the dielectric layer with high dielectric constant is around the conductive fill part.
5. semiconductor structure as described in claim 1, wherein respectively second active structure includes a conductive central portion and one
Insulating layer, the insulating layer is around the conductive central portion.
6. semiconductor structure as described in claim 1, wherein each of these secondary array structures includes:
One stacks, including the multiple conductive layers and multiple insulating layers being alternately stacked；And
One or more active structures, pass through the stacking, and each of one or more active structures includes:
One channel layer；And
One accumulation layer is arranged between the channel layer and the stacking；
These storage units of the storage unit groups in each of these secondary array structures are provided with, are by the heap
Intersection point between these folded conductive layers and one or more active structures defines.
7. semiconductor structure as claimed in claim 6, wherein each of these conductive layers includes that two high dielectric constants are situated between
Electric layer and the Conductive Core being disposed there between.
8. semiconductor structure as claimed in claim 6, the wherein each of these secondary array structures further include:
One or more conductive connection pads are respectively coupled to one or more active structures.
9. a kind of manufacturing method of semiconductor structure, comprising:
One initial structure is provided, wherein the initial structure includes the preliminary array structure of a substrate and formation on the substrate,
The substrate includes a virtual region and a burst of column region, which includes a stacking and have across the multiple of the stacking
Source structure, each of these active structures include a channel layer and the storage being formed between the channel layer and the stacking
Layer；
Multiple first predetermined channels position in the preliminary array structure forms multiple first extended along a first direction
The preliminary array structure being located on the virtual region is separated into multiple secondary virtual architectures by channel；
Multiple second predetermined channels position in preliminary array structure forms multiple second ditches extended along a second direction
The preliminary array structure being located on the array region is separated into multiple secondary array structures by road；
Multiple first conductive structures and multiple second conductive knots are respectively formed in these first channels and in these second channels
Structure, wherein respectively first conductive structure extends along the first direction, respectively second conductive structure extends along the second direction,
The first direction and the second direction are different.
10. manufacturing method as claimed in claim 9, wherein the first direction is perpendicular to the second direction.
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| CN201810328457.3A CN110379810A (en) | 2018-04-13 | 2018-04-13 | Semiconductor structure and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20090074536A (en) * | 2008-01-02 | 2009-07-07 | 주식회사 하이닉스반도체 | Method for manufacturing a nonvolatile memory device |
| CN105206613A (en) * | 2014-06-23 | 2015-12-30 | 三星电子株式会社 | Vertical memory devices and methods of manufacturing the same |
| CN106952926A (en) * | 2016-01-07 | 2017-07-14 | 三星电子株式会社 | Semiconductor storage unit |
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2018
- 2018-04-13 CN CN201810328457.3A patent/CN110379810A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090074536A (en) * | 2008-01-02 | 2009-07-07 | 주식회사 하이닉스반도체 | Method for manufacturing a nonvolatile memory device |
| CN105206613A (en) * | 2014-06-23 | 2015-12-30 | 三星电子株式会社 | Vertical memory devices and methods of manufacturing the same |
| CN106952926A (en) * | 2016-01-07 | 2017-07-14 | 三星电子株式会社 | Semiconductor storage unit |
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