KR20180099460A - An active matrix display and a method for threshold voltage compensation in an active matrix display - Google Patents

Abstract

Provided is a method for compensating for a threshold voltage in an active matrix display (200). The display (200) includes pixels (100). Each of the pixels includes: a drive transistor (102) having a driver gate (104) and a compensation gate (106); a first data line (110) selectively connected to the driver gate (104); and a second data line (114) selectively connected to the compensation gate (106). The method of the present invention comprises steps of: (402) driving a display (200) in a compensation measurement mode for measuring a threshold voltage of pixels (100), wherein a first data line is connected to a driver gate (104), a second data line (114) is connected to a compensation gate (106), a measurement signal is actively applied to one of the first and second data lines (110, 114), and the compensation signal is measured on the other of the first and second data lines (110, 114); (404) determining compensation data on the basis of the measured compensation signal; and (406) driving the display (200) in a compensation refresh mode, wherein the second data line is connected to the compensation gate (106) of the drive transistor (102), and the determined compensation data is provided for the compensation gate (106) of the drive transistor (102) on the second data line (114).

Description

TECHNICAL FIELD [0001] The present invention relates to a method of compensating a threshold voltage in an active matrix display and an active matrix display,

The inventive concept relates to a threshold voltage compensation method in an active matrix display and an active matrix display.

The active matrix displays include a plurality of pixels arranged in an array, each pixel having a light emitting element. The light emitted by the light emitting elements of the pixels forms the image displayed by the display. The light emitting device may be, for example, an organic light emitting diode (OLED), and the display may therefore be an active matrix OLED (AMOLED) display.

Active matrix displays, such as AMOLED displays, may use a driving backplane, for example in the form of one or more thin-film transistor (TFT) arrays. The backplane can be fabricated with low temperature fabrication, which enables the use of suitable substrates-for example, to form flexible displays. Active matrix displays such as AMOLED displays are therefore frequently used in a variety of applications and are also promising for future applications.

The drive transistor may be used to drive current through the OLED for light emission from the pixel. The current through the OLED may depend on the characteristics of the drive transistor. These characteristics, in particular the threshold voltage of the drive transistor, can vary over time and can vary between pixels and pixels. Therefore, in order to avoid non-uniform output from the display, correction may be required to compensate for variations and degradation.

A dual-gate drive transistor may be used to provide compensation for changes in the threshold voltage. In current AMOLED displays, it is common to measure the current through an OLED, the change being the result of a change in the threshold voltage of the drive transistor and providing compensation in a current-programmed circuit. For example, WO 02/067327 discloses a pixel current driver that includes each of a plurality of TFTs for driving OLED layers with double gates. The plurality of TFTs may be five TFTs formed by the programmed? VT compensation method. This current-programmed compensation yields complex circuits and thus reduces the maximum resolution of the AMOLED display.

For example, C. Jeon et al., Society for Information Display Digest, Vol. In another approach as discussed in "Simple Architecture and AMOLED Pixel Circuits with Double Gate a-IGZO TFTs for High-Speed Vth Extraction", Vol. 47, Issue 1, pages 65-68 (2016) The transistor was used as an operation scheme to compensate for changes in the threshold voltage. The pixel is driven independently of the threshold voltage so that the degradation due to the change in the threshold voltage can be eliminated. However, this approach instead requires a structure to perform the compensation before the data can be provided to drive the pixels.

The purpose of the inventive concept is to provide an improved method for threshold voltage compensation. It is a particular object of the inventive concept to provide threshold voltage compensation using a simple pixel circuit (and a calibration scheme that only needs to be intermittently applied).

These and other objects of the inventive concept are at least partially satisfied by the invention as defined in the independent claims. Preferred embodiments are described in the dependent claims.

SUMMARY OF THE INVENTION According to a first aspect there is provided an active matrix display device comprising a plurality of pixels arranged in an array including a plurality of rows and a plurality of columns, There is provided a method for threshold voltage compensation in an active matrix display wherein the pixel comprises a driver transistor having a driver gate and a calibration gate, A selection transistor for selectively connecting a first data line and a correction transistor for selectively connecting a second data line to the correction gate of the drive transistor, calibrate transistor, the method comprising: measuring a threshold voltage of at least one pixel, Driving the display in a calibration measurement mode to enable correction of a pixel of the at least one pixel in the calibration measurement mode, Wherein the gate of the correction transistor of the at least one pixel is open to connect the first data line to the driver gate of the driver transistor, Wherein a measurement signal is actively driven to one of the first and second data lines and a correction signal is measured at the other of the first and second data lines, Determining the at least one pixel based on the measured calibration signal; Determining calibration data for the calibration data; And driving the display in a calibration refresh mode to correct for at least one pixel, wherein, in the calibration refresh mode, a gate of the select transistor of the at least one pixel is coupled to the driver A gate of the correction transistor of the at least one pixel is opened to connect the second data line to the correction gate of the drive transistor, And the determined correction data is provided to the correction gate of the drive transistor on the second data line.

According to the invention, the display can be driven in a correction measurement mode for measuring the threshold voltage of the drive transistor of the at least one pixel. The measurement then compensates for the measured threshold voltage at the pixel and provides the determined correction signal to the correction gate of the drive transistor to handle non-uniformities and / or variations between pixels . This may cause the drive transistor to be operated by a simple drive signal to induce a desired output from the light emitting device driven by the drive transistor.

The correction may be performed for all pixels of the display, wherein the correction measurements for all the pixels may be performed in a single session of the correction measurement mode, for example a single frame, or a plurality of sessions of the correction measurement mode And the correction measurements are performed on different pixels in different sessions. Thus, once the active matrix display is corrected and the threshold voltage is compensated, the driving data is provided to the drive transistors of each of the pixels without having to consider variations in the threshold voltage between the pixels .

The correction data provided to the correction gate of the drive transistor may be held at the correction gate for a substantial period of time in the correction refresh mode such that the display is only occasionally & It can be operated in the correction refresh mode.

The correction measurement mode may also be used to measure drift at the threshold voltage, thus identifying a change in the threshold voltage and allowing the active matrix display to detect changes in the threshold voltage of the drive transistors And can be applied at regular intervals to ensure that it can always be compensated for.

The present invention also allows a simple pixel structure with few devices to be used. This indicates that the active matrix can be arranged in high resolution.

The active matrix display must be interpreted as any display comprising an active matrix for driving light output from the light emitting elements associated with the respective drive transistors of the pixels of the display. The light emitting elements may be, for example, an OLED, and thus the active matrix display is an AMOLED display.

The pixels are arranged in an array comprising a plurality of rows and columns. This may mean that the pixels are logically organized into rows and columns and may be generally addressed by lines for controlling the pixels. Terms such as " row " or " column " need not refer to the actual physical orientation of the display. As will be appreciated by one of ordinary skill in the art, rows and columns can be easily interchanged and terms in this disclosure are intended to be interchangeable.

The measurement signal may be actively driven on the first data line and the correction signal may be measured on the second data line. However, the measurement signal may instead be actively applied to the second data line and the correction signal may be measured for the first data line.

The display may be arranged such that the measurement signals are provided on the first data line of all pixels. Alternatively, however, the display may be configured such that for some pixels the measurement signal is actively applied to the first data line and the correction signal can be measured for the second data line, A measurement signal may be actively applied to the second data line and the correction signal may be measured relative to the first data line. If the data lines are shared between adjacent pixels, it may be possible to use the same data line for receiving the correction signals for the adjacent pixels sharing the data line One pixel providing one data line and the other pixel providing the correction signal to its second data line).

According to one embodiment, a first storage capacitor may be connected between the driver gate of the drive transistor and a source or drain of the drive transistor. This indicates that the data provided to the driver gate can be maintained by the storage capacitor, for example to maintain the output by the pixel while drive data is being provided to other pixels. Although such a first storage capacitor ensures a well-controlled drive of the pixel, it can alternatively use a parasitic capacitance between the source or drain of the drive transistor and the driver gate.

According to another embodiment, a second storage capacitor may be coupled between the source or drain of the drive transistor and the correction gate of the drive transistor. This ensures that the data provided to the correction gate by the storage capacitor can be maintained, e.g., without requiring a calibration refresh operation, so that correction data is maintained on the correction gate for a significant period of time To ensure, that means. The parasitic capacitance between the source or drain of the drive transistor and the correction gate can alternatively be used, although such a second storage capacitor can ensure that the correction data is maintained for a period of time that is significant to the correction gate. Also, the display can be operated more frequently in the calibration refresh mode.

According to one embodiment, the driver gate is a front gate of the drive transistor and the correction gate is a back gate of the drive transistor. However, the driver gate may alternatively be the back gate of the drive transistor, and the correction gate may be the front gate of the drive transistor. In addition, the front gate and the back gate of the transistor are relative terms that can be used interchangeably depending on how the transistor is viewed (how the transistor is viewed). Thus, the terms such as " driver gate " and " correction gate ", as used herein, should be interpreted as different gates of the transistor and the correction gate may represent both the front gate or the back gate of the transistor.

Wherein the channel of the drive transistor is not conductive and the driver gate and the correction gate serve as two plates of a capacitor when the transfer to the driver gate of the drive transistor is below a threshold voltage, do. Thus, there is a capacitive coupling between the driver gate and the correction gate. When the voltage at the driver gate of the drive transistor is higher than the threshold voltage, the channel of the drive transistor is conductive and therefore charges of the channel screen the capacitive coupling between the driver gate and the compensation gate . Therefore, the threshold voltage may insight that it can be determined by identifying a change in the capacitance between the driver gate and the correction gate.

According to one embodiment, the measurement signal is a periodically varying signal having a first frequency. It is an insight of the present invention that periodically varying signals can facilitate determination of the threshold voltage in a particularly useful and reliable manner. The periodically varying signal enables extraction of information associated with the threshold voltage from other parameters that affect the measured correction signal.

According to one embodiment, the measurement signal varies in relation to a constant signal, and the constant signal is selected based on the highest possible or lowest possible threshold voltage. The determination of the threshold voltage may not distinguish between the threshold voltage that is greater than or less than the DC voltage level provided by the constant signal (the threshold voltage is determined as an offset to the constant signal) Because it can. By choosing the constant signal above the highest possible threshold voltage, it can be concluded that the threshold voltage can be determined by subtracting the determined offset with respect to the constant signal. Similarly, it can be concluded that by selecting the constant signal below the lowest possible threshold voltage, the threshold voltage can be determined by adding an offset determined in relation to the constant signal. This may indicate that the threshold voltage can be directly determined based on a single measurement signal and does not need to provide different measurement signals (e.g., different DC voltage levels) to determine the threshold voltage have

According to one embodiment, at least a second or third harmonic associated with the first frequency is measured for the correction signal. Wherein the parasitic capacitance between the first data line and the second data line can be large in connection with the capacitive coupling between the driver gate and the correction gate, It may be difficult to identify a change in the capacitance between the driver gate and the correction gate when the voltage is varied higher or lower than the voltage. However, the second and third harmonics of the first frequency may not be affected by the parasitic capacitance between the data lines. Thus, by measuring the second or third harmonic, the parasitic capacitance between the data lines may be possible without affecting the ability to determine the threshold voltage.

As used herein, a " second harmonic " is a part of the measured calibration signal having a frequency that is twice the frequency of the measurement signal (i.e., the first frequency) It must be interpreted. The " third harmonic " should also be interpreted as part of the measured correction signal having a frequency three times the frequency of the measurement signal.

According to one embodiment, the threshold voltage is measured simultaneously with respect to a subset of pixels of a row, first and second measurement signals are provided, and the second measurement signal is Wherein a pixel in a subset of the pixels receiving the first measurement signal on the first data line is 180 占 phase shifted with respect to the first measurement signal, And adjacent pixels in the subset. In other words, the first and second measurement signals 180 [deg.] Phase-shifted with respect to each other are alternately provided to every other pixel in the subset of the pixels. This can be reduced such that the parasitic capacitive coupling between the data lines of adjacent pixels does not affect the determination of the threshold voltage of the drive transistor while still allowing simultaneous measurement of the threshold voltage for a plurality of pixels measurement.

All pixels of a row may be divided into a first and a second subset wherein the threshold voltage for all pixels of the first subset may be determined simultaneously in a first measurement period and all of the pixels of the second subset The threshold voltage for the pixels may be determined simultaneously in the second measurement period. It should be appreciated that more than one subset may be used and therefore more than one measurement period may be used to determine the threshold voltage for all pixels of the row.

In an embodiment, the first subset of pixels may be even pixels in a row. Thus, the threshold voltage can be measured simultaneously for the even pixels of the row. Likewise, the threshold voltage can be measured simultaneously for odd pixels of the row. This means that the threshold voltage can be determined for all pixels in two measurement periods, one for even pixels and one for odd pixels.

As used herein, " even pixels in a row " should be interpreted as pixels arranged in an even-numbered column, (Numbered sequentially starting with 1 for a leftmost column). Likewise, " odd pixels of a row " should be interpreted as pixels arranged in columns having an odd number.

According to another embodiment, the measurement signal is a linearly increasing or decreasing voltage. Thus, instead of applying a periodically varying signal, the measurement signal may be applied such that the voltage on the driver gate drops below the threshold voltage from the threshold voltage to be above the threshold voltage, To " sweep " Instead, the measurement signal can be reduced such that the voltage on the driver gate sweeps over the threshold voltage to switch below the threshold voltage. Thus, the shift can be determined in the measured correction signal when the measured signal is shifted from below the threshold voltage to above the threshold voltage or vice versa.

According to an embodiment, the step of determining the correction data comprises identifying a shift in a linear slope of the correction signal, extracting a threshold voltage based on the identified shift, And determining correction data based on the threshold voltage. The measured correction signal at the correction gate may have a linear dependence on the measurement signal. The threshold voltage may be determined based on an increasing slope of the measured correction signal relative to the smaller measurement signal when the measured signal is above the threshold voltage (the capacitive coupling between the driver gate and the correction gate Is shielded above the threshold voltage).

Using a linearly increasing voltage as the measurement signal can provide a very fast method of determining the threshold voltage. However, it may be difficult for the parasitic capacitance between the data lines to identify a change in the measured correction signal descriptor, since the parasitic capacitance is much less than the capacitive coupling between the driver gate and the correction gate. And can be a main factor that affects the tilt.

According to an embodiment, the method further comprises storing the correction data and using the stored correction data in the correction refresh mode. Thus, the correction data determined in the correction measurement can be stored to be re-used. This allows the calibration refresh mode to be operated separately from the calibration mode to perform a refresh of the calibration that does not necessarily perform the calibration measurement (which can time consuming a larger amount of time) . The voltage at the correction gate may not remain stable over a very long period of time due to gate dielectric leakage, for example. Thus, by storing the correction data, a refreshment of the threshold voltage that compensates for the voltage at the correction gate is performed regularly (e.g., to maintain a desired relation regularly.

According to one embodiment, the display is driven a plurality of times in the calibration refresh mode, between two successive cases driving the display in the calibration mode. The correction measurement may need to be performed only at intervals based on the risk that the threshold voltage of the drive transistor is changed. The correction refresh mode may be performed on the other hand to ensure that the desired voltage is maintained at the correction gate and therefore may need to be performed more frequently.

According to one embodiment, one single row at a time is driven in the correction refresh mode and a correction refresh is performed for the entire display in a normal video frame . This means that the stored correction data can be provided to the pixels of the display in a single frame so that the calibration refresh will not affect the visual experience provided by the display. During the calibration refresh mode, the select transistor may be turned off to keep the image on the display unchanged during the frame in which the calibration refresh is performed.

According to one embodiment, at least one pixel in a single row is driven in the correction measurement mode and the gates of the select transistors and the correction transistors for all other rows are closed to maintain an image of a previous frame on the display lt; / RTI > Thus, during calibration measurements, the image of all rows except one row may be kept on the display, in order to minimize the effect of the visual experience provided by the display. The correction measure may be performed on all pixels in the row before the display is driven to update the frame in which it is displayed. Correction measurements may be performed on individual frames for each row of the array such that the calibration period is not visible to the user viewing the display. One or more frame updates may be performed between calibration measurements for different rows of the array.

According to one embodiment, calibration measurements may be performed on individual frames for the pixels in the same row of the array (such as odd and even pixels that are corrected in different frames).

The combination of pixels that are corrected in a common frame can vary in a number of ways. According to one alternative, all pixels in one or more rows can be corrected in one frame. According to yet another alternative, some pixels from several rows, for example odd pixels or even pixels, are corrected in the common frame.

According to one embodiment, the method includes performing the calibration measurement mode for a row of at least one pixel associated with both a black display and an image displayed on the display, And using the difference of the calibration measurements to estimate a voltage drop of the calibration signal.

Thus, the method can be used for both compensation of changes in the threshold voltage of the drive transistors of the pixels and compensation of the voltage drop of the ground plane. Thus, the method estimates the profile of the ground plane across the display such that any changes in the ground plane profile can be compensated for in the drive of the drive transistors of the pixels. According to one embodiment, the data on the first data line is compensated by the estimated voltage drop when the display is driven in a normal mode for displaying an image.

The correction measurements associated with the black display may be performed during start-up of the active matrix before the first image is displayed on the display. The correction measurement associated with the image displayed on the display is then performed immediately after the start-up of the display such that no other shift occurs in the threshold voltage and the difference in the correction measurements is a ground resistance drop ground resistive drop).

The correction measurements for estimating the voltage drop of the ground plane may be performed on a few selected rows of the display. Thus, in this case, the correction measurements are not performed for all the rows, which may take too much time for certain display configurations, and thus may affect the visual experience of the images displayed on the display . The measurements performed on the selected rows may also be used to estimate the profile of the ground plane between the selected rows.

According to a second aspect, there is provided a liquid crystal display comprising: a plurality of pixels arranged in an array comprising a plurality of rows and a plurality of columns; A pixel includes a drive transistor having a driver gate and a correction gate, a selection transistor for selectively connecting a first data line to the driver gate of the drive transistor, a second transistor for selectively connecting a second data line to the correction gate of the drive transistor A correction transistor for making The data lines comprising the first and second data lines arranged in a direction of the rows or columns of the array, each data line being arranged in a matrix along the row or column of the array, Said data line being connected to said selection transistors of pixels on one side of said data line and to said correction transistors of pixels on an opposite side of said data line; And control circuitry coupled to the data lines, the control circuitry being arranged to provide data on the data lines to display an image in a normal mode of the display, Wherein the circuit is further arranged to provide correction data on the data lines to provide correction data to the correction gate of the drive transistor of the pixel in the correction refresh mode of the display, Further configured to provide a measurement signal on one of the first and second data lines and to measure a correction signal on the other of the first and second data lines in an active matrix display / RTI >

The effects and features of this second aspect are largely analogous to those described above in connection with the first aspect. Embodiments mentioned in connection with the first aspect are generally compatible with the second aspect.

The control circuit can thus control the display to drive the display in a normal mode, a correction refresh mode and a correction measurement mode, which are further described in connection with the method of the first aspect described above.

Each data line may be connected to both the selection transistor on one side of the data line and the correction transistor on the opposite side of the data line. This can be used for the data lines to provide data to the driver gates of the drive transistors of the pixels through the select transistors and to measure the correction signals for the other pixels via the correction transistors or to provide correction data. . A signal for the gates of the select transistors and the correction transistors may determine how the data lines are used.

According to one embodiment, the control circuit is arranged to provide the measurement signal with a periodically varying signal having a first frequency.

According to one embodiment, the control circuit is arranged to measure at least a second or third harmonic for the correction signal associated with the first frequency.

According to one embodiment, the display further comprises an oscillator used to provide a frequency of the measurement signal and used to provide a reference frequency for extracting the at least second or third harmonic. . This means that a single oscillator can be both re-used to provide the measurement signal and to measure the correction signal. Thus, the reference frequencies for measuring the second and third harmonics may be very accurately related to the first frequency of the measurement signal.

According to one embodiment, the control circuit is arranged to provide, for each data line, an analog signal when driving the display in a normal mode, and when driving the display in a corrected measurement mode, the successive approximation analog- and a digital to analog converter arranged in a component of a successive approximation analog to digital converter. Which means that the configurations of the control circuit can be re-used such that a compact layout of the control circuit can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the inventive concept will be better understood with reference to the following illustrative and non-limiting detailed description and the accompanying drawings. In the drawings, the same reference numerals will be used for the same elements unless otherwise stated.
Figures la-b are schematic diagrams of pixel topologies of an active matrix display.
2 is a schematic diagram of an active matrix display.
3-5 are schematic diagrams for explaining driving of a pixel in each of a normal operation mode, a correction refresh mode, and a correction measurement mode.
6A-B are schematic diagrams of a capacitive model of each pixel when the voltage on the driver gate of the drive transistor is below the threshold voltage and above the threshold voltage.
7-8 are charts illustrating the first, second and third harmonics of the correction signals measured for different frequencies of the measurement signal.
Figures 9a-b are schematic diagrams of the control circuit and illustrate the simultaneous display drive for odd or even pixels in the correction measurement mode, respectively.
10A is a schematic diagram of a control circuit according to one embodiment.
Figs. 10b-d are schematic diagrams of the control circuit of Fig. 10a, illustrating driving a display in a normal mode, a correction measurement mode for correcting odd pixels, and a correction measurement mode for correcting even pixels, respectively.
Figures 11A-B are schematic diagrams of rows of pixels and illustrate the simultaneous driving of a display in a calibration mode for two of four pixels.
11C is a schematic diagram of a control circuit according to one embodiment.
12 is a schematic diagram of a display illustrating calibration measurements for ground resistive drop compensation.
13 is a flow chart of a method according to one embodiment.

Figures 1a-b show two different variants of the pixel topology of the active matrix. Each pixel includes an organic light emitting diode (OLED) for emitting light when an electric current is applied to an OLED (organic light emitting diode). In Figure 1A, an inverted OLED stack is shown. In the pixel topology of Figure 1A, the OLEDs of each pixel have a common anode. In FIG. 1B, a normal OLED stack is shown, and each of the pillars' OLEDs has a common cathode. Although the topology of FIG. 1B is shown and discussed in the embodiments below, it should be noted that the inverted OLED stack topology of FIG. 1a may be used instead.

When light is emitted by the pixels provided by the OLEDs, an active matrix OLED (AMOLED) is provided. It should be noted that, although OLEDs are mainly discussed herein, active matrix displays can be applied to other types of light emitting elements that are controlled by an active matrix and arranged in an array. While AMOLED displays may be desirable in terms of, for example, fast switching speeds of the pixels, the current driven light emitting devices may be implemented in a number of different ways, as will be appreciated by one of ordinary skill in the art Lt; / RTI >

The pixel 100 includes a driver transistor 102 having a driver gate 104 and a correction gate 106. Pixel 100 includes a select transistor 108 for selectively connecting a first data line to a driver gate 104. The pixel 100 further includes a correction transistor 112 for selectively connecting the second data line 114 to the correction gate 106.

The signal on the first data line 110 may be provided to the driver gate 104 of the drive transistor 102 through the select transistor 108. [ The signal on the first data line 110 thus opens the channel of the driver transistor 102 and thus the current through the OLED 116 connected to the drain or source of the drive transistor 102 To provide data. The light output by the OLED 116 is controlled by the current level through the OLED 116 so that the control circuit can control the light output by the pixel by controlling the data provided to the first data line 110. [ current level.

The signal on the second data line 114 may be provided to the correction gate 106 of the drive transistor 102 via the correction transistor 112. The signal on the second data line 114 may thus provide data for setting the voltage at the correction gate 106 of the drive transistor 102. [ The voltage at the correction gate 106 can be adapted to compensate for a change in the threshold voltage of the drive transistor 102 so that data provided to the first data line 110 is applied to the pixel 100, And may disregard variations in the threshold voltage to control the light output by the light source. The current applied through the OLED 116 may thus depend on the voltage difference between the voltage at the driver gate 104 and the source of the drive transistor 102 and also between the correction gate 106 and the source of the transistor 102 The voltage level at the correction gate 106 is provided in association with a default threshold voltage that is assumed by the data provided on the first data line 110 .

The pixel 100 may further include a first storage capacitor 118 which may be connected between the driver gate 104 of the drive transistor 102 and the source of the drive transistor 102. This means that the data provided to the driver gate 104 can be maintained by the storage capacitor 118, e.g., to maintain the output by the pixel 100 in the display while drive data is being provided to other pixels, . The first storage capacitor 118 may alternatively be coupled to the drain of the drive transistor 102.

Driver gate 104 and drive transistor 104 may be used to maintain data on driver gate 104 even though such first storage capacitor 118 may ensure driving of well- 102 may be alternatively used with parasitic capacitances between the source or drain of the transistors.

The pixel 100 may further include a second storage capacitor 120 which may be coupled between the correction gate 106 of the drive transistor 102 and the source of the drive transistor 102. This means that the data provided to the correction gate 106 can be maintained by the storage capacitor 120, for example, that the correction data is provided to the correction gate 116 on the second data line 114 But can be maintained on the correction gate 106 for a significant period of time that is not required. The second storage capacitor 120 may instead be connected to the drain of the drive transistor 102.

The parasitic capacitor between the correction gate 106 and the drive transistor 102 can be compensated for even if the second storage capacitor 120 can compensate for a significant period of time in the correction gate 106. [ May be used to hold data on the gate 106. In addition, if the second storage capacitor 120 is not provided, the correction data is instead provided more often to the correction gate 106 to refresh the correction data, and the threshold voltage of the drive transistor 102 of the pixel 100 Gt; 100 < / RTI >

Pixel 100 may thus be provided with three transistors 102,108 and 112 and two capacitors 118,120 and the topology of the pixel is thus the so-called 3T2C (three transistors, two capacitors) Topology.

In Figure 2, an active matrix 200 comprising an array of pixels 100 arranged in rows and columns is schematically illustrated. The display 200 includes data lines 110 and 114 that run along the columns of the array. The display 200 further comprises a control circuit 202, which is connected to the data lines 110 and 114. The control circuitry 202 may also be arranged to measure signals on the data lines 110 and 114 to provide data to the data lines 110 and 114 as will be described in detail below.

The control circuit 202 may be provided to a data driver integrated circuit, which generates data signals on the data lines and provides components for measuring the received data signals on the data lines. The control circuit 202 may be further coupled to a memory for storing correction data of the pixel 100 or may include an integrated memory of a data driver integrated circuit.

The multiplexer may be used to couple a plurality of data lines to one output of the multiplexer control circuit 202. Thus, the control circuit 202 may include multiplexers. If multiplexers are introduced, at least two multiplexers may be introduced to separately connect to each of the odd data lines and the even data lines, Since it requires even lines, and will be described further below.

The display 200 may further include select lines 204 and correction lines 206 that follow the direction of the rows of the array and are perpendicular to the data lines 110 and 114. Selection lines 204 may provide signals for selectively activating selection transistors 108 in a row of pixels 100. Similarly, correction lines 206 may provide signals for selectively activating correction transistors 112 in a row of pixels 100.

The display 200 includes a pair of select lines 204 for each row of pixels 100 to enable independent selection of pixels in each of the even or odd columns . Similarly, the display 200 may include a pair of correction lines 206 for each row of pixels 100. This may enable correction measurements for even pixels to be separated from correction measurements for odd pixels so that correction data determined for even pixels can be maintained during correction measurements for odd pixels.

The topology for driving the OLEDs of pixels as well as the data lines 110 and 114, the selection lines 204 and the correction lines 206 may be arranged on the backplane of the display 200 have.

The display 200 may further include driver circuitry 208 for driving the select lines 204 and the correction lines 206. The driver circuit 208 may be arranged, for example, in a gate-in-panel (GIP) integrated on the backplane. According to an alternative, the driver circuit 208 may be provided as dedicated silicon drivers.

The transistors for controlling the light output by the pixels 100 may be n-type transistors as well as p-type. The backplane may comprise a thin-film transistor (TFT), for example, a hydrogenated amorphous Si (a-Si: H), a polycrystalline silicon, (amorphous) indium-gallium zinc oxide (a IGZO, IGZO) TFT. The present invention can be applied to displays using an active matrix and is not limited to a particular type of display. For example, it may include RGB or RGBW AMOLED displays, which may include fluorescent or phosphorescent OLED, polymer or polydendimers, high power efficient phosphorescent polyfunctional dimers, And can be applied to the same AMOLED displays.

For example, it can be applied to RGB or RGBW AMOLED displays which may include AMOLED displays such as fluorescent or phosphorescent OLEDs, polymers or polydendrimers, high power efficient phosphorescent poly dendrimers, and the like.

3-5, three different modes of operating the pixel 100 will be discussed.

As shown in FIG. 3, the first mode is a normal mode and can be operated according to driving of the state of the art AMOLED displays. In this mode, data is provided on the first data line 110 of the pixel 100 to control the light output of the pixel 100. In the normal operation mode, the correction signal on the correction line 206 is low and the correction performed prior to (100) pixels is unchanged. The correction value stored in the second storage capacitor 120 therefore remains the same. In addition, the selection signal on the selection line 204 is high so that drive data provided on the first data line 110 is applied to the driver gate 104 of the drive transistor 102. The drive data is stored in the first storage capacitor 118 so that drive data on the driver gate 104 is maintained. The driving data controls the desired current to be applied through the OLED 116. [

The selection signals may be driven row by row with a horizontal synchronization (HSYNC) rate, which is synchronized with the data provided on the data lines 110 so that the correct driving data is provided to the driver Gate 104 as shown in FIG.

If the display 200 includes a pair of select lines 204 for each row of pixels 100, a high select signal is simultaneously provided to the select transistors 108 of all the pixels 100 in the row All of the pair of selection lines 204 can be driven together. In the calibration refresh mode, the select signal on select line 204 is

The second mode, shown in Figure 4, is the calibration refresh mode. In this mode, data is provided on the second data line 114 of the pixel 100 to provide calibration data to the pixel 100. In the calibration refresh mode, the selection signal on the selection line 204 is low and the light output by the pixel 100 is unchanged. The value of the driving data on the first storage capacitor 118 therefore remains the same. This means that the image displayed by the display 200 will be maintained during one frame of calibration refreshment. The correction signal on the correction line 206 is also high enough that the correction data provided on the second data line 114 can be applied to the correction gate 106 of the drive transistor 102. [ The correction data may also be stored on the second storage capacitor 120 so that the correction data on the correction gate 106 may then be retained. The correction data provides compensation associated with the threshold voltage of the drive transistor 102 to enable the drive data provided in normal operating mode to control the desired current to be applied to the OLED 116. [

The correction signals may be driven row by row at a rate of HSYNC and may be synchronized to the data provided on the data lines 114 so that correct calibration data is provided for each pixel 0.0 > 100, < / RTI >

Each of the data lines 110 and 114 may be shared by adjacent pixels 100 so that the data line is connected to the first data line 110 for one pixel and the second data line 114 ) Can be formed. This means that a data line providing correction data for a pixel in column n when the display 200 is driven in the calibration refresh mode is activated for a pixel at column n + 1 when the display 200 is driven in normal operation mode. Which can be used to provide drive data. Thus, the control circuit 202 may be arranged to provide correction data having a one column offset with respect to driving data for displaying an image on the display 200.

In addition, if the display 200 includes a pair of correction lines 206 for each row of pixels 100, then both of the correction lines 206 are all of the pixels 100 of the row Can be driven together to provide a high selection signal to the correction transistor 112 at the same time.

Since the correction refresh mode can be operated to refresh the correction data of all the pixels 100 of the display 200 in one frame, the correction refresh mode is performed without visual effect to the user viewing the display 200 .

The correction refresh mode must be performed sufficiently frequently so that the correction data provided on the correction gate 106 of the drive transistor 102 can be maintained. For example, the charge stored on the second storage capacitor 120 may vary due to leakage, and the correction refresh mode needs to be performed before the correction data on the correction gate 106 changes significantly .

The interval of the calibration refresh modes may depend on the gate dielectric leakage and the magnitude of transistor current when turned off. The measurement of these parameters can be performed once, for example as a manufacturing step of a display. The frequency at which the calibration refresh mode is performed can then be adapted to these parameters of the display to set the default interval of the calibration refresh mode.

The calibration refresh mode may need to be performed, for example, in one frame per minute, ten minutes, or even one frame per use of the display. Thus, the calibration refresh mode is not performed very often. Therefore, not only is the user not affected by a single frame performing the calibration refresh, but the frames assigned to the calibration refresh mode are far far apart (so far apart), so that a single frame of the calibration refresh mode is recognized by the user The total experience of images displayed on the sea chart display will be minimally affected.

The third mode is the calibration measurement mode, and is shown in Fig. In this mode, the selection signal on the select line 204 and the correction signal on the correction line 206 are high for the pixel (100). The measurement signal is actively applied on the first data line 110 and the measurement signal and the correction signal induced by the measurement signal are measured on the second data line 114. [ The measurement signal may be provided in relation to the threshold voltage of the driver transistor 102 so that the measured correction signal may be analyzed to extract the threshold voltage of the driver transistor. The associated determination of the different embodiments of the measurement signals and the threshold voltage of the drive transistor 102 will be further described below.

The threshold voltage for one pixel 100 may be determined using the first data line 110 and the second data line 114. [ Since the data lines 110 and 114 can be shared by the neighboring pixels 100 implementing the first data line 110 for one pixel, Lt; / RTI > Thus, the correction measurement mode for one row may include several operations of measuring the threshold voltage for the drive transistors 102 of different pixels in the row. However, as will be described below, it is possible to measure the threshold voltages for several pixels simultaneously, even if not for the rowed pixels.

Correction measurements may be performed on all pixels in one row. For all other rows, the signals on select lines 204 and correction lines 206 are all low such that an image of a former frame of display on display 200 can be maintained. In order to accommodate losses in the visual experience during a single frame of correction measurements, the intensity of the row to be calibrated may be increased by, for example, 40% in the frame before the correction measurement and in the frame after the correction measurement, Can be increased.

As can be appreciated, the correction measurement mode can provide correction measurements for a row of pixels 100. [ The correction measurement mode may thus be repeated a number of times to perform correction measurements on all the pixels 100 in all the rows. Several normal operating mode frames pass between two subsequent frames where correction measurements are performed to allow the visual experience of the images displayed on the display 200 to be minimally affected.

The correction measurement mode can be used to determine the threshold voltage of the drive transistor 102 of each pixel 100 so that the pixel 100 can be corrected to the specific threshold voltage of the drive transistor 102 of the pixel 100. [ This allows the display to be compensated for threshold voltage variations in the display 200. These differences can be compensated for by the correction measurements that cause the correction measurements to display high quality images on the display 200.

The threshold voltage of the drive transistor 102 may vary over time and may be different for different pixels 100, depending on, for example, the light output by the pixel 100, It may be necessary to perform at regular intervals. The correction refresh mode can be performed, for example, in one frame per minute, but the correction measurement can be performed once in an hour. The frequency of the correction measurement can be set depending on the light output. If the display 200 is driven to provide a bright output, the calibration measurements can be measured more frequently.

The drive transistors 102 of the pixel 100 are driven by a bias-stress effect, that is to say at a semiconductor substrate, a gate dielectric or an interface between a semiconductor and a dielectric, Charge is time-dependent trapped in a localized defect state from the channel of the channel. The trapped charges do not contribute to the current through the drive transistor 102 but affect the charge balance of the drive transistor 102. Thus, in use of the drive transistor 102, there may be a time-dependent shift of the threshold voltage due to bias stress.

When the voltage at the driver gate 104 of the driver transistor 102 is lower than the threshold voltage, the channel of the drive transistor 102 is not conductive and the driver gate 104 and the correction gate 106 are connected to the two plates of the capacitor, plates of a capacitor. Thus, there is a capacitive coupling between the driver gate 104 and the correction gate 106. The channel of the drive transistor 102 is conductive and therefore the charges of the channel are coupled to the capacitive couple 104 between the driver gate 102 and the correction gate 104. Thus, when the voltage of the driver gate 104 of the drive transistor 102 is higher than the threshold voltage, Screen the ring.

The correction signal provided in the correction measurement mode allows the threshold voltage to be determined by identifying a change in capacitance between the driver gate 104 and the correction gate 106.

Referring now to FIG. 6A, a capacitive model of a pixel is described when the voltage V _GS on the drain gate 104 is below the threshold voltage. In this model, it is assumed that the OLED capacitance is high enough to be regarded as a short for frequencies under consideration. There is a capacitive coupling C _FGBG between the driver gate 104 and the correction gate 106, as shown in Figure 6A.

The driver gate 104 is shielded from the correction gate 106 when the voltage V _GS on the driver gate 104 is higher than the threshold voltage as shown in Figure 6B.

In one embodiment, the measurement signal is a linear sweep of a voltage from a first voltage below an expected threshold voltage of the drive transistor 102 to a second voltage above an expected threshold voltage of the drive transistor 102 ). The measured signal may also be an increasing signal, but the incremental slope of the measured correction signal may change when the measured signal crosses the threshold voltage of the drive transistor 102. [ When the driver gate 104 is shielded from the correction gate 106, the increase in the measured correction signal is greater than the parasitic capacitance C _{N -N + 1} between the first data line 110 and the second data line 114 Lt; / RTI >

Similarly, the measurement signal may provide a linear sweep from the first voltage above the expected threshold voltage of the drive transistor 102 to the second voltage below the expected threshold voltage of the drive transistor 102, depending on the alternative. The measured correction signal may also be a decreasing signal, but the decreasing slope of the measured correction signal may change as the measured signal crosses the threshold voltage of driver transistor 102. [

In another embodiment, the measurement signal provides a periodically varying signal having a first frequency. For the first frequency below the maximum frequency, the capacitive model shown in Figures 6A-B is reasonable. The maximum frequency is the frequency at which the charge of the channel can still screen the capacitive coupling between the driver gate 104 and the correction gate 106. The maximum frequency is inversely related to the channel length of the driver transistor and the determination of the maximum frequency is described in Bhoolokam et al., "Analysis of frequency dispersion in amorphous In-Ga-Zn-O thin -film transistors ", Journal of Information Display, Vol. 16, No. 1, pages 31-36 (2015).

The measured correction signal can be analyzed to identify parts of the calibration signal to determine the threshold voltage for the drive transistor. The measured correction signal may include a first harmonic that is part of a measured correction signal having the same frequency as the measurement signal, i.e., a first frequency. The measured correction signal may also include a second or third harmonic (i.e., having a frequency that is two or three times the frequency of the first frequency). The measurement correction signal may also include even higher order harmonics, but the higher the order of the harmonics, the smaller the signal becomes. This also means that higher order harmonics may be more difficult to measure.

Therefore, even if higher order harmonics can be used, second and / or third harmonics may be preferred and use of the second and / or third harmonics is described in more detail below.

The amplitude of the first harmonic H1 can be approximated as shown in Equation 1 when the periodically varying signal changes in association with the DC voltage V _GS below the threshold voltage.

Where C _{Data (N + 1)} is the capacitive coupling between the second data line 114 and ground and A is the amplitude of the applied periodic signal.

The amplitude of the first harmonic H1 can be approximated as shown in Equation 2 when the periodically varying signal is changed in association with the DC voltage on the threshold voltage.

The capacitive coupling C _FGBG between the driver gate 104 and the correction gate 106 is generally small with respect to the parasitic capacitance C _{N -N + 1} between the data lines and ground and A is the amplitude of the measurement signal. This means that it is difficult to identify whether the DC voltage is above or below the threshold voltage and thus make it difficult to determine the threshold voltage from the first harmonic of the measured correction signal.

However, when a DC voltage close to the threshold voltage is provided, the measured signal swings across the threshold voltage, and the second and third harmonics can be identified in the measured correction signal and the threshold voltage Can be used to determine.

A ratio of the difference between the DC voltage level V _GS and the threshold voltage V _T associated with the amplitude of the measured signal when the measured signal crosses the threshold voltage is less than one. That is, Equation 3 is obtained.

In these situations, the amplitudes of the first, second and third harmonics for the ideal screening of the capacitive coupling between the driver gate 104 and the correction gate 106 are given by equations (4) - (6).

Thus, if the measured signal crosses the threshold voltage, the second and / or third harmonics can be advantageously used to determine the threshold voltage. As is clear from the above equations 5-6, the amplitudes of the second and third harmonics do not depend on the parasitic capacitance between the data lines 110 and 114, and thus may not be affected by this parasitic capacitance .

The relationship between the amplitude of the second or third harmonic and the ratio x ₀ can be used to determine the threshold voltage. 7 shows the amplitudes of the first, second and third harmonics as a function of x _{0 (as} a function of ΔC _FGBG / C _{Data (N + 1)} ) * A. The effect of the parasitic capacitance is shown in the description of the first harmonic not included. By analyzing the measured calibration signal for a given DC voltage V _GS and amplitude A of the measurement signal, x ₀ can be determined and therefore the threshold voltage of the driver transistor 102 can be extracted.

The analysis of the measured correction signal can be performed in several different ways. For example, the applied correction signal may vary iteratively to change x ₀ . The maximum amplitude of the second harmonic or the minimum (or both) of the third harmonic may then be identified, which corresponds to x ₀ = 0. Thus, the threshold voltage can be determined to be equal to the DC voltage V _GS used in iteration with x ₀ = 0.

Thus, according to one embodiment, repetitions of periodically varying signals related to a constant signal can be provided as a measurement signal, and the constant signal varies between iterations.

According to the alternative, iterative processes are not necessary. Thus, the measured signal can be provided as a periodically varying signal associated with a constant signal and the threshold voltage can be determined directly. In this approach, the ratio between the amplitude of the third harmonic and the amplitude of the second harmonic is used. As is clear from Equations 5-6, this ratio is given by Equation 7. " (7) "

Thus, by determining the amplitudes of the second and third harmonics, the threshold voltage can be directly calculated as in equation (8).

This means that the change in the threshold voltage can be compensated by varying the voltage of the correction gate in relation to the voltage used during the correction measurement. The voltage change of the correction gate is thus given by Equation (9).

The voltage to be used for the given correction gate by the voltage used during the calibration measurement and the change? V _BG determined in equation (9) can be stored in the memory of the control circuit 202 to store the correction data. It should be noted that other information may be stored instead so that the threshold voltage to be applied to the correction gate 106 can be determined. Thus, the change [Delta] V _BG may be stored, or even the difference between the applied DC voltage V _GS and the threshold voltage may be stored.

If there is no further voltage dependence of the capacitance CFGBG within the swing of the applied measurement signal, Equation (7) above in the voltage swing may no longer apply. Therefore, it may not be possible to use a non-iterative approach, since the determined threshold voltage may not be correct. However, using an iterative approach, the minimum of the amplitude of the third harmonic can still be determined and can be associated with VGS = VT at iteration where the minimum is determined. Thus, it may still be possible to determine the threshold voltage.

Also, as described above, when applying ideal screening of the capacitive coupling between the driver gate 104 and the correction gate 106, there is a maximum frequency of the first frequency. For example, if the driver transistor 102 has a channel length of 10 [mu] m and the applied DC voltage is 1 V, frequencies up to 5 MHz must be available at the first frequency. Near and above this maximum frequency, oscillations around the driver gate voltage above the threshold voltage will also be coupled to the correction gate. Thus, the difference of the correction signal measured between above and below the driver gate voltage will be smaller, and therefore it may be more difficult to determine the threshold voltage.

However, it may still be possible to use the first frequency above the maximum frequency. In Fig. 8, a simulation of the first, second and third harmonic responses to the 3dB frequency of the drive transistor is shown. As is apparent from Fig. 8, it may still be possible to determine the maximum of the second harmonic and / or the minimum of the third harmonic, and thus the threshold voltage can be determined even using a frequency higher than the maximum frequency.

The selection of the first frequency to be used can take all of the frequencies of the maximum frequency and noise sources discussed above and avoid noise interference from these sources. For example, there may be environmental noise (e.g., from lamps around the display) at frequencies up to nearly 100 kHz. In addition, charger noise and display noise can be greater up to 100 kHz and can also occur up to 500 kHz and above. Measurement systems for capacitive touch can also use frequencies of 100-500 kHz that produce noise in this frequency spectrum. Thus, the first frequency may be selected above 100 kHz, 50 kHz, or 1 MHz to avoid noise interference. For example, the first frequency may be selected in the range of 100 kHz-5 MHz or 500 kHz-5 MHz.

In the discussion above, the OLED capacitance is also sufficiently high for frequencies that the OLED can be regarded as shorted. If the OLED capacitance is not large, the measured correction signal is affected.

For the driver voltage below the threshold voltage, an additional signal corresponding to (C ₁ * C ₂ ) / (C _{Data (N + 1)} * C _OLED ) * A may be present in the measured correction signal. On the threshold voltage, the voltage at the OLED follows the driver gate voltage. The fraction C ₂ / C _{Data (N + 1)} is obtained from the measured correction signal. Even in this case, the intersection above the threshold voltage below the threshold voltage generates the second and third harmonics. Again, by repeatedly determining the minimum of the amplitude of the third harmonic, the threshold voltage can be determined.

The analytical equations for calculating the threshold voltage also depend on the correctness of the assumption that the OLED can be regarded as a short for frequencies considered. Thus, this assumption is based on OLEDs with sufficient conductivity or sufficiently high capacitance. In normal circumstances, an OLED will meet having either a sufficiently high conductivity or a sufficiently high capacitance. Nevertheless, if the OLED does not fulfill any assumption, it may also be more appropriate to perform iterative procedures in this respect, and the DC voltage level V _GS may be identified when the amplitude of the third harmonic is at a minimum And is varied to determine the threshold voltage based on this identification.

As discussed above, the measurement signal in the correction measurement mode is performed at repetitions of a selected DC voltage level VGS near the threshold voltage or a DC voltage level VGS near the threshold voltage. This means that there is almost no output of light by the OLED 116 induced by the measurement signal.

When a single iteration of the measurement signal is made, the DC voltage level can be selected corresponding to the highest possible or lowest possible threshold voltage. As indicated above, the ratio between the amplitudes of the third harmonic and the second harmonic provides only the difference between the DC voltage level and the threshold voltage. Thus, by selecting a DC voltage level that corresponds to the anticipated highest possible or lowest possible threshold voltage, the determined difference is the threshold voltage that is below the highest possible threshold voltage, whichever is used as the DC voltage level, As shown in Fig.

Therefore, the calibration measurement may include the following procedure.

First, a DC voltage is applied to the first data line 110, and in one embodiment the DC voltage corresponds to the highest possible threshold voltage and in yet another embodiment corresponds to the lowest possible threshold voltage. The DC voltage is then applied to the second data line 114 to provide the desired voltage at the correction gate 106.

The signals on the select line 204 and the correction line 206 are then high enough to open the gates of the select transistors 108 and the correction transistor 112 drives the data on the first data line 110 Is high enough to provide the driver gate 104 of the transistor 102 and the data on the second data line 114 to the correction gate 106 of the drive transistor 102. [ The second data line 114 is then made high impedance and the calibration measurement can be initiated.

Now, the periodically varying signal is provided on the first data line 110 providing the AC voltage of the first frequency. The amplitude of the AC voltage may correspond to a double of the difference between the lowest possible and the highest possible threshold voltage (the lowest possible and the highest possible threshold voltage). This means that the voltage at the driver gate 104 will change above and below the threshold voltage so that the second and third harmonics can be generated.

In one embodiment, when the DC voltage is at the highest possible threshold voltage, the AC voltage will bring the driver gate voltage below the threshold voltage for below-zero voltages. On the other hand, in the embodiment, in the embodiment, when the DC voltage is the lowest threshold voltage, the AC voltage will bring the driver gate voltage above the threshold voltage for voltages above zero.

The second and third harmonics may be determined in the measured correction signal. Based on the amplitudes of the determined second and third harmonics, the corrected voltage of the correction gate 106 may be calculated.

The signal on select line 204 may then be turned low enough to close the gate of select transistor 108. [ The signals may then be actively provided on the data lines 114 to provide correction signals to correct voltages at the correction gates 106 of the pixels 100. [ Finally, the signal on the calibrate line 206 may be turned low enough to close the gate of the correction transistor 112 and the next frame may be provided on the display by driving the display in normal operation mode.

Referring now to Figures 9-11, the drive architectures for providing measurement signals and determining measured correction signals will be discussed.

The control circuit 202 may include an oscillator 210, which may be used to both generate a measurement signal and extract the second and third harmonics.

A signal from the oscillator 210 may thus be provided to a phase-locked loop (PLL) 212 and the frequency provided by the oscillator 210 may be provided to a sixth of the oscillator frequency the oscillator frequency. This means that the signals for extracting the second and third harmonics can be generated at half of the oscillator frequency and the oscillator frequency, respectively, so that the oscillator 210 can be advantageously re-used.

The PLL 212 may provide modulations to output two different signals 214 and 216 to adjacent pixels 100 on the two data lines 218a and 218b. The modulations are preferably related to the phase of the signal, but alternatively amplitude modulation may be used. In one embodiment, the second measurement signal 216 is 180 DEG phase shifted relative to the first measurement signal 214. This can reduce the overall external radiation and reflections at the end of the data lines. In addition, since the second data line 114 may be coupled with opposite signals on both sides of the pixel 100, the second data for the first data lines 110 of adjacent pixels The capacitive coupling on line 114 will be minimal.

In Fig. 9A, simultaneous driving of odd pixels in a row is described. A first measurement signal is provided on the first data line 218a coupled to the first data line 110 of the first pixel 100a in the row and the drive transistor 102 of the first pixel 100a ) Driver gates 104 of the driver IC. A second measurement signal is provided on the second data line 218b coupled to the first data line 110 of the third pixel 100c in the row and the drive transistor 102 of the third pixel 100c ) Driver gates 104 of the driver IC. Thus, these odd pixels can be driven simultaneously in the correction measurement mode.

The first data line 110 of the second pixel 100b in the row may also function as the second data line 114 of the first pixel 100a. Accordingly, the data line 114 is used for measuring a correction signal based on the measurement signal provided to the first pixel 100a by the data line 110. [ Therefore, the data line 114 may be coupled to the amplifier 220b to enable measurement of the correction signal of the first pixel 100a. Similarly, the second data line 114 of the third pixel 100d may function as the first data line 110 of the fourth pixel 100d and may be coupled with the amplifier 220d to form a third pixel 100c 0.0 > a < / RTI > calibration signal.

In Figure 9B, simultaneous driving of even pixels of a row is shown. Now, the first measurement signal is coupled to the first data line 110 of the second pixel 100b and the second measurement signal is coupled to the first data line 110 of the fourth pixel 100d. The first data lines of the first and third pixels 100a, 100c are now used for the measurement of the correction signal.

Thus, as shown by FIGS. 9A-B, all pixels in a row can be corrected in two operations, all odd pixels can be corrected in a first operation, Can be corrected in operation.

With reference now to Figs. 10A-D, the control circuit 202 for providing measurement signals and correction signals will be further described. In FIG. 10A, the configurations associated with pixels 100a-100d appear as connections that can be switched depending on the operating modes of display 200 indicated by dashed lines. In Fig. 10b-d, the connections used in the normal operating mode and the correction measuring mode are also shown.

10A, the control circuitry 202 associated with one pixel includes a sampling latch 222, a holding latch 224, and a plurality of pixels 100 of the display 200, To-analog converter (" digital-to-analog converter ") that can be used to convert a digital signal that provides data for light output to a corresponding analog signal that can be supplied to a first data line 110 of pixel 100 DAC), 226).

The control circuitry 202 associated with one pixel may further comprise configurations for analog-to-digital conversion of the measured correction signal. The DAC 226 may be reused to implement a successive approximation analog-to-digital converter. Thus, the control circuit 202 includes a comparator 228 that is capable of receiving a portion of the measured analog signal and a signal from the DAC 226. The output from the comparator 228 may be provided to a holding latch 224 that may function as a successive approximation register and may be an approximate digital code of an analog signal received at the DAC 226 ). ≪ / RTI >

The control circuit 202 includes a bandpass filter 230 for filtering out the second or third harmonics from the measured correction signal, a filter for filtering out the second or third harmonics based on the filtered signal and an oscillator frequency A mixer 232 that mixes a reference signal provided by a PLL 234 generating a second harmonic frequency or a PLL 236 generating a third harmonic frequency based on the oscillator frequency, . Thus, the mixer 232 can accurately extract the second or third harmonics, which is further coupled to a lowpass filter 238 to isolate the second or third harmonics from the mixer 232 Can be passed. The low pass filter 238 may also perform a sample and hold of an analog signal to provide a constant signal to the comparator 228 that may be converted to a digital form.

Thus, the control circuitry 202 associated with one pixel can be arranged to extract the second harmonic or the third harmonic of the measured correction signal and output the extracted signal through the sampling latch 222. [

In Fig. 10B, it is shown driving the display in normal operating mode. Data from the DACs 226 of the control circuit 202 is applied to the data lines of each pixel 100 to output light by the pixels.

It is shown in Fig. 10c to drive the display 200 in the correction measurement mode for correction of odd pixels of a row. Thus, the first measurement signal 214 is provided on the first data line 110 of the first pixel and the second measurement signal is provided on the first data line 110 of the third pixel.

The correction signal on the second data line 114 of the first pixel passes through an amplifier 220b and is then coupled to a control circuit 202 associated with both the first pixel and the second pixel.

The control circuitry 202 associated with the first pixel receives the correction signal and passes the correction signal through the bandpass filter 230a to extract the third harmonic. The mixer 232a associated with the first pixel then receives the signal from the band pass filter 230a and a signal from the PLL 236 that generates a third harmonic frequency based on the oscillator frequency. Thus, the control circuitry 202 associated with the first pixel can extract the third harmonic from the measured correction signal.

The control circuitry 202 associated with the second pixel also receives the correction signal on the second data line 114 and passes the correction signal through the bandpass filter 230b to extract the second harmonic. The mixer 232b associated with the second pixel then receives the signal from the band-pass filter 230b and the signal from the PLL 234 that generates a second harmonic frequency based on the oscillator frequency. Thus, the control circuitry 202 associated with the second pixel can extract the second harmonic signal from the measured correction signal.

The extracted second and third harmonics are then passed to an analyzing circuitry for calculating the ratio between the amplitude of the third harmonic and the amplitude of the second harmonic to determine the threshold voltage, as discussed above .

In Fig. 10d, it is shown driving a display in a correction measurement mode for correcting even pixels in a row. Here, the second and third harmonics are extracted and analyzed in the same way as for odd lines discussed above. The first measurement signal 214 is now provided on the first data line 110 of the second pixel and the second measurement signal 216 is provided on the first data line 11 of the fourth pixel. The correction signals are received on the second data lines 114 of even pixels.

Referring now to Figures 11A-C, yet another embodiment for providing a measurement signal and measuring the correction signals will be further described.

In this embodiment, capacitive coupling from the driver gate 104 to the correction gate 106 is used equivalent to capacitive coupling from the correction gate 106 to the driver gate 104. The measurement signal may be provided to the correction gate 110 by the first data line 110 to the driver gate 104 or by the second data line 114. The correction signal can then be measured on the other data lines. Therefore, the same data line can always be used to receive the correction signal.

The correction signal is repeated every 4 pixels. In Figure 11A, four pixels 100a-d of a row are shown and the correction measurements of the first and fourth pixels 100a, 100d are shown.

Here, the first measurement signal is provided on the first data line 218a, which is coupled to the first data line 110 of the first pixel 100a and the drive transistor 102 of the first pixel 100a As a measurement signal on the driver gate 104 of the driver IC. A second measurement signal is also provided on the second data line 218b which is coupled to the second data line 114 of the fourth pixel 100d and the driver transistor 102 of the fourth pixel 100d As a measurement signal. Thus, the first and fourth pixels of this row can be driven simultaneously in the correction measurement mode.

The first data line 110 of the second pixel 100b in the row may also function as the second data line 114 of the first pixel 100a. Accordingly, this data line 114 is used to measure the correction signal based on the measurement signal provided to the first pixel 100a by the first data line 110. [ Thus, the data line 114 may be coupled to the amplifier 220 to allow measurement of the correction signal for the first pixel 100a. Also, the first data line 110 of the fourth pixel 100d may be coupled to the amplifier 220 to make a measurement of the correction signal for the fourth pixel 100d, and the correction signal may be coupled to the fourth pixel < RTI ID = 0.0 & 100d on the driver gate 104 of the drive transistor 102. The first data line 110 of the third pixel 100c functioning as the second data line 114 of the second pixel 100b is also connected to the drive transistor (not shown) for the second and third pixels 100b, 102 are conductive and thus can be driven with a DC signal high enough to shield the capacitive coupling between the driver gate 104 and the correction gate 106 of the driver transistors 102 of these pixels. Thus, the capacitive coupling between the gates of these pixels does not affect the correction measurements of the first and fourth pixels 100a, 100d.

The first and second measurement signals 216 and 216 may be used and the second measurement signal 216 is associated with the first measurement signal 214 and is 180 degrees phase shifted. This can reduce the overall external radiation and reflections at the end of the datalines.

In Fig. 11B, the correction measurements of the second and third pixels 100b, 100c are shown.

Here, the measurement signal is provided on the first data line 218a, which is coupled to the first data line 110 of the third pixel 100c and also to the second data line 100b of the second pixel 100b 114). The measurement signal is thus provided as a measurement signal on the driver gate 104 of the drive transistor 102 of the third pixel 100c and also on the correction gate 106 of the drive transistor 102 of the second pixel 100b And is provided as a measurement signal. Thus, the second and third pixels of this row can be driven simultaneously in the correction measurement mode using the same measurement signal.

The first data line 110 of the second pixel 100b of the row is similar to the measurement of the correction signal of the first pixel 100a and is again used to measure the correction signal, ) Can be measured. Also, the first data line of the fourth pixel 100d, which functions as the second data line 114 of the third pixel 100c, can be used for the measurement of the correction signal for the third pixel 100c. The first data line 110 of the first pixel 100a and the second data line 114 of the fourth pixel 100d can be driven with a sufficiently high DC signal so that the first and fourth pixels 100a and 100d The channel of the drive transistor 102 to the driver transistor 102 is conductive and thus shields the capacitive coupling between the driver gate 104 and the correction gate 106 of the drive transistor 102 of these pixels. Thus, the capacitive coupling between the gates in these pixels does not affect the correction measurements of the second and third pixels 100b, 100c.

In the correction measurements of the second and third pixels 100b, 100c, the same measurement signal can be used to perform the correction measurement of the two signals. The first and second measurement signals 180 占 out of phase with respect to each other can still be provided and actively applied to all the other data lines in the row receiving the measurement signal (i.e., Every eighth data line).

Thus, as shown in Figs. 11A-B, all the pixels of a row can be corrected in two operations, two of all four pixels can be corrected in the first operation and all the remaining four pixels Two of which can be corrected in the second operation. Since the same data lines are used to measure the correction signal, the control circuit 302 can be arranged differently.

In FIG. 11C, the components associated with pixels 100a-d appear as connections that can be switched depending on the operating modes of display 200 indicated by dashed lines. The control circuit 302 is not described in detail because it can function in a manner similar to the control circuit 202 described above with respect to Figures 10A-D. Also, as shown in Fig. 11C, it is not necessary to have an amplifier 220 associated with every data line, since the same data lines are always used to measure correction signals.

As indicated above, it is possible to measure the threshold voltage for the drive transistor 102 of each pixel 100 in the display 200. The threshold voltage can be measured in association with the black display (no image is shown on the display) and the image displayed on the display. The difference in threshold voltages from these two assurance measures can then be used to estimate the voltage drop of the ground plane of the display 200.

The first calibration measurement may thus be performed during the start-up of the active matrix display 200 before the first image is provided on the display. The first calibration measurement thus makes it possible to measure the difference between the gate-source voltage VGS on the driver gate 104 and the threshold voltage of the driver transistor 102 when no pixels 100 are active And therefore can not cause any voltage drop on the ground plane. A second correction measurement associated with the image displayed on the display 200 can then be performed shortly after the start-up of the display, so that it can be assumed that no other shifts occur in the threshold voltage. The second calibration measurement may be made to determine the same difference between the voltage V _GS on the driver gate 104 of the drive transistor 102 and the threshold voltage when the pixels 100 of the display are activated. The difference between the first and second calibration measurements may then provide a difference in the source voltage V _s of the drive transistor 102 in the first and second calibration measurements and may be at a ground resistive drop Can be attributed.

As shown in FIG. 12, correction measurements for estimating the voltage drop of the ground plane may be performed for several selected rows 304 of the display 200. Thus, correction measurements do not have to be performed for all the rows, which consumes too much time and, therefore, can affect the visual experience of the images displayed on the display. Measurements performed on some selected rows 304 determine the profile of the source voltage V _s for these rows 304 (and consequently determine the ground resistance drop for these rows 304) Can be used to estimate the profile of the ground plane for the rows.

For example, these rows 304 may be recalibrated in the frame displayed on the display 200. [ This may be repeated several times to perform calibration measurements for several rows. The profile of the ground plane determined for the selected rows 304 may also be used to estimate the profile of the ground plane intersecting the entire display 200 (between selected rows 304).

In the normal mode of operation of the display, each estimated resistance drop value V _s at the pixel is provided on the first data line 11 of the pixel 100 to compensate for the ground resistance drop when driving the pixel 100 May be added to the data value.

In the case of a normal OLED stack as shown in FIG. 1B, the ground is typically a vaporized counter electrode of OLEDs. The opposite electrode is not usually patterned, which causes current to flow in all directions of the opposite electrode. Thus, the slope of the voltage drop profile of the ground plane can be averaged across the ground plane. This means that measuring the ground profile on a number of selected reference lines enables a good assessment of the ground resistance drop across the entire display 200.

In the case of an inverted OLED stack as shown in FIG. 1A, the ground connections are typically implemented as metal wirings in the TFTs of the display 200. The wirings are independent and thus can make it difficult to perform an evaluation of the ground resistance drop profile across the entire display 200 once correction of the ground plane associated with some of the ground wiring lines is made.

Thus, the data lines 110, 114 of the display, which can extend along the columns of the array, can preferably be arranged in parallel to the ground lines, The correction of the selected rows provides some reference points for the voltage drop for each column (where the ground lines extend). Thus, a good evaluation of the total voltage drop of the column is possible.

If the ground wiring lines extend along both the rows of the display 200 and the columns of the display 200, it may be much easier to evaluate the ground resistance drop across the entire display 200.

In the case of an inverted OLED stack, the ground resistance profile is alternatively the actual expected current of all pixels given by the data provided on the first data line 110 of each pixel, Lt; / RTI > If only ground wirings along the direction perpendicular to the data lines are present, a grounding resistance drop can be determined. Voltage drop ΔV _n (and hence the ground profile according to) over the ground line can be calculated in pixel resistance R _m and the pixel current I _k dual overlapping sum (double-nested sum) over the pixels k, m as a function of, and which (10).

Referring now to FIG. 13, the method of compensating the threshold voltage in the active matrix display will be briefly summarized.

The method includes driving a display (step 402) in a correction measurement mode for measuring a threshold voltage of at least one pixel to enable correction of at least one pixel (100). In the calibration mode, the measurement signal is actively applied to one of the first and second data lines 110 and 114 and the correction signal is applied to the other of the first and second data lines 110 and 114 of the pixel 100 It is measured on one side.

The method further includes determining correction data for at least one pixel based on the measured correction signal (step 404). Thus, the correction data can be determined from the correction data that can be used to compensate for the threshold voltage variation of the pixel 100.

The method further includes driving the display in the correction refresh mode to correct at least one pixel (step 406). In the correction refresh mode, the correction data may be provided to the correction gate 106 of the drive transistor 102 on the second data line 114. By driving the display in the calibration refresh mode, the pixels 100 can be kept in a calibrated state.

The display may thus be driven in a normal operating mode and data may be provided on first data lines 110 for driving the output of light from each pixel, Lt; / RTI >

In the foregoing, the inventive concept has been described primarily with reference to a limited number of examples. However, as will be readily appreciated by one of ordinary skill in the art, other examples than those described above are equally possible within the scope of the inventive concept as defined by the appended claims.

Although correction measurements are performed primarily by driving an active measurement signal on the driver gate 104 and measuring the correction signal on the correction gate 106, The capacitive coupling to the driver gate 104 must be the same as the capacitive coupling from the driver gate 104 to the correction gate 106 so that the correction leads can alternatively be formed on the correction gate 106, And measuring the correction signal on the driver gate 104.

Claims (15)

A threshold voltage compensation method in an active matrix display (200) comprising a plurality of pixels (100) arranged in an array comprising a plurality of rows and a plurality of columns, the method comprising the steps of: A selection transistor 108 for selectively connecting the first data line 110 to the driver gate 104 of the drive transistor 102; And a correction transistor (112) for selectively connecting a second data line (114) to the correction gate (106).
- driving (402) the display (200) in a correction measurement mode to measure a threshold voltage of at least one pixel (100) to enable correction of the at least one pixel (100) , The gate of the select transistor (108) of the at least one pixel (100) is open to the driver gate (104) of the drive transistor (102) for connection to the first data line The gate of the correction transistor 112 of at least one pixel 100 is opened to connect the second data line 114 to the correction gate 106 of the drive transistor 102, (110, 114), and a correction signal is applied to one of the first and second data lines (110, 114), wherein the correction signal is applied to one of the first and second data lines
Determining (404) correction data for the at least one pixel (100) based on the measured correction signal; And
- driving (406) the display (200) in a correction refresh mode to correct at least one pixel (100), - in the correction refresh mode, the selection transistor (108) of the at least one pixel (100) Wherein the gate of the correction transistor (112) of the at least one pixel (100) is closed to disconnect the first data line (110) from the driver gate (104) of the drive transistor Is opened to connect the second data line (114) to the correction gate (106) of the drive transistor (102), and the determined correction data is applied to the first electrode of the drive transistor (102) The -, < RTI ID = 0.0 >
≪ / RTI >
The method according to claim 1,
The measurement signal is a periodically varying signal having a first frequency
Way.
3. The method of claim 2,
The measurement signal varies in relation to a constant signal and the constant signal is selected based on a highest possible or lowest possible threshold voltage
Way.
3. The method of claim 2,
Wherein at least a second or third harmonic associated with the first frequency is measured for the correction signal
Way.
3. The method of claim 2,
The threshold voltage is measured simultaneously for a subset of pixels 100b, 100d in a row,
The first and second measurement signals 214 and 216 are provided and the second measurement signal 216 is 180 ° phase shifted with respect to the first measurement signal 214 so that the first data line 110 ) In the subset of pixels (100b, 100d) receiving the first measurement signal (214) on the second measurement signal (216) has adjacent pixels in the subset of pixels
Way.
The method according to claim 1,
And providing the stored correction data on the second data line (114) to the correction gate (106) of the drive transistor (102) in the correction refresh mode
≪ / RTI >
The method according to claim 1,
The display (200) is adapted to be driven between a first and second consecutive cases for driving the display (200) in the correction measurement mode,
Way.
The method according to claim 1,
At least one pixel 100 in a single row is driven in the correction measurement mode and for all other rows the gate of the select transistors 108 and the correction transistors 112 are on the display 200 Closed to maintain the image of the previous frame
Way.
The method according to claim 1,
Performing the correction measurement mode on a row of at least one pixel (100) associated with both a black display and an image displayed on the display (200), thereby obtaining a correction signal associated with the black display Acquiring a correction signal associated with a display that displays an image based on a difference between the measured correction signal associated with the black display and the measured correction signal associated with the display displaying an image, Lt; RTI ID = 0.0 >
≪ / RTI >
10. The method of claim 9,
The data on the first data line 110 is compensated for by the estimated voltage drop when the display 200 is driven to display an image in normal mode
Way.
In the active matrix display 200,
A plurality of pixels (100) arranged in an array comprising a plurality of rows and a plurality of columns, the pixels (100) comprising a driver transistor (102) having a driver gate (104) and a correction gate (106) (108) for selectively connecting a first data line (110) to the driver gate (104) of the driver transistor (102), a second data line And a correction transistor (112) for selectively coupling the transistor
Each of the data lines (110; 114) including a first data line (110; 114) arranged along a direction of the rows or the columns of the array, Is coupled to the select transistors (108) of the pixels (100) along a row or column such that the data lines (110; 114) are coupled to the pixels (100) on one side of the data lines Select transistors 108 and to the correction transistors 112 of the pixels 100 on the opposite side of the data lines 110; And
A control circuit 202 connected to the data lines 110 and 114 to control the display of the image on the data lines 110 and 114 in order to display an image in a normal mode of the display 200; And the control circuit 202 is configured to provide correction data to the correction gate 106 of the drive transistor 102 of the pixel 100 in the correction refresh mode of the display 200 Wherein the control circuitry is further configured to provide correction data on the data lines and wherein the control circuitry controls the first and second data lines in the correction measurement mode of the display, ) And further configured to measure a correction signal for the other of the first and second data lines (110, 114)
(200).
12. The method of claim 11,
The control circuit (202) is arranged to provide the measurement signal with a periodically varying signal having a first frequency
display.
13. The method of claim 12,
The control signal (202) is arranged to measure at least a second or third harmonic for the correction signal in relation to the first frequency
display.
14. The method of claim 13,
An oscillator 210 used to provide a frequency of the measurement signal and used to provide a reference frequency for extracting the at least second or third harmonic,
≪ / RTI >
12. The method of claim 11,
The control circuit 202 is arranged to provide an analog signal to each of the data lines 110 and 114 when driving the display 200 in a normal mode and to drive the display 200 in a corrected measurement mode To-analog converter 226 arranged in the configuration of a successive approximate analog-to-digital converter,
≪ / RTI >

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