JP2018141955A - Active matrix display and method for compensating for threshold voltage in active matrix display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for compensating for a threshold voltage in an active matrix display (200).SOLUTION: A display (200) includes a plurality of pixels (100), and each of the pixels includes a drive transistor (102) having a driver gate (104) and a calibration gate (106), a first data line (110) selectively connected to the driver gate (104), and a second data line (114) selectively connected to the calibration gate (106). The present method includes a step (402) of driving the display (200) in a calibration and measurement mode for measuring a threshold voltage of the pixels (100); the first data line is connected to the driver gate, and the second data line is connected to the calibration gate. A measurement signal is actively driven in one of the first and second data lines (110, 114), and a calibration signal is measured in the other of the first and second data lines (110, 114).SELECTED DRAWING: Figure 13

Description

  The inventive concept relates to an active matrix display and a method for threshold voltage compensation in an active matrix display.

  An active matrix display includes a plurality of pixels arranged in an array, and each pixel has a light emitting element. The light emitted by the light emitting elements of the pixels forms an image presented by the display. The light emitting device is, for example, an organic light emitting diode (OLED), and thus the display may be an active matrix OLED (AMOLED) display.

  An active matrix display, such as an AMOLED display, can use a driven back surface and can be, for example, in the form of one or more thin film transistor (TFT) arrays. The back surface can be manufactured by low temperature manufacturing, which allows the use of a suitable substrate and can form, for example, a flexible display. Therefore, active matrix displays such as AMOLED displays are frequently used in various applications and are promising technologies for future applications.

  The drive transistor may be used to drive the current flowing through the OLED to emit light from the pixel. The current through the OLED can depend on the characteristics of the drive transistor. These characteristics, particularly the threshold voltage of the driving transistor, change with the passage of time and may vary from pixel to pixel. Therefore, in order to avoid uneven output from the display, calibration may be necessary to correct variations and degradation.

A dual gate drive transistor can be used to compensate for threshold voltage variations. In current AMOLED displays, it is common to measure the current through the OLED, the variation being the result of variations in the threshold voltage of the drive transistor, providing compensation in the current programmed circuit. For example, Patent Document 1 discloses a pixel current driver including a plurality of TFTs having a dual gate and driving an OLED layer. The plurality of TFTs may be five TFTs formed in a manner compensated by ΔV _T programmed with current. Such current programmed compensation results in a complex circuit and thus reduces the maximum resolution of the AMOLED display.

  In another approach, for example, as discussed in Non-Patent Document 1, an operation-type dual gate drive transistor that compensates for variations in threshold voltage is used. This pixel is driven independently with respect to the threshold voltage so as to eliminate deterioration due to variations in threshold voltage. However, this approach requires a way to compensate instead before providing data to drive the pixels.

International Publication No. 2002/067327 Pamphlet

C. Jeon et al, "AMOLED Pixel Circuit using Dual Gate a-IGZO TFTs for Simple Scheme and High Speed VTH Extraction", Society for Information Display Digest, Vol. 47, Issue 1, pages 65-68 (2016) Bhoolokam et al, "Analysis of frequency dispersion in amorphous In-Ga-Zn-O thin-film transistors", Journal of Information Display, Vol. 16, No. 1, pages 31-36 (2015)

  The purpose of the inventive concept is to provide an improved method for threshold voltage compensation. A particular object of the inventive concept is to provide threshold voltage compensation using a simple pixel circuit (a calibration method that only needs to be applied intermittently).

  These and other objects of the inventive concept are at least partially met by the present invention as defined in the independent claims. Preferred embodiments are set forth in the dependent claims.

According to a first aspect, there is provided a threshold voltage compensation method in an active matrix display, the display comprising a plurality of pixels arranged in an array including a plurality of rows and a plurality of columns, wherein the pixels ,
A drive transistor having a driver gate and a calibration gate;
A select transistor for selectively connecting the first data line to the driver gate of the drive transistor;
A calibration transistor for selectively connecting the second data line to the calibration gate of the drive transistor;
The method
Driving the display in a calibration measurement mode to measure a threshold voltage of at least one pixel to allow calibration of the at least one pixel;
In the calibration measurement mode, the gate of the selection transistor of at least one pixel is opened to connect the first data line to the driver gate of the driving transistor;
A gate of the calibration transistor of the at least one pixel is open to connect the second data line to a calibration gate of the drive transistor;
A measurement signal is actively driven on one of the first and second data lines, and a calibration signal is measured on the other of the first and second data lines;
The method
Determining calibration data for at least one pixel based on the measured calibration signal;
Driving the display in a calibration refresh mode to calibrate at least one pixel;
In the calibration refresh mode, the gate of the selection transistor of at least one pixel is closed, and the first data line is disconnected from the driver gate of the driving transistor;
A gate of the calibration transistor of the at least one pixel is open to connect the second data line to a calibration gate of the drive transistor;
The determined calibration data is supplied on the second data line to the calibration gate of the driving transistor.

  According to the invention, the display may be driven in a calibration measurement mode for measuring the threshold voltage of the drive transistor of at least one pixel. Measurements can supply the determined calibration signal to the calibration gate of the drive transistor to compensate the measured threshold voltage within the pixel and to compensate for pixel-to-pixel variation and / or non-uniformity To. Thereby, in order to induce a desired output from the light emitting element driven by the driving transistor, the driving transistor can be operated by a simple driving signal.

  Calibration may be performed for all pixels in the display, where calibration measurements for all pixels may be performed in a single session, eg, one frame in calibration measurement mode, Or includes at least one of a plurality of sessions in a calibration measurement mode, where calibration measurements are performed on different pixels in different sessions. Thus, once the active matrix display is calibrated and the threshold voltage is compensated, drive data can be supplied to each drive transistor of the pixel without having to consider the threshold voltage variation between the pixels. .

  Calibration data supplied to the calibration gate of the drive transistor may be held in the calibration gate for a significant amount of time so that the display only needs to operate occasionally in the calibration refresh mode.

  In addition, the calibration measurement mode may be used to measure threshold voltage drift, and therefore applies at regular intervals to allow threshold voltage changes to be identified. And allows the active matrix display to always compensate for changes to the threshold voltage of the drive transistor.

  The invention also makes it possible to use a simple pixel structure with a small number of elements. This means that the active matrix display can be arranged with high resolution.

  An active matrix display is configured as any display that includes an active matrix for driving the light output from the light emitting elements associated with the respective drive transistors of the pixels of the display. The light emitting element may be, for example, an OLED and the active matrix display is an AMOLED display.

  The plurality of pixels are arranged in an array including a plurality of rows and columns. This means that the pixels are logically organized in rows and columns, and may be addressed in common by a plurality of lines for controlling the pixels. The term “row” or “column” need not refer to the actual physical orientation of the display. As will be appreciated by those skilled in the art, rows and columns can be easily interchanged, and in this disclosure these terms are intended to be interchangeable.

  The measurement signal may be actively driven on the first data line and the calibration signal may be measured on the second data line. However, alternatively, the measurement signal may be actively driven to the second data line and the calibration signal may be measured on the first data line.

  The display may be configured such that a measurement signal is provided on the first data line for all pixels. However, instead, the display can be configured such that the measurement signal is actively driven to the first data line and the calibration signal is measured for some pixels on the second data line, while the other For the pixel, the measurement signal is actively driven to the second data line and the calibration signal is measured on the first data line. If a data line is shared between adjacent pixels, this can allow the same data line to be used to receive calibration signals for adjacent pixels sharing the data line (one The pixel provides a calibration signal on its first data line and the other pixel provides a calibration signal on its second data line).

  According to one embodiment, the first storage capacitor may be connected between the driver gate of the driving transistor and the source or drain of the driving transistor. This means that the data supplied to the driver gate may be held by a storage capacitor, for example, drive data is supplied to other pixels to hold the output by the pixels in the display. Means. Such a first storage capacitor can ensure a well-controlled drive of the pixel, but a parasitic capacitance between the driver gate and the source or drain of the drive transistor can be used instead. .

  According to another embodiment, a second storage capacitor can be connected between the calibration gate of the drive transistor and the source or drain of the drive transistor. This means that the data provided to the calibration gate is retained by the storage capacitor, e.g., the calibration data is retained on the calibration gate for a substantial period of time without requiring a calibration refresh operation. Means. In such a second storage capacitor, the calibration data is held for a considerable time at the calibration gate, and instead a parasitic capacitance between the calibration gate and the source or drain of the driving transistor may be used. The display may also be operated more frequently in calibration refresh mode.

  According to one embodiment, the driver gate is the front gate of the drive transistor and the calibration gate is the back gate of the drive transistor. However, the driver gate may alternatively be the back gate of the drive transistor, and the calibration gate may be the front gate of the drive transistor. Also, the front gate and back gate of a transistor are relative terms that can be used interchangeably depending on how the transistor looks. Thus, the terms “driver gate” and “calibration gate” as used herein are to be interpreted as different gates of a transistor, where each of the driver gate and the calibration gate is a front gate or a back gate of the transistor. Any of these may be pointed to.

  When the driver gate voltage of the drive transistor falls below the threshold voltage, the channel of the drive transistor is not conducting and the driver gate and calibration gate function as two plates of capacitors. Thus, there is a capacitive coupling between the driver gate and the calibration gate. When the driver gate voltage of the drive transistor exceeds the threshold voltage, the channel of the drive transistor becomes conductive and the charge in the channel blocks capacitive coupling between the driver gate and the calibration gate. Thus, it is understood that the threshold voltage may be determined by identifying the change in capacitance between the driver gate and the calibration gate.

  According to one embodiment, the measurement signal is a periodically changing signal having a first frequency. It is an understanding of the present invention that a periodically changing signal is particularly useful and can facilitate the determination of the threshold voltage in a reliable manner. The periodically changing signal may allow information regarding the threshold voltage to be extracted from other parameters that affect the measured calibration signal.

According to one embodiment, the measurement signal varies in relation to a constant signal, which is selected based on the highest or lowest possible threshold voltage possible. The determination of the threshold voltage may not be able to distinguish threshold voltages above or below the DC voltage level provided by the constant signal (since the threshold voltage is determined as an offset to the constant signal) . By selecting a constant signal above the highest possible threshold voltage, it can be concluded that the threshold voltage can be determined by subtracting the offset determined for the constant signal. Similarly, by selecting a constant signal below the lowest possible threshold voltage as much as possible, it can be concluded that the threshold voltage can be determined by adding a determined offset to the constant signal. This allows the threshold voltage to be determined directly based on a single measurement signal and provides different measurement signals (eg, based on different DC voltage levels) to determine the threshold voltage. It means no need.

According to one embodiment, at least a second or third harmonic for the first frequency is measured for the calibration signal. The parasitic capacitance between the first data line and the second data line may be large with respect to capacitive coupling between the driver gate and the calibration gate. This is because when the driver gate voltage changes above or below the threshold voltage, parasitic capacitance can make it difficult to identify capacitance changes between the driver gate and the calibration gate. Arise. However, the second and third harmonics of the first frequency are not affected by the parasitic capacitance between the data lines. Therefore, by measuring the second or third harmonic, it is possible to extract the threshold voltage without affecting the ability of the parasitic capacitance between the data lines to determine the threshold voltage. .

  As used herein, “second harmonic” should be interpreted as part of a measurement calibration signal having a frequency twice that of the measurement signal (ie, the first frequency). Furthermore, the “third harmonic” should be interpreted as part of a measurement calibration signal having a frequency three times that of the measurement signal.

  According to one embodiment, a threshold voltage is measured simultaneously for a subset of pixels in a row, and first and second measurement signals phase-shifted 180 degrees relative to the first measurement signal are provided, One pixel of the subset of pixels that receives the first measurement signal on a first data line includes one pixel of the subset of pixels that receives a second measurement signal. In other words, the first and second measurement signals that are 180 degrees out of phase with each other are alternately supplied to every other pixel in the subset of pixels. This reduces the parasitic capacitive coupling between the data lines of adjacent pixels so as not to affect the determination of the threshold voltage of the drive transistor, allowing simultaneous measurement of threshold voltages for multiple pixels simultaneously That means

  For all the pixels in the row, the threshold voltages of all the pixels of the first subset are determined simultaneously in the first measurement period, and the threshold voltages of all the pixels of the second subset are determined in the second measurement period. Determined at the same time. It should be understood that more than one subset can be used and thus more than one measurement period can be used to determine the threshold voltage of all pixels in a row.

  In one embodiment, the first subset of pixels may be an even number of pixels in a row. In this way, threshold voltages can be measured simultaneously for even pixels in a row. Similarly, threshold voltages can be measured simultaneously for odd pixels in a row. This means that the threshold voltage may be determined for all pixels in one row for two measurement periods, one for even pixels and one for odd pixels.

  In this specification, “even pixels in a row” should be construed as pixels arranged in columns having even numbers, where the columns are numbered sequentially from 1 to the leftmost column. Attached. Similarly, “odd pixels in a row” should be interpreted as pixels arranged in columns having odd numbers.

  According to another embodiment, the measurement signal is a voltage that increases or decreases linearly. Thus, instead of applying a periodically changing signal, the measurement signal can be switched to sweep above the threshold voltage by sweeping the voltage on the driver gate and below the threshold voltage. Alternatively, the measurement signal can be switched from sweeping the voltage on the driver gate above the threshold voltage to below the threshold voltage. Thus, as the measurement signal shifts below the threshold voltage and above the threshold voltage or vice versa, the shift may be determined in the measured calibration signal.

  According to one embodiment, determining the calibration data includes identifying a linear slope shift of the calibration signal, extracting a threshold voltage based on the identified shift, and extracting the extracted threshold voltage. Determining calibration data based on. The measured calibration signal at the calibration gate can have a linear dependence on the measurement signal. The threshold voltage is measured because the measurement signal is smaller when the measurement signal exceeds the threshold voltage (the capacitive coupling between the driver gate and the calibration gate is shielded above the threshold voltage) It may be determined based on the slope of the increase in the calibration signal.

  Using a linearly increasing voltage as the measurement signal can provide a very fast way to determine the threshold voltage. However, the parasitic capacitance between the data lines can make it difficult to identify changes in the slope of the measured calibration signal, which is more than the capacitive coupling between the driver gate and the calibration gate. It can be much larger and can therefore be a major factor affecting the slope.

  According to one embodiment, the method includes storing calibration data and using the stored calibration data in a calibration refresh mode. Accordingly, the calibration data determined in the calibration measurement may be stored for reuse. This means that the calibration refresh mode can be operated separately from the calibration measurement mode, and the calibration measurement can be performed without necessarily performing the calibration measurement (to perform a calibration refresh). The calibration gate voltage may not be held stable for a very long time, for example due to leakage of the gate dielectric. Thus, by storing calibration data, a threshold voltage compensation voltage refresh at the calibration gate is performed periodically to provide the desired relationship between the emitted light in the pixel and the provided control signal. Can be held.

  According to one embodiment, the display is driven multiple times in calibration refresh mode between two subsequent opportunities to drive the display in calibration measurement mode. Calibration measurements need only be performed at intervals based on the risk that the threshold voltage of the drive transistor has changed. On the other hand, the calibration refresh mode is performed to ensure that the desired voltage is held at the calibration gate, and therefore may need to be performed more frequently.

  According to one embodiment, one row at a time is driven in a calibration refresh mode, and a calibration refresh is performed on the entire display of normal video frames. This means that the stored calibration data may be provided in a single frame to the display pixels so that the calibration refreshment does not affect the visual experience provided by the display. During the calibration refresh mode, the select transistor can be turned off to prevent the image on the display from changing during the frame in which the calibration refresh is performed.

  According to one embodiment, at least one pixel in one row is driven in the calibration measurement mode, and for all other rows, the gates of the selection transistor and the calibration transistor are closed and an image of the original frame on the display. Hold. Thus, during calibration measurements, all images except one row may be maintained on the display to have a minimal effect on the visual experience provided by the display. Calibration measurements may be performed on all pixels in the row before the display is driven to update the displayed frame. Calibration measurements may be performed in separate frames for each row of the array so that the calibration period is not noticed by the user viewing the display. Thus, one or more frame updates can be performed during calibration measurements for different rows of the array.

  According to one embodiment, calibration measurements can be performed in separate frames for pixels in the same row of the array (eg, odd and even pixels in the row are calibrated in different frames).

  The combination of pixels calibrated within the common frame may be changed in a number of ways. According to one alternative, all pixels in one or more rows can be calibrated in one frame. According to another alternative, some pixels, for example odd or even pixels, are calibrated in a common frame.

  According to one embodiment, the method determines the difference between performing a calibration measurement mode on at least one row of pixels for both the black display and the image presented on the display and the calibration measurement. Using to estimate the voltage drop across the ground plane of the display.

  Therefore, this method can be used for both the compensation of the threshold voltage fluctuation of the driving transistor of the pixel and the compensation of the voltage drop of the ground plane. Thus, this method estimates the ground profile on the display and, as a result, can compensate for any variations in the ground plane profile in driving the pixel drive transistors. According to one embodiment, the data on the first data line when the display is driven in the normal mode to display an image is compensated by the estimated voltage drop.

  Calibration measurements for the black display may be performed during activation of the active matrix display before the first image is presented on the display. Next, a calibration measurement associated with the image presented on the display may be performed immediately after the display is started, so that no other shifts in threshold voltage have occurred and the calibration measurement and The difference may be due to ground resistance drop.

  Calibration measurements to estimate ground plane voltage drop may be performed on several selected rows of the display. Therefore, in this case, the calibration measurement may take too long for a particular display configuration, which can affect the visual experience of the image presented on the display, so for every row Calibration measurement is not performed. Measurements performed on several selected rows may be used to estimate the ground plane profile between the selected rows.

  According to a second aspect, there is provided an active matrix display comprising a plurality of pixels arranged in an array comprising a plurality of rows and a plurality of columns, the pixels comprising a drive transistor having a driver gate and a calibration gate; A select transistor that selectively connects a first data line to a driver gate of the drive transistor, a calibration transistor that selectively connects a second data line to the calibration gate of the drive transistor, and a row or column of the array Data lines including first and second data lines arranged along a direction, each data line being connected to a selection transistor of a pixel along a row or column of the array, Connected to the select transistor of the pixel on one side of the data line and the calibration transistor of the pixel on the other side of the data line. The active matrix display includes a control circuit connected to the data line. The control circuit is configured to provide data on the data line to display an image in a normal mode of the display, and the control circuit is configured to calibrate the drive transistor of the pixel in a calibration refresh mode of the display. Is further configured to provide calibration data to the data line to provide calibration data. The control circuit further provides a measurement signal to one of the first and second data lines to measure the calibration signal on the other of the first and second data lines in a calibration measurement mode of the display. Composed.

  The effects and features of this second aspect are generally similar to those described above in connection with the first aspect. The embodiment described with respect to the first aspect is largely compatible with the second aspect.

  Thus, the control circuit can control the display to drive the display in normal mode, calibration refresh mode and calibration measurement mode, which are further described with respect to the method of the first aspect above.

  Each data line can be connected to both a select transistor on one side of the data line and a calibration transistor on the opposite side of the data line. This means that the data line supplies data to the driver gate of the pixel drive transistor via the selection transistor and provides calibration data or to measure the calibration signal of another pixel via the calibration transistor It means that it may be used. Signals to the gates of the select and calibration transistors can determine how the data line is used.

  According to one embodiment, the control circuit is configured to provide the measurement signal as a periodically changing signal having a first frequency.

  According to one embodiment, the control circuit is configured to measure at least a second or third harmonic of the calibration signal with respect to the first frequency.

  According to one embodiment, the display further comprises an oscillator, which is used to provide the frequency of the measurement signal and is used to provide a reference frequency for extracting at least the second or third harmonic. The This can reuse a single oscillator to provide a measurement signal and to measure a calibration signal. Thus, the reference frequency for measuring the second and third harmonics is very accurately related to the first frequency of the measurement signal.

  According to one embodiment, the control circuit comprises a digital / analog converter for each data line, the digital / analog converter being configured to provide an analog signal when driving the display in a normal mode; It is configured as a component of a successive approximation analog-to-digital converter when the display is driven in a calibration measurement mode. This can reuse the components of the control circuit and, as a result, provide a compact layout of the control circuit.

  The above objects, as well as additional objects, features and advantages of the inventive concept will be better understood with reference to the accompanying drawings and the following illustrative and non-limiting detailed description. In the drawings, similar reference numerals are used for similar elements unless otherwise specified.

1 is a schematic diagram of a pixel topology of an active matrix display. FIG. 1 is a schematic diagram of a pixel topology of an active matrix display. FIG. 1 is a schematic view of an active matrix display. It is a schematic diagram explaining the drive of the pixel in normal operation mode. It is a schematic diagram explaining the drive of the pixel in a calibration refresh mode. It is a schematic diagram explaining the drive of the pixel in a calibration measurement mode. It is the schematic of the capacitive model of a pixel when the voltage on the driver gate of a drive transistor is less than a threshold voltage. FIG. 6 is a schematic diagram of a capacitive model of a pixel when a voltage on a driver gate of a driving transistor exceeds a threshold voltage. Fig. 6 is a chart showing the first, second and third harmonics of the measured calibration signal for different frequencies of the measurement signal. Fig. 6 is a chart showing the first, second and third harmonics of the measured calibration signal for different frequencies of the measurement signal. FIG. 2 is a schematic diagram of a control circuit, each showing driving the display simultaneously in an odd pixel calibration measurement mode. FIG. 5 is a schematic diagram of a control circuit, each illustrating driving the display simultaneously in an even pixel calibration measurement mode. 2 is a schematic diagram of a control circuit according to one embodiment. FIG. FIG. 10b is a schematic diagram of the control circuit of FIG. 10a, illustrating driving the display in a normal operating mode. FIG. 10b is a schematic diagram of the control circuit of FIG. 10a showing driving the display in a calibration measurement mode for calibrating odd pixels. FIG. 10b is a schematic diagram of the control circuit of FIG. 10a showing driving the display in a calibration measurement mode that calibrates even pixels. FIG. 5 is a schematic diagram of a row of pixels, showing two of the four pixels driving the display in calibration measurement mode simultaneously. FIG. 5 is a schematic diagram of a row of pixels, showing two of the four pixels driving the display in calibration measurement mode simultaneously. 2 is a schematic diagram of a control circuit according to one embodiment. FIG. FIG. 6 is a schematic diagram of a display showing calibration measurements for ground resistance drop compensation. 3 is a flowchart of a method according to an embodiment.

  FIGS. 1 a-1 b show two different variants of the pixel topology of an active matrix display. Each pixel comprises an organic light emitting diode (OLED) that emits light when current is driven through the OLED. In FIG. 1a, an inverted OLED stack is shown. In the pixel topology of FIG. 1a, the OLED of each pixel has a common anode. FIG. 1b shows a typical OLED stack, where the OLED of each pixel has a common cathode. The topology of FIG. 1b is shown and discussed in the following embodiments, but it should be understood that the inverted OLED stack topology of FIG. 1a can be used instead.

  An active matrix OLED (AMOLED) display is provided when light emission by the pixel is provided by the OLED. Although primarily discussed herein for OLEDs, it should be understood that the active matrix display can also be applied to other types of light emitting devices arranged in an array and controlled by the active matrix. Current-driven light-emitting elements can be provided in many different ways, as will be appreciated by those skilled in the art, but an AMOLED display may be preferred, for example, in terms of pixel fast switching speed.

  The pixel 100 includes a drive transistor 102 having a driver gate 104 and a calibration gate 106. The pixel 100 includes a selection transistor 108 that selectively connects the first data line 110 to the driver gate 104. The pixel 100 further comprises a calibration transistor 112 for selectively connecting the second data line 114 to the calibration gate 106.

  A signal on the first data line 110 may be supplied to the driver gate 104 of the driving transistor 102 via the selection transistor 108. Thus, the signal on the first data line 110 opens the channel in the drive transistor 102 and thus provides data to drive the current through the OLED 116 connected to the drain or source of the drive transistor 102. Can do. The light output by the OLED 116 depends on the current level through the OLED 116 so that the control circuit controls the light output by the pixel by controlling the data provided on the first data line 110. it can.

  The signal on the second data line 114 may be supplied to the calibration gate 106 of the driving transistor 102 via the calibration transistor 112. Thus, the signal on the second data line 114 can provide data for setting the voltage at the calibration gate 106 of the drive transistor 102. This voltage at the calibration gate 106 is driven so that the data provided on the first data line 110 can ignore variations in the threshold voltage for controlling the light output by the pixel 100. The transistor 102 can be adapted to compensate for variations in the threshold voltage. The current driven through the OLED 116 depends on the voltage difference between the voltage at the driver gate 104 and the source of the driving transistor 102, and also on the voltage difference between the voltage at the calibration gate 106 and the source of the transistor 102. Dependent. Here, the voltage level at the calibration gate 106 is provided in relation to the default threshold voltage assumed by the data provided on the first data line 110.

  The pixel 100 further includes a first storage capacitor 118 that can be connected between the driver gate 104 of the driving transistor 102 and the source of the driving transistor 102. This means that the data supplied to the driver gate 104 is maintained by the storage capacitor 118, for example, to maintain the output by the pixel 100 in the display 100 while drive data is being supplied to other pixels. Means. In addition, the first storage capacitor 118 may be connected to the drain of the driving transistor 102.

  Such a first storage capacitor 118 can ensure a well-controlled drive of the pixel 100, but using parasitic capacitance between the driver gate 104 and the source or drain of the drive transistor 102, Data on the driver gate 104 can be held.

  The pixel 100 further includes a second storage capacitor 120 connected between the calibration gate 106 of the drive transistor 102 and the source of the drive transistor 102. This means, for example, that data supplied to the calibration gate 106 is retained by the storage capacitor 120 to ensure that the calibration data is retained on the calibration gate 106. The second data line 114 is connected to the calibration gate 106. The second storage capacitor 120 may be connected to the drain of the driving transistor 102.

  Such a second storage capacitor 120 can ensure that calibration data is retained at the calibration gate 106 for a substantial period of time, but alternatively, the source or drain of the calibration gate 106 and the drive transistor 102. May be used to hold the data on the calibration gate 106. Also, if the second storage capacitor 120 is not provided, the calibration data is frequently supplied to the calibration gate 106 to refresh the calibration data and calibrated to the threshold voltage of the drive transistor 102 of the pixel 100. 100 can be held.

  Therefore, the pixel 100 includes three transistors 102, 108, and 112 and two capacitors 118 and 120, and the topology of the pixel 100 can be a so-called 3T2C (three transistors, two capacitors) topology.

  In FIG. 2, an active matrix display 200 is schematically shown including an array of pixels 100 arranged in rows and columns. Display 200 includes data lines 110 and 114 that run along the direction of the columns of the array. The display 200 further includes a control circuit 202 connected to the data lines 110 and 114. The control circuit 202 can be configured to provide data on the data lines 110, 114 and also measure signals on the data lines 110, 114, as will be described in detail below.

  The control circuit 202 can be provided as a data driver integrated circuit that generates data signals on the data lines and provides components for measuring the data signals received on the data lines. The control circuit 202 may be further connected to a memory for storing the calibration data of the pixel 100 or may include an integrated memory in the data driver integrated circuit.

  Multiplexers can be used to connect multiple data lines to one output of the control circuit 202. Thus, the control circuit 202 can include a multiplexer. If a multiplexer is introduced, at least two normal chipplexers can be introduced and each connected separately to the odd and even data lines, and as further described below, the calibration measurements are the odd lines and This is because it is necessary to drive and measure even lines simultaneously.

  The display 200 can further include a selection line 204 and a calibration line 206 extending perpendicular to the data lines 110, 114 along the direction of the rows of the array. The select line 204 can provide a signal for selectively activating the select transistors 108 in the row of pixels 100. Similarly, the calibration line 206 can provide a signal for selectively activating the calibration transistors 112 in the row of pixels 100.

  The display 200 can include a pair of selection lines 204 for each row of pixels 100 to allow independent selection of even or odd columns of pixels, respectively. Similarly, the display 200 can include a pair of calibration lines 206 for each row of pixels 100. This allows the even pixel calibration measurement to be separated from the odd pixel calibration measurement so that the calibration data determined for the even pixel is retained during the odd pixel calibration measurement.

  Similar to the topology for driving the pixel OLED 116, the data lines 110, 114, the selection line 204 and the calibration line 206 may be arranged on the back of the display 200.

  The display 200 may further include a driver circuit 208 that drives the select line 204 and the calibration line 206. The driver circuit 208 can be arranged, for example, as a gate-in-panel (GIP) integrated on the back surface. According to an alternative, the driver circuit 208 may be provided as a dedicated silicon driver.

  The transistors for controlling the light output by the plurality of pixels 100 may be p-type transistors and n-type transistors. The back surface includes a thin film transistor (TFT), for example, a TEF such as a thin film transistor (a-Si: H), polycrystalline silicon, organic semiconductor, (amorphous) indium-gallium zinc oxide (IGZO, IGZO) TFT. The present invention is an active matrix display and is not limited by a particular type of display. For example, it can be applied to AMOLED displays, including RGB or RGBW AMOLED displays, fluorescent or phosphorescent OLEDs, polymers or polydendrimers, high power efficiency phosphorescent polydendrimers, and the like.

  Three different modes of operating the pixel 100 will now be described with reference to FIGS.

  The first mode is the normal mode of operation shown in FIG. 3, which can operate according to the state-of-the-art AMOLED display drive. In this mode, data is supplied to the first data line 110 of the pixel 100 and the light output by the pixel 100 is controlled. In the normal operating mode, the calibration signal on the calibration line 206 is low and the previously performed calibration of the pixel 100 is not changed. Thus, the calibration value stored in the second storage capacitor 120 remains the same. Further, the selection signal on the selection line 204 is at a high level so that the driving data provided on the first data line 110 is applied to the driver gate 104 of the driving transistor 102. The drive data is stored in the first storage capacitor 118, and the drive data on the driver gate 104 is held. The drive data controls the desired current that is driven through the OLED 116.

  The selection signal can be driven row by row at the rate of the horizontal sync signal (HSYNC), and the horizontal sync signal (HSYNC) is used to connect the data line so that correct drive data is applied to the driver gate 104 of each pixel 100. The data provided on 110 can be synchronized.

  If the display 200 includes a pair of select lines 204 for each row of pixels 100, both of the select lines 204 in the pair are turned on to simultaneously supply a high select signal to the select transistors 108 of all the pixels 100 in the row. Can be driven together.

  The second mode is a calibration refresh mode shown in FIG. In this mode, data is provided on the second data line 114 of the pixel 100 to provide calibration data to the pixel 100. In the calibration refresh mode, the selection signal on the selection line 204 is low and the light output by the pixel 100 does not change. Accordingly, the drive data value stored in the first storage capacitor 118 remains the same. This means that the image presented by the display 200 is retained during a one frame calibration refresh. Further, the calibration signal on the calibration line 206 is high and the calibration data provided on the second data line 114 can be applied to the calibration gate 106 of the drive transistor 102. The calibration data is also stored in the second storage capacitor 120 so that the calibration data on the calibration gate 106 can be retained. The calibration data provides compensation related to the threshold voltage of the drive transistor 102. The drive data provided in the normal operating mode controls the desired current that is driven through the OLED 116.

  A plurality of calibration signals may be driven row by row at a rate of HSYNC, which is the data provided on the data line 114 such that the correct calibration data is applied to the calibration gate 106 of each pixel 100. Synchronize.

  Each data line 110, 114 can be shared by adjacent pixels 100 such that the data line forms a first data line 110 for one pixel and a second data line 114 for the adjacent pixel. . This means that when the display 200 is driven in the calibration refresh mode, the data line that provides the calibration data for the pixels in column n is the drive data for the pixels in column n + 1 when the display 200 is driven in the normal operation mode. It can be used to provide. Accordingly, the control circuit 202 can be configured to provide calibration data having a single column offset for drive data for presenting an image on the display 200.

  Also, when the display 200 includes a pair of calibration lines 206 for each row of pixels 100, the calibration in that pair is used to simultaneously provide a high level selection signal to the calibration transistors 112 of all the pixels 100 in the column. Lines 206 are driven together.

  Since the calibration refresh mode operates to refresh the calibration data of all the pixels 100 of the display 200 to one frame, it is possible to execute the calibration refresh mode without affecting the visual experience for the user watching the display 200. it can.

  The calibration refresh mode should be performed frequently enough so that the calibration data provided on the calibration gate 106 of the drive transistor 102 is retained. For example, before the calibration data on the calibration gate 106 is significantly changed, the charge stored in the second storage capacitor 120 changes due to leakage and a calibration refresh mode needs to be performed.

  The interval between calibration refresh modes depends on the leakage of the gate dielectric and the magnitude of the transistor current when turned off. Such a parameter measurement can be performed once and can be used, for example, as a step in the manufacture of a display. The frequency of performing the calibration refresh mode can then be adapted to these parameters of the display, setting a default interval for performing the calibration refresh mode.

  The calibration refresh mode needs to be performed, for example, one frame per minute of use of the display, every ten minutes, or per hour. Therefore, the calibration refresh mode is not performed very often. Thus, not only is the user affected by a single frame performing a calibration refreshment, but the frame assigned to the calibration refresh mode is displayed even if the single frame in the calibration refresh mode is noticed by the user. The overall experience of the images presented above will be minimally affected.

  The third mode is a calibration measurement mode shown in FIG. In this mode, both the selection signal on the selection line 204 and the calibration signal on the calibration line 206 are high for the pixel 100. The measurement signal is actively driven on the first data line 110 and the calibration signal induced by the measurement signal is measured on the second data line 114. The measurement signal is provided in relation to the threshold voltage of the drive transistor 102 so that the measured calibration signal can be analyzed to extract the threshold voltage of the drive transistor 102. Different embodiments of the measurement signal and the associated determination of the threshold voltage of the drive transistor 102 are further described below.

  The threshold voltage for one pixel 100 can be determined using the first data line 110 and the second data line 114. Since the data lines 110, 114 can be shared by adjacent pixels 100 that implement the first data line 110 for one pixel and the second data line 114 for the second pixel, the calibration measurement is You may perform separately with respect to an adjacent pixel. Thus, one row calibration measurement mode can include several operations to measure the threshold voltage of the drive transistors 102 of different pixels 100 in the row. However, it is possible to measure the threshold voltages of several pixels simultaneously, not for all the pixels in one row, as further described below.

  The calibration measurement mode may be performed on one row of pixels. For all other rows, both the selection line 204 and calibration line 206 signals are low, so that the previous frame image is retained on the display 200. In order to accommodate the loss of visual experience during a single frame calibration measurement, the intensity of the row to be calibrated is increased, for example by 40%, in the frame before and after the calibration measurement.

  As will be appreciated from the above, the calibration measurement mode can provide a calibration measurement for a row of pixels 100. Thus, the calibration measurement mode may be repeated many times to perform a calibration measurement for all pixels 100 in all rows. Some normal operating mode frames can be passed between two subsequent frames where calibration measurements are performed, and the visual experience of the image presented on the display 200 is minimally affected.

  The calibration measurement mode may be used to determine the threshold voltage of the drive transistor 102 of each pixel 100, so that each pixel 100 is at a specific threshold voltage of the drive transistor 102 of the pixel 100. It is calibrated. This allows the display 200 to compensate for threshold voltage variations within the display 200. Such changes can be compensated by a calibration measurement that allows a high quality image to be presented on the display 200.

  The threshold voltage of the drive transistor 102 can be changed over time and can be changed differently for different pixels 100, for example, depending on the light output by each pixel 100, the calibration The measurement mode needs to be executed at regular intervals. The calibration refresh mode can be performed, for example, at one frame per minute, but the calibration measurement can be performed once an hour. The frequency of the calibration measurement can be set depending on the light output. If the display 200 is driven to provide a bright output, the calibration measurement may be performed more frequently.

  The drive transistor 102 of the pixel 100 may be subject to a bias stress effect, i.e. charge from the channel of the drive transistor to a local defect state at the semiconductor substrate, gate dielectric, or interface between the semiconductor and the dielectric. Is the time-dependent trapping. The trapped charge does not contribute to the current flowing through the driving transistor 102 and affects the charge balance of the driving transistor 102. Therefore, in using the driving transistor 102, there may be a time dependent shift of the threshold voltage due to bias stress.

  If the voltage at the driver gate 104 of the drive transistor 102 is lower than the threshold voltage, the channel of the drive transistor 102 is not conductive and the driver gate 104 and calibration gate 106 function as two plates of capacitors. Thus, there is capacitive coupling between driver gate 104 and calibration gate 106. When the voltage on the driver gate 104 of the drive transistor 102 exceeds the threshold voltage, the channel of the drive transistor 102 becomes conductive, so that the charge in the channel causes capacitive coupling between the driver gate 104 and the calibration gate 106. Shield.

  The measurement signal provided in the calibration measurement mode is configured to allow the threshold voltage to be determined by identifying the change in capacitance between the driver gate 104 and the calibration gate 106.

Referring now to FIG. 6a, a pixel capacitance model is shown when the voltage V _GS on the driver gate 104 is below the threshold voltage. In this model, the OLED capacity is high enough so that it can be considered a short circuit at the frequency under consideration. As shown in FIG. 6 a, there is a capacitive coupling CFBBG between the driver gate 104 and the calibration gate 106.

When the voltage V _GS on driver gate 104 exceeds the threshold voltage, driver gate 104 is shielded from calibration gate 106, as shown in FIG. 6b.

In one embodiment, the measurement signal is linear in voltage from a first voltage that is lower than the expected threshold voltage of the drive transistor 102 to a second voltage that exceeds the expected threshold voltage of the drive transistor 102. Provides a sweep. The measured calibration signal may be an increase signal, but when the measurement signal crosses the threshold voltage of the drive transistor 102, the slope of the increase of the measurement calibration signal may be changed. When the driver gate 104 is shielded from the calibration gate 106, the increase in the measured calibration signal is caused by the parasitic capacitance C _{N−N + 1} between the first data line 110 and the second data line 114.

  Similarly, the measurement signal may alternatively be a voltage from a first voltage that exceeds the expected threshold voltage of the drive transistor 102 to a second voltage that is less than the expected threshold voltage of the drive transistor 102. A linear sweep can be provided. The measured calibration signal may also be a decrease signal, but when the measurement signal crosses the threshold voltage of the driving transistor 102, the slope of the decrease of the measurement calibration signal may be changed.

  In another embodiment, the measurement signal provides a periodically changing signal having a first frequency. For the first frequency lower than the maximum frequency, the capacitive model shown in FIGS. 6a and 6b is valid. The maximum frequency is the frequency at which charge in the channel can still screen for capacitive coupling between driver gate 104 and calibration gate 106. For example, the maximum frequency is inversely proportional to the channel length of the driving transistor, and the determination of the maximum frequency is described in Non-Patent Document 2. The measured calibration signal may be analyzed to identify a portion of the calibration signal to determine the threshold voltage of the drive transistor.

  The measured calibration signal can include a first harmonic that is part of the measurement calibration signal having the same frequency as the measurement signal, ie, a first frequency. The measured calibration signal can also include a second or third harmonic (ie, having a frequency that is twice or three times the first frequency). The measurement calibration signal can further include higher order harmonics, but the higher the harmonic order, the smaller the signal. This also means that higher order harmonics can be more difficult to measure.

  Thus, higher order harmonics can be used, but second and / or third harmonics may be preferred, and the use of second and / or third harmonics is described in more detail below. explain.

The amplitude of the first harmonic H1 can be approximated as follows when the periodically varying signal varies with respect to the DC voltage V _GS lower than the threshold voltage.

（式１）

(Formula 1)

C _{Data (N + 1)} is a capacitive coupling between the second data line 114 and the ground, and A is the amplitude of the applied periodic signal.

  The amplitude of the first harmonic H1 can be approximated as follows when a periodically changing signal changes with respect to a DC voltage exceeding the threshold voltage.

（式２）

(Formula 2)

The capacitive coupling C _FGBG between the driver gate 104 and the calibration gate 106 may typically be small with respect to the parasitic capacitance C _{N−N + 1} between the data line and ground. A is the amplitude of the measurement signal. This means that it can be difficult to identify whether the DC voltage is above or below the threshold voltage. Accordingly, the threshold voltage can be determined from the first harmonic of the measured calibration signal.

  However, when a DC voltage close to the threshold voltage is supplied, the measurement signal fluctuates across the threshold voltage, and the second and third harmonics are identified in the measured calibration signal, Can be used to determine the voltage.

When the measurement signal crosses the threshold voltage, the ratio of the difference between the DC voltage level V _GS and the threshold voltage V _T with respect to the amplitude A of the measurement signal is less than 1. In other words, it is expressed by the following formula.

（式３）

(Formula 3)

And | x ₀ | <1.

  In such a situation, the first, second and third harmonic amplitudes for an ideal screening of capacitive coupling between driver gate 104 and calibration gate 106 are given by the following equations:

（式４）

(Formula 4)

（式５）

(Formula 5)

（式６）

(Formula 6)

  Thus, if the measurement signal is supplied across the threshold voltage, the second and / or third harmonic can be advantageously used to determine the threshold voltage. As apparent from the above equations 5 to 6, the amplitudes of the second and third harmonics do not depend on the parasitic capacitance between the data lines 110 and 114 and are not affected by this parasitic capacitance.

Relationship between the amplitude and the ratio x ₀ of the second or third harmonic can be used to determine the threshold voltage. 7 (a fractional part of _{ΔC FGBG / C Data (N +} 1) * A) as a function of _{x 0} indicating the first, the amplitude of the second and third harmonics. Here, the influence of the parasitic capacitance is not included in the first harmonic diagram. By analyzing the measured calibration signal for a given DC voltage V _GS and amplitude A of the measurement signal, x ₀ can be determined so that the threshold voltage of the drive transistor 102 can be extracted.

Analysis of the measured calibration signal may be performed in a number of different ways. For example, the applied measurement signal may be repeatedly changed in order to change the x _0. Next, the maximum value of the second harmonic amplitude and / or the minimum value of the third harmonic corresponding to x ₀ = 0 can be identified. Accordingly, the threshold voltage may be determined to be equal to the DC voltage V _GS used in the iteration of x ₀ = 0.

  Thus, according to one embodiment, a periodically changing signal repetition associated with a constant signal is provided as a measurement signal, and the constant signal is changed during the repetition.

  According to an alternative, an iterative procedure is not necessary. Therefore, the measurement signal may be supplied as a signal that changes periodically with respect to the constant signal, and the threshold voltage may be determined directly. In this approach, the ratio of the third harmonic amplitude to the second harmonic amplitude is used. As is apparent from the equation, this ratio is given by the following equation, as shown in FIGS.

（式７）

(Formula 7)

  Thus, by determining the amplitudes of the second and third harmonics, the threshold voltage may be calculated directly as:

（式８）

(Formula 8)

  This can compensate for threshold voltage variations by changing the voltage on the calibration gate relative to the voltage used during the calibration measurement. Thus, the change to voltage at the calibration gate is given by:

（式９）

(Formula 9)

The voltage used at the calibration gate given by the voltage used during the calibration measurement, and the change ΔV _BG determined in (Eqn. 9), is the data of FIG. 9 for the control circuit 202 to store the calibration data. It may be stored in a memory. Instead, it should be understood that other information may be stored to allow the voltage to be applied to the calibration gate 106 to be determined. Accordingly, the change ΔV _BG may be stored, or the difference between the applied DC voltage V _GS and the threshold voltage may be stored.

The above (Equation 7) is no longer applicable if there is another voltage dependence of the capacitance C _FGBG within the voltage amplitude of the applied measurement signal. Therefore, it may not be possible to use a non-iterative approach because the determined threshold voltage may be incorrect. However, using an iterative approach, in the iteration where the minimum value is determined, the minimum value of the third harmonic amplitude may still be determined and associated with V _GS = V _T. Therefore, it is still possible to determine the threshold voltage.

  As described above, when ideal screening for capacitive coupling between driver gate 104 and calibration gate 106 is applied, there is a maximum frequency of the first frequency. For example, if the channel length of the driving transistor 102 is 10 μm and the applied DC voltage is 1 V, a frequency up to 5 MHz should be usable as the first frequency. Before and after this maximum frequency, oscillations around the driver gate voltage that exceed the threshold voltage are also coupled to the calibration gate. Thus, the measured calibration signal difference between the driver gate voltage exceeding the threshold voltage is reduced, which can make it more difficult to determine the threshold voltage.

  However, it is still possible to use a first frequency above the maximum frequency. FIG. 8 shows a simulation of the first, second and third harmonic responses for the 3 dB frequency of the drive transistor. As is apparent from FIG. 8, it is still possible to determine the maximum value of the second harmonic and / or the minimum value of the third harmonic, so that even if a frequency higher than the maximum frequency is used, the threshold is reached. The value voltage can be determined.

  The selection of the first frequency to be used can take into account both the maximum frequency mentioned above and the frequency of the noise source in order to avoid noise interference from such a sound source. For example, at frequencies up to approximately 100 kHz, there may be ambient noise (eg, from lamps around the display). Further, the charger noise and display noise increase to a maximum of 100 kHz and may occur even at 500 kHz or higher. Also, capacitive touch measurement systems may use frequencies of 100-500 kHz that generate noise in this frequency spectrum. Accordingly, the first frequency can be selected from a frequency exceeding 100 kHz, a frequency exceeding 500 kHz, or a frequency exceeding 1 MHz in order to avoid noise interference. For example, the first frequency can be selected in the range of 100 kHz to 5 MHz, or 500 kHz to 5 MHz.

  In the above discussion, the OLED capacity is high enough for the operating frequency so that the OLED is considered shorted. If the OLED capacity is not large, the measured calibration signal is affected.

For driver gate voltages below the threshold voltage, an additional signal corresponding to (C ₁ * C ₂ ) / (C _{Data (N + 1)} * C _OLED ) * A is present in the measured calibration signal Good. When the threshold voltage is exceeded, the OLED voltage follows the driver gate voltage. In the measured calibration signal, the fractional part C ₂ / C _{Data (N + 1)} is obtained. Even in this situation, the second and third harmonics are produced when crossing below the threshold voltage and above the threshold voltage. Again, the threshold voltage can be determined by iteratively determining the minimum value of the third harmonic amplitude.

The analytical expression for calculating the threshold voltage also depends on the correctness of the assumption that the OLED can be considered a short circuit at the frequency under consideration. This assumption is therefore based on OLEDs with sufficient conductivity or sufficiently high capacitance. Under normal circumstances, the OLED has sufficient conductivity or a sufficiently high capacitance. Nevertheless, it may be more appropriate to perform an iterative procedure from this point of view, even if the OLED does not satisfy any assumptions. The DC voltage level V _GS is changed to identify when the third harmonic amplitude is minimum and to determine the threshold voltage based on this identification.

As described above, the measurement signal in the calibration measurement mode is performed at a selected DC voltage level V _GS close to the threshold voltage or at a repetition of the DC voltage level V _GS centered on the threshold voltage. This means that the light output by the OLED 116 is hardly induced by the measurement signal.

  When one iteration of the measurement signal is performed, the DC voltage level may be selected to correspond to the highest possible or lowest possible threshold voltage. As mentioned above, the ratio between the third harmonic amplitude and the second harmonic amplitude only provides the difference between the DC voltage level and the threshold voltage. Thus, by selecting the DC voltage level to correspond to the highest possible or lowest possible threshold voltage expected, a threshold voltage that is less than the highest possible threshold voltage determined or Used as a DC voltage level that can be directly concluded to correspond to a threshold voltage above the lowest possible threshold voltage.

  Thus, the calibration measurement can include the following procedure.

  First, a DC voltage is applied to the first data line 110, and in one embodiment, the DC voltage corresponds to the highest possible threshold voltage, and in another embodiment, it corresponds to the lowest possible threshold voltage. . Next, a DC voltage is applied to the second data line 114 to supply a desired voltage to the calibration gate 106.

  Next, the signals on select line 204 and calibration line 206 go high to open the gates of select transistor 108 and calibration transistor 112 and the data on first data line 110 is driven to driver gate 104 of drive transistor 102. And the data on the second data line 114 is supplied to the calibration gate 106 of the driving transistor 102. The second data line 114 can then be brought to a high impedance and a calibration measurement can be initiated.

  Here, a periodically changing signal is provided on the first data line 110 to provide an AC voltage of a first frequency. The amplitude of the AC voltage corresponds to twice the difference between the lowest possible threshold voltage and the highest possible threshold voltage. This means that the voltage at driver gate 104 varies above and below the threshold voltage, resulting in the generation of second and third harmonics.

  In this embodiment, when the DC voltage is at the highest possible threshold voltage, an AC voltage for a voltage below zero causes the driver gate voltage to be lower than the threshold voltage. On the other hand, in the present embodiment, when the DC voltage is at the lowest threshold voltage, the driver gate voltage exceeds the threshold voltage when the AC voltage becomes higher than zero.

  The second and third harmonics may be determined in the measured calibration signal. Based on the determined amplitudes of the second and third harmonics, the corrected voltage of the calibration gate 106 can be calculated.

  Next, the signal on select line 204 can be pulled low to close the gate of select transistor 108. A signal can then be actively applied to the data line 114 to provide a calibration signal that corrects the voltage at the calibration gate 106 of the pixel 100. Finally, the next frame can be provided to the display 200 by bringing the signal on the calibration line 206 low, closing the gate of the calibration transistor 112 and driving the display in the normal mode of operation.

  A drive architecture for providing a measurement signal and determining a measured calibration signal will now be described with reference to FIGS.

  The control circuit 202 includes an oscillator 210 that can be used both to generate a measurement signal and to extract second and third harmonics.

  Thus, the signal from the oscillator 210 is supplied to a first phase locked loop (PLL) 212 where the frequency supplied by the oscillator 210 is downconverted to the sixth oscillator frequency. This means that the signal for extracting the second and third harmonics is generated as one third of the oscillator frequency and half of the oscillator frequency, and the oscillator 210 can be advantageously reused. To do.

  PLL 212 can provide modulation to output two different signals 214, 216 to adjacent pixels 100 on two data lines 218a, 218b. The modulation can preferably be done with respect to the phase of the signal, but amplitude modulation can also be used. In one embodiment, the second measurement signal 216 is phase shifted by 180 degrees with respect to the first measurement signal 214. This can reduce the overall external radiation and reflection at the end of the data line. Also, capacitive coupling of adjacent pixels on the second data line 114 to the first data line 110 is minimal, which is coupled to opposite signals on both sides of the pixel 100. This is because that.

  In FIG. 9a, driving of odd pixels in a row is shown simultaneously. Accordingly, the first measurement signal is provided on the first data line 218a, and the first data line 218a is coupled to the first data line 110 of the first pixel 100a in the row, and the first pixel 100a. Is supplied as a measurement signal to the driver gate 104 of the driving transistor 102. Further, the second measurement signal is supplied on the second data line 218b, and the second data line 218b is coupled in a row to the first data line 110 of the third pixel 100c, and the third pixel 100c A measurement signal is supplied to the driver gate 104 of the drive transistor 102. Therefore, these odd pixels may be driven simultaneously in the calibration measurement mode.

  The first data line 110 of the second pixel 100b in the row can also function as the second data line 114 of the first pixel 100a. Thus, this data line 114 is used to measure the calibration signal based on the measurement signal supplied to the first pixel 100a by the data line 110. Thus, the data line 114 is coupled to the amplifier 220b and allows measurement of the calibration signal of the first pixel 100a. Similarly, the second data line 114 of the third pixel 100c can also function as the first data line 110 of the fourth pixel 100d and is coupled to the amplifier 220d to calibrate the third pixel 100c. Enable signal measurement.

  In FIG. 9b, the driving of even pixels in the row is shown simultaneously. Here, the first measurement signal is coupled to the first data line 110 of the second pixel 100b. The second measurement signal is coupled to the first data line 110 of the fourth pixel 100d. The first data lines of the first and third pixels 100a, 100c are used here for measuring the calibration signal.

  Thus, as shown in FIGS. 9a and 9b, all pixels in a row may be calibrated in two operations, all odd pixels are all even pixels that may be calibrated in the first operation. May be calibrated in the second operation.

  Referring now to FIGS. 10a-10d, the control circuit 202 for providing the measurement signal and measuring the calibration signal will be further described. In FIG. 10a, the components related to the pixels 100a to 100d are illustrated as having connection portions, and the connection portions may be switched according to the operation mode of the display 200 indicated by a broken line. 10b to 10d show the connections used in the normal operation mode and the calibration measurement mode.

  As shown in FIG. 10a, the control circuit 202 associated with one pixel includes a sampling latch 222, a holding latch 224, and a digital / analog converter (DAC) 226. The digital / analog converter (DAC) 226 includes: Used to convert a digital signal providing data for the desired light output by the pixel 100 of the display 200 into a corresponding analog signal, which is supplied to the first data line 110 of the pixel 100.

  The control circuit 202 associated with one pixel may further include components for analog / digital conversion of the measured calibration signal. The DAC 226 may be reused to implement a successive approximation analog to digital converter. Thus, the control circuit 202 includes a comparator 228 that can receive a portion of the measured analog signal and the signal from the DAC 226. The output from the comparator 228 is supplied to a holding latch 224. The holding latch 224 functions as a successive approximation register and supplies an approximate digital code of the received analog signal to the DAC 226.

  The control circuit 202 includes a bandpass filter 230 that filters (pass-filters) the second or third harmonic from the measured calibration signal, and a PLL 234 that generates the frequency of the second harmonic, or the filtered signal. A mixer 232 for mixing with a reference signal provided by a PLL 236 that generates a third harmonic frequency based on the oscillator frequency. Thus, the mixer 232 can accurately extract the second or third harmonic and can further pass through a low-pass filter 238 for separating the second or third harmonic from the mixer 232. The low pass filter 238 can also sample and hold an analog signal to provide a constant signal to the comparator 228 for conversion to digital form.

  Accordingly, the control circuit 202 associated with one pixel can be configured to extract the second or third harmonic of the measured calibration signal and output the extracted signal through the sampling latch 222. .

  In FIG. 10b, it is shown that the display 200 is driven in the normal operation mode. Data from the DAC 226 of the control circuit 202 is driven to the data line of each pixel 100 in order to output light by a plurality of pixels.

  In FIG. 10c, driving the display 200 in a calibration measurement mode for calibrating odd pixels in a row is shown. Accordingly, the first measurement signal 214 is provided on the first data line 110 of the first pixel, and the second measurement signal 216 is provided on the first data line 110 of the third pixel. .

  The calibration signal on the second data line 114 of the first pixel is further coupled to the control circuit 202 associated with both the first pixel and the second pixel after passing through the amplifier 220b.

  A control circuit 202 associated with the first pixel receives the calibration signal and passes the calibration signal through a bandpass filter 230a for extracting the third harmonic. The mixer 232a associated with the first pixel receives the signal from the bandpass filter 230a and the signal from the PLL 236 that generates a third harmonic frequency based on the frequency of the oscillator. Thus, the control circuit 202 associated with the first pixel can extract the third harmonic signal from the measured calibration signal.

  The control circuit 202 associated with the second pixel also receives the calibration signal on the second data line 114 and passes the calibration signal through a bandpass filter 230b for extracting the second harmonic. The mixer 232b associated with the second pixel receives the signal from the bandpass filter 230b and the signal from the PLL 234 that generates a second harmonic frequency based on the oscillator frequency. Accordingly, the control circuit 202 associated with the second pixel can extract the second harmonic signal from the measured calibration signal.

  The second and third harmonics thus extracted are further analyzed to calculate the ratio of the third harmonic amplitude to the second harmonic amplitude to determine the threshold voltage as described above. It may be passed to the circuit.

  In FIG. 10d, driving the display 200 in a calibration measurement mode to calibrate even pixels in the row is shown. Here, the second and third harmonics are extracted and analyzed in the same manner as described above for odd lines. However, the first measurement signal 214 is provided on the first data line 110 of the second pixel, and the second measurement signal 216 is provided on the first data line 110 of the fourth pixel. . A calibration signal is received on the second data line 114 of even pixels.

  With reference now to FIGS. 11a-11c, another embodiment for providing a measurement signal and measuring a calibration signal is further described.

  In this embodiment, it is utilized that the capacitive coupling from driver gate 104 to calibration gate 106 is equal to the capacitive coupling from calibration gate 106 to driver gate 104. The measurement signal may be supplied to the driver gate 104 by the first data line 110 or may be supplied to the calibration gate 106 by the second data line 114. The calibration signal can then be measured on another data line. Thus, the same data line can always be used to receive the calibration signal.

  The calibration measurement is repeated every 4 pixels. In FIG. 11a, four pixels 100a-100d are shown in a row, and calibration measurements of the first and fourth pixels 100a, 100d are shown.

  Here, the first measurement signal is supplied onto the first data line 218a, and the first data line 218a is coupled to the first data line 110 of the first pixel 100a to drive the first pixel 100a. A measurement signal is supplied to the driver gate 104 of the transistor 102. Further, the second measurement signal is supplied onto the second data line 218b, and the second data line 218b is coupled to the second data line 114 of the fourth pixel 100d to drive the fourth pixel 100d. A measurement signal is supplied to the calibration gate 106 of the transistor 102. Accordingly, these first and fourth pixels in a row may be driven simultaneously in a calibration measurement mode.

  The first data line 110 of the second pixel 100b in the row can also function as the second data line 114 of the first pixel 100a. Thus, this data line 114 is used to measure the calibration signal based on the measurement signal supplied to the first pixel 100a by the first data line 110. Accordingly, the data line 114 is coupled to the amplifier 220 and allows measurement of the calibration signal of the first pixel 100a. Also, the first data line 110 of the fourth pixel 100d is connected to the amplifier 220, which enables measurement of the calibration signal for the fourth pixel 100d, which is the driving transistor 102 of the fourth pixel 100d. Obtained on the driver gate 104. The first data line 110 of the third pixel 100c, which also functions as the second data line 114 of the second pixel 100b, is driven as follows using a sufficiently high DC signal. That is, the channel of the driving transistor 102 for the second and third pixels 100b and 100c is turned on, and the capacitive coupling between the driver gate 104 and the calibration gate 106 of the driving transistor 102 of these pixels is shielded. Driven. Therefore, capacitive coupling between the gates in these pixels does not affect the calibration measurement of the first and fourth pixels 100a, 100d.

  As described, the first measurement signal 216 and the second measurement signal 216 can be used, where the second measurement signal 216 is 180 degrees phase shifted with respect to the first measurement signal 214. The This can reduce the overall external radiation and reflection at the end of the data line.

  FIG. 11b shows the calibration measurements of the second and third pixels 100b, 100c.

  Here, a measurement signal is supplied to the first data line 218a, the first data line 218a is coupled to the first data line 110 of the third pixel 100c, and the second data line of the second pixel 100b. It also functions as 114. Therefore, the measurement signal is supplied as a measurement signal on the driver gate 104 of the driving transistor 102 of the third pixel 100c, and is supplied as a measurement signal to the calibration gate 106 of the driving transistor 102 of the second pixel 100b. Thus, these second and third pixels in a row may be driven simultaneously in the calibration measurement mode using the same measurement signal.

  The first data line 110 of the second pixel 100b in the row is used to measure the calibration signal again, similar to the measurement of the calibration signal for the first pixel 100a, but this time the second data line 110 A calibration signal of the pixel 100b is measured. The first data line 110 of the fourth pixel 100d also functions as the second data line 114 of the third pixel 100c, and the first data line 110 is a calibration for the third pixel 100c. It may be used for signal measurement. The first data line 110 of the first pixel 100a and the second data line 114 of the fourth pixel 100d are driven as follows using a sufficiently high DC signal. That is, the channels of the drive transistors 102 for the first and fourth pixels 100a and 100d are turned on to shield capacitive coupling between the driver gate 104 and the calibration gate 106 of the drive transistors 102 of these pixels. Driven. Therefore, capacitive coupling between the gates in these pixels does not affect the calibration measurement of the second and third pixels 100b, 100c.

  In the calibration measurement of the second and third pixels 100b, 100c, the same measurement signal can be used to perform a calibration measurement of the two signals. Further, the first and second measurement signals whose phases are shifted from each other by 180 degrees are supplied, and other than the column that receives the measurement signals (that is, the first measurement signal is the eighth data line in the pixel row). All data lines can be actively driven.

  Thus, as shown in FIGS. 11a and 11b, all the pixels in a row can be calibrated with two operations, and two of the two pixels out of the four pixels are calibrated in the first operation, In the second operation, the remaining two of the four pixels may be calibrated. Since the same data line is used to measure the calibration signal, the control circuit 302 may be arranged differently.

  In FIG. 11 c, components related to the pixels 100 a to 100 d are illustrated using a connection unit, and the connection unit may be switched according to the operation mode of the display 200 indicated by a broken line. The control circuit 302 functions similarly to the control circuit 202 described above in connection with FIGS. 10a-10d and will not be described in detail. As shown in FIG. 11c, it is not necessary to have an amplifier 220 associated with every data line, since the same data line is always used to measure the calibration signal.

  As described above, it is possible to measure the threshold voltage of the driving transistor 102 of each pixel 100 in the display 200. The threshold voltage may be measured in relation to a black display (no image is displayed on the display) and in relation to an image presented on the display, from two such calibration measurements. Can be used to estimate the voltage drop across the ground plane of the display 200.

Accordingly, a first calibration measurement may be performed during activation of the active matrix display 200 before the first image is presented on the display 200. Thus, the first calibration measurement makes it possible to measure the difference between the gate-source voltage V _GS on the driver gate 104 and the threshold voltage of the drive transistor 102 when the pixel 100 is not active. Therefore, no voltage drop occurs on the ground plane. Next, a second calibration measurement associated with the image presented on the display 200 is performed immediately after the display is activated, so that it can be assumed that no other shift in the threshold voltage has occurred. . The second calibration measurement then allows determining the same difference between the voltage V _GS on the driver gate 104 and the threshold voltage of the drive transistor 102 when the display pixel 100 is active. . The difference between the first calibration measurement and the second calibration measurement results in a difference in the power supply voltage Vs of the drive transistor 102 in the first and second calibration measurements and may be due to a ground resistance drop.

  As shown in FIG. 12, a calibration measurement to estimate the ground plane voltage drop may be performed on several selected rows 304 of the display 200. Thus, calibration measurements are not necessarily performed for every row, as it can be time consuming, thus affecting the visual experience of the image presented on the display. Measurements performed on several selected rows 304 are used to determine the profile of the source voltage Vs for these rows 304 (resulting in determining the ground resistance drop for these rows 304). The ground plane profile can also be estimated for other rows in the display 200.

  For example, the three rows 304 may be recalibrated in a frame presented on the display 200. This is repeated several times and several lines of calibration measurements can be performed. The determined ground plane profile for the selected row 304 may also be used to estimate the ground plane profile across the display 200 (between the selected rows 304).

In the normal operation mode of the display 200, each estimated value of the voltage drop V _S due to resistance at the pixel is on the first data line 110 of the pixel 100 to compensate for the ground resistance drop when driving the pixel 100. Added to the provided data value.

  As shown in FIG. 1b, for a typical OLED stack, the ground is typically the deposited counter electrode of the OLED. The counter electrode is usually not patterned, which allows current to flow in all directions of the counter electrode. Thus, the slope in the ground plane voltage drop profile may be averaged across the ground plane. This allows a good assessment of the ground resistance voltage drop across the display 200 by measuring the ground profile of several selected reference rows.

  In the case of an inverted OLED stack, as shown in FIG. Since the wiring may be independent, it may be difficult to evaluate the ground resistive drop profile across the display 200 if the ground plane is calibrated to a small number of ground wiring.

  Accordingly, the display data lines 110, 114 extending along the columns of the array may preferably be arranged parallel to the ground wiring, which may be selected in several selected rows of the display 200 (to it). Calibration with a ground wire extending along) has several reference points for the voltage drop. Therefore, a good evaluation of the overall voltage drop of the column is possible.

  It may be easier to evaluate the ground resistance drop profile across the display 200 if the ground wiring extends along the display 200 row in both directions along the display 200 row.

For an inverted OLED stack, the ground resistance profile may instead be estimated based on the actual expected current in all pixels, which actual expected current is provided on the first data line 110 of each pixel. Data and the resistance value of each pixel, where the resistance value is known and stable. The voltage drop of the ground resistance is determined when only the ground wiring exists along the direction perpendicular to the data line. The voltage drop ΔV _n on the ground line (and hence the ground profile) can be calculated as a double nested sum across pixels k, m as a function of pixel resistance R _m and pixel current I _k .

  Here, referring to FIG. 13, a method of threshold voltage compensation in an active matrix display will be briefly summarized.

  The method includes step 402 of driving the display in a calibration measurement mode to measure the threshold voltage of at least one pixel to allow calibration of the at least one pixel 100. In the calibration measurement mode, the measurement signal is actively driven to one of the first and second data lines 110, 114, 115. A calibration signal is measured on the other of the first and second data lines 110, 114 of the pixel 100.

  The method includes determining 404 calibration data for at least one pixel based on the measured calibration signal. Therefore, the calibration data used to compensate for the threshold voltage variation of the pixel 100 is determined.

  The method further includes driving 406 the display in a calibration refresh mode to calibrate at least one pixel. In the calibration refresh mode, calibration data may be provided on the second data line 114 to the calibration gate 106 of the drive transistor 102. By driving the display in a calibration refresh mode, the pixel 100 can be held in a calibrated state.

  Thus, the display is driven in a normal mode of operation, where data can be provided on the first data line 110 to drive the light output from each pixel, where the pixel calibration. Thus, a desired output is received from each pixel.

  In the above, the concepts of the present invention have been mainly described with reference to a limited number of examples. However, as will be readily appreciated by those skilled in the art, other examples than those disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.

  Although the calibration measurement has been described primarily as being performed by driving the active measurement signal on the driver gate 104 and measuring the calibration signal on the calibration gate 106, the calibration gate 106 to the driver gate 104 has been described. Capacitive coupling is equivalent to capacitive coupling from driver gate 104 to calibration gate 106, so it replaces the calibration measurement by driving the active measurement signal on calibration gate 106 and measuring the calibration signal on driver gate 104. Can be done automatically.

Claims (15)

A method for threshold voltage compensation in an active matrix display comprising:
The display is
Comprising a plurality of pixels arranged in an array comprising a plurality of rows and a plurality of columns;
The pixel is
A drive transistor having a driver gate and a calibration gate;
A select transistor for selectively connecting the first data line to the driver gate of the drive transistor;
A calibration transistor for selectively connecting the second data line to the calibration gate of the drive transistor;
The method
Driving the display in a calibration measurement mode to measure a threshold voltage of at least one pixel to allow calibration of the at least one pixel, wherein in the calibration measurement mode, the at least one pixel The gate of the select transistor is opened to connect the first data line to the driver gate of the driving transistor, and the gate of the calibration transistor of the at least one pixel has the second data line as the calibration gate of the driving transistor. Open to connect, a measurement signal is actively driven on one of the first and second data lines, a calibration signal is measured on the other of the first and second data lines,
The method
Determining calibration data for at least one pixel based on the measured calibration signal;
Driving the display in a calibration refresh mode to calibrate the at least one pixel, wherein in the calibration refresh mode, the gate of the selection transistor of the at least one pixel is closed to One data line is cut, the gate of the calibration transistor of the at least one pixel is opened to connect the second data line to the calibration gate of the driving transistor, and the determined calibration data is a second Supplied to the calibration gate of the drive transistor on the data line of
A method for threshold voltage compensation in an active matrix display.   The method of claim 1, wherein the measurement signal is a periodically changing signal having a first frequency.   The method of claim 2, wherein the measurement signal varies in relation to a constant signal, the constant signal being selected based on the highest or lowest possible threshold voltage possible.   4. A method according to claim 2 or 3, wherein at least a second or third harmonic with respect to the first frequency is measured for a calibration signal. The threshold voltage is measured simultaneously for a subset of pixels in a row;
First and second measurement signals are provided, wherein the second measurement signal is received by one pixel of the subset of pixels that receives the first measurement signal on the first data line. 5. A method according to any one of claims 2 to 4, wherein the method is phase-shifted 180 degrees relative to the first measurement signal so as to have adjacent pixels in the subset of pixels to be detected.   6. The method of claim 1, further comprising storing the calibration data and supplying the stored calibration data on the second data line to a calibration gate of the drive transistor in the calibration refresh mode. The method according to one.   The method according to any one of the preceding claims, wherein the display is driven multiple times in a calibration refresh mode between two consecutive opportunities to drive the display in a calibration measurement mode. At least one pixel in a row is driven in a calibration measurement mode;
8. A method according to any one of claims 1 to 7, wherein for all other rows, the gates of the selection transistor and calibration transistor are closed to retain the original frame image on the display. Obtain a calibration signal associated with the black display and present the image by performing a calibration measurement mode on at least one row of pixels in both the black display and the image presented on the display Obtaining a calibration signal for a display to perform;
Estimating the voltage drop across the display ground plane based on the difference between the measured calibration signal associated with the black display and the measured calibration signal associated with the display presenting the image; 9. A method according to any one of claims 1-8.   The method of claim 9, wherein when the display is driven in a normal mode to display an image, data on the first data line is compensated by an estimated voltage drop. An active matrix display comprising a plurality of pixels arranged in an array comprising a plurality of rows and a plurality of columns,
The pixel is
A drive transistor having a driver gate and a calibration gate;
A select transistor for selectively connecting the first data line to the driver gate of the drive transistor;
A calibration transistor for selectively connecting a second data line to a calibration gate of the drive transistor;
The active matrix display is
Comprising data lines comprising first and second data lines arranged along the row or column direction of the array;
Each data line is in a row or column of the array such that each data line is connected to the select transistor of a pixel on one side of the data line and to the calibration transistor of a pixel on the other side of the data line. Connected to the pixel selection transistor along the
The active matrix display is
A control circuit connected to the plurality of data lines;
The control circuit is configured to provide data on the plurality of data lines to display an image in a normal mode of the display;
The control circuit is further configured to provide calibration data on the data line to provide calibration data to a calibration gate of a pixel drive transistor in a calibration refresh mode of the display;
The control circuit further provides a measurement signal to one of the first and second data lines and measures a calibration signal on the other of the first and second data lines in a calibration measurement mode of the display. An active matrix display configured to do.   The display of claim 11, wherein the control circuit is configured to provide a measurement signal as a periodically changing signal having a first frequency.   The display of claim 12, wherein the control circuit is configured to measure at least a second or third harmonic of the calibration signal with respect to the first frequency.   The display of claim 13, further comprising an oscillator used to provide a frequency of the measurement signal and to provide a reference frequency for extracting at least a second or third harmonic. The control circuit includes a digital / analog converter for each data line,
The digital / analog converter is configured to provide an analog signal when the display is driven in a normal mode and is used when driving the display in a calibration measurement mode. 15. A display according to any one of claims 11 to 14, configured as a component of a vessel.

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