TW201837891A - An active matrix display and a method for threshold voltage compensation in an active matrix display - Google Patents

Abstract

A method for threshold voltage compensation in an active matrix display (200) is provided. The display (200) comprises pixels (100), each comprising a drive transistor (102) having a driver gate (104) and a calibration gate (106), a first dataline (110) selectively connected to the driver gate (104), a second dataline (114) selectively connected to the calibration gate (106). The method comprises: driving (402) the display (200) in a calibration measurement mode for measuring a threshold voltage of a pixel (100), wherein the first dataline (110) is connected to the driver gate (104) and the second dataline (114) is connected to the calibration gate (106), and a measurement signal is actively driven to one of the first and the second dataline (110; 114) and a calibration signal is measured on the other of the first and the second dataline (110; 114), determining (404) calibration data based on the measured calibration signal; and driving (406) the display (200) in a calibration refresh mode, wherein the second dataline (114) is connected to the calibration gate (106) of the drive transistor (102), and the determined calibration data is provided on the second dataline (114) to the calibration gate (106) of the drive transistor (102).

Description

Active matrix display and threshold voltage compensation method in active matrix display

The inventive concept relates to an active matrix display and a threshold voltage compensation method in an active matrix display.

The active matrix display includes a plurality of pixels arranged in an array, wherein each pixel has a light emitting element. The light emitted by the light-emitting elements of the pixels together forms an image that is presented by the display. The light emitting element can be, for example, an organic light emitting diode (OLED), and thus, the display can be an active matrix OLED (AMOLED) display. An active matrix display, such as an AMOLED display, can drive the backplane using, for example, one of one or more thin film transistor (TFT) array forms. The backplane can be fabricated using a low temperature fabrication program suitable for forming a flexible display, for example, a substrate. Therefore, active matrix displays, such as AMOLED displays, are frequently used in a variety of applications and are also one of the promising technologies for future applications. A drive transistor can be used to drive a current through the OLED to emit light from a pixel. The current through the OLED can depend on the characteristics of the drive transistor. These characteristics (specifically, one of the threshold voltages of the driving transistor) may vary over time, and the variations may vary from pixel to pixel. Therefore, to avoid non-uniform output from one of the displays, calibration may be required to compensate for variations and degradation. A double gate drive transistor can be used to compensate for variations in threshold voltage. In current AMOLED displays, measuring the current through the OLED and providing a compensation system in a current through a programmed circuit, the change in current through the OLED is the result of a change in the threshold voltage of the drive transistor. For example, WO 02/067327 discloses a pixel current driver comprising a plurality of TFTs each having a double gate and for driving an OLED layer. The plurality of TFTs may be five TFTs formed by a current ΔV _T -compensation method. This current is programmed to generate complex circuitry and thus reduce the maximum resolution of the AMOLED display. In another method, such as, for example, C. Jeon et al. "AMOLED Pixel Circuit using Dual Gate a-IGZO using a dual gate a-IGZO TFT for a simple scheme and high speed _VTH capture. "TFTs for Simple Scheme and High Speed V _TH Extraction"" (Society for Information Display Digest, Vol. 47, No. 1, pp. 65-68 (2016)), a double gate The pole drive transistor is used with an operational scheme to compensate for variations in the threshold voltage. The pixels can be driven independently of the threshold voltage such that degradation due to variations in threshold voltage can be eliminated. However, this method alternatively requires one of the schemes for performing compensation before data can be provided for driving the pixels.

One of the objectives of the inventive concept is to provide an improved threshold voltage compensation method. One particular object of the inventive concept is to provide a threshold voltage compensation using a simple pixel circuit (and only one calibration scheme needs to be applied intermittently). The invention as defined in the independent technical solution at least partially satisfies these and other objects of the inventive concept. The preferred embodiment is set forth in the accompanying technical solutions. According to a first aspect, a threshold voltage compensation method in an active matrix display is provided, the display comprising a plurality of pixels configured to include a plurality of columns and an array of a plurality of rows, wherein one pixel comprises: a driving a crystal having a driver gate and a calibration gate; a selection transistor for selectively connecting a first data line to the driver gate of the driver transistor; a calibration transistor for use And selectively connecting a second data line to the calibration gate of the driving transistor, wherein the method comprises: driving the display in a calibration measurement mode to measure a threshold voltage of one of the at least one pixel, so as to achieve Calibration of the at least one pixel, wherein in the calibration measurement mode, one of the select transistors of the at least one pixel is turned on to connect the first data line to the driver gate of the drive transistor, and One of the calibration transistors of the at least one pixel is turned on to connect the second data line to the calibration gate of the driving transistor, and a measurement signal is Driving to one of the first data line and the second data line, and measuring a calibration signal on the other of the first data line and the second data line; and based on the measured calibration signal Determining the calibration data of the at least one pixel; and driving the display to calibrate at least one pixel in a calibration renew mode, wherein in the calibration renew mode, one of the selection transistors of the at least one pixel is turned off Disconnecting the first data line from the driver gate of the driving transistor, and one of the calibration transistors of the at least one pixel is turned on to connect the second data line to the driving transistor The gate is calibrated and the determined calibration data is provided to the calibration gate of the drive transistor on the second data line. Thanks to the invention, the display can be driven in a calibration measurement mode to measure a threshold voltage of the drive transistor of the at least one pixel. The measurement can then provide a determined calibration signal to the calibration gate of the drive transistor to compensate for the measured threshold voltage in the pixel and to handle variations and/or non-uniformities between pixels. . This may allow the drive transistor to be operated by a simple drive signal to induce the desired output from one of the light-emitting elements driven by the drive transistor. Calibration can be performed for all pixels in the display, where calibration measurements for all pixels can be in a single working phase (eg, a single frame) or a plurality of working phases of the calibration measurement mode in one of the calibration measurement modes Execution, where calibration measurements are performed for different pixels in different stages of operation. Thus, once the active matrix display is calibrated and the threshold voltage is compensated, the drive data can be provided to the respective drive transistors of the pixels without taking into account the threshold voltage variations between the pixels. The calibration data provided to the calibration gate of the drive transistor can be maintained at the calibration gate for a substantial period of time so that the display can only be operated irregularly in the calibration re-mode. In addition, the calibration measurement mode can be used to measure deviations in the threshold voltage, and thus can be applied at regular intervals to enable identification of changes in threshold voltage and allow the active matrix display to always compensate for changes to the threshold voltage of the drive transistor. The invention also allows the use of a simple pixel structure with several elements. This implies that the active matrix display can be configured with high resolution. An active matrix display should be interpreted as any display that includes an active matrix for driving the light output from the light-emitting elements associated with the respective drive transistors of the pixels of the display. The light emitting elements can be, for example, OLEDs, whereby the active matrix display is an AMOLED display. The pixels are configured to include an array of a plurality of columns and rows. This may imply that the pixels are logically organized into columns and rows and may be addressed collectively by the lines used to control the pixels. The term "column" or "row" does not need to refer to the actual physical orientation of one of the displays. As will be understood by those skilled in the art, the columns and rows can be readily interchanged, and in the present invention, the terms are intended to be interchangeable. The measurement signal can be actively driven to the first data line, and the calibration signal can be measured on the second data line. Alternatively, however, the measurement signal can be actively driven to the second data line and the calibration signal can be measured on the first data line. The display can be configured to provide a measurement signal for all of the pixels on the first data line. However, in an alternative, the display can be configured such that the measurement signal can be actively driven to the first data line and the calibration signal can be measured on the second data line for certain pixels, while for other pixels, the measurement will be measured The signal is actively driven to the second data line, and the calibration signal can be measured on the first data line. If a data line is shared between adjacent pixels, this may allow the same data line to be used to receive calibration signals for adjacent pixels of the shared data line (one pixel provides a calibration signal on its first data line and another pixel in its second A calibration signal is provided on the data line). According to an embodiment, a first storage capacitor can be coupled between the driver gate of the drive transistor and one of the source or drain of the drive transistor. This implies that the data provided to the driver gate can be maintained by the storage capacitor, for example to maintain one of the pixel outputs in the display while the drive data is being provided to other pixels. Although this first storage capacitor ensures a well controlled drive of one of the pixels, parasitic capacitance can alternatively be used between the driver gate and the source or drain of the drive transistor. In accordance with another embodiment, a second storage capacitor can be coupled between the calibration gate of the drive transistor and the source or drain of the drive transistor. This implies that the data provided to the calibration gate can be maintained by the storage capacitor, for example to ensure that the calibration data remains on the calibration gate for a substantial period of time without requiring a new calibration operation. Although this second storage capacitor ensures that the calibration data remains at the calibration gate for a substantial period of time, alternatively a parasitic capacitance can be used between the calibration gate of the drive transistor and the source or drain. In addition, the display can then be operated more frequently by calibrating the new mode. According to an embodiment, the driver gate drives one of the front gates of the transistor and the calibration gate drives one of the back gates of the transistor. Alternatively, however, the driver gate can drive one of the back gates of the transistor and the calibration gate can drive one of the front gates of the transistor. In addition, the front and back gates of a transistor are dependent on the relative terminology of how the transistors are used interchangeably. Therefore, as used herein, the terms "driver gate" and "calibrated gate" shall be interpreted as different gates of a transistor, and each of the driver gate and the calibration gate may be referred to as a transistor, respectively. One of the front gates or one of the back gates. When one of the voltages at the driver gate of the drive transistor is below the threshold voltage, one of the channels of the drive transistor is non-conductive, and the driver gate and the calibration gate act as two plates of a capacitor. Therefore, there is a capacitive coupling between the driver gate and the calibration gate. When the voltage at the driver gate of the drive transistor is above a threshold voltage, the channel driving the transistor is conductive and, therefore, the capacitive coupling between the gate of the charge shield driver and the calibrated gate in the channel. Thus, it is insightful that the threshold voltage can be determined by identifying a change in capacitance between the driver gate and the calibration gate. According to an embodiment, the measurement signal has a periodic variation signal of one of the first frequencies. The present invention provides insight into that a periodically varying signal can be particularly useful and can facilitate determining the threshold voltage in a reliable manner. The periodically varying signal may allow for the acquisition of information related to the threshold voltage from other parameters affecting the measured calibration signal. According to an embodiment, the measurement signal varies with respect to a constant signal, wherein the constant signal is selected based on a highest possible or lowest possible threshold voltage. The determination of the threshold voltage may be indistinguishable from whether the threshold voltage is above or below one of the DC voltage levels provided by the constant signal (this is because the threshold voltage may be determined to be one of the relatively constant signals). By picking a constant signal equal to or higher than a highest possible threshold voltage, it can be inferred that the threshold voltage can be determined by subtracting the offset determined from one of the constant signals. Similarly, by selecting a constant signal equal to or lower than a lowest possible threshold voltage, it can be inferred that the threshold voltage can be determined by adding an offset determined relative to one of the constant signals. This implies that the threshold voltage can be directly determined based on a single measurement signal and that different measurement signals need not be provided (eg, based on different DC voltage levels) to determine the threshold voltage. According to an embodiment, the at least one second harmonic or the third harmonic is measured for the calibration signal relative to the first frequency. The parasitic capacitance between the first data line and the second data line can be relatively large with respect to the capacitive coupling between the driver gate and the calibration gate, suggesting that the parasitic capacitance makes it difficult to identify the voltage at the gate of the driver. One of the changes in capacitance between the driver gate and the calibration gate changes when the voltage is above or below the threshold voltage. However, the second and third harmonics of the first frequency may be unaffected by parasitic capacitance between the data lines. Therefore, by measuring the second harmonic or the third harmonic, the threshold voltage can be drawn without the parasitic capacitance between the data lines affecting the ability to determine the threshold voltage. As used herein, a "second harmonic" shall be interpreted as having a portion of the measured calibration signal having a frequency that is one of twice the frequency of the measurement signal (ie, the first frequency). In addition, a "third harmonic" should be interpreted as having a portion of the measured calibration signal that is one-third the frequency of the measurement signal. According to an embodiment, the threshold voltage is simultaneously measured for a subset of pixels in a column, and wherein a first measurement signal and a second measurement signal are provided, the second measurement signal being relative to the first measurement The signal is phase shifted by 180° such that one of the subset of pixels receiving the first measurement signal on the first data line has adjacent pixels in the subset of pixels that receive the second measurement signal. In other words, the first measurement signal and the second measurement signal that are phase shifted by 180 relative to each other are alternately supplied to every other pixel among the subset of pixels. This implies that the parasitic capacitive coupling between the data lines adjacent to the pixels can be reduced so as not to affect the determination of the threshold voltage of the drive transistor while still achieving simultaneous measurement of the threshold voltages of the plurality of pixels. All pixels in a column may be divided into a first subgroup and a second subgroup such that threshold voltages of all pixels in the first subgroup may be simultaneously determined in a first measurement period, and the second subgroup The threshold voltages of all of the pixels can be simultaneously determined in a second measurement period. It will be appreciated that more than two subgroups may be used, and thus, more than two measurement periods may be used in order to determine the threshold voltage of all pixels in the column. In an embodiment, the first subset of pixels may be an even number of pixels in a column. Thus, the threshold voltage can be measured simultaneously for even pixels in the column. Similarly, the threshold voltage can be measured simultaneously for odd pixels in the column. This implies that the threshold voltage can be determined for all pixels in a column in two measurement periods (one measurement period for even pixels and one measurement period for odd pixels). As used herein, "an even number of pixels in a column" shall be interpreted as a pixel configured to have one even numbered row, wherein the rows are sequentially numbered starting at 1 for a leftmost row. Similarly, "odd pixels in a column" should be interpreted as pixels configured to have one of the odd-numbered rows. According to another embodiment, the measurement signal is a voltage that increases or decreases linearly. Thus, instead of applying a periodic change signal, the measurement signal can be increased to sweep the voltage across the gate of the driver to switch from below the threshold voltage to above the threshold voltage. Alternatively, the measurement signal can be reduced to sweep the voltage across the gate of the driver to switch from above the threshold voltage to below the threshold voltage. Thus, when the equivalent signal is shifted from below the threshold voltage to above the threshold voltage, or vice versa, the shift can be determined in the measured calibration signal. According to an embodiment, the determining of the calibration data comprises: identifying a shift in one of the linear slopes of the calibration signal; extracting a threshold voltage based on the identified shift; and determining the calibration data based on the captured threshold voltage. The measured calibration signal at the calibration gate can have a linear dependence on one of the measurement signals. The threshold voltage can be determined based on the fact that when the equivalent measurement signal is above the threshold voltage (when the capacitive coupling between the driver gate and the calibration gate is shielded above the threshold voltage), the measured calibration signal is relative to the amount One of the measured signals increases the slope less. Using a linearly increasing voltage as the measurement signal provides a very fast way to determine the threshold voltage. However, the parasitic capacitance between the data lines can make it difficult to identify one of the slopes of the measured calibration signal, since the parasitic capacitance can be much larger than the capacitive coupling between the driver gate and the calibration gate, and thus It is one of the main factors affecting the slope. According to an embodiment, the method further comprises: storing the calibration data, and using the stored calibration data in the calibration regeneration mode. Therefore, the calibration data determined in the calibration measurement can be stored for reuse. This implies that the calibration re-mode can operate independently of the calibration measurement mode to perform a renewed calibration without having to perform a calibration measurement, which can be more time consuming. The voltage at the calibrated gate can be, for example, not stably maintained for a very long period of time due to leakage of the gate dielectric. Therefore, by storing the calibration data, one of the threshold voltage compensation voltages at the calibration gate can be renewed to maintain a desired relationship between the emitted light in a pixel and a provided control signal. According to an embodiment, the display is driven multiple times in a calibration renew mode between two subsequent moments in which the display is driven in the calibration measurement mode. The calibration measurement may only need to be performed at intervals based on the risk that the threshold voltage of the drive transistor has changed. On the other hand, the calibration re-mode can be performed to ensure that a desired voltage is maintained at the calibration gate, and thus may need to be performed more frequently. According to an embodiment, a single column is driven at a time in a calibration renew mode and calibration is performed for the entire display in a normal video frame. This implies that the stored calibration data can be provided to the pixels of the display in a single frame so that the calibration will not affect the visual experience provided by the display. During the calibration refresh mode, the selection transistor can be turned off to maintain the image on the display during the calibration of the frame in which the calibration is performed. According to an embodiment, at least one pixel in a single column is driven in a calibration measurement mode, and for all other columns, the gates of the selection transistor and the calibration transistor are turned off to maintain an image of the previous frame on the display . Thus, during calibration measurements, images on all columns except one column can be maintained on the display to minimize the visual experience provided by the display. Calibration measurements can be performed for all of the pixels in the column before the display is driven to update the frame being displayed. Calibration measurements can be performed in a separate frame for each column of the array such that one user viewing the display does not notice a calibration cycle. Thus, one or more frame updates can be performed between calibration measurements for different columns of the array. According to an embodiment, calibration measurements may be performed in separate frames for pixels within the same column of the array, such as odd and even pixels being aligned in one of the different frames. The combination of one of the pixels that are calibrated within a common frame can vary in a number of ways. According to an alternative, all pixels of one or more columns can be calibrated in one frame. According to another alternative, certain pixels from a number of columns, such as odd or even pixels, are calibrated within a common frame. According to an embodiment, the method further comprises: performing a calibration measurement mode for at least one column of pixels with respect to a black display and with respect to one of the images being rendered on the display; and estimating the display using a difference from the calibration measurement One of the ground planes has a voltage drop. Therefore, the method can be used to compensate for the threshold voltage variation of the driving transistor of the pixel and to compensate for the voltage drop of the ground plane. Thus, the method estimates a strain curve across the ground of the display such that any changes in the ground plane volume curve can be compensated for when driving the drive transistor of the pixel. According to an embodiment, when the display is driven in a normal mode to display an image, the data on the first data line is compensated by the estimated voltage drop. A calibration measurement relative to the black display can be performed during startup of the active matrix display prior to presenting a first image on the display. Then, the calibration measurement relative to one of the images being presented on the display can be performed immediately after the display is activated, such that it can be assumed that no other shift has occurred in the threshold voltage, and the difference from the calibration measurement can be attributed to the ground resistance. Pressure drop. A calibration measurement to estimate a voltage drop of one of the ground planes can be performed for several selected columns of the display. Therefore, in this case, calibration measurements are not performed for all columns, as performing calibration measurements for all columns can be too time consuming for certain display configurations, and thus affecting the image presented on the display. A visual experience. The measurements performed for several selected columns can also be used to estimate a measure of the ground plane between the selected columns. According to a second aspect, an active matrix display includes: a plurality of pixels configured to include an array of a plurality of columns and a plurality of rows, wherein a pixel includes: a driving transistor having a driver gate and a calibration gate; a selection transistor for selectively connecting a first data line to the driver gate of the driver transistor; a calibration transistor for using a first a second data line selectively coupled to the calibration gate of the driver transistor; a data line including the first data line and the second data disposed along one of the columns or one of the rows of the array a line, wherein each data line is coupled to the select transistors of the pixel along the column or row of the array such that the data line is coupled to the select transistors of the pixel on one side of the data line, and The calibration transistors coupled to the pixels on opposite sides of the data line; and control circuitry coupled to the data lines, wherein the control circuitry is configured to be in the normal mode of the display Information for displaying an image is provided on the stock line, wherein the control circuit is further configured to provide the drive transistor for providing calibration data to a pixel on the data line in a calibration renew mode of the display The calibration gate calibration data, and wherein the control circuit is further configured to provide a measurement signal to one of the first data line and the second data line in one of the display calibration modes of the display and A calibration signal is measured on the other of the first data line and the second data line. The effects and characteristics of this second aspect are largely similar to those described above in connection with the first aspect. The embodiments mentioned with respect to the first aspect are largely compatible with the second aspect. Thus, the control circuitry can control the display to drive the display in a normal mode, a calibration re-mode, and a calibration measurement mode, which are further illustrated above with respect to the first aspect. Each data line can be connected to a selective transistor at one side of the data line and to a calibration transistor at one of the opposite sides of the data line. This implies that the data lines can be used both to provide data to the driver gate of the driver transistor via the selection transistor and to provide calibration data for other pixels via the calibration transistor or to measure the calibration signal for other pixels. The signal to the gate of the selected transistor and the calibration transistor determines how the data line is used. According to an embodiment, the control circuit is configured to provide the measurement signal as a periodic change signal having a first frequency. According to an embodiment, the control circuit is configured to measure at least a second harmonic or a third harmonic of the calibration signal relative to the first frequency. According to an embodiment, the display further includes an oscillator for providing a frequency of the measurement signal and for providing a reference frequency for capturing at least one of the second harmonic or the third harmonic. This implies that a single oscillator can be used again to provide the measurement signal and to measure the calibration signal. Therefore, the reference frequency for measuring the second harmonic and the third harmonic can be extremely accurately correlated with the first frequency of the measurement signal. According to an embodiment, the control circuit includes a digital to analog converter for each data line, the digital to analog converter being configured to provide an analog signal when driving the display in a normal mode and to be driven in a calibration measurement mode The display is configured as a component of a continuous approximation analog-to-digital converter. This implies that the components of the control circuit can be reused so that a compact layout of one of the control circuits can be provided.

Figures 1a-1b illustrate two different variations of one of the pixel topologies of an active matrix display. Each pixel includes an organic light emitting diode (OLED) for emitting light when driving a current through the OLED. In Figure 1a, an inverted OLED stack is illustrated. In the pixel topology of Figure 1a, the OLED of each pixel has a common anode. In Figure Ib, a normal OLED stack is illustrated in which the OLED of each pixel has a common cathode. Although the topology of FIG. 1b will be shown and discussed in the following embodiments, it will be appreciated that the inverted OLED stack topology of FIG. 1a can alternatively be used. In the case where light emission from a pixel is provided by an OLED, an active matrix OLED (AMOLED) display is provided. Although OLEDs are primarily discussed herein, it should be recognized that active matrix displays are applicable to other types of light emitting elements that are configured in an array and that are controlled by an active matrix. Light-emitting elements driven by a current can be provided in a number of different ways, as will be appreciated by those skilled in the art, but an AMOLED display can be preferred in view of, for example, the fast switching speed of the pixels. The pixel 100 includes a drive transistor 102 having a driver gate 104 and a calibration gate 106. Pixel 100 includes a select transistor 108 for selectively connecting a first data line 110 to one of driver gates 104. Pixel 100 further includes a calibration transistor 112 for selectively connecting a second data line 114 to one of calibration gates 106. A signal on the first data line 110 can be provided to the driver gate 104 of the drive transistor 102 via the select transistor 108. Thus, the signal on the first data line 110 can provide information for turning on one of the channels in the drive transistor 102 and thus driving a current through the OLED 116, which is connected to one of the drain or source of the drive transistor 102. . One of the light output by OLED 116 may depend on a current level through one of OLEDs 116 such that the control circuitry can control the light output by a pixel by controlling the data provided on first data line 110. A signal on the second data line 114 can be provided to the calibration gate 106 of the drive transistor 102 via the calibration transistor 112. Thus, the signal on the second data line 114 can provide information for setting the voltage at one of the calibration gates 106 of the drive transistor 102. The voltage at the calibration gate 106 can be adapted to compensate for a change in threshold voltage of the drive transistor 102 such that the data provided on the first data line 110 can be ignored for controlling the threshold voltage of the light output by the pixel 100. Variety. Thus, the current driven through the OLED 116 may depend on the voltage difference between the driver gate 104 of the drive transistor 102 and the voltage at the source, and also depends on the calibrated gate 106 and source of the transistor 102. The voltage difference between the voltages at which the voltage level at the calibration gate 106 is provided relative to one of the predetermined threshold voltages assumed by the data provided on the first data line 110. The pixel 100 can further include a first storage capacitor 118 connectable between the driver gate 104 of the drive transistor 102 and one source of the drive transistor 102. This implies that the data provided to the driver gate 104 can be maintained by the storage capacitor 118, for example, to maintain one of the outputs of the pixel 100 in the display while the drive data is being provided to other pixels. Alternatively, the first storage capacitor 118 can be connected to one of the drains of the drive transistor 102. Although this first storage capacitor 118 can ensure a well controlled drive of one of the pixels 100, alternatively, a parasitic capacitance can be used between the driver gate 104 of the drive transistor 102 and the source or drain to maintain the driver gate. 104 on the information. The pixel 100 can further include a second storage capacitor 120 connectable between the calibration gate 106 of the drive transistor 102 and the source of the drive transistor 102. This implies that the data provided on the calibration gate 106 can be maintained by the storage capacitor 120, for example, to ensure that the calibration data remains on the calibration gate 106 for a substantial period of time without requiring a new calibration on the second data line 114. A signal is provided to the calibration gate 106. Alternatively, the second storage capacitor 120 can be connected to one of the drains of the drive transistor 102. Although the second storage capacitor 120 can ensure that the calibration data remains at the calibration gate 106 for a substantial period of time, alternatively, parasitic can be used between the calibration gate 106 of the drive transistor 102 and the source or drain. The capacitor maintains the data on the calibration gate 106. Moreover, if the second storage capacitor 120 is not provided, calibration data may instead be provided to the calibration gate 106 more frequently to re-calibrate the data and maintain the pixel 100 calibrated to the threshold voltage of the drive transistor 102 of the pixel 100. . Thus, pixel 100 can be provided with three transistors 102, 108, 112 and two capacitors 118, 120, and thus, the topology of pixel 100 can be a so-called 3T2C (3 transistors, 2 capacitors) topology. In FIG. 2, an active matrix display 200 comprising one of an array of pixels 100 arranged in columns and rows is schematically illustrated. Display 200 includes data lines 110, 114 that continue along one of the rows of the array. Display 200 further includes control circuitry 202 coupled to data lines 110, 114. Control circuitry 202 can be configured to provide data on data lines 110, 114 and also to measure signals on data lines 110, 114, as will be described in more detail below. The control circuit 202 can be provided as a data driver integrated circuit that provides components for generating a data signal to the data line and a data signal received on the measurement data line. The control circuit 202 can be further connected to a memory for storing calibration data of the pixel 100, or can include an integrated memory in the data driver integrated circuit. A multiplexer can be used to connect multiple data lines to one of the outputs of control circuit 202. Thus, control circuit 202 can include a multiplexer. If a multiplexer is introduced, at least two multiplexers may be introduced for individually connecting to the odd data lines and the even data lines, respectively, because the calibration measurements may need to simultaneously drive and measure the odd and even lines. As explained further below. Display 200 can further include select line 204 and calibration line 206 that extend perpendicular to one of data lines 110, 114 in one of the arrays. Select line 204 can provide a signal for selectively activating select transistor 108 in a column of pixels 100. Similarly, calibration line 206 can provide a signal for selectively activating calibration transistor 112 in a column of pixels 100. Display 200 can include a pair of select lines 204 for each column of pixels 100 to achieve independent selection of pixels in even numbered rows and odd numbered rows, respectively. Similarly, display 200 can include a pair of calibration lines 206 for each column of pixels 100. This may allow the calibration measurements for even pixels to be separated from the calibration measurements for odd pixels such that the calibration data determined for even pixels may be maintained during calibration measurements for odd pixels. The data lines 110, 114, the select lines 204 and the calibration lines 206, and the topology of the OLEDs 116 for driving the pixels can all be disposed on one of the substrates of the display 200. Display 200 can further include driver circuit 208 for driving select line 204 and calibration line 206. Driver circuit 208 can be disposed on the backplane, for example, as an integrated on-board gate (GIP). According to an alternative, the driver circuit 208 can be provided as a dedicated 矽 driver. The transistor for controlling the light output by the pixel 100 may be a p-type transistor and an n-type transistor. The substrate may comprise a thin film transistor (TFT), for example, hydrogenated amorphous Si (a-Si:H), polycrystalline germanium, organic semiconductor, (amorphous) indium gallium zinc oxide (a-IGZO, IGZO) TFT. The invention is applicable to displays using active matrix, but is not limited by a particular type of display. For example, the present invention is applicable to AMOLED displays, for example, RGB or RGBW AMOLED displays, which may include fluorescent or phosphorescent OLEDs, polymers or poly dendrimers, high power efficiency phosphorescent dendrimers, etc. . Referring now to Figures 3-5, three different modes of operating pixel 100 will be discussed. A first mode is one of the normal modes of operation illustrated in Figure 3, which can be operated in accordance with the driving of the state of the AMOLED display of the prior art. In this mode, information for controlling the light output by the pixel 100 is provided on the first data line 110 of the pixel 100. In the normal mode of operation, the calibration signal on calibration line 206 is low and the previously performed calibration of pixel 100 is unchanged. One of the calibration values stored on the second storage capacitor 120 thus remains unchanged. Additionally, the select signal on select line 204 is high to allow the drive data provided on first data line 110 to be applied to driver gate 104 of drive transistor 102. The drive data is stored on the first storage capacitor 118 such that the drive data on the driver gate 104 is maintained. The drive data controls the desired current through the OLED 116. The select signal can be driven column by column at a rate of one horizontal sync (HSYNC), which can be synchronized with the data provided on data line 110 such that the correct drive data is applied to driver gate 104 of each pixel 100. If display 200 includes a pair of select lines 204 for each column of pixels 100, then the two select lines 204 of the pair can be driven together to simultaneously provide a high select signal to the select transistors of all of the pixels 100 in the column. 108. A second mode is one of the illustrations illustrated in Figure 4 to calibrate the refresh mode. In this mode, data for providing calibration data to pixel 100 is provided on second data line 114 of pixel 100. In the calibration re-mode, the selection signal on select line 204 is low and the light output by pixel 100 does not change. One of the drive data values stored on the first storage capacitor 118 thus remains unchanged. This implies that one of the images presented by display 200 will be maintained during the calibration of a new frame. Additionally, the calibration signal on calibration line 206 is high to allow calibration data provided on second data line 114 to be applied to calibration gate 106 of drive transistor 102. The calibration data is also stored on the second storage capacitor 120 such that the calibration data on the calibration gate 106 can then be maintained. The calibration data provides a compensation relative to the threshold voltage of the drive transistor 102 such that the drive data provided in the normal mode of operation will control the desired current driven through the OLED 116. The calibration signal can be driven column by column at a rate of HSYNC, which can be synchronized with the data provided on data line 114 such that the correct calibration data is applied to the calibration gate 106 of each pixel 100. Each data line 110, 114 can be shared by adjacent pixels 100 such that a data line can form a first data line 110 for one pixel and a second data line 114 for adjacent pixels. This implies that one of the calibration data is provided for one of the rows n when the display 200 is driven in the calibration renew mode. The data line can be used to provide driving data for one of the rows n+1 when the display 200 is driven in the normal operating mode. . Accordingly, control circuit 202 can be configured to provide calibration data having a line offset relative to the drive data used to present an image on display 200. Moreover, if display 200 includes a pair of calibration lines 206 for each column of pixels 100, then the two calibration lines 206 of the pair can be driven together to simultaneously provide a high selection signal to the calibration of all pixels 100 in the column. The transistor 112. Since the calibration regeneration mode can be operated to renew the calibration data for all of the pixels 100 of the display 200 in one frame, the calibration regeneration mode can be performed without affecting the visual experience of one of the users viewing the display 200. The calibration re-synchronization mode should be performed frequently enough to maintain the calibration data provided on the calibration gate 106 of the drive transistor 102. For example, the charge stored on the second storage capacitor 120 may change due to leakage, and the calibration re-synchronization mode may need to be performed before the calibration data on the calibration gate 106 is significantly changed. The interval between the calibration and re-modes may depend on the amount of gate dielectric leakage and transistor current when turned off. Measurement of one of these parameters can be performed, for example, once as one of the steps during the manufacture of the display. A frequency of one of the calibration re-modes can then be adapted to the parameters of the display to set a preset interval for performing the calibration re-mode. For example, when using a display, it may be necessary to perform a calibration regeneration mode in one frame every minute, every 10 minutes, or even every hour. Therefore, the calibration renew mode is performed infrequently. Therefore, not only will a user be unaffected by performing a single calibration of a single frame, but the frames assigned to the calibration re-pattern will be far enough apart that even a user will notice a single map of the calibration re-mode. The box will also minimally affect the overall experience of one of the images presented on the display. A third mode is one of the calibration measurement modes illustrated in FIG. In this mode, both the select signal on select line 204 and the calibration signal on calibration line 206 are high for pixel 100. A measurement signal is actively driven on the first data line 110, and one calibration signal induced by the measurement signal is measured on the second data line 114. The measurement signal is provided relative to a threshold voltage of the drive transistor 102 such that the measured calibration signal can be analyzed to capture the threshold voltage of the drive transistor 102. Different embodiments of the measurement signal and the associated determination of the threshold voltage of the drive transistor 102 are further explained below. The threshold voltage of one pixel 100 can be determined using the first data line 110 and the second data line 114. Since the data lines 110, 114 can be shared by the adjacent pixels 100 (implemented as a first data line 110 for one pixel and as a second data line 114 for a second pixel), calibration measurements can be performed separately for adjacent pixels. Thus, a calibration measurement mode for a column may involve several operations of measuring the threshold voltages of the drive transistors 102 of different pixels 100 in the column. However, it is possible to simultaneously measure the threshold voltages of several pixels (even if not all of the pixels in a column), as will be further explained below. The calibration measurement mode can be performed for a number of pixels in a column. For all other columns, the signals on both select line 204 and calibration line 206 are low, such that one of the images of the previous frame is maintained on display 200. In order to adapt to the loss of the visual experience during the single frame of the calibration measurement, the intensity of one of the columns to be calibrated may be increased, for example, by 40%, in the frame before the calibration measurement and in the frame after the calibration measurement. . As can be appreciated from the above, the calibration measurement mode can provide calibration measurements for pixels 100 in a column. Therefore, the calibration measurement mode can be repeated several times to perform calibration measurements for all of the pixels 100 in all columns. A number of normal operating mode frames may pass between two subsequent frames in which calibration measurements are performed such that the visual experience of the images presented on display 200 is minimally affected. The calibration measurement mode can be used to determine the threshold voltage of the drive transistor 102 of each pixel 100 such that each pixel 100 can be calibrated to a particular threshold voltage of the drive transistor 102 of the pixel 100. This allows display 200 to compensate for threshold voltage variations in display 200. These changes can be compensated for by calibration measurements, allowing for high quality images to be presented on display 200. The threshold voltage of the drive transistor 102 may vary over time and may vary differently for different pixels 100, such as depending on the light output by each pixel 100, and thus, the calibration measurement mode may need to be performed at regular intervals. Although the calibration regeneration mode can be performed, for example, in one frame per minute, the calibration measurement can be performed every hour. The frequency of the calibration measurement can be set depending on the light output. If display 200 is driven to provide a bright output, the calibration measurements can be performed more frequently. The driving transistor 102 of the pixel 100 can undergo a bias stress effect, that is, a charge from a channel of the driving transistor to a semiconductor substrate, a gate dielectric or an interface between the semiconductor and the dielectric. One of the localized defect states is time-dependent. The trapped charge does not contribute to the current through the drive transistor 102, but affects the charge balance of one of the drive transistors 102. Thus, in use of the drive transistor 102, there may be a time dependent shift in threshold voltage due to bias stress. When one of the voltages at the driver gate 104 of the drive transistor 102 is below a threshold voltage, the channel that drives the transistor 102 is non-conductive, and the driver gate 104 and the calibration gate 106 act as two plates of a capacitor. Therefore, there is a capacitive coupling between the driver gate 104 and the calibration gate 106. When the voltage at the driver gate 104 of the drive transistor 102 is above a threshold voltage, the channel driving the transistor 102 is electrically conductive, and thus, the capacitance between the charge shield driver gate 104 and the calibration gate 106 in the channel. Sexual coupling. The measurement signal provided in the calibration measurement mode is configured to enable determination of the threshold voltage by identifying a change in capacitance between the driver gate 104 and the calibration gate 106. Referring now to Figure 6a, a voltage V across the driver gate 104 is illustrated. _GS A capacitive model of a pixel below the threshold voltage. In this model, it is assumed that the OLED capacitance is high enough that it is considered a short circuit for the frequency under consideration. As indicated in Figure 6a, there is a capacitive coupling C between the driver gate 104 and the calibration gate 106. _FGBG . When the voltage on the driver gate 104 is V _GS Above the threshold voltage, the driver gate 104 is shielded from the calibration gate 106 as illustrated in Figure 6b. In one embodiment, the measurement signal is provided from a linear sweep of one of a first voltage that is lower than one of the expected threshold voltages of the drive transistor 102 to a second voltage that is higher than one of the expected threshold voltages of the drive transistor 102. . The measured calibration signal can also be an increased signal, but increasing the slope of one of the measured calibration signals can change when the measurement signal crosses the threshold voltage of the drive transistor 102. When the driver gate 104 is shielded from the calibration gate 106, the measured calibration signal is increased by a parasitic capacitance C between the first data line 110 and the second data line 114. _N-N+1 Caused. Similarly, according to an alternative, the measurement signal can be provided from one of a first voltage that is higher than one of the expected threshold voltages of one of the driving transistors 102 to a second voltage that is lower than one of the expected threshold voltages of the driving transistor 102. Sexual sweep. The measured calibration signal can also be a reduced signal, but the reduced slope of one of the measured calibration signals can change when the measurement signal crosses the threshold voltage of the drive transistor 102. In another embodiment, the measurement signal provides a periodic change signal having a first frequency. For a first frequency below one of the maximum frequencies, the capacitive model shown in Figures 6a-6b is effective. The maximum frequency is one in which the charge in the channel can still shield one of the capacitive couplings between the driver gate 104 and the calibration gate 106. The maximum frequency (for example) is inversely related to the channel length of one of the driving transistors, and Bhoolokam et al. "Analysis of frequency dispersion in amorphous In-Analysis of amorphous In-Ga-Zn-O thin film transistors" Ga-Zn-O thin-film transistors) (Journal of Information Display, Vol. 16, No. 1, pp. 31-36 (2015)) discusses the determination of one of the maximum frequencies. The measured calibration signal can be analyzed to identify portions of the calibration signal to determine the threshold voltage of the drive transistor. The measured calibration signal can include a first harmonic having a portion of the measured calibration signal having the same frequency (ie, the first frequency) as the measurement signal. The measured calibration signal may also include a second harmonic or a third harmonic (ie, having a frequency that is one or two times the first frequency). The measurement calibration signal may further include even higher order harmonics, but the higher the order of the harmonics, the smaller the signal. This also implies that higher order harmonics can be more difficult to measure. Thus, although higher order harmonics may be used, the second harmonic and/or third harmonic may be preferred, and the use of the second harmonic and/or third harmonic is set forth in greater detail below. When the periodic change signal is relative to one of the threshold voltages, the DC voltage V _GS The first harmonic H when changing ₁ One of the amplitudes can be approximated as: (Equation 1) where C _Data(N+1) A capacitive coupling between the second data line 114 and ground, and A is the amplitude of the periodic signal applied. The first harmonic H when the periodic change signal changes with respect to one of the DC voltages above the threshold voltage ₁ One of the amplitudes can be approximated as: (Equation 2) Capacitive coupling between driver gate 104 and calibration gate 106 _FGBG Parasitic capacitance C between the data line and ground _N-N+1 Usually it can be small, and the A system measures the amplitude of the signal. This implies that it may be difficult to identify whether the DC voltage is above or below the threshold voltage and thus the threshold voltage from the first harmonic of the measured calibration signal. However, when a DC voltage close to one of the threshold voltages is provided and the measurement signal will oscillate across the threshold voltage, a second harmonic and a third harmonic can be identified in the measured calibration signal and can be used to determine the threshold voltage . When the equivalent measurement signal crosses the threshold voltage, the DC voltage level V _GS With threshold voltage V _T One of the differences between the ratios relative to the amplitude A of the measurement signal is less than one. In other words, (Equation 3) and . In such cases, one of the capacitive couplings between the driver gate 104 and the calibration gate 106 is ideally shielded, and the amplitudes of the first, second, and third harmonics are given by: (Equation 4) (Equation 5) (Equation 6) Therefore, if the measurement signal is supplied to cross the threshold voltage, the second harmonic and/or the third harmonic can be advantageously used to determine the threshold voltage. As is apparent from Equation eq. 5-6 above, the amplitudes of the second and third harmonics are independent of the parasitic capacitance between the data lines 110, 114 and are therefore unaffected by this parasitic capacitance. The amplitude and ratio of the second or third harmonic x ₀ The relationship between the two can be used to determine the threshold voltage. Figure 7 illustrates with x ₀ And the amplitude of the first harmonic, the second harmonic, and the third harmonic (as (ΔC) _FGBG /C _Data(N+1) A score of *A), where the effect of the parasitic capacitance is not included in the diagram of the first harmonic. By analyzing the DC voltage V for one of the measured signals _GS And the calibration signal measured by the amplitude A can determine x ₀ And, therefore, the threshold voltage of the drive transistor 102 can be retrieved. Analysis of the measured calibration signals can be performed in several different ways. For example, the applied measurement signal can be iteratively changed to change x ₀ . A maximum of one of the amplitudes of the second harmonic or a minimum of the third harmonic (or both) may be identified, which corresponds to x ₀ = 0. Therefore, it can be determined that the threshold voltage is equal to x ₀ DC voltage V used in the iteration of = 0 _GS . Thus, according to an embodiment, the iteration of the periodic variation signal relative to a constant signal is provided as a measurement signal, wherein the constant signal changes between iterations. According to an alternative, an iterative procedure is not required. Therefore, a measurement signal is provided as a periodic change signal with respect to a constant signal, and the threshold voltage can be directly determined. In this method, a ratio between the amplitude of the third harmonic and the amplitude of the second harmonic is used. As is clear from equation eq. 5-6, this ratio is given by the following equation: (Equation 7) Therefore, by determining the amplitudes of the second and third harmonics, the threshold voltage can be directly calculated as: (Equation 8) This implies that the variation of the threshold voltage can be compensated by changing the voltage on one of the calibration gates with respect to the voltage used during the calibration measurement. The change in voltage at the calibrated gate can therefore be given by: (Equation 9) If the voltage used during the calibration measurement and the change ΔV determined in eq. _BG The voltage that will be used at the calibration gate can be stored in a memory of control circuit 202 to store calibration data. It will be appreciated that other information may alternatively be stored to enable determination of the voltage to be applied to the calibration gate 106. Therefore, the change ΔV can be stored _BG , or even store the applied DC voltage V _GS The difference from the threshold voltage. If there is a capacitor C in the voltage swing of one of the applied measurement signals _FGBG For the other voltage dependence, the above equation eq. 7 can no longer be applied. Therefore, the use of a non-iterative method may not be possible because the threshold voltage determined may be incorrect. However, using an iterative method, the minimum of one of the amplitudes of the third harmonic can still be determined, and the V in the iteration in which the minimum is determined _GS =V _T Associated. Therefore, determining the threshold voltage may still be possible. As also discussed above, when applying the ideal shielding of the capacitive coupling between the driver gate 104 and the calibration gate 106, there is one of the first frequencies. For example, if the drive transistor 102 has a channel length of 10 μm and the applied DC voltage is 1 V, then a frequency of up to 5 MHz should be used as the first frequency. Around or above this maximum frequency, oscillations around the gate voltage of one of the threshold voltages will also be coupled to the calibration gate. Therefore, one of the measured calibration signals between the driver gate voltage higher than the threshold voltage and the driver gate voltage lower than one of the threshold voltages will become smaller, and thus, it may be more difficult to determine the threshold voltage. However, it is still possible to use a first frequency above one of the maximum frequencies. In Figure 8, one of the first harmonic response, the second harmonic response, and the third harmonic response for one of the 3 dB frequencies of the drive transistor is illustrated. As is apparent in FIG. 8, determining one of the maximum values of the second harmonic and/or the minimum of the third harmonic may still be possible, and thus, even using a frequency higher than the maximum frequency may allow the decision threshold. Voltage. The selection of one of the first frequencies to be used may take into account both the maximum frequency discussed above and the frequency of the noise source to avoid noise interference from such sources. For example, there may be ambient noise at frequencies of up to almost 100 kHz (eg, lights from around the display). In addition, charger noise and display noise can be as high as 100 kHz and can be as high as 500 kHz and above. In addition, measurement systems for capacitive touch can use frequencies from 100 kHz to 500 kHz to generate noise in this spectrum. Therefore, the first frequency can be chosen to be above 100 kHz, above 500 kHz or above 1 MHz in order to avoid noise interference. For example, the first frequency can be selected from one hundred kHz to 5 MHz or from one of 500 kHz to 5 MHz. In the above discussion, it has also been assumed that the OLED capacitance is sufficiently high for the frequency used so that the OLED can be considered as a short circuit. If the OLED capacitance is not large, it will affect the measured calibration signal. For a driver gate voltage below one of the threshold voltages, corresponding to (C ₁ *C ₂ ) / (C _Data(N+1) *C _OLED An additional signal of *A may be present in the measured calibration signal. Above the threshold voltage, one of the voltages at the OLED follows the driver gate voltage. Obtain a fraction C from the measured calibration signal ₂ /C _Data(N+1) . Even in this scenario, the second harmonic and the third harmonic are generated from below the threshold voltage across to above the threshold voltage. Again, the threshold voltage can be determined by iteratively determining one of the amplitudes of the amplitude of the third harmonic. The analytical equation used to calculate the threshold voltage also depends on one of the following assumptions: The OLED can be considered a short circuit for the frequency under consideration. Therefore, this assumption is based on the OLED having sufficient conductivity or a sufficiently high capacitance. Under normal conditions, the OLED will satisfy either full conductivity or a sufficiently high capacitance. In any case, even if the OLED will not satisfy any of the assumptions, from this perspective, it is more appropriate to perform an iterative procedure in which the DC voltage level is made V. _GS A change is made to identify when the amplitude of the third harmonic is minimal and to determine the threshold voltage based on this identification. As discussed above, the measurement signal in the calibration measurement mode is at a DC voltage level selected near one of the threshold voltages. _GS DC voltage level V below or around the threshold voltage _GS The iteration is done. This implies that the measurement signal hardly induces light output by the OLED 116. When a single iteration of the measurement signal is made, the DC voltage level can be selected to correspond to a highest possible or lowest possible threshold voltage. As indicated above, the ratio between the amplitude of the third harmonic and the second harmonic provides only a difference between the DC voltage level and the threshold voltage. Thus, by selecting the DC voltage level to correspond to an expected highest possible or lowest possible threshold voltage, it can be directly inferred that the determined difference corresponds to a voltage below the highest possible threshold voltage or above the lowest possible threshold voltage (whichever Used as one of the threshold voltages of the DC voltage level. Therefore, a calibration measurement can involve the following procedure. First, a DC voltage is applied to the first data line 110, wherein in one embodiment, the DC voltage corresponds to the highest possible threshold voltage, and in another embodiment, the DC voltage corresponds to the lowest possible threshold voltage. A DC voltage is then applied to the second data line 114 to provide a desired voltage at the calibration gate 106. The signals on select line 204 and calibration line 206 can then be high enough to turn on the gates of select transistor 108 and calibration transistor 112 to provide data on first data line 110 to driver gate 104 of drive transistor 102 and The data on the second data line 114 is provided to the calibration gate 106 of the drive transistor 102. The second data line 114 is then made high impedance and the calibration measurement can be initiated. A periodic change signal is now provided on the first data line 110 to provide an AC voltage at one of the first frequencies. One of the amplitudes of the AC voltage may correspond to twice the difference between the lowest possible threshold voltage and the highest possible threshold voltage. This implies that the voltage at the driver gate 104 will be varied above and below the threshold voltage such that a second harmonic and a third harmonic will be generated. In an embodiment, when the DC voltage is at the highest possible threshold voltage, the AC voltage will cause the driver gate voltage to be below the threshold voltage for voltages below zero. On the other hand, in an embodiment, when the DC voltage is at the lowest threshold voltage, the AC voltage will cause the driver gate voltage to be above the threshold voltage for voltages above zero. The second harmonic and the third harmonic can be determined in the measured calibration signal. Based on the determined amplitude of the second harmonic and the third harmonic, a corrected voltage of one of the calibration gates 106 can be calculated. The signal on select line 204 can then be turned low to turn off the gate of select transistor 108. A signal can then be actively provided on data line 114 for providing a calibration signal that corrects the voltage at calibration gate 106 of pixel 100. Finally, the signal on calibration line 206 can be turned low to turn off the gate of calibration transistor 112, and the next frame can be provided on display by driving display 200 in the normal mode of operation. Referring now to Figures 9-11, a drive architecture for providing a measurement signal and determining the measured calibration signal will be discussed. Control circuit 202 can include an oscillator 210 that can be used to generate both the measurement signal and the second and third harmonics. The signal from oscillator 210 can thus be provided to a first phase locked loop (PLL) 212 in which one of the frequencies provided by oscillator 210 is downconverted to one sixth of the oscillator frequency. This implies that the signals for the second and third harmonics can be generated by one third of the oscillator frequency and one-half of the oscillator frequency, respectively, so that the oscillator 210 can advantageously be used again. . The PLL 212 can provide modulation to output two different signals 214, 216 to adjacent pixels 100 on the two data lines 218a, 218b. The modulation may preferably be related to one of the phases of the signal, but alternatively an amplitude modulation may be used. In one embodiment, a second measurement signal 216 is phase shifted by 180 relative to a first measurement signal 214. This reduces overall external radiation and reflection at one end of the data line. Moreover, the capacitive coupling of adjacent pixels on the second data line 114 to the first data line 110 will be minimized because the second data line 114 can be coupled to the opposite signals on both sides of the pixel 100. In Figure 9a, the illustrated odd-numbered pixels in a column are simultaneously driven. Therefore, the first measurement signal is provided on a first data line 218a coupled to one of the first data lines 110 of the first pixel 100a of one of the columns, and is provided as a driver gate of the driving transistor 102 as the first pixel 100a. One of the poles 104 measures the signal. In addition, the second measurement signal is provided on a second data line 218b coupled to one of the first data lines 110 of the third pixel 100c in a column, and is provided as a driver gate of the driving transistor 102 as the third pixel 100c. One of the 104 measurements signals. Therefore, the measurement mode can be calibrated to simultaneously drive these odd pixels. The first data line 110 of the second pixel 100b in the column can also serve as the second data line 114 of the first pixel 100a. Therefore, the data line 114 is used to measure the calibration signal based on the measurement signal supplied from the data line 110 to the first pixel 100a. Thus, data line 114 can be coupled to an amplifier 220b to allow measurement of the calibration signal for first pixel 100a. Similarly, a second data line 114 of the third pixel 100c can be coupled to an amplifier 220d to allow measurement of the calibration signal for the third pixel 100c, which can also serve as the first data for the fourth pixel 100d. Line 110. In Figure 9b, the simultaneous driving of even pixels in a column is illustrated. Now, the first measurement signal is coupled to the first data line 110 of the second pixel 100b, and the second measurement signal is coupled to the first data line 110 of the fourth pixel 100d. The first data lines of the first pixel 100a and the third pixel 100c are now used to measure the calibration signal. Thus, as illustrated by Figures 9a-9b, all of the pixels in a column can be calibrated in two operations, where all odd pixels can be calibrated in a first operation and all even pixels can be in a second operation Perform calibration in . Referring now to Figures 10a-10d, one of the control circuits 202 for providing a measurement signal and measuring a calibration signal will be further explained. In Figure 10a, the components associated with pixels 100a-100d are shown as having connections that can be switched depending on the mode of operation of display 200 indicated by the dashed lines. In Figures 10b-10d, the connections used in the normal mode of operation and in the calibration measurement mode are shown. As shown in FIG. 10a, control circuitry 202 associated with a pixel can include a sampling latch 222, a holding latch 224, and a digital to analog converter (DAC) 226 that can be used to provide The digital signal of one of the desired light data output by the pixel 100 of the display 200 is converted into a corresponding analog signal that can be fed to one of the first data lines 110 of the pixel 100. Control circuitry 202 associated with a pixel may further include components for analog to digital conversion of a measured calibration signal. The DAC 226 can again be used to implement a continuous approximation analog to digital converter. Accordingly, control circuit 202 includes a comparator 228 that receives a portion of a measured analog signal and a signal from DAC 226. The output from comparator 228 can be provided to a holding latch 224 that can act as a continuous approximation register and provide an approximate digital code to one of the received analog signals to DAC 226. The control circuit 202 can further include: a band pass filter 230 for filtering a second harmonic or a third harmonic from the measured calibration signal; a mixer 232 for mixing the filtered signal with a The reference signal is provided by a PLL 234 that generates one of the second harmonic frequencies based on the oscillator frequency or a PLL 236 that produces a third harmonic frequency based on the oscillator frequency. Therefore, the mixer 232 can accurately capture the second harmonic or the third harmonic, which can be further separated from the mixer 232 by the second harmonic or the third harmonic One of the low pass filters 238. The low pass filter 238 can also perform one of the analog signal samples and hold to provide a constant signal to the comparator 228, which can be converted to digital form. Accordingly, control circuitry 202 associated with a pixel can be configured to capture a second harmonic or a third harmonic of one of the measured calibration signals and output the captured signal through sampling latch 222. In Figure 10b, the display 200 is driven in a normal mode of operation. Information from the DAC 226 of the control circuit 202 is driven to the data lines of each pixel 100 to output light from the pixels. In Figure 10c, the display 200 is illustrated in a calibration measurement mode for calibrating one of the odd pixels in a column. Therefore, the first measurement signal 214 is provided on the first data line 110 of the first pixel, and the second measurement signal 216 is provided on the first data line 110 of the third pixel. A calibration signal on the second data line 114 of the first pixel passes through amplifier 220b and is then further coupled to control circuit 202 associated with both the first pixel and the second pixel. The control circuit 202 associated with the first pixel receives the calibration signal and passes the calibration signal through a bandpass filter 230a for capturing a third harmonic. The mixer 232a associated with the first pixel then receives a signal from the bandpass filter 230a and a signal from the PLL 236 that produces a third harmonic frequency based on the oscillator frequency. Therefore, the control circuit 202 associated with the first pixel can extract a third harmonic signal from the measured calibration signal. The control circuit 202 associated with the second pixel also receives the calibration signal on the second data line 114 and passes the calibration signal through a band pass filter 230b for capturing a second harmonic. The mixer 232b associated with the second pixel then receives a signal from the bandpass filter 230b and a signal from the PLL 234 that produces a second harmonic frequency based on the oscillator frequency. Therefore, the control circuit 202 associated with the second pixel can extract a second harmonic signal from the measured calibration signal. Therefore, the second harmonic and the third harmonic extracted may be further transmitted to the analysis circuit for calculating a ratio between the amplitude of the third harmonic and the amplitude of one of the second harmonics to determine the threshold voltage, as above The article discusses. In Figure 10d, the display 200 is illustrated in a calibration measurement mode for calibrating one of the even pixels in a column. Here, the second and third harmonics are extracted and analyzed in the same manner as discussed above for the odd lines. However, now, the first measurement signal 214 is provided on the first data line 110 of the second pixel, and the second measurement signal 216 is provided on the first data line 110 of the fourth pixel. A calibration signal is received on the second data line 114 of the even pixels. Referring now to Figures 11a-11c, another embodiment for providing a measurement signal and measuring a calibration signal will be further explained. In this embodiment, the capacitive coupling from the driver gate 104 to the calibration gate 106 is equivalent to the capacitive coupling of the self-calibrating gate 106 to the driver gate 104. The measurement signal may be provided by the first data line 110 to the driver gate 104 or by the second data line 114 to the calibration gate 106. The calibration signal can then be measured on another data line. Therefore, the same data line can always be used to receive the calibration signal. The calibration measurement is repeated every four pixels. In Figure 11a, four pixels 100a-100d in one column are illustrated and the calibration measurements for the first pixel 100a and the fourth pixel 100d are illustrated. Here, the first measurement signal is provided on one of the first data lines 218a coupled to the first data line 110 of the first pixel 100a, and is provided on the driver gate 104 of the driving transistor 102 as the first pixel 100a. One of the measurement signals. In addition, the second measurement signal is provided on the second data line 218b coupled to the second data line 114 of the fourth pixel 100d, and is provided on the calibration gate 106 of the driving transistor 102 as the fourth pixel 100d. A measurement signal. Therefore, the measurement mode can be calibrated to simultaneously drive the first and fourth pixels in the column. The first data line 110 of the second pixel 100b in the column can also serve as the second data line 114 of the first pixel 100a. Therefore, the data line 114 is for measuring the calibration signal based on the measurement signal supplied from the first data line 110 to the first pixel 100a. Thus, data line 114 can be coupled to an amplifier 220 to allow measurement of the calibration signal for first pixel 100a. In addition, one of the first data lines 110 of the fourth pixel 100d can be coupled to an amplifier 220 to allow measurement of the calibration signal for the fourth pixel 100d, wherein the driver gate 102 of the driving transistor 102 of the fourth pixel 100d is driven. Get the calibration signal. The first data line 110 of the third pixel 100c (which also serves as the second data line 114 of the second pixel 100b) can be driven by a sufficiently high DC signal such that the second pixel 100b and the third pixel 100c drive the transistor 102. The capacitive coupling between the driver gate 104 of the drive transistor 102 that is electrically conductive and thus shields the pixels and the calibration gate 106. Therefore, the capacitive coupling between the gates in such pixels does not affect the calibration measurements of the first pixel 100a and the fourth pixel 100d. As illustrated, a first measurement signal 214 and a second measurement signal 216 can be used, wherein the second measurement signal 216 is phase shifted by 180 relative to a first measurement signal 214. This reduces overall external radiation and reflection at one end of the data line. In Figure 11b, calibration measurements for the second pixel 100b and the third pixel 100c are illustrated. Here, a measurement signal is provided on one of the first data lines 218a coupled to the first data line 110 of the third pixel 100c, and the first data line 110 also serves as the second data line 114 of the second pixel 100b. Therefore, the measurement signal is provided as a measurement signal on the driver gate 104 of the driving transistor 102 of the third pixel 100c, and is also provided on the calibration gate 106 of the driving transistor 102 as the second pixel 100b. A measurement signal. Therefore, the same measurement signal can be used to simultaneously drive the second and third pixels in the column in the calibration measurement mode. Similar to the measurement of the calibration signal of the first pixel 100a, the first data line 110 of the second pixel 100b in the column can be used again to measure a calibration signal, but at this time, the calibration of the second pixel 100b is measured. signal. In addition, the first data line 110 of the fourth pixel 100d (which also serves as the second data line 114 of the third pixel 100c) can be used to measure the calibration signal of the third pixel 100c. The first data line 110 of the first pixel 100a and the second data line 114 of the fourth pixel 100d can be driven by a sufficiently high DC signal, such that the channels of the driving transistor 102 of the first pixel 100a and the fourth pixel 100d are electrically conductive and The capacitive coupling between the driver gate 104 of the drive transistor 102 of these pixels and the calibrated gate 106 is thus shielded. Therefore, the capacitive coupling between the gates in such pixels does not affect the calibration measurements of the second pixel 100b and the third pixel 100c. In the calibration measurements of the second pixel 100b and the third pixel 100c, the same measurement signal can be used to perform calibration measurements of the two signals. However, one of the first measurement signal and the second measurement signal that are phase-shifted by 180° with respect to each other may be provided, and the first measurement signal and the second measurement signal are actively driven to one of the reception measurement signals. Every other data line (ie, the first measurement signal is provided to every eighth data line in the column of pixels). Thus, as illustrated by Figures 11a-11b, all of the pixels in a column can be calibrated in two operations, where each of the four pixels can be calibrated in a first operation, and every four pixels The remaining two can be calibrated in a second operation. Since the calibration signal is measured using the same data line, the control circuit 302 can be configured differently. In Figure 11c, the components associated with pixels 100a-100d are shown as having connections that can be switched depending on the mode of operation of display 200 indicated by the dashed lines. Control circuit 302 is not described in detail as control circuit 302 can function in a manner similar to control circuit 202 described above with respect to Figures 10a-10d. As shown in Figure 11c, there is no need to have an amplifier 220 associated with each data line, since the same data line is always used to measure the calibration signal. As shown above, it is possible to measure the threshold voltage of the drive transistor 102 of each pixel 100 in a display 200. The threshold voltage can be measured relative to a black display (the image is not present on the display) and relative to one of the images being rendered on the display. One of the threshold voltages from the two such calibration measurements can then be used to estimate one of the ground planes of the display 200. Thus, a first calibration measurement can be performed during activation of the active matrix display 200 prior to presenting a first image on display 200. Thus, the first calibration measurement can enable one of the gate-source voltages V on the driver gate 104 to be measured when no pixel 100 is active and thus no voltage drop can occur in the ground plane. _GS A difference from the threshold voltage of the drive transistor 102. A second calibration measurement relative to one of the images being presented on display 200 can then be performed immediately after the display is activated, such that it can be assumed that no other shift has occurred in the threshold voltage. The second calibration measurement can then allow the voltage on the driver gate 104 to be determined when the pixel 100 of the display is active. _GS The same difference from the threshold voltage of the drive transistor 102. Then, a difference between the first calibration measurement and the second calibration measurement may provide a source voltage V of the driving transistor 102 in the first calibration measurement and the second calibration measurement. _s One difference is attributable to the grounded resistive voltage drop. As illustrated in FIG. 12, a calibration measurement to estimate a voltage drop of one of the ground planes can be performed for several selected columns 304 of display 200. Therefore, calibration measurements need not be performed for all columns, as performing calibration measurements for all columns can be time consuming and thus affect one of the visual experiences of the images presented on the display. The measurements performed for several selected columns 304 can be used to determine the source voltage V of such columns 304. _s One of the quantized curves (and thus the grounded resistive voltage drop of such columns 304) is evaluated and one of the ground planes for the other columns in display 200 is estimated. For example, three columns 304 can be recalibrated in one of the frames being presented on display 200. This can be repeated several times to perform calibration measurements for several columns. The determined magnitude curve for the ground plane of the selected column 304 can also be used to estimate the magnitude curve across the ground plane of the entire display 200 (between selected columns 304). In the normal operating mode of display 200, the resistive voltage drop at one pixel can be V _S The respective estimated values are applied to one of the data values provided on the first data line 110 of the pixel 100 to compensate for the ground resistive voltage drop when the pixel 100 is driven. In the case of a normal OLED stack, as shown in Figure Ib, the ground is typically one of the OLEDs that is vapor deposited with the opposite electrode. The opposing electrodes are typically not patterned, which allows current to flow in all directions relative to the electrodes. Therefore, the gradient in the voltage drop curve of the ground plane can be averaged across the ground plane. This implies that measuring the ground magnitude curve on several selected reference columns would result in a good evaluation of one of the grounded resistive voltage drops across the entire display 200. In the case of an inverted OLED stack, as shown in FIG. 1a, the ground connection is typically implemented in the metal wiring of one of the TFTs of display 200. These wirings can be independent, and thus, if calibration of the ground plane is made relative to several ground wiring lines, one can make it difficult to evaluate one of the ground resistive voltage drop variations across one of the displays 200. Thus, the data lines 110, 114 of the display that are extendable along the rows of the array are preferably configured to be parallel to the ground wiring, which implies that the calibration of several selected columns of the display 200 is for each row (grounding along the ground It extends) to provide several reference points for the voltage drop. Therefore, a good evaluation of one of the overall voltage drops of the line is possible. If the ground wiring lines extend in both directions along the display 200 and along the row of the display 200, it may be even easier to evaluate the ground resistive voltage drop variation curve across the entire display 200. In the case of an inverted OLED stack, the ground resistive magnitude curve can alternatively be based on the actual expected current in each pixel (which is given by the information provided on the first data line 110 of each pixel) and each pixel The value of one of the resistors (where the resistance is known and stable) is estimated. If there is a ground wiring only in a direction perpendicular to one of the data lines, the ground resistance voltage drop can be determined. Voltage drop ΔV on the ground wire (and therefore the grounding curve) _n Can be used as pixel resistance R _m And pixel current I _k And the pixel k, m one of the double nested and calculated: . Referring now to Figure 13, a threshold voltage compensation method in an active matrix display will be briefly outlined. The method includes driving a display (step 402) in a calibration measurement mode to measure a threshold voltage of at least one of the pixels to achieve calibration of the at least one pixel 100. In the calibration measurement mode, a measurement signal is actively driven to one of the first data line 110 and the second data line 114, and the other of the first data line 110 and the second data line 114 of the pixel 100 One measures a calibration signal. The method further includes determining calibration data for the at least one pixel based on the measured calibration signal (step 404). Therefore, calibration data that can be used to compensate for threshold voltage variations of pixel 100 can be determined. The method further includes driving the display in a calibration renewed mode (step 406) to calibrate at least one pixel. In the calibration re-mode, calibration data can be provided on the second data line 114 to the calibration gate 106 of the drive transistor 102. Pixel 100 can be maintained in a calibrated state by driving the display in a calibration refresh mode. Thus, the display can be driven in a normal mode of operation wherein data for driving light output from each pixel can be provided on the first data line 110, wherein calibration of the pixels ensures that the desired output is received from the respective pixel. In the above, the inventive concept has been mainly explained with reference to a limited number of examples. However, it will be readily apparent to those skilled in the art that other examples, other than the examples disclosed above, are also within the scope of the inventive concepts as defined by the appended claims. Although the calibration measurement is primarily described above by driving one of the active measurement signals on the driver gate 104 and measuring one of the calibration signals on the calibration gate 106, the self-calibrating gate 106 to the driver gate The capacitive coupling of 104 should be equivalent to the capacitive coupling from the driver gate 104 to the calibration gate 106, and thus can be actively sensed by driving one of the calibration gates 106 and measuring the driver gate 104. Calibrate the signal to perform a calibration measurement.

100‧‧ ‧ pixels

100a‧‧‧first pixel/pixel

100b‧‧‧second pixel/pixel

100c‧‧‧ third pixel/pixel

100d‧‧‧ fourth pixel/pixel

102‧‧‧Drive transistor/transistor

104‧‧‧Drive gate

106‧‧‧ Calibration gate

108‧‧‧Select transistor/transistor

110‧‧‧First data line/data line

112‧‧‧ Calibrated transistor/transistor

114‧‧‧Second data line/data line

116‧‧‧Organic Luminescent Diodes

118‧‧‧First storage capacitor/storage capacitor/capacitor

120‧‧‧Second storage capacitor/storage capacitor/capacitor

200‧‧‧Active Matrix Display/Monitor

202‧‧‧Control circuit

204‧‧‧Selection line

206‧‧‧ calibration line

208‧‧‧Drive circuit

210‧‧‧Oscillator

212‧‧‧First phase-locked loop/phase-locked loop

214‧‧‧Signal/first measurement signal

216‧‧‧Signal/second measurement signal

218a‧‧‧data line/first data line

218b‧‧‧data line/second data line

220‧‧‧Amplifier

220b‧‧‧Amplifier

220d‧‧‧Amplifier

222‧‧‧Sampling latch

224‧‧‧ Holding latches

226‧‧‧Digital to analog converter

228‧‧‧ Comparator

230‧‧‧ bandpass filter

232‧‧‧mixer

234‧‧‧ phase-locked loop

236‧‧‧ phase-locked loop

238‧‧‧Low-pass filter

302‧‧‧Control circuit

304‧‧‧Selected columns/columns

A‧‧‧ amplitude

C _Data(N+1) ‧‧‧Capacitive coupling

C _{FGBG ‧‧‧Capacitive} coupling / capacitor

C _N-N+1 ‧‧‧Parasitic capacitance

V _GS ‧‧‧Voltage / DC voltage / DC voltage level / established DC voltage / applied DC voltage / selected DC voltage level / gate - source voltage

V _T ‧‧‧ threshold voltage

x ₀ ‧‧‧ ratio

The above and additional objects, features and advantages of the present invention will become more apparent from the description of the appended claims. In the drawings, similar component symbols will be used for similar components unless otherwise stated. 1a-1b are schematic diagrams of pixel topologies of an active matrix display. Figure 2 is a schematic diagram of one of the active matrix displays. 3-5 are diagrams illustrating driving a pixel in a normal operation mode, a calibration refresh mode, and a calibration measurement mode, respectively. Figures 6a-6b are schematic illustrations of one capacitive model of a pixel when the voltage across one of the driver transistors of the driver transistor is below a threshold voltage and above a threshold voltage. 7-8 are graphs illustrating one of a first harmonic, a second harmonic, and a third harmonic of a measured calibration signal for different frequencies of a measured signal. 9a-9b are schematic diagrams of a control circuit and respectively illustrate driving a display in a calibrated measurement mode for odd or even pixels, respectively. Figure 10a is a schematic illustration of one of the control circuits in accordance with one embodiment. Figures 10b-10d are schematic illustrations of the control circuit of Figure 10a and illustrate respectively driving the display in a normal mode of operation, in one of the calibration measurement modes for calibrating odd pixels and in one calibration measurement mode for calibrating even pixels. Figures 11a-11b are schematic illustrations of a column of pixels and illustrate driving the display in a calibrated measurement mode for both of the four pixels simultaneously. Figure 11c is a schematic illustration of one of the control circuits in accordance with one embodiment. Figure 12 is a schematic diagram showing one of the calibration measurements for ground resistive voltage drop compensation. Figure 13 is a flow diagram of one of the methods in accordance with an embodiment.

Claims (15)

A threshold voltage compensation method in an active matrix display (200), the display (200) comprising a plurality of pixels (100) configured to include a plurality of columns and an array of a plurality of rows, wherein one pixel comprises: a driving transistor (102) having a driver gate (104) and a calibration gate (106); a selection transistor (108) for selectively connecting a first data line (110) to the Driving the gate (104) of the transistor (102); a calibration transistor (112) for selectively connecting a second data line (114) to the calibration gate of the driving transistor (102) a pole (106), wherein the method comprises: driving (402) the display (200) in a calibration measurement mode to measure a threshold voltage of one of the at least one pixel (100) to achieve calibration of the at least one pixel (100) In the calibration measurement mode, one of the select transistors (108) of the at least one pixel (100) is turned on to connect the first data line (110) to the drive transistor ( 102) the driver gate (104), and one of the calibration transistors (112) of the at least one pixel (100) The second data line (114) is connected to the calibration gate (106) of the driving transistor (102), and a measurement signal is actively driven to the first data line (110) and the One of the second data lines (114), and on the other of the first data line (110) and the second data line (114), measuring a calibration signal based on the measured calibration Signaling to determine (404) calibration data for the at least one pixel (100); and driving (406) the display (200) in a calibration refresh mode to calibrate at least one pixel (100), wherein in the calibration re-mode a gate of the at least one pixel (100) of the selection transistor (108) is turned off to cause the first data line (110) and the driver gate (104) of the driving transistor (102) Disconnecting, and one of the calibration transistors (112) of the at least one pixel (100) is open to connect the second data line (114) to the calibration gate of the driving transistor (102) The pole (106), and on the second data line (114), provides the determined calibration data to the calibration gate (106) of the driver transistor (102). The method of claim 1, wherein the measurement signal has a periodic change signal of one of the first frequencies. The method of claim 2, wherein the measurement signal is varied relative to a constant signal, wherein the constant signal is selected based on a highest possible or lowest possible threshold voltage. The method of claim 2 or 3, wherein for the calibration signal, at least a second harmonic or a third harmonic relative to the first frequency is measured. The method of claim 1, wherein the threshold voltage is simultaneously measured for one of the pixel subgroups (100b, 100d) in a column, and wherein a first measurement signal (214) and a second measurement signal are provided (216) The second measurement signal (216) is phase-shifted by 180° with respect to the first measurement signal (214) such that the first measurement signal (214) is received on the first data line (110). One of the subset of pixels (100b, 100d) has an adjacent pixel among the subset of pixels (100b, 100d) that receives the second measurement signal (216). The method of claim 1, further comprising: storing the calibration data, and using the stored calibration data in the calibration regeneration mode. The method of claim 1, wherein the display (200) is driven multiple times in the calibration renew mode between two consecutive moments of driving the display (200) in the calibration measurement mode. The method of claim 1, wherein at least one pixel (100) in a single column is driven in the calibration measurement mode, and for all other columns, the selection transistor (108) and the calibration transistor (112) The gates are turned off to maintain an image of the previous frame on the display (200). The method of claim 1, further comprising: performing the calibration measurement mode for at least one column of pixels (100) with respect to a black display and with respect to one of the images being rendered on the display (200); and using calibration from One difference is measured to estimate a voltage drop across one of the ground planes of the display (200). The method of claim 9, wherein when the display (200) is driven in a normal mode to display an image, the data on the first data line (110) is compensated by the estimated voltage drop. An active matrix display (200) comprising: a plurality of pixels (100) configured to include an array of a plurality of columns and a plurality of rows, wherein a pixel (100) comprises: a driving transistor (102), It has a driver gate (104) and a calibration gate (106); a selection transistor (108) for selectively connecting a first data line (110) to the driver transistor (102) The driver gate (104); a calibration transistor (112) for selectively connecting a second data line (114) to the calibration gate (106) of the driving transistor (102); The first data line (110) and the second data line (114) disposed along one of the columns or one of the rows of the array, wherein each data line (110; 114) is along the edge The column or row of the array is coupled to the select transistors (108) of the pixel (100) such that the data line (110; 114) is coupled to the pixel on one side of the data line (110; 114) The selected transistors (108) of (100), and the calibrated transistors (112) connected to the pixels (100) on opposite sides of the data line (110; 114); and the control circuit (20) 2), which is connected to the data lines (110; 114), wherein the control circuit (202) is configured to be in the normal mode of the display (200) on the data lines (110; 114) Providing information for displaying an image, wherein the control circuit (202) is further configured to provide on the data line (110; 114) for calibration in a calibration refresh mode of the display (200) The calibration data is provided to calibration data of the calibration gate (106) of the one (100) of the drive transistor (102), and wherein the control circuit (202) is further configured to be on the display (200) In a calibration measurement mode, a measurement signal is provided to one of the first data line (110) and the second data line (114), and the first data line (110) and the second On the other of the data lines (114), a calibration signal is measured. The display of claim 11, wherein the control circuit (202) is configured to provide the measurement signal as a periodic change signal having a first frequency. The display of claim 12, wherein the control circuit (202) is configured to measure at least a second harmonic or a third harmonic relative to the first frequency for the calibration signal. The display of claim 13, further comprising an oscillator (210) for providing a frequency of the measurement signal and for providing the at least second harmonic or the One of the three harmonic reference frequencies. The display of claim 11 or 12, wherein the control circuit (202) includes a digital to analog converter (226) for each data line (110; 114), the digital to analog converter (226) being configured to An analog signal is provided when the display (200) is driven in the normal mode, and is configured as a component of a continuous approximation analog-to-digital converter when the display (200) is driven in a calibration measurement mode.