WO2012045874A1

WO2012045874A1 - Complementary logic circuits with self-adaptive body bias

Info

Publication number: WO2012045874A1
Application number: PCT/EP2011/067585
Authority: WO
Inventors: Senthil Kumar Jayapal
Original assignee: Stichting Imec Nederland
Priority date: 2010-10-07
Filing date: 2011-10-07
Publication date: 2012-04-12

Abstract

Complementary logic circuits with self-adaptive body bias Logic circuit comprising at least one logic gate implemented in complementary logic, each logic gate comprising at least one input node, an output node and a combination of at least one PMOS transistor and at least one NMOS transistor connected between the input and output nodes, the combination implementing an inverting logic function,the at least one NMOS transistor having a first body biasing node for receiving a first body bias for influencing the threshold voltage of the NMOS transistor. The first body biasing node of the at least one NMOS transistor is connected to the output node of the respective logic gate, such that the voltage present on the output node is used as first body bias for the at least one NMOS transistor.

Description

Complementary logic circuits with self-adaptive body bias Technical field

The present invention relates to logic circuits implemented in complementary logic, i.e. comprising at least one logic gate which comprises at least one input node, an output node and a combination of at least one PMOS transistor and at least one NMOS transistor connected between the input and output nodes, the combination implementing the complementary logic function of the gate.

Background art

Energy efficient computations are a primary concern in today's battery enabled ubiquitous computing portable devices. As we know, applications like autonomous wireless sensor nodes in which the minimum energy consumption is the main focus for extending the battery life time will opt for sub-threshold operation of transistors at the cost of severe performance penalty. Improving energy efficiency in the traditional way by lowering the supply voltage is limited because of the large portion of leakage power in the total power consumption, severe delay degradation and circuit failure at the very low supply voltages. However, the performance targets and proper circuit operation at lower supply voltage can be achieved by applying forward body bias (FBB) symmetrically to entire circuitry for high performance microprocessor applications, which is shown in Fig. 1. In this conventional approach, carefully designed external body bias circuitry is required.

In Narendra, Siva G. et. al., "Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique", ISSCC, Feb. 2004, vol.1 , pp. 156-518, a swapped-body bias approach has been proposed. However, the substantial active leakage power originating from the body-biased non-evaluation logic stages minimizes their effectiveness with the ultra-low supply voltages. For example, in a simple two-input NAND or two-input NOR gate with input vector "1 1 " or "00", only half of the logic devices are turned 'ON' for evaluation and the remaining devices reside in the steady state (turned 'OFF'). FBB lowers the threshold-voltage of non-evaluation devices, but it increases the overall power consumption due to unwanted sub-threshold leakage and source/drain-to-body junction leakage. In conventional static CMOS, the symmetrical FBB increases the unwanted active leakage power from non- evaluation logic stages.

US 2009/0224803 A1 discloses circuits with CMOS back gate biasing based on the non-inverted output node voltage. But this approach increases the power dramatically and has a performance penalty, as will be shown in the simulation results section herein.

Disclosure of the invention

It is an aim of the invention to provide a logic circuit which does not show at least one of the above mentioned drawbacks.

This aim is achieved according to the invention with the logic circuit of the first claim.

The invention provides a logic circuit comprising at least one logic gate implemented in complementary logic. Each logic gate comprises at least one input node, an output node and a combination of at least one PMOS transistor and at least one NMOS transistor connected between the input and output nodes, the combination implementing an inverting logic function. Examples of such "inverting" logic functions are NAND, NOR, NXOR, NOT, whereas AND, OR, XOR are examples of non-inverting logic functions. The NMOS transistor(s) of each logic gate comprise(s) a body biasing node which is connected to the output node of the respective logic gate. The body biasing node is provided for receiving a body bias for influencing the threshold voltage of the NMOS transistor(s). According to the invention, the voltage present on the output node of the respective logic gate is used as body bias for the NMOS transistor(s) of that logic gate.

In embodiments according to the invention, also each PMOS transistor has a body biasing node connected to the output node of the respective logic gate, so that all NMOS and PMOS transistors of the same logic gate receive the same body bias. Such embodiments are called "type I" circuits in this document.

In alternative embodiments according to the invention, each PMOS transistor has a body biasing node connected to a node of the circuit which is complementary to the output node of the respective logic gate, i.e. a node which during operation of the circuit carries a complementary output voltage complementary to the output voltage on the output node (e.g. a logic "1" vs. a logic "0" and vice versa). Such alternative embodiments are called "type II" circuits in this document.

Hence, two different types of body-biasing are introduced herein, in type-l the body biasing nodes of a PUN (pull-up network with PMOS transistors) as well as a PDN (pull-down network with NMOS transistors) of the same logic gate are connected to the output node of that logic gate. In type-l I , the body biasing nodes of the PDN are connected to the output node of that logic gate, while the body biasing nodes of the PUN are connected to a complementary internal node, complementary to the output node of that logic gate.

The invention further relates to a method for device threshold-voltage adjustment using the output voltage of each logic gate as body bias for at least the NMOS transistor(s) of that logic gate. This body bias is generated locally, on an internal node of the logic circuit, in particular the logic gate, and not globally by means of external body bias circuits. In this way extra circuitry can be omitted and circuit design can be simplified.

In embodiments according to the invention, the circuit is a precharge- evaluate logic circuit wherein each logic gate comprises a clock input node for receiving a clock signal defining a precharge phase and an evaluation phase. The body biasing nodes of the precharge and evaluate transistors are connected to a precharge node voltage. During the precharge phase, the evaluation transistors are forward body biased (to lower their threshold voltage) and the precharge transistors are kept less leaky (in a high-threshold state). During the evaluation phase, the low-threshold evaluation transistors make a faster transition (which improves performance). After finishing the transition the evaluation transistors are switched back to high-threshold state (low leakage) and the precharge transistors are switched back to the forward body bias state.

In embodiments according to the invention, the logic circuit is a CMOS circuit with PMOS pull-up networks (PUN) and NMOS pull-down logic networks (PDN). In such embodiments, the body biasing nodes of the transistors of both the pull-up and pull-down logic networks of each logic gate may be connected to the output node of that particular logic gate. This technique provides threshold- voltage adjustment of either the pull-up PMOS or the pull-down NMOS transistors based on the output node voltage. It can improve the performance due to low- threshold pull-up PMOS (pull-down NMOS) and maintains the pull-down NMOS (pull-up PMOS) in the high-threshold state.

In one embodiment, the transistors are double gate transistors such as FinFETs or planar transistors formed in SOI-substrate, wherein one gate is used for executing the logic function and the other gate is used as body biasing node for biasing the body of the transistor.

Brief description of the drawings

The invention will be further elucidated by means of the following description and the appended drawings.

Fig. 1 shows a prior art logic circuit with forward body bias applied by means of two external body bias circuits.

Fig. 2 shows a first example of a logic circuit according to the present invention, with output node body bias, in particular a static NAND gate with output inverter.

Fig. 3 shows a second example of a logic circuit according to the present invention with output node body bias, in particular a NAND-NOR-NAND chain.

Fig. 4A shows a third example of a logic circuit according to the present invention, in particular a static skewed two-input NAND gate.

Fig 4B shows a fourth example of a logic circuit according to the present invention, in particular a dynamic NAND gate followed by an output inverter, together forming a two-input AND gate. Fig. 5 shows a fifth example of a logic circuit according to the invention, in particular a dynamic NAND gate with output inverter.

Figures 6A-6D show embodiments according to the invention of a 2-input NAND gate with output inverter, implemented in respectively (A) type I static CMOS, (B) type I dynamic CMOS, (C) type II static CMOS, (D) type II dynamic CMOS.

Fig. 7 shows a graph comparing the speed of a thirteen-stage CMOS NAND-NOR delay chain with no body bias (NBB), inverted output body bias (IOBB), and non-inverted output body bias (NIOBB), for several supply voltages.

Fig. 8 shows a graph comparing the active energy per cycle for the same circuit as used in Fig 7, with no body bias, inverted output body bias, and non- inverted output body bias, for several supply voltages.

Fig. 9 shows a table with simulation results of the pre-charge delay, evaluation delay and average power consumption for a 2- and 3-input dynamic NAND gate, using non-body bias, output body bias type I, output body bias type II.

Fig. 10A shows another example of a static logic circuit according to the invention, implemented in Independent Double Gate (IDG) Finfet, in particular a static skewed NAND gate with output body bias type I.

Fig. 10B shows another example of a dynamic logic circuit according to the invention, implemented in Independent Double Gate (IDG) Finfet, in particular a dynamic NAND gate followed by an output inverter with output body bias type I.

Fig. 1 1 shows another example of a dynamic logic circuit according to the invention, implemented in Independent Double Gate (IDG) Finfet, in particular a dynamic NAND gate with output inverter, with output body bias type II.

Modes for carrying out the invention

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice of the invention.

Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. The terms are interchangeable under appropriate circumstances and the embodiments of the invention can operate in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. The terms so used are interchangeable under appropriate circumstances and the embodiments of the invention described herein can operate in other orientations than described or illustrated herein.

The term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It needs to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

Fig. 1 shows a prior art logic circuit, in particular a two-input NAND-gate, with forward body bias (FBB) applied to the transistors of the logic circuit. An NMOS body bias generation circuit 16 generates a body bias voltage Vbn for the NMOS transistors of the pull-down network PDN, 14 of the logic gate, and a PMOS body bias generation circuit 17 generates a body bias voltage Vbp for the PMOS transistors of the pull-up-network PUN, 12 of the logic gate. The logic NAND-gate 10 has two inputs A, 1 1 a and B, 1 1 b and one output Y, 12. A problem of such a scheme is that the body bias generation circuits 16, 17 and their routing require considerable additional silicon area, and additional design effort.

Embodiments of the invention can be seen as an intrinsic fine-grained self- adaptive body biasing in which the "inverting output node" voltage is used as bias voltage for at least the NMOS transistors, preferably also for the PMOS transistors. In embodiments of the invention, the speed versus energy efficiency can be improved compared to the prior art, without much design and area overhead.

As used herein, the output node of a logic gate which implements an inverting logic function is called the "inverting output node". A complementary node of the same circuit, for example the output node of a subsequent inverter stage, is called the "non-inverting output node". Using the inverting output node for body biasing a transistor of the same logic gate is herein called "inverting output body bias" (IOBB). Using a complementary node, complementary to the inverting output node, for body biasing a transistor of the same logic gate is herein called "non-inverting output body bias" (NIOBB).

As used herein, with "implementation in complementary logic" is meant that the logic gates comprise complementary pull-up and pull-down networks, comprising respectively at least one PMOS transistor and at least one NMOS transistor, connected in a way to implement the desired logic function. As shown in the figures, the PUN and PDN of each gate can be connected in series between the supply voltage VDD and ground GND, so that there is substantially no static power consumption.

In preferred embodiments according to the present invention, a fine- grained body bias circuit technique is proposed in which for each logic gate both the pull-up network, PUN, comprising one or more PMOS transistors, and the pull-down network, PDN, comprising one or more NMOS transistors, are body biased by the voltage of an output node of the logic gate. The technique can be applied to HVT (high threshold voltage) or SVT (standard threshold voltage) transistors. As the threshold potential of a gate moves inversely to its body potential, the functioning of the transistors can be influenced by adapting its bias voltage. The proposed method lowers the threshold voltage of either PUN or PDN based on non-precharge or precharge output node voltage, which depends on input vectors or precharge and evaluate phases respectively. When the positive output node voltage forward biases pull-down NMOS devices, the same voltage zero biases the pull-up PMOS devices and vice versa. It means that the respective PUN or PDN can maintain its high or standard threshold voltage state to keep the leakage current under control. Thus, this approach can improve the transition rate by lowering the threshold voltage and on the other hand, it can combat the leakage increase by maintaining the high or standard threshold state.

Fig. 2 shows a first example of a logic circuit according to the present invention. The left part of Fig 2 is a two-input NAND gate, the right part of Fig 2 is an inverter output stage NOT, together forming a two-input AND-gate. The inverting output node Yinv, 21 of the NAND stage is connected to the body biasing nodes of each NMOS-transistor T1 , T2 of the Pull-Down-network PDN and each PMOS transistor T3, T4 of the pull-up network PUN. The output 21 of the NAND gate is connected to the input of the inverter stage NOT, which has output Yn, 22. For the inverter stage NOT, the same bias principle is applied, i.e. the inverting output node (inverting for this stage) Yn, 22 is connected to the body biasing nodes of the NMOS transistor T5 and the body biasing node of the PMOS transistor T6.

The output Yinv, 21 is an inverting output for the NAND-gate. The node Yn, 22 is an inverting output for the NOT stage and a non-inverting output for the NAND stage. As shown, the body biasing nodes of the NMOS transistors and PMOS transistors of each inverting logic gate (i.e. each stage) are connected to the respective output nodes 21 , 22.

The proposed bias-method lowers the threshold voltage VT of either PUN or PDN of the logic gate, in this case the two-input NAND gate, based on the inverted output node voltage, in this case Yinv, 21 which depends on the input vectors A and B. A "high" output node voltage Yinv forward biases the pull-down NMOS devices T1 , T2, and zero biases the pull-up PMOS devices T3, T4. A "low" output node voltage Yinv forward biases the pull-up PMOS devices T3, T4, and zero biases the pull-down NMOS devices T1 , T2. As a result, the PUN or PDN can maintain its high or standard threshold voltage HVT, SVT state to keep the leakage current under control.

Fig. 3 shows a second example of a logic circuit using inverting output node body bias. This circuit has three logic stages, a first stage forming X3=NAND(in1 , in2), connected to a second stage forming Y3=NOR(X3, in3), connected to a third stage forming Z3=NAND(Y3, in4). This is an example of a more complicated logic circuit, for illustrating how the inverting outputs 31 , 32, 33 of each stage are respectively connected to the body bias nodes of the transistors of the respective stages.

The proposed bias-method is suitable for conventional static CMOS, but it is also ideally suited for precharge-evaluate logic families, as will be illustrated by examples of static skewed CMOS (e.g. Fig 4A) and domino logic circuits (e.g; Fig 4B), although the proposed bias-method may be applicable to other precharge- evaluate circuits as well. Skewed logic refers to fully complementary static pull-up and pull-down circuits in which the NMOS and PMOS transistor sizes are adjusted to make one of the transitions faster than the other. Like Domino gates, skewed gates operate in two phases like precharge and evaluate to obtain a monotonic transition at their gate output. During precharge, all the nodes are precharged to the initial state (VDD or GND) and the circuit performs the logic function during evaluation mode.

Fig. 4A shows an example of a static skewed two-input NAND gate. It has two inputs nodes for input vectors A, B and clock input nodes CLK in both PUN and PDN. As can be seen, the inverting output Y0, 41 is connected to the body bias nodes of all the NMOS and all the PMOS transistors of the NAND gate.

Fig 4B shows a dynamic NAND gate followed by an output inverter, thereby forming a two-input AND gate. If a NAND-function is desired instead of an AND-function, the output inverter can be omitted. The inverting output 42 of the NAND gate is connected to the bias nodes of the NMOS and PMOS transistors of the NAND gate, while the bias nodes of the NMOS and PMOS transistors of the output inverter are connected to the non-inverting output Y1 , 43 of the inverter stage.

The operation for both the circuits of Fig 4A and Fig 4B is as follows. Forward body bias (FBB) is applied to either PUN or PDN depending on evaluation transitions or input vectors. Precharge-evaluate logic circuits have two phases: a precharge phase when CLK is "low", "0" and an Evaluation phase when CLK is "high", "1 ". During the precharge phase, the body of evaluation logic device is pre-conditioned to the inverted output, i.e. the output of the logic gate, or precharge node voltage to establish a faster switching condition before the actual input arrives (High VT or Standard VT becomes Low VT). During the Evaluation phase, a faster evaluation transition occurs, after which the evaluation device returns to high (standard) threshold state after the evaluation transition to maintain low active-leakage power (Low VT becomes Standard VT or High VT). The precharge device will again be pre-conditioned after the evaluation transition. Thus in the Precharge Phase:

- CLK=0,

- Y0=0 becomes VDD (i.e. goes from 0 to VDD),

- PDN = FBB,

- PUN = NBB (no body bias = zero body bias).

In the Evaluate Phase:

- CLK=VDD,

- Y0= VDD becomes 0,

- PDN = FBB becomes NBB,

- PUN = NBB becomes FBB.

Fig. 5 shows a type-ll version of a dynamic two-input NAND gate with output inverter. It is a variant of the type-l circuit of Fig 4B, whereby the body biasing node of the PMOS transistor of the NAND gate is connected to the output Y1 , 52 of the output inverter stage, which is a non-inverting output for the NAND- gate. The NMOS transistors of the NAND gate are connected to the inverting output 51 of the NAND gate. In this case, the bias node of the NMOS transistor of the output inverter is connected to ground GND, while the bias node of the PMOS transistor of the output inverter is connected to the supply voltage VDD.

Figures 6A-6D shows an overview of several embodiments of a two-input NAND gate, with body-bias according to embodiments of the present invention. The NAND-gates in Figs 6A-6D are followed by an output inverter, thus actually forming a two-input AND gate, but as mentioned before, the output inverter of type-l circuits may be omitted.

The circuit of Fig 6A is implemented as a static CMOS with a type I connection of the bias nodes. Fig 6A is the same as Fig 2. As can be seen, the bias nodes of all NMOS and PMOS transistors of each stage, i.e. the NAND- stage (left) and the inverter stage (right) are connected to the inverting output 61 - 62 of the respective stage, i.e. the stage of which the transistors form part.

Fig 6B shows a two-input NAND gate implemented in dynamic CMOS, with a type I connection of the bias nodes. Note that for dynamic CMOS implementation, there is only one PMOS transistor in the pull-up network PUN of the logic gate. As can be seen, the bias nodes of all NMOS and PMOS transistors of each stage, i.e. the NAND-stage (left) and the inverter stage (right) are connected to the inverting output 63-64 of the respective stage, i.e. the stage of which the transistors form part.

Fig 6C shows a two-input NAND gate implemented in static CMOS with a type II connection of the bias nodes. The bias nodes of the NMOS transistors of the NAND gate are connected to the inverting output node 65 of the NAND gate. But the bias nodes of the PMOS transistors of the NAND gate are connected to the output node 66 of the inverter gate, which is a non-inverting output with respect to the inputs A, B. The bias node of the NMOS transistor of the output inverter is connected to ground GND in this case, while the bias node of the PMOS transistor of the output inverter is connected to the supply voltage VDD.

Fig 6D shows a two-input NAND gate implemented in dynamic CMOS, with a type II connection of the bias nodes, respectively for NMOS to the inverting output 67 and for PMOS to the non-inverting output 68. The embodiments of the invention can be further applied in double-gate devices (SOI, FinFETs). Fig. 10A shows an example of an Independent Double Gate (IDG) Finfet device, namely a static skewed NAND gate with output body bias type I according to embodiments of the present invention. As described before, in type I, the inverting output node 101 is connected to the bias nodes of all the NMOS and PMOS transistors of the logic gate. Operation of the circuit is as follows. In the Precharge Phase:

- CLK=0,

- Y0=0 becomes VDD,

- PDN = FBB,

- PUN = NBB (no body bias = zero body bias).

In the Evaluate Phase:

- CLK=VDD,

- Y0= VDD becomes 0,

- PDN = FBB becomes NBB,

- PUN = NBB becomes FBB.

Fig. 10B shows another example of an Independent Double Gate (IDG) Finfet device, namely a dynamic NAND gate followed by an output inverter with output body bias type I, according to the present invention. The bias nodes of the NMOS and PMOS transistors of the NAND gate are connected to the output node Y0, 102, which acts as an inverting output node of the NAND gate. The bias nodes of the NMOS and PMOS transistors of the output inverter are connected to the output node Y1 , 103 of the output inverter.

Fig. 1 1 shows another example of an IDG-Finfet device, namely a dynamic NAND gate, with inverter, with output body bias type II according to the present invention. The bias nodes of the NMOS transistors of the logic gate are connected to the inverting output node 1 1 1 , which acts as an inverting node of the logic gate, while the bias node of the PMOS transistor of the logic gate is connected to the output Y1 , 1 12 of the output inverter, acting as a non-inverting output node of the logic gate. Simulation results and discussion

From the above, it should be clear that the principle of applying inverted output body-bias can be applied to a wide range of logic circuits like static CMOS, skewed CMOS, dynamic Circuits and Differential Cascode Voltage Switch Pass Gate (DCVSPG), and is especially useful for supply voltages below diode cut-in voltages (VDD<0.6V).

The proposed biasing technique is verified with industrial standard 65nm low power CMOS technology and an eda simulator.

Fig 7 show the frequency and Fig 8 shows the active Power-Delay- Product (active energy) for a thirteen-stage CMOS NAND-NOR delay chain of Type-1 (inverted output body bias) in comparison to the conventional no body bias (NBB) schemes and non-inverted output node schemes (N-IOBB) as described in US 2009/0224803A1. The results are shown for supply voltages ranging from 0.2V to 0.5V in steps of 0.5V, which are sub-threshold voltages. In the case of non-inverted output delay chain, the active energy is increased significantly (see Fig 8, N-IOBB curve) without any performance benefits (see Fig 7, N-IOBB curve). This is due to the fact that the non-inverted output does not forward bias the pull-up or pull-down before or during a transition. In type-l (inverted output node) according to the present invention, the delay chain frequency compared to the conventional NBB scheme is improved moderately due to the use of SVT devices, however it further improves if HVT devices are used instead. The proposed bias technique lowers the threshold voltage VT of the logic devices before it makes transitions.

Fig. 9 shows a table with simulation results of the pre-charge delay, evaluation delay and average power consumption for a two-input dynamic NAND gate (as shown in Fig 6B and Fig 6D) and a three-input dynamic NAND gate, using non-body bias (classical), output body bias type I (present invention), and output body bias type II (present invention). For comparison, also the simulation results for the non-inverting body bias technique as described in US2009/0224803A1 are shown. The table of Fig 9 shows the precharge and evaluation delay, active power consumption for the conventional NBB (no body bias), inverted output body bias (IOBB) type-l and type-ll according to the present invention, and non-inverted output body bias (NIOBB) as a reference. From two-input NAND and three-input NAND dynamic gates, it is clear that the inverting body biasing technique (type-l and type-ll) improves both the precharge and evaluation delay at the cost of a moderate power increase mainly due to the increased bulk to substrate capacitance. The proposed inverting body biasing technique outperforms the body bias technique disclosed in US2009/0224803A1 , both in terms of delay and power consumption. The type-l two-input-NAND gate reduces both precharge and evaluation delay by 1.6X and 1.7X with 12% power increase as compared to the conventional NBB scheme. In type-ll, the evaluation delay is further reduced to 1.74X due to the precharge device connected to the non-inverted output node.

Similarly, in the three-input NAND gate, the type-l and type-ll improves the evaluation delay significantly by 1.55X and 1.7X compared to the conventional scheme, while the power is reduced.

In the technique of US 2009/0224803 A1 , the non-inverted output node of a two- and three-input NAND gate increase the active power consumption by 34% and 40.6% without any performance improvement, whereas the biasing technique according to embodiments of the present invention can improve both the precharge and evaluation delay with minimal increase in power consumption (as compared to the no body bias). Making one end of the transition faster by the inverted output node voltage gives substantial performance improvement with a minimal power penalty in the ultra low voltage regime (e.g. 0.2V-0.5V), which is highly energy efficient.

In-built forward body bias further has the advantage that it can minimize the process variations without adding much design complexity.

The embodiments according to the invention are generally applicable to CMOS complementary logic circuits with HVT or SVT transistors, as well as any double-gate complementary logic circuits with double-gate transistors such as SOI, FinFETs, or other.

Claims

1. Logic circuit comprising at least one logic gate implemented in complementary logic, each logic gate comprising at least one input node, an output node and a combination of at least one PMOS transistor and at least one NMOS transistor connected between the input and output nodes, the combination implementing an inverting logic function, the at least one NMOS transistor having a first body biasing node for receiving a first body bias for influencing the threshold voltage of the NMOS transistor, characterised in that the first body biasing node of the at least one NMOS transistor is connected to the output node of the respective logic gate, such that the voltage present on the output node is used as first body bias for the at least one NMOS transistor.

2. Logic circuit according to claim 1 , characterised in that the at least one PMOS transistor has a second body biasing node for receiving a second body bias for influencing the threshold voltage of the PMOS transistor, wherein the second body biasing node is connected to the output node of the respective logic gate, such that the voltage present on the output node is used as second body bias for the PMOS transistor.

3. Logic circuit according to claim 1 , characterised in that the at least one PMOS transistor has a second body biasing node for receiving a second body bias for influencing the threshold voltage of the PMOS transistor, wherein the second body biasing node is connected to a complementary node of the circuit which is complementary to the output node of the respective logic gate, such that the voltage present on the complementary node is used as second body bias for the PMOS transistor.

4. Logic circuit according to claim 3, characterised in that said at least one logic gate comprises a first logic gate of which the output node is an inverting output node and a second logic gate, as a subsequent stage of the first logic gate, of which the output node is a non-inverting output node, the second body biasing node of the at least one PMOS transistor of the first logic gate being connected to said non-inverting output node.

5. Logic circuit according to any one of the preceding claims, characterised in that the circuit is a precharge-evaluate logic circuit wherein each logic gate comprises a clock input node for receiving a clock signal defining a precharge phase and an evaluation phase and wherein the body biasing nodes of the NMOS and PMOS transistors of each logic gate are connected to the respective output nodes for receiving a precharge voltage during the precharge phase.

6. Logic circuit according to any one of the preceding claims, characterised in that the logic circuit is a CMOS circuit wherein the PMOS transistors form part of pull-up networks and the NMOS transistors form part of pull-down logic networks.

7. Logic circuit according to claim 6, characterised in that the body biasing nodes of the transistors of the pull-up and pull-down logic networks of each logic gate are connected to the output node of the respective logic gate.

8. Logic circuit according to any one of the claims 1 -5, characterized in that the transistors are double gate transistors, wherein one gate is provided for executing the inverting logic function and the other gate is provided for being used as the body biasing node for biasing the body of the transistor.

9. Logic circuit according to any one of the preceding claims, wherein the inverting logic function is chosen from the group consisting of NAND, NOR, NXOR, NOT.