KR20180051253A - Printed circuit board and method for manufacturing the same - Google Patents

Abstract

A printed circuit board is disclosed. The printed circuit board according to an aspect of the present invention includes an insulating layer; an upper conductor pattern layer and a lower conductor pattern layer individually formed on the insulating layer; and a via which includes a high melting point metal layer and a low melting point metal layer having a melting point lower than that of the high melting point metal layer, and penetrates the insulating layer to connect the upper conductor pattern layer and the lower conductor pattern layer. The low melting point metal layer contains 0.1 wt% or more and 1 wt% or less of carbon with respect to the total weight of the low melting point metal layer. It is possible to improve connection reliability between a conductor pattern layer and a via.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a printed circuit board (PCB)

The present invention relates to a printed circuit board and a method of manufacturing a printed circuit board.

Typically, a printed circuit board is produced by sequentially laminating a plurality of buildup layers on a core substrate. The production of the printed circuit board by sequentially stacking the build-up layers can be referred to as a sequential layer construction method.

When a printed circuit board is manufactured by a sequential lamination method, the number of lamination steps increases as the number of printed circuit boards increases. Such a lamination process may cause unnecessary and unpredictable deformation because heat is applied to a portion already existing in the lamination process. The more such deformation, the more difficult the interlayer matching becomes.

Accordingly, a batch lamination method has been developed in which a plurality of unit substrates are collectively laminated at the same time after the respective buildup layers are separated and produced as a unit substrate to produce a printed circuit board.

Korean Patent Publication No. 10- 2011-0066044 (June 16, 2011)

According to the embodiment of the present invention, a printed circuit board with improved connection reliability between the conductor pattern layer and the via can be provided.

1 shows a printed circuit board according to an embodiment of the invention.
2 illustrates a printed circuit board according to another embodiment of the present invention.
FIGS. 3 to 8 sequentially illustrate a process of manufacturing a unit substrate according to an embodiment of the present invention. FIG.
Figs. 9 and 10 are views showing the unit substrates laminated through Figs. 3 to 8 in a lump.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. In the specification, "on" means to be located above or below the object portion, and does not necessarily mean that the object is located on the upper side with respect to the gravitational direction.

In addition, the term " coupled " is used not only in the case of direct physical contact between the respective constituent elements in the contact relation between the constituent elements, but also means that other constituent elements are interposed between the constituent elements, Use them as a concept to cover each contact.

The sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for convenience of explanation, and thus the present invention is not necessarily limited to those shown in the drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like parts And redundant explanations thereof will be omitted.

Printed circuit board

(One embodiment)

1 is a view illustrating a printed circuit board according to an embodiment of the present invention.

1, a printed circuit board 1000 according to an embodiment of the present invention includes a conductive pattern layer 110, 210, 310, 410, 510, an insulating layer 120, 220, 320, V1).

Referring to FIG. 1, a plurality of conductor pattern layers 110, 210, 310, 410, and 510 are formed, but they are collectively referred to as conductor pattern layers when they are not required to be distinguished from each other. However, when it is necessary to distinguish between the conductor pattern layers 110, 210, 310, 410 and 510, the first conductor pattern layer 110, the second conductor pattern layer 210, the third conductor pattern layer 310, The conductor pattern layer 410 or the fifth conductor pattern layer 510 will be described. 1, the insulating layers 120, 220, 320, and 420 are collectively referred to as an insulating layer when a plurality of insulating layers 120, 220, 320, and 420 are not required to be distinguished from each other. However, the first insulating layer 120, the second insulating layer 220, the third insulating layer 320, or the fourth insulating layer 420 may be formed of the same material as the insulating layer 120, 220, 320, .

Each of the conductor pattern layers 110, 210, 310, 410 and 510 is formed to be spaced apart from each other. Each of the conductor pattern layers 110, 210, 310, 410, and 510 may include at least one of a signal pattern, a power pattern, a ground pattern, and an external connection terminal.

The conductor pattern layers 110, 210, 310, 410 and 510 may be formed of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium And may be formed of platinum (Pt).

The pattern shapes of the conductor pattern layers 110, 210, 310, 410, and 510 may be all the same, but may be formed differently depending on the design design.

Although FIG. 1 shows five conductive pattern layers 110, 210, 310, 410 and 510, this is only an example. The number of the conductor pattern layers 110, 210, 310, 410, and 510 applied to the present embodiment may be variously changed depending on design requirements and the like.

Each of the insulating layers 120, 220, 320 and 420 may include adjacent conductor pattern layers 110, 210, 310, 410 and 510 to electrically isolate adjacent conductor pattern layers 110, 210, 310, . For example, the first insulation layer 120 may include a first conductor pattern layer 110 and a fifth conductor pattern layer (not shown) so as to insulate the first conductor pattern layer 110 and the fifth conductor pattern layer 510, 510).

The insulating layer 120, 220, 320, 420 may include a photosensitive material. That is, the insulating layer 120, 220, 320, and 420 may be a photo-curable insulating resin containing a photosensitive material responsive to light.

When the insulating layers 120, 220, 320, and 420 are photocurable, the degree of curing of the insulating layers 120, 220, 320, and 420 may be controlled by light. However, the photo-curable insulating layers 120, 220, 320 and 420 are also thermosetting, and the degree of curing can be controlled by heat.

When the insulating layers 120, 220, 320, and 420 are photocurable, the insulating layers 120, 220, 320, and 420 may be subjected to a photolithography process, that is, an exposure and development process, without a separate photoresist. In this case, holes can be formed in the insulating layers 120, 220, 320, and 420 using a photolithography process. Therefore, the process can be simplified because a plurality of holes can be formed in any one of the insulating layers 120, 220, 320, and 420 at the same time. In addition, the shape of holes formed in the insulating layers 120, 220, 320, and 420 can be variously formed. For example, the shape of the vertical cross-section of the hole may be an inverted trapezoid, an orthogonal trapezoid, a rectangle, or the like.

The photocurable insulating layers 120, 220, 320 and 420 may be of a positive type or a negative type. If the insulating layer 120, 220, 320, 420 is of a positive type, the photopolymer polymer bond of the exposed portion is broken. Thereafter, when the developing process is performed, a portion where the photopolymer polymer bond breaks due to light is removed.

When the insulating layers 120, 220, 320 and 420 are of a negative type, the exposed portions cause a photopolymerization reaction to form a three-dimensional network structure of a chain structure in a single structure. When a developing process is performed, Unused parts are removed.

The insulating layers 120, 220, 320, and 420 may include an inorganic filler in the photocurable insulating resin. The inorganic filler improves the rigidity of the insulating layers 120, 220, 320 and 420. As the inorganic filler, silica (SiO ₂ ), alumina (Al ₂ O ₃ ), silicon carbide (SiC), barium sulfate (BaSO ₄ ), talc, clay, mica powder, aluminum hydroxide (AlOH ₃ ), magnesium hydroxide OH) ₂ ), calcium carbonate (CaCO ₃ ), magnesium carbonate (MgCO ₃ ), magnesium oxide (MgO), boron nitride (BN), aluminum borate (AlBO ₃ ), barium titanate (BaTiO ₃ ) and calcium zirconate ₃ ) may be used.

Each of the insulating layers 120, 220, 320 and 420 is included in the unit substrates 100, 200, 300 and 400 to be described later together with any one of the first to fourth conductive pattern layers 110, 210, 310 and 410. do. That is, unlike the sequential layering method, the insulating layers 120, 220, 320, and 420 are formed separately from each other and then laminated together at a time according to the embodiment of the present invention in which the printed circuit board is manufactured by the batch lamination method.

Each of the insulating layers 120, 220, 320, and 420 may fill any one of the first through fourth conductive pattern layers 110, 210, 310, and 410. That is, the first insulating layer 120 may fill at least a portion of the first conductor pattern layer 110. Each of the second to fourth insulating layers 220, 320 and 420 embeds the second to fourth conductive pattern layers 210, 310 and 410, respectively.

The fifth conductor pattern layer 510 is not buried in the insulating layers 120, 220, 320 and 420, unlike the first through fourth conductor pattern layers 110, 210, 310 and 410. This will be described in detail in a method for manufacturing a printed circuit board according to this embodiment, which will be described later.

Vias V1 pass through insulating layers 120, 220, 320 and 420 to connect adjacent conductor pattern layers 110, 210, 310, 410 and 510 to each other. For example, the via V1 is formed through the first insulating layer 120 to connect the adjacent first conductor pattern layer 110 and the fifth conductor pattern layer 510 with each other. The via V1 is formed through the second insulating layer 220 so as to connect the adjacent first conductor pattern layer 110 and the second conductor pattern layer 210 with each other.

The via V1 includes a low melting point metal layer 620 having a melting point lower than the melting point of the high melting point metal layer 610 and the high melting point metal layer 610.

The refractory metal layer 610 may include copper (Cu). By way of example, the refractory metal layer 610 may be formed of copper (Cu), but is not limited thereto. That is, the refractory metal layer 610 may be formed of Ag, Pd, Al, Ni, Ti, Au, or Pt, And an alloy including at least one of metals other than copper (Cu) and copper (Cu).

The low melting point metal layer 620 has a lower melting point than the melting point of the high melting point metal layer 610 and is formed between the high melting point metal layer 610 and the conductor pattern layers 110, 210, 310, 410 and 510. At least part of the low melting point metal layer 620 is melted when the unit substrates 100, 200, 300, 400, and 500 are stacked together. Accordingly, the low-melting-point metal layer 620 may be formed by a pressure nonuniformity between the conductor pattern layers 110, 210, 310, 410, and 510 generated during the laminating of the unit substrates 100, 200, 300, It is possible to prevent pressure unevenness between the pattern layers 110, 210, 310, 410, 510 and the refractory metal layer 610. Since the low-melting metal layer 620 is melted at least partially during the lamination, it is possible to easily form the inter-metallic compound 610 and / or the conductor pattern layer 110, 210, 310, , IMC) can be formed. The interlayer metal compound can improve the bonding force between the refractory metal layer 610 and / or the conductor pattern layers 110, 210, 310, 410 and 510 and the low melting point metal layer 620, 300, 400 and 500 can be improved.

The low melting point metal layer 620 may be made of a solder material. Here, 'solder' means a metal material which can be used for solder, and may be an alloy including lead (Pb), but may not contain lead. For example, the low melting point metal layer 620 may be an alloy of tin (Sn), silver (Ag), copper (Cu), bismuth (Bi) and indium (In) Specifically, the solder used in the embodiment of the present invention may be at least one of silver (Ag), copper (Cu), bismuth (Bi), and indium (In) ). ≪ / RTI >

The low melting point metal layer 620 contains 0.1 wt% or more and 1 wt% or less of carbon based on the total weight of the low melting point metal layer 620. The carbon contained in the low-melting-point metal layer 620 is derived from an organic compound contained in the tin-plated solution described later.

The low-melting-point metal layer 620 is formed through electrolytic plating, which is known as glossy plating, which can form a low-luminance. The low melting point metal layer 620 before the unit substrates 100, 200, 300, and 400 are stacked together has a surface roughness Ra of 0.1 m or less. Specifically, the low-melting-point metal layer 620 formed on any one of the first to fourth unit substrates 100, 200, 300, and 400 may be formed of a conductor pattern layer (not shown) of the other unit substrates 100, 200, 300, 110, 210, 310, and 410 are formed to have a roughness of 0.1 탆 or less.

The formation of voids between the conductor pattern layers 110, 210, 310, and 410 and the low melting point metal layer 620 is reduced by the formation of the low-melting-point metal layer 620 with a surface roughness of 0.1 μm or less. Accordingly, the reliability of bonding between the conductor pattern layers 110, 210, 310, and 410 and the low melting point metal layer 620 can be improved in the printed circuit board 1000 according to the present embodiment.

1, the printed circuit board 1000 according to the present embodiment includes a fourth conductor pattern layer 410 and / or a fifth conductor pattern layer 510 formed on the outermost layer to protect the fourth conductor pattern layer 410 and / And / or a solder resist layer formed on the fifth conductive pattern layer 510. [0034]

The solder resist layer may be formed with openings for exposing the external connection terminals of the printed circuit board 1000 according to the present embodiment to the outside. The solder resist layer may comprise a photosensitive material, in which case the opening may be formed through a photolithography process. Alternatively, the opening of the solder resist layer may be formed through laser drilling.

(Another embodiment)

2 is a view illustrating a printed circuit board according to another embodiment of the present invention.

2, a printed circuit board 2000 according to another embodiment of the present invention includes conductor pattern layers 110, 210, 310, 410 and 510, insulating layers 120, 220, 320, 420 and 520, And includes a first via V1 and a second via V2.

A printed circuit board 2000 according to an embodiment of the present invention and a printed circuit board 1000 according to an embodiment of the present invention are compared with each other because the second vias V2 are different. Meanwhile, the first via V1 applied to the present embodiment corresponds to the via V1 described in the embodiment of the present invention.

2, the second via V2 includes a first insulating layer 120 and a fifth insulating layer 520 to connect the adjacent first conductor pattern layer 110 and the fifth conductor pattern layer 510, As shown in FIG. The second vias V2 are formed in a three-layer structure unlike the first vias V1. That is, the first via V1 has a two-layer structure of the refractory metal layer 610 and the low melting point metal layer 620, while the second via V2 includes the refractory metal layer 610, the low melting point metal layer 620, And a melting point metal layer (610).

The refractory metal layer 610 and the low melting point metal layer 620 of the second via V2 have been described in the printed circuit board 1000 according to an embodiment of the present invention and therefore will not be described in detail.

The reason why the second vias V2 are formed in a three-layer structure is that the fifth unit substrate 500 includes the fifth insulating layer 520. Unlike the other unit substrates 100, 200, 300, and 400, the fifth unit substrate 500 has a fifth conductor pattern layer 510, which is different from the other unit substrates 100, 200, 300, As shown in FIG.

The description of the first to fourth insulating layers 120, 220, 320, and 420 described in the embodiment of the present invention is directly applied to the fifth insulating layer 520.

2, the second via V2 is formed on the first insulating layer 120 and the fifth insulating layer 520 so as to connect the first conductor pattern layer 110 and the fifth conductor pattern layer 510 to each other. But this is merely an example. That is, the second vias V2 may be formed in the first insulating layer 120 and the second insulating layer 220 to connect the first conductor pattern layer 110 and the second conductor pattern layer 210 to each other .

Unlike the printed circuit board 1000 according to the embodiment of the present invention, the printed circuit board 2000 according to the present embodiment can eliminate the process of forming the fifth conductor pattern layer 510 after collective lamination.

Manufacturing method of printed circuit board

3 to 10 are views sequentially illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention.

3 and 8 are views sequentially illustrating a process of manufacturing a unit substrate according to an embodiment of the present invention. FIGS. 9 and 10 are sectional views of FIGS. 3 to 8, Fig. 3 is a view showing the unit substrates manufactured through the above process.

3 to 10, a method of manufacturing a printed circuit board according to an embodiment of the present invention includes forming each of a plurality of unit substrates and stacking a plurality of unit substrates collectively.

The step of forming each of the plurality of unit substrates includes the steps of forming a conductor pattern layer, forming an insulating layer for embedding the conductor pattern layer, forming a refractory metal layer on the insulating layer, To form a metal layer.

Hereinafter, the step of forming the unit substrate and the step of laminating the unit substrates together will be described separately.

(Manufacturing Method of Unit Substrate)

FIGS. 3 to 8 are views sequentially illustrating steps of manufacturing a unit substrate, which is applied to a method of manufacturing a printed circuit board according to an embodiment of the present invention. 3 to 8 are views showing a manufacturing process of the fourth unit substrate including the fourth insulating layer and the fourth conductor pattern layer.

The description of the manufacturing process of the fourth unit substrate 400 is directly applied to the manufacturing processes of the first through third unit substrates 100, 200, and 300. Therefore, only the manufacturing process of the fourth unit substrate 400 will be described, and the manufacturing process of the first, second, and third unit substrates 100, 200, 300 will be omitted.

Unlike the first through fourth unit substrates 100, 200, 300, and 400, the fifth unit substrate 500 does not include an insulating layer but includes only a copper foil for forming a fifth conductor pattern layer. The copper foil for forming the fifth conductor pattern layer, which is the fifth unit substrate 500, is easy for an ordinary artisan, so a detailed description thereof will be omitted.

First, referring to FIG. 3, a carrier C having copper foil CF formed on both sides of a supporting film F is prepared. The copper foil CF can be pressed onto the support film F after being formed separately from the support film F. [ Alternatively, the copper foil CF may be formed on both sides of the support film F through copper plating. On the other hand, although not shown, the carrier C may further include a release layer formed between the support film F and the copper foil CF. The release layer allows the support film (F) and the copper foil (CF) to be easily separated when the support film (F) is removed from the fourth unit substrate (400).

Next, referring to FIG. 4, a fourth conductor pattern layer 410 is formed on the carrier C. As shown in FIG. The fourth conductor pattern layer 410 is formed by forming a plating resist in which a pattern of the fourth conductor pattern layer 410 is reversely formed on the copper foil CF and then plating the copper foil CF by electrolytic plating using the copper foil as a seed layer . After forming the fourth conductor pattern layer 410, the plating resist is removed from the copper foil CF. The plating resist may be formed through a photolithography process after forming a material for forming a plating resist on the entire upper surface area of the copper foil CF. The plating resist may be formed of a dry film, but is not limited thereto.

Although the method of forming the fourth conductor pattern layer 410 has been described by the so-called Modified Semi Additive Process (MSAP) method, it is also possible to form the fourth conductor pattern layer 410 by the subtractive method, the semiadaptive method or the pull additive method . In this case, a carrier having a structure different from that of the above-described carrier C may be used.

Although the process of forming the fourth conductor pattern layer 410 with reference to the upper surface of the carrier C has been described above, the present invention is not limited thereto. That is, the process for forming any one of the first through fourth conductor pattern layers 110, 210, 310, and 410 may be performed concurrently on the lower surface of the carrier C, if necessary. This is also applied to FIGS. 5 to 7, and only the upper surface of the carrier C will be described with reference to the following description.

5, a fourth insulating layer 420 is formed to fill at least a portion of the fourth conductive pattern layer 410, and a via hole H is formed in the fourth insulating layer 420. Referring to FIG. Since the fourth insulating layer 420 is photo-curable, the via hole H may be formed in the fourth insulating layer 420 through a photolithography process. Or the via hole H may be formed through laser drilling.

The fourth insulating layer 420 may be laminated on the carrier C using a vacuum laminator. However, since the fourth insulating layer 420 which has been laminated and subjected to the selective exposure process is not subjected to the post-curing process before the batch-laminating process, the semi-cured state (B-stage) is obtained. For example, the fourth insulating layer 420 having undergone the selective exposure process may have a degree of curing of 10 to 20% as compared with the fully cured state (C-stage). On the other hand, if necessary, the fourth insulating layer 420 may be semi-cured through a separate process so as to have a 50% curability relative to the fully cured state (C-stage). The separate semi-curing process may be performed using light used in the photolithography process for forming the via hole H. [ However, also in this case, the fourth insulating layer 420 is not completely cured before the batch-laminating process.

Next, referring to FIG. 6, a refractory metal layer 610 is formed on the fourth insulating layer 420. The refractory metal layer 610 may be formed through electrolytic plating. In the case of electrolytic plating, it includes both anisotropic and isotropic plating. The refractory metal layer 610 may be formed through copper electroplating to include copper (Cu). In forming the refractory metal layer 610 by electrolytic plating, the seed layer may be the fourth conductor pattern layer 410. Or the seed layer may be formed through a separate process other than the fourth conductor pattern layer 410. In the latter example, after forming the fourth conductor pattern layer 410, a seed layer is formed by electroless plating along the surface of the fourth conductor pattern layer 410, and a fourth insulating layer 420 is formed thereon can do.

Next, referring to FIG. 7, a low melting point metal layer 620 is formed on the high melting point metal layer 610. The low melting point metal layer 620 is formed such that the surface roughness Ra of the other surface opposite to the one surface contacting the high melting point metal layer 610 is 0.1 탆 or less. The low-melting-point metal layer 620 is generally called a glossy plating and is formed through electrolytic plating capable of low-luminance formation, so that the surface roughness Ra of the other surface can be formed to be 0.1 占 퐉 or less. In order to form such a low melting point metal layer 620, a tin plating solution containing tin and an organic compound is used.

The organic compound includes acetaldehyde. The acetaldehyde contained in the plating solution can lower the surface roughness of the low melting point metal layer 620. The organic compound may further include a sulfur-based compound. The sulfur-based compound may include one or more of thiourea and saccarine. The sulfur-based compound can lower the surface roughness of the low melting point metal layer 620 like acetaldehyde.

The concentration of the organic compound contained in the tin plating solution exceeds 100 ppm. The concentration of the organic compound in the conventional tin plating solution is several tens of ppm, whereas the concentration of the organic compound in the tin plating solution used in the method of manufacturing the printed circuit board according to the present embodiment exceeds 100 ppm. Therefore, the low-melting-point metal layer 620 has a relatively high content of carbon as compared with a conventional tin-plated layer. Specifically, the low melting point metal layer 620 contains 0.1 wt% or more and 1 wt% or less of carbon based on the total weight of the low melting point metal layer 620. This is in contrast to the conventional tin plating layer containing 0.1 wt% or less of carbon relative to the total weight of the tin plating layer.

Next, referring to FIG. 8, the fourth unit substrate 400 is manufactured by removing the carrier C from the fourth insulating layer 420. At this time, the support film F is firstly removed on the basis of the release layer formed between the copper foil CF of the carrier C and the support film F, and then the copper foil CF bonded to the lower surface of the fourth insulation layer 420 The fourth unit substrate 400 can be manufactured. However, for the rigidity of the fourth unit substrate 400, the copper foil CF can be removed immediately before the batch-laminating process.

 (Step of collectively laminating unit substrates)

Figs. 9 and 10 are views showing the unit substrates laminated through Figs. 3 to 8 in a lump.

Referring to FIG. 9, the unit substrates 100, 200, 300, 400, and 500 are vertically arranged to align with each other. At this time, the unit substrates 100, 200, 300, 400, and 500 are aligned with each other through alignment marks formed on the unit substrates 100, 200, 300, 400 and 500.

Next, referring to FIG. 10, a fifth conductor pattern layer 510 is formed after the unit substrates 100, 200, 300, 400, and 500 are bonded together. The unit substrates 100, 200, 300, 400, and 500 are collectively hot-pressed using a V-press laminator or the like.

In the batch lamination, the temperature may be set at 180 to 200 DEG C and the press pressure may be set to 30 to 50 kg / cm < 2 > , 420, or the components of the low-melting-point metal layer 620, and the like. In particular, the temperature at the time of laminating may be more than the melting point of the low melting point metal layer 620.

The low melting point metal layer 620 is melted to bond the neighboring first to fourth conductor pattern layers 110, 210, 310 and 410 and the fifth unit substrate 500 to each other. In this case, the low-melting-point metal layer 620 can spread toward the insulating layers 120, 220, 320, and 420 due to the pressure during the laminating process. Therefore, the upper cross-sectional area of the low melting point metal layer 620 and the lower cross-sectional area of the low melting point metal layer 620 may be different from each other.

The insulating layers 120, 220, 320, and 420 in the semi-cured state are in a fully cured state after the collective lamination.

The fifth conductor pattern layer 510 is formed by selectively etching the copper foil for forming the fifth conductor pattern layer which is the fifth unit substrate 500. An etching resist in which the pattern of the fifth conductor pattern layer 510 is reversed is formed on the copper foil 500 for forming a fifth conductor pattern layer 510 and then the copper foil 500 for forming the fifth conductor pattern layer is selectively etched, A pattern layer 510 may be formed. The etching resist is then removed.

Although not shown, a solder resist layer may be formed on the fourth conductor pattern layer 410 and / or the fifth conductor pattern layer 510, respectively. The solder resist layer may be formed by forming a solder resist on the entire surface of the fourth conductor pattern layer 410 and / or the fifth conductor pattern layer 510 and then forming the fourth conductor pattern layer 410 and / As shown in FIG.

The solder resist layer may be formed after the batch laminating process as described above, but may be laminated together with the unit substrates 100, 200, 300, 400, and 500 in the batch laminating process.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

C: Carrier
CF: Copper
F: Support film
H: Via hole
V1: 1st Via
V2: Second Via
100, 200, 300, 400, 500: unit substrate
110, 210, 310, 410, 510: conductor pattern layer
210, 220, 320, 420, 520: insulating layer
610: High melting point metal layer
620: Low melting point metal layer
1000, 2000: printed circuit board

Claims (9)

Insulating layer;
An upper conductor pattern layer and a lower conductor pattern layer respectively formed on the insulating layer; And
And a via hole penetrating the insulating layer so as to connect the upper conductive pattern layer and the lower conductive pattern layer, wherein the low melting point metal layer has a melting point lower than the melting point of the high melting point metal layer,
Wherein the low melting point metal layer contains 0.1 wt% or more and 1 wt% or less of carbon based on the total weight of the low melting point metal layer.
The method according to claim 1,
Wherein the low melting point metal layer comprises tin (Sn).
3. The method of claim 2,
The low-melting-
Further comprising at least one of silver (Ag), copper (Cu), bismuth (Bi), and indium (In).
The method according to claim 1,
Wherein the insulating layer comprises a photosensitive material.
Forming each of a plurality of unit substrates; And
And a step of collectively laminating the plurality of unit substrates,
Wherein forming the plurality of unit substrates comprises:
Forming a conductor pattern layer,
Forming an insulating layer for embedding the conductor pattern layer,
Forming a refractory metal layer on the insulating layer, and
And forming a low-melting-point metal layer on the high-melting-point metal layer, the low-melting-point metal layer having a surface roughness (Ra) of 0.1 mu m or less on the other surface opposite to the one surface contacting the high- melting- point metal layer.
6. The method of claim 5,
The low-melting-
(Sn) and an organic compound. 2. A method for manufacturing a printed circuit board, comprising the steps of:
The method according to claim 6,
Wherein the organic compound comprises acetaldehyde. ≪ RTI ID = 0.0 > 11. < / RTI >
8. The method of claim 7,
Wherein the organic compound further comprises a sulfur-based compound.
The method according to claim 6,
Wherein a concentration of the organic compound in the plating solution exceeds 100 ppm.

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