KR20180041309A - Display device and its driving method - Google Patents

Abstract

An embodiment of the present invention relates to a display device in which a residual image does not occur on a display panel and a driving method thereof. According to the present invention, a GIP drive part turns off a panel gate after an input voltage, a gate high voltage, and a gate low voltage are supplied during an initial driving period for generating power required for the GIP drive part. Therefore, supplying an abnormal voltage to gate lines on the display panel can be prevented during the initial driving period, thereby preventing a problem that a residual image occurs on the display panel.

Description

DISPLAY DEVICE AND ITS DRIVING METHOD [0002]

One example of the present invention relates to a display device and a driving method thereof.

BACKGROUND ART [0002] A lot of related technologies are being developed in the field of display devices for displaying visual information as images or images in an information society. The display device includes a display panel having a display area provided with pixels for displaying an image and a non-display area disposed at a periphery of the display area and not displaying an image, a gate driver for inputting a gate signal to the pixels, A timing controller (T-con) for inputting a signal for controlling a plurality of source drive ICs (hereinafter referred to as " IC "), a gate driver and a plurality of source drive ICs to be inputted, And a power management integrated circuit (hereinafter referred to as "PMIC") that generates input voltages required for driving.

The gate driver may be disposed on one side or both sides of the non-display area. In this case, the gate driver is formed in a separate integrated circuit form and is not connected to the pixels through the flexible films but is formed directly in the non-display region of the display panel together with the thin film transistor (TFT) Lt; / RTI > The gate driver of this type is defined as a GIP (Gate In Panel) driver. The GIP driver is composed of a shift register circuit including a gate pattern, a gate insulating portion, and a plurality of transistors having a source / drain pattern on a thin film transistor substrate. The GIP driver is connected to the gate line provided in the display region through the gate connection pattern.

An initial driving period for supplying the input voltage to the display device and then generating a power required by the GIP driver, and a normal driving period for charging the display panel. In this case, when the panel gate of the GIP driver is turned on due to an external voltage or the like in the initial driving period, the gate line on the display panel is turned on and a residual image is generated on the display panel.

An example of the present invention is to provide a display device in which no afterimages are generated on a display panel and a driving method thereof.

A display device according to an exemplary embodiment of the present invention includes a display panel for displaying an image, a GIP driver formed on a non-display area of the display panel, and an input voltage, a gate high voltage and a gate low voltage for driving the GIP driver, And a PMIC for supplying panel control signals for controlling the panel gate of the GIP driving unit during a normal driving period during which charging of the GIP driving unit is performed. The GIP driver of the present invention turns off the panel gate after the input voltage, the gate high voltage, and the gate low voltage are supplied during the initial driving period for generating a necessary power in the GIP driver.

A method of driving a display device according to an exemplary embodiment of the present invention includes: supplying an input voltage for driving a GIP driver; generating a gate low voltage; generating a gate high voltage; Turning off the panel gate during the initial driving period and supplying the panel control signals during the normal driving period in which the display panel is charged after the initial driving period to charge the display panel.

According to the display apparatus and the driving method thereof according to the present invention, the panel gate of the GIP driver is turned off during the initial driving period before the display panel is charged. Thus, it is possible to prevent the GIP driver from supplying an abnormal voltage to the gate lines on the display panel in the initial driving period, thereby preventing a problem that a residual image is generated on the display panel.

1 is a plan view of a display device according to an example of the present invention.
2 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention.
3 is a circuit diagram illustrating a GIP driver according to an exemplary embodiment of the present invention.
4 is a block diagram illustrating a GIP driver, a timing controller, and a power management integrated circuit according to an exemplary embodiment of the present invention.
5 is a waveform diagram of signals input to and output from the GIP driver according to an exemplary embodiment of the present invention.
6 is a flowchart of a method of driving a display device according to an embodiment of the present invention.

Brief Description of the Drawings The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the examples which are described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers and the like disclosed in the drawings for describing an example of the present invention are merely exemplary, and the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "first horizontal axis direction "," second horizontal axis direction ", and "vertical axis direction" should not be interpreted solely by the geometric relationship in which the relationship between them is vertical, It may mean having a wider directionality in the inside.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

Each of the features of the various examples of the present invention can be combined or combined with each other partly or entirely, and technically various interlocking and driving are possible, and each example can be independently performed with respect to each other, .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an example of the present invention. 1, the first horizontal axis direction X is a direction parallel to the gate lines, the second horizontal axis direction Y is a direction parallel to the data lines, and the vertical axis direction Z is a direction Thickness (or height) direction. A display device according to an exemplary embodiment of the present invention includes a display panel 110, a GIP driver 120, a source drive integrated circuit (IC) 131, a flexible circuit film 140, A timing controller 150, and a timing controller (T-con) 160.

The display device according to an exemplary embodiment of the present invention can be implemented in various ways such as a liquid crystal display, an electrophoresis display, and an organic light emitting display. Hereinafter, a case where the display device according to an exemplary embodiment of the present invention is a liquid crystal display device will be mainly described.

The display panel 110 includes a thin film transistor substrate 111, a counter substrate 112 and a counter substrate 112 between the thin film transistor substrate 111 and the counter substrate 112. In this case, And a liquid crystal layer interposed therebetween.

The thin film transistor substrate 111 includes a plurality of gate lines and a plurality of data lines arranged to cross each other.

The plurality of gate lines extend along the first horizontal axis direction X of the thin film transistor substrate 111 and extend at regular intervals along the second horizontal axis direction Y crossing the first horizontal axis direction X .

The plurality of data lines intersect the plurality of gate lines, extend long along the second horizontal axis direction Y, and are spaced apart at regular intervals along the first horizontal axis direction X. [

2 is a circuit diagram showing a pixel P according to an example of the present invention in detail. The pixels P are arranged at the intersections of the data lines DLj and the gate lines GLk, respectively. Each of the pixels P is connected to the data line DLj and the gate line GLk. Each of the pixels P includes a thin film transistor T, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, and a storage capacitor Cst. The thin film transistor T is turned on by the gate signal of the gate line GLk. The turn-on thin film transistor T supplies the data voltage of the data line DLj to the pixel electrode PE. The common electrodes CE are connected to the common line Lj and are supplied with a common voltage from the common line Lj.

Each of the pixels P drives the liquid crystal of the liquid crystal layer LC by an electric field generated by a potential difference between a data voltage supplied to the pixel electrode PE and a common voltage supplied to the common electrode CE. The arrangement of liquid crystals changes according to the presence or absence of an electric field and the intensity of an electric field, and the amount of light transmitted from the backlight unit can be adjusted. As a result, the pixels P can display an image having a gradation corresponding to the data voltage. The storage capacitor Cst is disposed between the pixel electrode PE and the common electrode CE. The storage capacitor Cst maintains a constant potential difference between the pixel electrode PE and the common electrode CE.

The common electrode CE is disposed on the counter substrate 112 in a vertical field driving system such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode. The common electrode CE is disposed on the thin film transistor substrate 111 together with the pixel electrode PE in a horizontal electric field driving method such as an IPS (In Plane Switching) mode or an FFS (Fringe Field Switching) mode. The liquid crystal mode of the display panel 110 may be implemented in any liquid crystal mode as well as the TN mode, the VA mode, the IPS mode, and the FFS mode described above.

The thin film transistor substrate 111 includes a display region DA and a non-display region. In the display area DA, the gate lines and the data lines are arranged to cross each other. The intersection regions of the gate lines and the data lines define a pixel region, respectively.

The non-display area is disposed at the outer periphery of the display area DA. More specifically, the non-display region means the remaining region of the thin film transistor substrate 111 excluding the display region DA. For example, the non-display region may be the upper, lower, left, and right edge portions of the thin film transistor substrate 111. The counter substrate 112 includes a black matrix, a color filter, and the like. The color filters may be disposed in openings that are not covered by the black matrix. When the display panel 110 has a color filter on TFT (COT) structure, the black matrix and the color filters may be disposed on the thin film transistor substrate 111.

An alignment film may be provided on each of the thin film transistor substrate 111 and the counter substrate 112 to attach a polarizing plate and set a pre-tilt angle of the liquid crystal. A spacer may be provided between the thin film transistor substrate 111 and the counter substrate 112 to maintain a cell gap of the liquid crystal layer.

Meanwhile, when the display device according to an exemplary embodiment of the present invention is an organic light emitting diode display, the counter substrate 112 is adhered to the TFT substrate 111 so as to serve as an encapsulating substrate for preventing penetration of oxygen or foreign substances do.

The GIP driver 120 generates a gate signal according to a gate control signal input from the panel driver and supplies the gate signal to the gate line. The GIP driver 120 according to an exemplary embodiment of the present invention is provided with a gate in panel (GIP) circuit in a non-display region of the TFT substrate 111.

The GIP circuit is embedded in the non-display region of the thin film transistor substrate 111 together with the transistor of the pixel. For example, the GIP driver 120 formed of a GIP circuit may be provided on one side and / or the other non-display area of the display area DA, but the present invention is not limited thereto. Any arbitrary And is provided in the non-display area.

Each of the plurality of source drive ICs 131 is mounted on the flexible circuit film 140 and receives the digital video data and the data control signal supplied from the timing controller 160 and outputs the digital video data to the analog data And supplies it to the data lines. When the source drive IC 131 is fabricated from a drive chip, each of the source drive ICs 131 may be mounted on the flexible circuit film 140 using a chip on film (COF) method or a chip on plastic (COP) method.

Each of the plurality of flexible circuit films 140 is attached to a pad portion provided on the thin film transistor substrate 111. At this time, each of the plurality of flexible circuit films 140 is attached to the pads using an anisotropic conductive film (ACF). Each of the plurality of flexible circuit films 140 supplies the data voltage supplied from the source drive IC 131 to the data line through the pad portion. At least one of the plurality of flexible circuit films 140 supplies a gate control signal supplied from the timing controller 160 to the GIP driver 120. [

The circuit board 150 is connected to a plurality of flexible circuit films 140. The circuit board 150 supports a plurality of circuits implemented with driving chips. For example, the timing controller 160 may be mounted on the circuit board 150. The circuit board 150 may be a printed circuit board or a flexible printed circuit board.

The timing controller 160 is mounted on the circuit board 150 and receives digital video data and timing synchronization signals (Timing Signal) from an external system board. Here, the timing synchronization signals include a vertical sync signal defining one frame period, a horizontal sync signal defining one horizontal period, a data enable signal indicating a valid data, ), And a dot clock (Dot Clock) which is a clock signal having a predetermined period.

The timing controller 160 generates a gate control signal for controlling the operation timing of the GIP circuit 120 and a data control signal for controlling the source drive ICs 131 based on the timing synchronization signals. The timing controller 160 supplies a gate control signal to the GIP driver 120 and a data control signal to the plurality of source drive ICs 131. [

3 is a circuit diagram showing a GIP driver 120 according to an exemplary embodiment of the present invention. The GIP driver 120 includes a first transistor 121, a second transistor 122, and a gate signal generator 123.

The first transistor 121 receives the VST signal VST as a gate terminal. The VST signal VST is a vertical start signal and controls the GIP driver 120 to simultaneously generate a plurality of gate signals within one frame. The first transistor 121 is turned off when the VST signal VST is at a high logic level. The first transistor 121 is turned on when the VST signal VST is at a low logic level.

The first transistor 121 is supplied with the input voltage Vin to the drain terminal. The input voltage Vin serves as a power source for the GIP driver 120 to drive. In addition, the input voltage Vin acts as a power source for a plurality of chips and ICs, and serves as a power source for the display device. The input voltage Vin is also referred to as an LCM (Liquid Crystal Module) power source in the case of a liquid crystal display device.

The first transistor 121 is supplied with the gate-low voltage VGL to the source terminal. The gate-low voltage VGL serves as a ground voltage or a reference voltage of the GIP driver 120. The gate-low voltage (VGL) becomes the lowest logic level of the gate signal.

The second transistor 122 is supplied with the gate high voltage VGH to the gate terminal. The gate high voltage VGH serves as a start signal for outputting gate signals in the GIP driver 120. [ Also, the gate high voltage VGH becomes the highest logic level of the gate signal.

The second transistor 122 is supplied with the input voltage Vin to the drain terminal. The second transistor 122 is supplied with the gate-low voltage VGL to the source terminal.

The gate signal generator 123 is connected to the drain terminal of the first transistor 121 and the drain terminal of the second transistor 122. The gate signal generator 123 receives the gate clock signal GCLKx.

The gate signal generator 123 generates gate signals GS1 to GSn based on the voltage at the drain terminal of the first transistor 121, the voltage at the drain terminal of the second transistor 122, and the gate clock signal GCLKx. . The gate signal generator 123 sequentially outputs the gate signals GS1 to GSn to the gate lines.

4 is a block diagram illustrating a GIP driver 120, a timing controller 160, and a power management integrated circuit (PMIC) 170 according to an exemplary embodiment of the present invention.

The GIP driver 120 receives the gate driver control signal GCS from the timing controller 160. The GIP driver 120 receives the input voltage Vin, the gate high voltage VGH, the gate low voltage VGL, the VST signal VST, and the gate clock signal GCLKx from the PMIC 170. The gate signal generator 123 sequentially outputs the gate signals GS1 to GSn to the gate lines.

The timing controller 160 supplies a gate driver control signal GCS to the GIP driver 120. [ The gate driver control signal GCS includes a gate masking signal GMA for masking the output of the gate signals GS1 to GSn and a gate enable signal GMA for starting the output of the gate signals GS1 to GSn GOE). Accordingly, the timing controller 160 can control whether the gate signals GS1 to GSn of the GIP driver 120 are output.

The PMIC 170 supplies the input voltage Vin, the gate high voltage VGH, the gate low voltage VGL, the VST signal VST and the gate clock signal GCLKx to the GIP driver 120. In addition, the PMIC 170 generates various kinds of power supply voltages used in chips and ICs in the display device and supplies them to power pins or power terminals of corresponding chips or ICs.

5 is a waveform diagram of signals input to and output from the GIP driver 120 according to an exemplary embodiment of the present invention.

The initial driving period A is a period for generating power required by the GIP driver 120. The initial driving period A includes the first period A1 to the fourth period A4.

The first period A1 is a period in which the input voltage Vin begins to be supplied. The remaining voltages maintain a low logic level state.

The second period A2 is a period in which the gate-low voltage VGL starts to be supplied. The gate-low voltage VGL is a voltage that sets the lowest logic level of the gate signals, and thus is a negative voltage having a negative magnitude. Therefore, when the gate low voltage VGL starts to be supplied, the gate low voltage VGL becomes a logic level lower than before the gate low voltage VGL is supplied.

The third period A3 is a period in which the gate high voltage VGH starts to be supplied. The gate high voltage VGH is a voltage that sets the highest logic level of the gate signals and is therefore a positive voltage having a positive magnitude. Therefore, when the gate high voltage VGH starts to be supplied, the gate high voltage VGH has a logic level higher than that before the supply.

The fourth period A4 is a period during which the panel gate of the GIP driver 120 is turned off after the input voltage Vin, the gate high voltage VGH, and the gate low voltage VGL are supplied.

When the panel gate of the GIP driver 120 is turned on due to the input voltage Vin, the gate high voltage VGH and the gate low voltage VGL in the initial driving period A, There is a problem that a residual image is generated on the display panel 110 due to the turn-on of the gate line. That is, the panel gate must be turned on after the normal driving period (B), but the afterglow occurs before the panel gate is turned on in an undesired period due to the external voltage and the display panel 110 displays an image do.

In the present invention, panel gates can be turned off using panel control signals. The panel control signals are signals generated by the PMIC 170 and input to the GIP driver 120, excluding power supply voltages. The panel control signals include the VST signal (VST) and the gate clock signal (GCLKx). When the panel gate is turned off in the initial driving period A, it is possible to solve the problem that a residual image on the display panel 110 occurs.

Specifically, the VST signal VST of the panel control signals is raised to a high logic level after the input voltage Vin, the gate high voltage VGH, and the gate low voltage VGL are supplied during the initial driving period A . That is, the VST signal VST can be raised to the high logic level in the fourth period A4.

The VST signal VST turns off the first transistor 121 in the GIP driver 120 when the VST signal VST is at a high logic level. Therefore, the VST signal VST can be raised to the high logic level in the fourth period A4 to turn off the first transistor 121. [ Accordingly, after the voltages necessary for driving the GIP driver 120 are supplied in the initial driving period A, the panel gate of the GIP driver 120 can be turned off.

Here, the high logic level during the initial driving period A of the VST signal VST is the third logic level V3 equal to the logic level of the normal driving period B of the VST signal VST. The VST signal VST maintains the first logic level V1 in the first section A1. In the second period A2, the second logic level V2 is lowered as the gate low voltage VGL and the second logic level V2 is maintained in the third period A3.

In order for the VST signal VST to have a logic level different from the logic level of the normal driving period B during the initial driving period A, a separate element or component must be added inside the circuit such as a voltage divider. However, in the present invention, the high logic level in the initial driving period A of the VST signal VST is set to be the same as the logic level of the normal driving period B of the VST signal VST, The panel gate of the GIP driver 120 can be turned off without adding a component.

In the present invention, the GIP driver 120 does not generate the DC voltage DC after the panel gate of the GIP driver 120 is turned off, that is, the fourth period A4. Since the first transistor 121 is turned off by the VST signal VST, the GIP driver 120 can not output the DC voltage. Further, it is also not possible to supply a DC voltage to the gate lines GS1 to GSn.

The DC voltage must not be supplied to the gate lines GS1 to GSn until the normal driving period B starts from the fourth section A4 to prevent the residual image on the display panel 110 due to the DC voltage. Therefore, the present invention can cut off the DC voltage which causes the residual image on the display panel 110 during the initial driving period (A).

Also, the present invention does not charge the display panel 110 until the gate clock signal GCLKx of the panel control signals rises to a high logic level. The gate clock signal GCLKx has the same logic level as the VST signal VST except that it maintains the second logic level V2 in the fourth section A4. That is, the gate clock signal GCLKx maintains a low logic level during the initial driving period A.

When the display panel 110 is charged while the gate clock signal GCLKx is maintained at the low logic level, a residual image due to the charged voltage may occur. Therefore, the present invention can prevent the problem that the afterimage due to the charged voltage is generated because the charging is not performed during the initial driving period (A).

The normal driving period B is a period during which the display panel 110 is charged or charged. To this end, the GIP driver 120 supplies gate signals to the gate line using panel control signals. Accordingly, the PMIC 170 supplies the VST signal VST and the gate clock signal GCLKx to the GIP driver 120 at a high logic level. When the conductor is made, the transistor T of the pixels on the display panel 110 is turned on and an image can be displayed.

6 is a flowchart of a method of driving a display device according to an embodiment of the present invention.

First, an input voltage Vin for driving the GIP driver 120 is supplied. As described above, the input voltage Vin is commonly referred to as an LCM (Liquid Crystal Module) power source in the liquid crystal display device. Therefore, it can also be expressed as a step of applying the LCM power. (S1 in Fig. 6)

Second, a gate-low voltage VGL is generated. The gate low voltage VGL is generated by the PMIC 170 and supplied to the GIP driver 120. [ (S2 in Fig. 6)

Third, a gate high voltage (VGH) is generated. The gate high voltage VGH is generated by the PMIC 170 and supplied to the GIP driver 120. (S2 in Fig. 6)

Fourth, the panel gate of the GIP driver 120 is turned off during the initial driving period A in which the GIP driver 120 generates necessary power. To this end, the PMIC 170 outputs a high logic level VST signal (VST) to turn off the panel gate of the GIP driver 120. (S4 in Fig. 6)

Fifthly, after the initial driving period A, the panel control signals are supplied during the normal driving period B in which the display panel 110 is charged to charge the display panel 110. As described above, the panel control signals include the VST signal VST and the gate clock signal GCLKx.

According to the display apparatus and the driving method thereof according to the present invention, the panel gate of the GIP driver is turned off during the initial driving period before the display panel is charged. Thus, it is possible to prevent the GIP driver from supplying an abnormal voltage to the gate lines on the display panel in the initial driving period, thereby preventing a problem that a residual image is generated on the display panel.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Accordingly, it should be understood that the above-described embodiments are illustrative and non-restrictive in every respect. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

110: display panel 111: thin film transistor substrate
112: counter substrate 120: GIP driver
121: first transistor 122: second transistor
123: Gate signal generator 131: Source drive IC
140: flexible circuit film 150: circuit board
160: timing controller 170: PMIC
DA: Display area

Claims (10)

A display panel for displaying an image;
A GIP driver formed on a non-display area of the display panel; And
And a PMIC for supplying panel control signals for controlling the panel gate of the GIP driver during an input voltage, a gate high voltage, a gate low voltage for driving the GIP driver, and a normal driving period in which the display panel is charged,
The GIP driver,
Wherein the panel gate is turned off after the input voltage, the gate high voltage, and the gate low voltage are supplied during an initial driving period for generating power required by the GIP driver. The method according to claim 1,
And the VST signal among the panel control signals is raised to a high logic level after the input voltage, the gate high voltage, and the gate low voltage are supplied during the initial driving period. 3. The method of claim 2,
Wherein the high logic level during the initial driving period of the VST signal is the same as the logic level during the normal driving period of the VST signal. The method according to claim 1,
Wherein the GIP driver does not generate a DC voltage after the panel gate is turned off. The method according to claim 1,
And does not charge the display panel until a gate clock signal of the panel control signals rises to a high logic level. Supplying an input voltage for driving the GIP driver;
Generating a gate low voltage;
Generating a gate high voltage;
Turning off the panel gate during an initial driving period for generating power required by the GIP driver; And
And supplying the panel control signals during a normal driving period during which the display panel is charged after the initial driving period to charge the display panel. The method according to claim 6,
And the VST signal among the panel control signals is raised to a high logic level after the input voltage, the gate high voltage, and the gate low voltage are supplied during the initial driving period. 8. The method of claim 7,
Wherein the high logic level during the initial driving period of the VST signal is equal to the logic level during the normal driving period of the VST signal. The method according to claim 6,
And the GIP driver does not generate a DC voltage after the panel gate is turned off. The method according to claim 6,
Wherein the display panel is not charged until a gate clock signal of the panel control signals rises to a high logic level.

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