KR20180036860A - Display device and display module - Google Patents

Abstract

Embodiments of the present invention relate to a display device and a display module. The display device comprises a driving voltage supply control circuit positioned between a driving voltage supply source and a display panel, and controlling a driving voltage output by the driving voltage supply source to be supplied to the display panel. Furthermore, the display device can quickly prevent the driving voltage from being supplied to the display panel when an error sensing signal related to a panel burnt situation occurs, thereby preventing a situation where the display panel is burnt.

Description

[0001] DISPLAY DEVICE AND DISPLAY MODULE [0002]

The embodiments relate to a display device and a display module.

2. Description of the Related Art [0002] With the development of an information society, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display device (LCD), a plasma display panel (PDP) Various display devices such as an organic light emitting display device (OLED) and the like are being utilized.

The display panel of the display device is driven by using a driving voltage, and a crack may be generated in the display panel, or a short circuit may occur, resulting in a situation where the display panel is burnt.

Therefore, a technique for detecting in advance the situation where the display panel is burned has been developed. However, even if the panel bang state is detected, the panel bang can not be substantially prevented if the driving voltage supplied to the display panel is not quickly blocked.

It is an object of the present embodiments to provide a display device and a display module which can quickly cut off a driving voltage supplied to a display panel when an error such as a panel bunt situation is detected.

In one aspect, the present embodiments include a display panel in which a plurality of subpixels are arranged and a driving voltage line for transmitting a driving voltage for driving a plurality of subpixels to a plurality of subpixels is arranged, And a driving voltage supply control circuit which is disposed between the driving voltage supply source and the display panel and controls supply of the driving voltage outputted from the driving voltage supply source to the display panel.

The driving voltage supply control circuit of the display device includes a first transistor electrically connected between the driving voltage supply source and the driving voltage line, and a second transistor electrically connected to the gate node of the first transistor, A second transistor electrically connected between a first voltage node to which a voltage is applied and a second transistor electrically connected between the driving voltage control node and a second voltage node to which the second voltage is applied, And a third transistor connected thereto.

According to another aspect of the present invention, there is provided a display panel comprising a display panel driven by a drive voltage, a power board outputting a drive voltage, a control printed circuit board supplying a drive voltage output from the power board to the display panel, A display board including a set board for outputting a power-off signal can be provided.

Such a display device may include a drive voltage supply control circuit for controlling supply of drive voltage to the display panel.

This drive voltage supply control circuit can interrupt the supply of the drive voltage before the error is detected, before the power off signal is output from the set board, or before the operation of the power board is turned off.

In another aspect, the present embodiments can provide a display module including a display panel driven by a drive voltage and a control printed circuit board for receiving a drive voltage and supplying the drive voltage to the display panel.

Such a display module may include a drive voltage supply control circuit for controlling supply of drive voltage to the display panel.

Such a drive voltage supply control circuit can cut off the supply of drive voltage to the display panel when an error is detected even if a drive voltage is supplied to the control printed circuit board.

According to the embodiments as described above, it is possible to provide a display device and a display module which can quickly cut off the driving voltage supplied to the display panel when an error such as a panel bunting situation is detected.

1 is a schematic system configuration diagram of a display apparatus according to the present embodiments.
2 is an exemplary view of a sub-pixel structure of a display device according to the present embodiments.
3 is another example of the sub-pixel structure of the display device according to the present embodiments.
4 is a system implementation example of the display device according to the present embodiments.
5 is a diagram showing a drive voltage transfer path in the display device according to the present embodiments.
6 is a diagram illustrating power cutoff in a panel bang state of the display apparatus according to the present embodiments.
FIG. 7 is a diagram illustrating a phenomenon in which power interruption is delayed after a panel bunt situation occurs in a display apparatus according to the present embodiments.
8 is a diagram showing a drive voltage control system of a display device according to the present embodiments.
Fig. 9 is an illustration of a drive voltage supply control circuit of the display device according to the present embodiments.
FIGS. 10 and 11 are diagrams showing that the driving voltage is instantly cut off when a panel bunt situation occurs by the driving voltage supply control circuit of the display device according to the present embodiments.
12 is an exemplary view of a drive voltage supply system of a display device according to the present embodiments.
FIG. 13 is a diagram illustrating an error detection unit transmitting an error detection signal to a driving voltage control circuit in the display device according to the present embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a schematic system configuration diagram of a display apparatus 100 according to the present embodiments.

Referring to FIG. 1, the display device 100 according to the present embodiment includes a plurality of data lines DL and a plurality of gate lines GL, and a plurality of data lines DL and a plurality of gate lines GL. A display panel 110 in which a plurality of sub pixels (SP) defined by a plurality of gate lines GL (GL) are arranged, a data driver 120 driving a plurality of data lines DL, A gate driver 130 for driving the data driver 120 and a controller 140 for controlling the data driver 120 and the gate driver 130, and the like.

The controller 140 supplies various control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130.

The controller 140 starts scanning according to the timing implemented in each frame, switches the input image data input from the outside according to the data signal format used by the data driver 120, and outputs the converted image data , And controls the data driving at a suitable time according to the scan.

The controller 140 may be a timing controller used in a conventional display technology or a control device including a timing controller to perform other control functions.

The controller 140 may be implemented as a separate component from the data driver 120, or may be implemented as an integrated circuit together with the data driver 120.

The data driver 120 drives the plurality of data lines DL by supplying data voltages to the plurality of data lines DL. Here, the data driver 120 is also referred to as a 'source driver'.

The data driver 120 may drive a plurality of data lines including at least one source driver integrated circuit (S-DIC).

Each source driver integrated circuit (S-DIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer .

Each source driver integrated circuit (S-DIC) may further include an analog to digital converter (ADC), as the case may be.

The gate driver 130 sequentially supplies the scan signals to the plurality of gate lines GL to sequentially drive the plurality of gate lines GL. Here, the gate driver 130 is also referred to as a " scan driver ".

The gate driver 130 may include at least one gate driver integrated circuit (G-DIC).

Each gate driver IC (G-DIC) may include a shift register, a level shifter, and the like.

The gate driver 130 sequentially supplies a scan signal of an On voltage or an Off voltage to the plurality of gate lines GL under the control of the controller 140.

When a specific gate line is opened by the gate driver 130, the data driver 120 converts the image data received from the controller 140 into an analog data voltage and supplies the data voltage to a plurality of data lines DL.

1, the data driver 120 may be located only on one side (e.g., on the upper side or the lower side) of the display panel 110, and in some cases, on the display panel 110 (E.g., the upper side and the lower side).

1, the gate driver 130 may be located only on one side (e.g., the left side or the right side) of the display panel 110, and in some cases, depending on the driving method, (E.g., the left side and the right side).

The controller 140 described above is capable of outputting various kinds of signals including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the input data enable signal (DE), and the clock signal (CLK) Timing signals from the outside (e.g., the host system).

The controller 140 receives a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal, and a clock signal to control the data driver 120 and the gate driver 130, And generates various control signals and outputs them to the data driver 120 and the gate driver 130.

For example, in order to control the gate driver 130, the controller 140 generates a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal GOE Gate Output Enable), and the like.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driver 130. The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE specifies the timing information of one or more gate driver ICs.

In order to control the data driver 120, the controller 140 may further include a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE) And outputs various data control signals (DCS: Data Control Signals).

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits constituting the data driver 120. The source sampling clock SSC is a clock signal for controlling sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driver 120.

The display panel 110 may be various types of display panels such as a liquid crystal display panel, an organic light emitting display panel, and the like.

When the display panel 110 is an organic light emitting display panel, each subpixel SP arranged in the display panel 110 includes an organic light emitting diode (OLED), an organic light emitting diode (OLED) And a driving transistor (driving transistor) for driving the organic EL element.

The types and the number of the circuit elements constituting each subpixel SP can be variously determined depending on the providing function, the design method, and the like.

2 is an exemplary view of a subpixel structure of the display device 100 according to the present embodiments.

Referring to FIG. 2, in the display device 100 according to the present embodiment, each sub-pixel SP basically includes an organic light emitting diode OLED, a driving transistor (not shown) for driving the organic light emitting diode OLED A switching transistor T1 for transmitting a data voltage to a first node N1 corresponding to a gate node of the driving transistor DRT; And a storage capacitor (Cst: Storage Capacitor) that holds the voltage for one frame time.

The organic light emitting diode OLED may include a first electrode (e.g., an anode electrode or a cathode electrode), an organic layer, and a second electrode (e.g., a cathode electrode or an anode electrode).

A base voltage EVSS may be applied to the second electrode of the organic light emitting diode OLED.

The driving transistor DRT drives the organic light emitting diode OLED by supplying a driving current to the organic light emitting diode OLED.

The driving transistor DRT has a first node N1, a second node N2, and a third node N3.

The first node N1 of the driving transistor DRT is a node corresponding to a gate node and may be electrically connected to a source node or a drain node of the switching transistor Tl.

The second node N2 of the driving transistor DRT may be electrically connected to the first electrode of the organic light emitting diode OLED and may be a source node or a drain node.

The third node N3 of the driving transistor DRT may be electrically connected to a driving voltage line DVL that supplies a driving voltage EVDD as a node to which the driving voltage EVDD is applied, Node or source node.

The driving transistor DRT and the switching transistor Tl may be implemented as an n-type or a p-type as illustrated in FIG.

The switching transistor T1 is electrically connected between the data line DL and the first node N1 of the driving transistor DRT and can be controlled by receiving the scan signal SCAN through the gate line to the gate node .

The switching transistor Tl may be turned on by the scan signal SCAN to transfer the data voltage Vdata supplied from the data line DL to the first node N1 of the driving transistor DRT.

The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

The storage capacitor Cst is not a parasitic capacitor (for example, Cgs or Cgd) which is an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor DRT, And is an external capacitor intentionally designed outside the driving transistor DRT.

On the other hand, in the case of the display device 100 according to the present embodiment, as the driving time of each sub-pixel SP becomes long, deterioration (degradation) of circuit elements such as the organic light emitting diode OLED and the driving transistor DRT Degradation can proceed.

Accordingly, inherent characteristic values of the circuit elements such as the organic light emitting diode (OLED) and the driving transistor (DRT) can be changed. Here, the intrinsic property value of the circuit element may include a threshold voltage of the organic light emitting diode OLED, a threshold voltage of the driving transistor DRT, a mobility of the driving transistor DRT, and the like.

A change in the characteristic value of the circuit element may cause a change in luminance of the corresponding subpixel. Therefore, the change in the characteristic value of the circuit element can be used in the same concept as the change in luminance of the subpixel.

In addition, the degree of change in the characteristic value between the circuit elements may be different depending on the degree of deterioration of each circuit element.

Such a difference in degree of characteristic value change between circuit elements may cause a deviation in characteristic value between circuit elements, resulting in luminance deviation between subpixels. Therefore, the characteristic value deviation between the circuit elements can be used in the same concept as the luminance deviation between the subpixels.

Variations in the characteristic values of the circuit elements (luminance variation of the subpixels) and characteristic deviations between the circuit elements (luminance deviation between the subpixels) cause problems such as degradation of the accuracy of luminance expressions of subpixels or occurrence of screen anomalies .

The display device 100 according to the present embodiments can provide a sensing function for sensing a characteristic value for a subpixel and a compensation function for compensating a subpixel characteristic value using a sensing result.

Sensing a characteristic value for a subpixel in this specification means sensing a characteristic value or a characteristic value change of a circuit element (a driving transistor DRT, an organic light emitting diode (OLED)) in a subpixel, DRT), and organic light emitting diode (OLED)).

In this specification, the compensation of the characteristic value for the subpixel means that the characteristic value or the characteristic value change of the circuit element (drive transistor DRT, organic light emitting diode (OLED)) in the subpixel is changed to a predetermined level, The transistor DRT, and the organic light emitting diode OLED) may be reduced or eliminated.

The display device 100 according to the present embodiments may include a compensation circuit including a sensing and compensation structure and a subpixel structure suitable for providing a sensing function and a compensation function.

3 is another example of the sub-pixel structure of the display device 100 according to the present embodiments.

The subpixel structure shown in FIG. 3 is an example of a suitable subpixel structure to provide a sensing function and a compensation function.

Referring to FIG. 3, each subpixel disposed in the display panel 110 according to the present exemplary embodiment includes, for example, an organic light emitting diode OLED, a driving transistor DRT, a switching transistor T1, and a storage capacitor Cst, and a sensing transistor T2.

3, the sensing transistor T2 is electrically connected between a second node N2 of the driving transistor DRT and a reference voltage line RVL for supplying a reference voltage Vref And may be controlled by receiving a sensing signal SENSE, which is a kind of a scan signal, to the gate node.

The voltage state of the second node N2 of the driving transistor DRT in the subpixel SP can be effectively controlled by further including the sensing transistor T2 described above.

The sensing transistor T2 is turned on by the sensing signal SENSE and applies a reference voltage Vref supplied through the reference voltage line RVL to the second node N2 of the driving transistor DRT.

Also, the sensing transistor T2 may be utilized as one of the voltage sensing paths for the second node N2 of the driving transistor DRT.

Meanwhile, the scan signal SCAN and the sense signal SENSE may be separate gate signals. In this case, the scan signal SCAN and the sense signal SENSE may be respectively applied to the gate node of the switching transistor Tl and the gate node of the sensing transistor T2 through different gate lines.

In some cases, the scan signal SCAN and the sense signal SENSE may be the same gate signal. In this case, the scan signal SCAN and the sense signal SENSE may be commonly applied to the gate node of the switching transistor Tl and the gate node of the sensing transistor T2 through the same gate line.

4 is a system implementation example of the display device according to the present embodiments.

Referring to FIG. 4, the data driver 120 may include at least one source driver integrated circuit (S-DIC).

Each source driver integrated circuit (S-DIC) is connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) Or may be disposed directly on the display panel 110, or may be integrated and disposed on the display panel 110 as occasion demands.

4, each of the source driver integrated circuits (S-DIC) includes a chip on film (COF) system (not shown) mounted on a film S-FL connected to the display panel 110 .

The gate driver 130 may include at least one gate driver integrated circuit (G-DIC).

Each gate driver IC (G-DIC) may be connected to a bonding pad of the display panel 110 by a tape automation bonding (TAB) method or a chip on glass (COG) ) Type, and may be directly disposed on the display panel 110, and may be integrated on the display panel 110 as the case may be.

In addition, each gate driver IC (G-DIC) may be implemented by a chip-on-film (COF) method, which is mounted on a film (G-FL) connected to the display panel 110.

The display device 100 according to the present embodiments includes at least one source printed circuit board (S-PCB) necessary for circuit connection to at least one source driver integrated circuit (S-DIC) And a control printed circuit board (C-PCB) for mounting control components and various electric devices.

At least one source driver integrated circuit (S-DIC) may be directly mounted on at least one source printed circuit board (S-PCB) or a film (S-DIC) on which at least one source driver integrated circuit (S- FL) can be connected.

The control printed circuit board (C-PCB) is provided with a controller 140 for controlling operations of the data driver 120 and the gate driver 130 and the like, and a display panel 110, a data driver 120, and a gate driver 130 ) Or the like, or a power controller for controlling various voltages or currents to supply or supply various voltages or currents.

The at least one source printed circuit board (S-PCB) and the control printed circuit board (C-PCB) may be circuitly connected via at least one connecting cable.

Here, the connection cable may be a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like.

At least one source printed circuit board (S-PCB) and a control printed circuit board (C-PCB) may be integrated into one printed circuit board.

4, the display panel 110, the data driver 120, the gate driver 130, the source printed circuit board (S-PCB) and the control printed circuit board (C-PCB) ).

Referring to FIG. 4, the control printed circuit board (C-PCB) may be connected to the power board (P-B / D) through a connection cable.

Various power sources may be present in the power board (P-B / D).

The power board P-B / D may be electrically connected to the set board S-B / D.

On the set board S-B / D, there may be a main controller for performing overall control of the display apparatus 100 and the like.

Often, the display module is manufactured by a panel manufacturer, and a display module is supplied from an electronic company, and the display device 100 can be manufactured by including a power board (P-B / D) and a set board (S-B / D).

5 is a view showing a drive voltage transfer path in the display device 100 according to the present embodiments.

5, the drive voltage EVDD is output from the drive voltage generator 510 in the power board PB / D and is supplied to the control printed circuit board C-PCB via the power board PB / D .

The driving voltage EVDD inputted to the control printed circuit board C-PCB is input to the power management integrated circuit (PMIC) 520 and output again in the power management integrated circuit 520 to the source printed circuit board S- (Not shown).

FIG. 6 is a diagram illustrating power cutoff in the panel bang state of the display device 100 according to the present embodiments. FIG. 7 is a timing chart of a power cutoff after the occurrence of the panel bang state of the display device 100 according to the present embodiments. Fig.

6, if there is a possibility that a panel bunt situation occurs in which the display panel 110 burns due to cracks, wiring shortage, or the like in the display panel 110, the control printed circuit board C-PCB) outputs the error detection signal (EDS) to the set board (SB / D).

The set board S-B / D recognizes the error detection signal EDS and outputs a power off signal to the power board P-B / D.

Thus, the power board P-B / D is subjected to the power-off processing.

Referring to FIG. 7, if the error detection signal EDS is recognized late on the set board S-B / D, the power-off signal may be outputted later and a part of the display panel 110 may be burned in between.

The following describes a method and circuit for enabling an immediate power-off upon occurrence of an error detection signal (EDS). Particularly, the driving voltage EVDD, which is one of the highest voltages among the power supplied to the display panel 110, will be described.

8 is a diagram showing a driving voltage control system of the display apparatus 100 according to the present embodiments.

8, the display device 100 according to the present embodiment includes a plurality of sub-pixels SP arranged and arranged to drive a driving voltage EVDD for driving a plurality of sub-pixels SP, A driving voltage supply source 810 for outputting a driving voltage EVDD, a driving voltage supply source 810 and a display panel 110, a display panel 110 for driving the display panel 110, And a driving voltage supply control circuit 800 for controlling the supply of the driving voltage EVDD output from the driving voltage supply source 810 to the display panel 110. [

The driving voltage supply source 810 may be, for example, a power management integrated circuit 520 or a power board (P-B / D).

FIG. 9 is an exemplary view of a drive voltage supply control circuit 800 of the display device 100 according to the present embodiments. FIG. 10 and FIG. 11 are diagrams showing drive voltage supply control of the display device 100 according to the present embodiments And the drive voltage EVDD is immediately shut off by the circuit 800 when a panel bunt situation occurs.

9, the driving voltage supply control circuit 800 includes a first transistor Q1 electrically connected between the driving voltage supply source 810 and the driving voltage line DVL, a first transistor Q1 electrically connected between the driving voltage control node A second transistor Q2 electrically connected between the gate node of the first transistor Q1 and the first voltage node NV1 to which the first voltage V1 is applied, A third transistor Q3 or the like which is controlled by the applied error detection signal EDS and is electrically connected between the driving voltage control node NC and the second voltage node NV2 to which the second voltage V2 is applied, .

With this simple circuit configuration, it is possible to immediately block the supply of the driving voltage EVDD to the display panel 110 when the error detection signal EDS is generated.

Referring to FIGS. 9 and 10, whether the driving voltage is supplied to the display panel 110 can be controlled according to the voltage state of the driving voltage control node NC.

The voltage state of the driving voltage control node NC is changed according to the error detection signal EDS so that the supply of the driving voltage to the display panel 110 can be effectively controlled.

9, in the driving voltage supply control circuit 800, the first transistor Q1 is a P-type transistor, and the second transistor Q2 and the third transistor Q3 are N-type transistors.

As described above, by designing the first transistor Q1 as a P-type transistor and designing the second transistor Q2 and the third transistor Q3 as N-type transistors, the first voltage V1 and the second voltage (V2) can be used as a ground voltage, and has an advantage that it can be used for driving voltage control without changing the signal level such as the error detection signal (EDS).

The first voltage V1 may be a turn-on level voltage that turns on the first transistor Q1. For example, when the first transistor Q1 is a P type, the first voltage V1 may be a ground voltage.

The second voltage V2 may be a turn-off level voltage that turns off the second transistor Q2. For example, when the second transistor Q2 is N type, the second voltage V2 may be a ground voltage.

The error detection signal EDS may have an error detection level voltage (e.g., a low level voltage) that indicates an error undetected state and an error detection level voltage (e.g., a high level voltage) that indicates an error detection state.

The drive voltage control node NC is activated when the error detection signal EDS changes from an error undetected level voltage (e.g., a low level voltage) to an error detection level voltage (e.g., a high level voltage) A high level voltage) to a second level voltage (e.g., a low level voltage).

As described above, the voltage state of the drive voltage control node NC that controls whether or not the drive voltage EVDD is supplied can be immediately changed in accordance with the level change of the error detection signal EDS.

The operation of the drive voltage control circuit 800 when an error such as a panel bunt situation is detected and an error is not detected will be described below.

The third transistor Q3 is turned off by the error undetecting level voltage of the error detection signal EDS applied to the gate node and the second transistor Q2 is turned off by the driving voltage control The first transistor Q1 is turned on by the drive voltage on control signal EVDD_ON_CON applied to the node NC and the first transistor Q1 is turned on by the first voltage V1 applied to the gate node through the second transistor Q2 And the driving voltage EVDD is supplied from the driving voltage supply source 810 to the display panel 110 according to the turn-on of the first transistor Q1.

The drive voltage control circuit 800 can normally supply the drive voltage EVDD to the display panel 110 when an error is not detected.

When an error is detected, the third transistor Q3 is turned on by the error detection level voltage of the error detection signal EDS applied to the gate node, and the second transistor Q2 is turned on through the third transistor Q3, And the first transistor Q1 is turned off according to the turn-off of the second transistor Q2 so that the driving voltage source 810 is turned off by the second voltage V2 applied to the display panel, The supply of the driving voltage EVDD to the driving transistor 110 can be blocked.

The drive voltage control circuit 800 can quickly cut off the drive voltage EVDD supplied to the display panel 110 when an error is detected.

The error detection level voltage can be maintained until the power supply voltage VDD of the display device 100 is turned off after the error detection signal EDS is changed from the error undetectable level voltage to the error detection level voltage.

By holding the error detection level voltage (e.g., a high level voltage) of the error detection signal EDS until the power supply voltage VDD is turned off, the error detection signal EDS can be recognized even late so that a countermeasure can be taken .

When the display panel 110 is an organic light emitting display panel, each subpixel SP in the display panel 110 includes an organic light emitting diode (OLED), an organic light emitting diode And a driving transistor DRT for driving the organic light emitting diode OLED.

The driving transistor DRT is controlled by the data voltage applied to the gate node and may be electrically connected between the first electrode of the organic light emitting diode OLED and the driving voltage line DVL.

The driving voltage supply control circuit 800 described above can control whether or not the driving voltage EVDD supplied to the organic light emitting display panel is supplied.

10 and 11, the set EVDD is a driving voltage EVDD supplied from the power board PB / D to the control printed circuit board C-PCB, and the module EVDD is driven by the driving voltage supply control circuit 800 And the drive voltage EVDD supplied from the control printed circuit board (C-PCB) to the display panel 110 is controlled. Set EVDD and Module EVDD are different representations of the position with the same drive voltage.

10 and 11, the module EVDD can be immediately shut off by the drive voltage on control signal EVDD_ON_CON.

Module EVDD does not have the same falling delay as set EVDD and does not apply the EVDD power until the drive voltage on control signal (EVDD_ON_CON) is input. Therefore, it can prevent the abnormal operation that may occur with EVDD residual voltage at turn on have.

Since the EVDD voltage input is controlled by the drive voltage on control signal (EVDD_ON_CON), it is possible to prevent abnormal operation that may occur due to the sequence reversal of the VDD voltage and the EVDD voltage.

10 and 11, the driving voltage control signal EVDD_ON_CON indicates the voltage state of the driving voltage control node NC.

FIG. 12 is an exemplary view of a drive voltage supply system of the display apparatus 100 according to the present embodiment. FIG. 13 is a diagram illustrating a display apparatus 100 according to the present embodiment in which the error detection unit 1300 controls the drive voltage And transmits an error detection signal (EDS) to the circuit (800).

12, the display device 100 according to the present embodiment includes a display panel 110 driven by a drive voltage EVDD, a power board PB / D for outputting a drive voltage EVDD, A control printed circuit board (C-PCB) for supplying a drive voltage (EVDD) output from the power board PB / D to the display panel 110, a set board SB for outputting a power- / D), and the like.

The display apparatus 100 according to the present embodiments may further include a drive voltage supply control circuit 800 for controlling supply of a drive voltage to the display panel 110. [

The drive voltage supply control circuit 800 outputs the drive voltage EVDD before the output of the power off signal from the set board SB / D or the operation of the power board PB / D is turned off, Can be cut off.

13, the driving voltage supply control circuit 800 receives the error detection signal EDS from the error detection unit 1300. [

Accordingly, the supply of the driving voltage EVDD can be cut off promptly when an error such as a panel burst is detected. As a result, the display panel 110 can be prevented from burning (panel bunching phenomenon) in advance.

On the other hand, the driving voltage supply control circuit 800 may be located on the control printed circuit board (C-PCB).

D and the set board SB / D by locating the drive voltage supply control circuit 800 on the control printed circuit board (C-PCB), which is a component included in the display module, The display module itself can perform drive voltage supply control.

The display module according to the present embodiment includes a display panel 110 driven by a drive voltage, a control printed circuit board (C-PCB) receiving a drive voltage EVDD and supplying the drive voltage EVDD to the display panel 110, And a drive voltage supply control circuit 800 for controlling the supply of the drive voltage to the panel 110. [

The drive voltage supply control circuit 800 controls the supply of the drive voltage module EVDD to the display panel 110 when an error is detected even if the drive voltage set EVDD is supplied to the control printed circuit board C- Can be blocked.

According to the above description, the display module itself can perform the drive voltage supply control without the help of the power board P-B / D and the set board S-B / D.

According to the embodiments as described above, there is an effect of providing a display device 100 and a display module which can quickly cut off a driving voltage supplied to a display panel when an error such as a panel bunting situation is detected.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device
110: Display panel
120: Data driver
130: gate driver
140: controller

Claims (11)

A display panel in which a plurality of subpixels are arranged and a driving voltage line for transmitting a driving voltage for driving the plurality of subpixels to the plurality of subpixels is disposed;
A drive voltage supply source for outputting the drive voltage; And
And a driving voltage supply control circuit which is located between the driving voltage supply source and the display panel and which controls supply of the driving voltage outputted from the driving voltage supply source to the display panel,
Wherein the driving voltage supply control circuit comprises:
A first transistor electrically connected between the driving voltage source and the driving voltage line;
A second transistor electrically connected between a gate node of the first transistor and a first voltage node to which a first voltage is applied, the gate node being electrically connected to the driving voltage control node; And
And a third transistor electrically connected between the driving voltage control node and a second voltage node to which the second voltage is applied, the third transistor being controlled by an error detection signal applied to the gate node. The method according to claim 1,
Wherein whether or not the drive voltage is supplied to the display panel is controlled according to a voltage state of the drive voltage control node. The method according to claim 1,
The first voltage is a turn-on level voltage that turns on the first transistor,
The second voltage is a turn-off level voltage that turns off the second transistor,
Wherein the error detection signal has an error detection level voltage indicating an error detection state and an error detection level voltage indicating an error detection state,
Wherein the drive voltage control node comprises:
When the error detection signal changes from the error non-detection level voltage to the error detection level voltage,
And the voltage state is changed from the first level voltage to the second level voltage. The method of claim 3,
When an error is detected,
The third transistor is turned off by an error undetecting level voltage of the error detection signal applied to the gate node,
The second transistor is turned on by a drive voltage on control signal applied to the drive voltage control node connected to the gate node,
The first transistor is turned on by the first voltage applied to the gate node through the second transistor,
And the driving voltage is supplied from the driving voltage supply source to the display panel in accordance with the turn-on of the first transistor. The method of claim 3,
When an error is detected,
The third transistor is turned on by an error detection level voltage of the error detection signal applied to the gate node,
The second transistor is turned off by the second voltage applied to the gate node through the third transistor,
The first transistor is turned off according to the turn-off of the second transistor,
Wherein supply of the driving voltage from the driving voltage supply source to the display panel is cut off. The method of claim 3,
Wherein the error detection signal comprises:
Wherein the error detection level voltage is maintained until the power supply (VDD) of the display device is turned off after the error detection level voltage is changed to the error detection level voltage. The method according to claim 1,
The first transistor is a P-type transistor,
And the second transistor and the third transistor are N-type transistors. The method according to claim 1,
Each subpixel in the display panel is a subpixel,
An organic light emitting diode,
And a driving transistor for driving the organic light emitting diode,
The driving transistor includes:
Wherein the organic light emitting diode is controlled by a data voltage applied to a gate node, and is electrically connected between the first electrode of the organic light emitting diode and the driving voltage line. A display panel driven by a driving voltage;
A power board for outputting the driving voltage;
A control printed circuit board for supplying the drive voltage outputted from the power board to the display panel;
A set board for outputting a power off signal in a power off state; And
And a drive voltage supply control circuit for controlling supply of the drive voltage to the display panel,
Wherein the driving voltage supply control circuit comprises:
And stops the supply of the drive voltage before outputting the power off signal from the set board or before the operation of the power board is turned off when an error is detected. 10. The method of claim 9,
And the driving voltage supply control circuit is located on the control printed circuit board. A display panel driven by a driving voltage;
A control printed circuit board for receiving the driving voltage and supplying the driving voltage to the display panel; And
And a drive voltage supply control circuit for controlling supply of the drive voltage to the display panel,
The driving voltage supply control circuit includes:
Wherein the supply of the driving voltage to the display panel is blocked when an error is detected even if the driving voltage is supplied to the control printed circuit board.

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