KR20180025523A - Display device - Google Patents

Abstract

The present invention provides a display device for preventing a short between pads due to a conductive ball of an anisotropic conductive film in a display panel. The display device of the present invention comprises: a display region on which multiple pixels and signal wires connected to the pixels are located in a substrate; and the pads located in a pad part outside the display region on the substrate, and connected to the signal wires. At least a part of the pads includes: first and second metal patterns separated at a predetermined interval in a surface direction of the substrate; and a third metal pattern connecting the first metal pattern and the second metal pattern via the substrate. Each of the first and second metal patterns includes first and second metal layers laminated in the thickness direction of the substrate with a gate insulating film interposed therebetween.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device including a repair area.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) that replaces bulky cathode ray tubes (CRTs). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED).

The display device includes a display panel and a drive IC for applying various drive signals to the display panel. The signal wiring of the display panel is connected to signal wirings of the drive IC through an anisotropic conductive film (ACF). The anisotropic conductive film is pressed through the tap bonding process, and the conductive ball in the anisotropic conductive film electrically connects the pad portion of the display panel and the flexible printed circuit board. However, depending on the amount and pressure of the anisotropic conductive film, the conductive ball of the anisotropic conductive film is pushed to the end of the pad portion to cause aggregation. As a result, a short phenomenon may occur between the pads of the display panel which must be electrically open.

The present invention provides a display device for preventing a shorting phenomenon between pads due to a conductive ball of an anisotropic conductive film in a display panel.

A display device according to the present invention includes a display area in which signal lines are connected to a plurality of pixels and pixels in a substrate, and pads disposed in a pad area outside the display area on the substrate and connected with the signal lines. At least some of the pads include first and second metal patterns spaced a predetermined distance in the plane direction of the substrate and a third metal pattern connecting the first metal pattern and the second metal pattern via the substrate. Each of the first and second metal patterns includes first and second metal layers stacked in a thickness direction of the substrate with a gate insulating film interposed therebetween.

The present invention has a repair region that can perform laser cutting inside the region where the conductive balls of the anisotropic conductive film are bundled, so that the repair region can be cut when the conductive balls are bundled.

The repair region includes only the metal layer immediately adjacent to the buffer layer, and can be easily removed by a laser process by a laser process.

1 is a schematic block diagram of an organic light emitting diode display.
2 is a first exemplary view showing a circuit configuration of a subpixel.
3 is a second example of a circuit configuration of subpixels
4 is a view showing a non-display region according to the present invention.
FIG. 5 is an enlarged view of the area A in FIG.
6 is a cross-sectional view taken along the line I-I 'in FIG.
7 and 8 are diagrams for explaining a shot phenomenon caused by the conductive balls.
Fig. 9 is a view for explaining a repair process for improving the shortage phenomenon.
10 is a view showing a pad portion according to another embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Although the present invention has been described with reference to an organic light emitting display, the technical idea of the present invention is not limited thereto. It is apparent that the present invention can also be applied to a liquid crystal display device, an electrophoretic display device, and the like.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is a first exemplary view showing a circuit configuration of a subpixel, and FIG. 3 is a second exemplary view showing a circuit configuration of a subpixel.

Referring to FIG. 1, the OLED display includes an image processing unit 10, a timing control unit 20, a data driving unit 30, a gate driving unit 40, and a display panel 50.

The image processing unit 10 outputs a data enable signal DE together with a data signal DATA supplied from the outside. The image processing unit 10 may output at least one of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of explanation. The image processing unit 10 is formed on the system circuit board in the form of an IC (Integrated Circuit).

The timing controller 20 receives a data signal DATA from a video processor 10 in addition to a data enable signal DE or a driving signal including a vertical synchronizing signal, a horizontal synchronizing signal and a clock signal.

The timing control unit 20 generates a gate timing control signal GDC for controlling the operation timing of the gate driving unit 40 and a data timing control signal DDC for controlling the operation timing of the data driving unit 30 based on the driving signal. . The timing control unit 20 is formed on the control circuit board in the form of an IC.

The data driver 30 samples and latches the data signal DATA supplied from the timing controller 20 in response to the data timing control signal DDC supplied from the timing controller 20 and converts the sampled data signal into a gamma reference voltage . The data driver 30 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 30 is mounted on the substrate in an IC form.

The gate driving unit 40 outputs the gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing control unit 20. [ The gate driver 40 outputs a gate signal through the gate lines GL1 to GLm. The gate driver 40 is formed on the gate circuit board in the form of an IC or is formed on the display panel 50 in a gate in panel manner.

The display panel 50 displays an image corresponding to the data signal DATA and the gate signal supplied from the data driver 30 and the gate driver 40. The display panel 50 includes subpixels SP for displaying an image.

Referring to FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a compensation circuit CC, and an organic light emitting diode (OLED). The organic light emitting diode OLED operates to emit light in accordance with the driving current generated by the driving transistor DR.

The switching transistor SW is operated so that the data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor in response to the gate signal supplied through the first gate line GL1. The driving transistor DR operates so that a driving current flows between the high potential power supply line VDD and the low potential power supply line GND in accordance with the data voltage stored in the capacitor. The compensation circuit CC is a circuit for compensating the threshold voltage and the like of the driving transistor DR. Also, the capacitor connected to the switching transistor SW or the driving transistor DR may be located inside the compensation circuit CC.

The compensation circuit CC consists of one or more thin film transistors and a capacitor. The configuration of the compensation circuit CC varies greatly depending on the compensation method, and a detailed illustration and description thereof will be omitted.

In addition, as shown in FIG. 3, when the compensation circuit CC is included, the sub-pixel further includes a signal line and a power supply line for supplying a specific signal or power, as well as driving the compensating thin film transistor. The added signal line may be defined as a 1-2 gate line GL1b for driving the compensating thin film transistor included in the subpixel. The added power supply line may be defined as an initialization power supply line (INIT) for initializing a specific node of the subpixel to a specific voltage. However, this is merely one example, but is not limited thereto.

In FIGS. 2 and 3, the compensation circuit CC is included in one sub-pixel. However, the compensation circuit CC may be omitted when the subject of compensation is located outside the sub-pixel such as the data driver 30 or the like. That is, one subpixel is basically composed of a 2T (Transistor) 1C (Capacitor) structure including a switching transistor SW, a driving transistor DR, a capacitor and an organic light emitting diode (OLED) 3T1C, 4T2C, 5T2C, 6T2C, 7T2C, or the like may be used.

Although the compensation circuit CC is shown between the switching transistor SW and the driving transistor DR in FIGS. 2 and 3, the compensation circuit CC is located between the driving transistor DR and the organic light emitting diode OLED. It is possible. The position and structure of the compensation circuit CC are not limited to those shown in Figs.

4 is a plan view of a display panel according to the present invention.

Referring to FIG. 4, the display panel includes a display area AA and a data pad part DP disposed at one side in a bezel area surrounding the display area AA. The display area AA has a plurality of R, G, B or R, G, B, W subpixels for color implementation. The data pad unit DP includes data pads PAD1, PAD2 and PAD3 connected to the data lines DL. Each data pad PAD1, PAD2, PAD3 is connected to the data lines DL arranged in the display area AA.

FIG. 5 is an enlarged view of the area A shown in FIG. 4, showing a data pad. 6 is a cross-sectional view taken along the line I-I 'shown in FIG.

Referring to FIGS. 5 and 6, the data pads PAD1, PAD2, and PAD3 use metal layers stacked in the process of forming the transistors on the substrate SUB.

A buffer layer BUF is located on the substrate PI. On the buffer layer BUF, a first metal pattern MP1 and a second metal pattern MP2 spaced apart by a repair area RA are located. The first metal pattern MP1 includes a gate metal layer GATE, a gate insulating layer GI, a source metal layer SD, a semiconductor layer ACT, a passivation layer PAS, and a transparent metal layer ITO ). The second metal pattern MP2 includes a gate metal layer GATE, a gate insulating film GI, a source metal layer SD, a passivation layer PAS, and a transparent metal layer ITO, which are located on the buffer layer BUF. The transparent metal layer (ITO) covers the entire surface of the first metal pattern MP1, the repair area RA and the second metal pattern MP2.

The buffer layer BUF protects the thin film transistor formed in a subsequent process from impurities such as alkali ions or the like, which are discharged from the substrate SUB. The buffer layer BUF may be silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof.

The gate metal layer GATE is a metal layer constituting a gate electrode of the transistors located in the display area AA. The gate metal layer GATE is selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper Any one of them or an alloy thereof. The gate electrode GA may be formed of a material selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy of any one selected from the above. For example, the gate electrode GA can be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum.

The gate insulating film GI may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof.

The source metal layer SD is a metal layer constituting a source electrode and a drain electrode of the transistors located in the display area AA. The source metal layer SD may be formed of a single layer or a multilayer and may be formed of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au) , Nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. Also, when the source metal layer SD is a multilayer, it may be formed of a triple layer of molybdenum / aluminum-neodymium, titanium / aluminum / titanium, molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum.

The passivation layer PAS may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof as an insulating film for protecting underlying devices

The transparent metal layer (ITO) is a metal layer constituting the anode electrode of the organic light emitting diode located in the display area AA. The transparent metal layer (ITO) may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

In the first metal pattern MP1, the transparent metal layer ITO is connected to the source metal layer SD through the contact hole CNT.

As shown in Fig. 7, when the anisotropic conductive film ACF is attached to the pad portion DP, the source metal layer SD is electrically connected to the conductive ball. The anisotropic conductive film ACF is formed by dispersing a plurality of conductive balls CB in an adhesive resin AR so that the substrate PI and the flexible printed board FPC are electrically connected while being bonded. The flexible printed board includes a signal wiring CL provided in the flexible film (FF).

In the repair area RA, the first metal pattern MP1 and the second metal pattern MP2 are electrically connected through a transparent metal layer (ITO). The data pads PAD1, PAD2, and PAD3 are not electrically connected to each other. As a result, each of the data pads PAD1, PAD2, and PAD3 applies signals output from the flexible printed circuit board (FPC) to the data lines DL of the display area AA. In the normal state, the data pads PAD1, PAD2, and PAD3 should not be electrically connected to each other. However, due to the phenomenon that the conductive balls of the anisotropic conductive film ACF accumulate, the adjacent data pads PAD1, There is a problem that they are electrically connected to each other.

The conductive ball CB of the anisotropic conductive film CACF is pushed to the end of the pad portion DP when the flexible printed board FPC is pressed on the pad portion DP with the anisotropic conductive film ACF sandwiched therebetween It is crowded. As a result, as shown in FIG. 8, the pads PAD1, PAD2 and PAD3 are electrically connected through the region where the conductive balls CB are formed.

The repair area RA is a place for electrically separating the region where the conductive balls CB are gathered. As shown in FIG. 8, when the conductive balls CB are bundled at the ends of the pad portions DP, the repair areas RA are removed through laser cutting as shown in FIG. As a result, the second metal pattern MP2 region in which the conductive balls CB are gathered is electrically separated from the first metal pattern MP1 region in which the contact holes CNT are located.

For the efficiency of the laser cutting process, only the transparent metal layer (ITO) is disposed on the buffer layer BUF in the repair area RA. That is, since no metal layer other than the transparent metal layer (ITO) is disposed in the repair area RA, the first metal pattern MP1 and the second metal pattern MP2 can be electrically separated reliably through laser cutting .

10 is a view showing a pad portion according to the second embodiment.

Fig. 8 shows an example in which the conductive balls CB are bundled in the region located at the end of the pad portion DP. Generally, the conductive balls CB are driven at the ends of the pad portions DP as shown in FIG. 8, but the conductive balls CB may be stacked in other regions than the end portions.

The second embodiment shown in FIG. 10 includes first and second repair areas RA. The first and second repair areas RA in the pad part DP according to the second embodiment can be selectively cut along the area where the conductive balls CB are bundled.

Although the present specification describes the data pad unit as a center, the technical idea of the present invention is not limited thereto. That is, it is obvious that the repair region of the present invention can be applied to a pad portion connecting a gate pad portion or another signal wiring.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SUB: Substrate BUF: Buffer layer
DP: Data pad part GI: Gate insulating film
SD: source metal layer PAS: passivation film

Claims (8)

A display region in which a plurality of pixels in a substrate and signal lines connected to the pixels are arranged; And
And pads disposed on the substrate and outside the display area, the pads being connected to the signal lines,
At least some of the pads
First and second metal patterns spaced apart from each other in a plane direction of the substrate; And
And a third metal pattern connecting the first metal pattern and the second metal pattern via the substrate,
Wherein each of the first and second metal patterns comprises:
And a first metal layer and a second metal layer stacked in a thickness direction of the substrate with a gate insulating film interposed therebetween. The method according to claim 1,
And the pads are connected to a data line arranged in the display area. 3. The method of claim 2,
Wherein the first metal layer is a gate metal layer located in a buffer layer of the substrate,
And the second metal layer is a source metal layer constituting the data line. The method according to claim 1,
Wherein the first metal pattern further comprises a semiconductor layer located on the second metal layer and a passivation layer covering the semiconductor layer,
Wherein the semiconductor layer and the third metal layer are connected through a contact hole passing through the passivation layer. The method of claim 3,
And the third metal layer is located on the buffer layer in a region between the first metal pattern and the second metal pattern. The method according to claim 1,
Wherein the first metal pattern is located closer to the display area than the second metal pattern. The method according to claim 6,
Further comprising a third metal pattern located closer to the display area than the first metal pattern and spaced apart from the first metal pattern,
The third metal pattern
And the first and second metal layers stacked in the thickness direction of the substrate with the gate insulating film interposed therebetween. 8. The method of claim 7,
Wherein the third metal pattern further comprises a semiconductor layer located on the second metal layer and a passivation layer covering the semiconductor layer,
Wherein the semiconductor layer and the third metal layer are connected through a contact hole passing through the passivation layer.

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