KR102589901B1 - Display device - Google Patents

Abstract

The display device according to the present invention includes a display area on a substrate where a plurality of pixels and signal wires connected to the pixels are disposed, and pads disposed on a pad portion outside the display area on the substrate and connected to the signal wires. At least some of the pads include first and second metal patterns spaced apart from each other by a predetermined distance in the surface direction of the substrate, and a third metal pattern connecting the first metal pattern and the second metal pattern via the substrate. Each of the first and second metal patterns includes first and second metal layers stacked in the thickness direction of the substrate with a gate insulating film interposed therebetween.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device including a repair area.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display device field has been rapidly changing toward thin, light, large-area flat panel displays (FPDs) replacing bulky cathode ray tubes (CRTs). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device. : ED), etc.

The display device includes a display panel and a drive IC that applies various driving signals to the display panel. The signal wires of the display panel are connected to the signal wires of the drive IC through an anisotropic conductive film (ACF). The anisotropic conductive film is pressed through a tab bonding process, and the conductive balls in the anisotropic conductive film electrically connect the pad portion of the display panel to the flexible printed circuit board. However, depending on the amount or pressure of the anisotropic conductive film, the conductive balls of the anisotropic conductive film are pushed to the end of the pad portion, causing aggregation. As a result, a short circuit may occur between the pads of the display panel, which must be electrically open.

The present invention provides a display device for preventing short-circuiting between pads in a display panel due to conductive balls of an anisotropic conductive film.

The display device according to the present invention includes a display area on a substrate where a plurality of pixels and signal wires connected to the pixels are disposed, and pads disposed on a pad portion outside the display area on the substrate and connected to the signal wires. At least some of the pads include first and second metal patterns spaced apart from each other by a predetermined distance in the surface direction of the substrate, and a third metal pattern connecting the first metal pattern and the second metal pattern via the substrate. Each of the first and second metal patterns includes first and second metal layers stacked in the thickness direction of the substrate with a gate insulating film interposed therebetween.

The present invention is provided with a repair area capable of laser cutting inside the area where the conductive balls of the anisotropic conductive film are clustered, so that the repair area can be cut when the conductive balls are clustered.

The repair area includes only the metal layer immediately adjacent to the buffer layer, so it can be easily removed using a laser process.

1 is a schematic block diagram of an organic light emitting display device.
Figure 2 is a first example diagram showing the circuit configuration of a subpixel.
3 is a second example diagram showing the circuit configuration of a subpixel.
Figure 4 is a diagram showing a non-display area according to the present invention.
Figure 5 is an enlarged view of area A in Figure 4.
FIG. 6 is a diagram showing a cross section taken along line II' in FIG. 5.
Figures 7 and 8 are diagrams explaining the short circuit phenomenon caused by a conductive ball.
Figure 9 is a diagram explaining a repair process to improve the shop phenomenon.
Figure 10 is a diagram showing a pad portion according to another embodiment.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

Although this specification is described focusing on the organic light emitting display device, the technical idea of the present invention is not limited thereto. It is obvious that the present invention can be applied to liquid crystal display devices, electrophoretic display devices, etc.

Hereinafter, embodiments of the present invention will be described with reference to the attached drawings.

FIG. 1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is a first example diagram showing the circuit configuration of a subpixel, and FIG. 3 is a second example diagram showing the circuit configuration of a subpixel.

Referring to FIG. 1 , the organic light emitting display device includes an image processing unit 10, a timing control unit 20, a data driver 30, a gate driver 40, and a display panel 50.

The image processing unit 10 outputs a data enable signal (DE) in addition to a data signal (DATA) supplied from the outside. The image processing unit 10 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of explanation. The image processing unit 10 is formed in the form of an integrated circuit (IC) on a system circuit board.

The timing control unit 20 receives a data enable signal (DE) or a driving signal including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, as well as a data signal (DATA) from the image processing unit 10.

The timing control unit 20 includes a gate timing control signal (GDC) for controlling the operation timing of the gate driver 40 and a data timing control signal (DDC) for controlling the operation timing of the data driver 30 based on the driving signal. outputs. The timing control unit 20 is formed in the form of an IC on a control circuit board.

The data driver 30 samples and latches the data signal DATA supplied from the timing control unit 20 in response to the data timing control signal DDC supplied from the timing control unit 20, converts it to a gamma reference voltage, and outputs it. . The data driver 30 outputs a data signal DATA through the data lines DL1 to DLn. The data driver 30 is attached in the form of an IC on a substrate.

The gate driver 40 outputs a gate signal while shifting the level of the gate voltage in response to the gate timing control signal (GDC) supplied from the timing controller 20. The gate driver 40 outputs a gate signal through the gate lines GL1 to GLm. The gate driver 40 is formed in the form of an IC on a gate circuit board or in the form of a gate in panel on the display panel 50.

The display panel 50 displays images in response to the data signal (DATA) and gate signal supplied from the data driver 30 and the gate driver 40. The display panel 50 includes subpixels SP that display images.

Referring to FIG. 2, one subpixel includes a switching transistor (SW), a driving transistor (DR), a compensation circuit (CC), and an organic light emitting diode (OLED). An organic light-emitting diode (OLED) operates to emit light according to a driving current formed by a driving transistor (DR).

The switching transistor SW performs a switching operation in response to the gate signal supplied through the first gate line GL1 so that the data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor. The driving transistor (DR) operates so that a driving current flows between the high-potential power line (VDD) and the low-potential power line (GND) according to the data voltage stored in the capacitor. The compensation circuit (CC) is a circuit for compensating the threshold voltage of the driving transistor (DR). Additionally, the capacitor connected to the switching transistor (SW) or driving transistor (DR) may be located inside the compensation circuit (CC).

The compensation circuit (CC) consists of one or more thin film transistors and a capacitor. The composition of the compensation circuit (CC) varies greatly depending on the compensation method, so specific examples and descriptions thereof will be omitted.

In addition, as shown in FIG. 3, when the compensation circuit (CC) is included, the subpixel further includes a signal line and a power line for supplying a specific signal or power in addition to driving the compensation thin film transistor. The added signal line may be defined as the 1-2 gate line GL1b for driving the compensation thin film transistor included in the subpixel. And the added power line can be defined as an initialization power line (INIT) for initializing a specific node of a subpixel to a specific voltage. However, this is only an example and is not limited to this.

Meanwhile, in Figures 2 and 3, one subpixel includes a compensation circuit (CC) as an example. However, if the subject of compensation is located outside the subpixel, such as the data driver 30, the compensation circuit (CC) may be omitted. In other words, one subpixel is basically composed of a 2T (Transistor) 1C (Capacitor) structure including a switching transistor (SW), a driving transistor (DR), a capacitor, and an organic light emitting diode (OLED), but the compensation circuit (CC) If added, it may be configured in various ways such as 3T1C, 4T2C, 5T2C, 6T2C, 7T2C, etc.

In addition, in Figures 2 and 3, the compensation circuit (CC) is shown as being located between the switching transistor (SW) and the driving transistor (DR), but it can also be located between the driving transistor (DR) and the organic light-emitting diode (OLED). It may be possible. The location and structure of the compensation circuit (CC) are not limited to FIGS. 2 and 3.

Figure 4 is a plan view of the display panel according to the present invention.

Referring to FIG. 4 , the display panel includes a display area AA and a data pad portion DP disposed on one side of the bezel area surrounding the display area AA. In the display area (AA), a large number of R, G, B or R, G, B, W subpixels are arranged for color implementation. The data pad unit DP includes data pads PAD1, PAD2, and PAD3 connected to the data line DL. Each data pad (PAD1, PAD2, and PAD3) is connected to data lines (DL) disposed in the display area (AA).

FIG. 5 is an enlarged view of area A shown in FIG. 4 and shows a data pad. FIG. 6 is a diagram showing a cross section along line II' shown in FIG. 5.

Referring to FIGS. 5 and 6, the data pads PAD1, PAD2, and PAD3 use metal layers stacked in the process of forming transistors on the substrate SUB.

A buffer layer (BUF) is located on the substrate (PI). The first metal pattern MP1 and the second metal pattern MP2 are positioned on the buffer layer BUF and are spaced apart from each other with the repair area RA in between. The first metal pattern (MP1) includes a gate metal layer (GATE), a gate insulating film (GI), a source metal layer (SD), a semiconductor layer (ACT), a passivation layer (PAS), and a transparent metal layer (ITO) located on the buffer layer (BUF). ) includes. The second metal pattern MP2 includes a gate metal layer (GATE), a gate insulating film (GI), a source metal layer (SD), a passivation layer (PAS), and a transparent metal layer (ITO) located on the buffer layer (BUF). The transparent metal layer (ITO) covers the entire surface of the first metal pattern (MP1), the repair area (RA), and the second metal pattern (MP2).

The buffer layer (BUF) serves to protect the thin film transistor formed in the subsequent process from impurities such as alkali ions leaking from the substrate (SUB). The buffer layer (BUF) may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

The gate metal layer (GATE) is a metal layer that forms the gate electrode of the transistors located in the display area (AA). The gate metal layer (GATE) is selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It is formed from either one or an alloy thereof. In addition, the gate electrode (GA) is a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multi-layer made of any one selected from or an alloy thereof. For example, the gate electrode GA may be a double layer of molybdenum/aluminum-neodymium or molybdenum/aluminum.

The gate insulating film (GI) may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

The source metal layer (SD) is a metal layer that forms the source and drain electrodes of the transistors located in the display area (AA). The source metal layer (SD) may be made of a single layer or multiple layers. If the source metal layer (SD) is a single layer, it may be made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), or titanium (Ti). , it may be made of any one selected from the group consisting of nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, when the source metal layer (SD) is a multi-layer, it may be a double layer of molybdenum/aluminum-neodymium, a triple layer of titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, or a triple layer of molybdenum/aluminum-neodymium/molybdenum.

The passivation layer (PAS) is an insulating film that protects the underlying device and may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or multiple layers thereof.

The transparent metal layer (ITO) is a metal layer that forms the anode electrode of the organic light emitting diode located in the display area (AA). The transparent metal layer (ITO) may be made of a transparent conductive material such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or Zinc Oxide (ZnO).

In the first metal pattern MP1, the transparent metal layer ITO is connected to the source metal layer SD through the contact hole CNT.

As shown in FIG. 7 , when the anisotropic conductive film (ACF) is bonded to the pad portion DP, the source metal layer SD is electrically connected to the conductive ball. Anisotropic conductive film (ACF) consists of a plurality of conductive balls (CB) dispersed in adhesive resin (AR) and electrically connects the substrate (PI) and flexible printed circuit board (FPC) by bonding them. The flexible printed board includes signal wiring (CL) provided on a flexible film (FF).

In the repair area RA, the first metal pattern MP1 and the second metal pattern MP2 are electrically connected through the transparent metal layer ITO. Each data pad (PAD1, PAD2, and PAD3) is not electrically connected to each other. As a result, each of the data pads PAD1, PAD2, and PAD3 applies signals output from the flexible printed circuit board (FPC) to the data lines DL of the display area AA. In this normal state, each data pad (PAD1, PAD2, PAD3) should not be electrically connected to each other, but due to the phenomenon of the conductive balls of the anisotropic conductive film (ACF) agglomerating, adjacent data pads (PAD1, PAD2, PAD3) Problems may arise when these are electrically connected to each other.

When the flexible printed circuit board (FPC) is pressed to the pad portion (DP) with the anisotropic conductive film (ACF) in between, the conductive ball (CB) of the anisotropic conductive film (CACF) is pushed to the end of the pad portion (DP). You will be crowded. As a result, as shown in FIG. 8, the pads (PAD1, PAD2, and PAD3) are electrically connected through the area where the conductive balls (CB) are clustered.

The repair area (RA) is a place to electrically separate the area where the conductive balls (CB) are clustered. As shown in FIG. 8 , when the conductive balls CB are clustered at the end of the pad portion DP, the repair area RA is removed through laser cutting as shown in FIG. 9 . As a result, the area of the second metal pattern MP2 where the conductive balls CB are clustered is electrically separated from the area of the first metal pattern MP1 where the contact hole CNT is located.

For the efficiency of the laser cutting process, only the transparent metal layer (ITO) is disposed on the buffer layer (BUF) in the repair area (RA). That is, since no metal layer other than the transparent metal layer (ITO) is disposed in the repair area (RA), the first metal pattern (MP1) and the second metal pattern (MP2) can be reliably electrically separated through laser cutting. .

Figure 10 is a diagram showing a pad portion according to the second embodiment.

Figure 8 shows an example where conductive balls (CB) are clustered in an area located at the end of the pad portion (DP). Generally, the conductive balls CB are gathered at the end of the pad portion DP, as shown in FIG. 8, but the conductive balls CB may be gathered in other areas other than the end.

The second embodiment shown in FIG. 10 includes first and second repair areas RA. In the pad portion DP according to the second embodiment, the first and second repair areas RA may be selectively cut according to the area where the conductive balls CB are clustered.

Although this specification focuses on the data pad unit, the technical idea of the present invention is not limited thereto. That is, it is obvious that the repair area of the present invention can also be applied to a gate pad part or a pad part connecting other signal wires.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

SUB: Substrate BUF: Buffer layer
DP: Data pad GI: Gate insulating film
SD: source metal layer PAS: passivation film

Claims (9)

A display area on a substrate where a plurality of pixels and signal wires connected to the pixels are arranged; and
and pads disposed on the substrate outside the display area and connected to the signal wires,
At least some of the pads
first and second metal patterns spaced apart from each other by a predetermined distance in the plane direction of the substrate; and
A transparent metal layer connecting the first metal pattern and the second metal pattern via the substrate,
Each of the first and second metal patterns,
Comprising first and second metal layers stacked in the thickness direction of the substrate with a gate insulating film interposed therebetween,
The transparent metal layer covers the entire surface of the first metal pattern, the second metal pattern, and a space separating the first metal pattern and the second metal pattern.
According to claim 1,
A display device wherein the pads are connected to data lines disposed in the display area. According to claim 2,
The first metal layer is a gate metal layer located in the buffer layer of the substrate,
The second metal layer is a source metal layer forming the data line. According to claim 1,
The first metal pattern further includes a semiconductor layer located on the second metal layer and a passivation layer covering the semiconductor layer,
A display device in which the semiconductor layer and the transparent metal layer are connected through a contact hole penetrating the passivation layer. According to claim 3,
In a region between the first metal pattern and the second metal pattern, the transparent metal layer is located on the buffer layer. According to claim 1,
The first metal pattern is located closer to the display area than the second metal pattern. According to claim 6,
It further includes a third metal pattern located closer to the display area than the first metal pattern and spaced apart from the first metal pattern,
The third metal pattern is
A display device comprising the first and second metal layers stacked in the thickness direction of the substrate with the gate insulating film interposed therebetween. According to claim 7,
The third metal pattern further includes a semiconductor layer located on the second metal layer and a passivation layer covering the semiconductor layer,
A display device in which the semiconductor layer and the transparent metal layer are connected through a contact hole penetrating the passivation layer.
A display area on a substrate where a plurality of pixels and signal wires connected to the pixels are arranged; and
and pads disposed on the substrate outside the display area and connected to the signal wires,
At least some of the pads
first and second metal patterns spaced apart from each other by a predetermined distance in the plane direction of the substrate; and
A transparent metal layer connecting the first metal pattern and the second metal pattern via the substrate,
Each of the first and second metal patterns,
Comprising first and second metal layers stacked in the thickness direction of the substrate with a gate insulating film interposed therebetween,
The second metal layer is disposed between the first metal layer and the transparent metal layer.

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