KR102505341B1 - Chip on film and display device comprising the same - Google Patents

Abstract

The present invention relates to a chip-on-film capable of reducing the width of the chip-on-film and a display device including the same. A chip-on-film according to an embodiment of the present invention includes a base film including a first terminal part and a second terminal part, a semiconductor chip mounted on a mounting area of the base film, and the first terminal so as to surround the mounting area of the semiconductor chip. and a power lead extending from the first terminal unit to the second terminal unit.

Description

Chip on film and display device including the same {CHIP ON FILM AND DISPLAY DEVICE COMPRISING THE SAME}

The present invention relates to a chip-on-film and a display device including the same.

As the information society develops, demands for display devices for displaying images are increasing in various forms. The field of display devices has rapidly changed to a flat panel display device (FPD) that is thin, light, and capable of large area, replacing a bulky cathode ray tube (CRT). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device (ELD). : ED), etc.

Among them, the organic light emitting display device is a self light emitting device that emits light by itself, and has advantages of fast response speed, high light emitting efficiency, luminance, and viewing angle. In particular, an organic light emitting display device can be formed on a flexible plastic substrate, can be driven at a lower voltage than a plasma display panel or an inorganic electroluminescent (EL) display, and consumes relatively little power. It has the advantage that it is small and the color is excellent.

The organic light emitting display device manufactures elements such as thin film transistors and organic light emitting diodes on a substrate and transfers driving signals from a printed circuit board (PCB) to a pad part. ) is attached. The chip-on-film includes a plurality of input leads and a plurality of output leads based on the semiconductor chip. However, as the number of input leads and output leads increases as the resolution increases, the size of the chip-on-film gradually increases. Therefore, research into designing a plurality of leads within a chip-on-film of a limited size is ongoing.

The present invention provides a chip-on-film capable of reducing the width of the chip-on-film and a display device including the same.

In order to achieve the above object, a chip on film according to an embodiment of the present invention includes a base film including a first terminal part and a second terminal part, a semiconductor chip mounted on a mounting area of the base film, and the semiconductor chip. and a power lead extending from the first terminal unit to the second terminal unit so as to surround a mounting area of the terminal unit.

The power lead includes a main lead and a plurality of branch leads, a power input bump is positioned at an end of each of the plurality of branch leads, and a power output bump is positioned at an end of the main lead.

The plurality of branch leads extend from the main lead toward the semiconductor chip.

The semiconductor device may further include a plurality of first output leads connected from the first terminal unit to a mounting area of the semiconductor chip, and a plurality of first input leads connected from the mounting area of the semiconductor chip to the second terminal unit.

A first input bump is positioned at each end of the plurality of first input leads, and a first output bump is positioned at each end of the plurality of first output leads.

The first input bump is positioned on the second terminal part.

A direction in which the first input lead extends from the mounting area of the semiconductor chip and a direction in which the branch lead of the power supply lead extends face each other.

An arbitrary first line connecting the plurality of first input bumps and an arbitrary second line connecting the plurality of power input bumps are spaced apart from each other.

In addition, a chip on film according to an embodiment of the present invention includes a base film including a first terminal part and a second terminal part, a semiconductor chip mounted on a mounting area on one surface of the base film, and located on the other surface of the base film. and a power lead extending from the first terminal unit to the second terminal unit.

The power lead penetrates the base film, and a plurality of power input bumps are positioned on one surface of the base film on which the semiconductor chip is mounted.

The semiconductor device may further include a plurality of first output leads connected from the first terminal unit to a mounting area of the semiconductor chip, and a plurality of first input leads connected from the mounting area of the semiconductor chip to the second terminal unit.

A first input bump is positioned at each end of the plurality of first input leads, and a first output bump is positioned at each end of the plurality of first output leads.

The first input bump is positioned on the second terminal part.

An arbitrary first line connecting the plurality of first input bumps and an arbitrary second line connecting the plurality of power output bumps are spaced apart from each other.

In addition, a display device according to an embodiment of the present invention includes a substrate including a display unit, a pad unit disposed below the substrate, and a plurality of chip-on films attached to the pad unit, wherein the chip-on film comprises: A base film including a first terminal part and a second terminal part, a semiconductor chip mounted on a mounting area of the base film, and a power lead extending from the first terminal part to the second terminal part so as to surround the mounting area of the semiconductor chip. includes

In the chip-on-film according to an embodiment of the present invention, since the power input bump is not disposed between the data input bumps, the width of the chip-on-film can be reduced by the same width occupied by the power input bump.

In addition, the chip-on film according to an embodiment of the present invention arranges the power lead at a distance from the mounting area of the semiconductor chip, so that data input/output leads connected to the mounting area can be easily designed.

In addition, in the chip-on-film according to an embodiment of the present invention, the width of the chip-on-film can be reduced by the width occupied by the power input bumps by arranging the power input bumps, which have been disposed between the data input bumps, elsewhere. It is possible to prevent a bump on the printed circuit board to be bonded with the bump from being erroneously bonded to the power input bump.

1 is a schematic block diagram of an organic light emitting display device;
2 is a first exemplary view showing a circuit configuration of a sub-pixel;
3 is a second exemplary view showing a circuit configuration of a sub-pixel;
4 is a plan view illustrating an organic light emitting display device according to the present invention.
5 is a cross-sectional view illustrating a sub-pixel portion of an organic light emitting display device according to an embodiment of the present invention.
6 is a plan view illustrating a chip-on-film;
7 is a cross-sectional view schematically illustrating a shape in which a chip-on-film and a display panel are attached;
8 is a schematic plan view of a part of a chip-on-film having another structure;
9 is a plan view illustrating a chip-on-film according to an embodiment of the present invention;
10 is a plan view schematically illustrating bumps;
11 is a plan view illustrating a chip-on-film according to another embodiment of the present invention;
Fig. 12 is a cross-sectional view taken along the line A-A' of Fig. 11;

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In addition, component names used in the following description may be selected in consideration of ease of writing specifications, and may be different from names of parts of actual products.

A display device according to the present invention is a display device in which display elements are formed on a glass substrate or a flexible substrate. As an example of the display device, an organic light emitting display device, a liquid crystal display device, an electrophoretic display device, etc. can be used, but an organic light emitting display device will be described as an example in the present invention. An organic light emitting display device includes an organic film layer made of an organic material between a first electrode serving as an anode and a second electrode serving as a cathode. Therefore, holes supplied from the first electrode and electrons supplied from the second electrode are combined in the organic layer to form an exciton, which is a hole-electron pair, and light is emitted by energy generated as the exciton returns to the ground state. It is a self-luminous display device.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is a first exemplary diagram illustrating a circuit configuration of a subpixel, and FIG. 3 is a second exemplary diagram illustrating a circuit configuration of a subpixel.

Referring to FIG. 1 , an organic light emitting display device includes an image processor 10 , a timing controller 20 , a data driver 30 , a gate driver 40 and a display panel 50 .

The image processor 10 outputs a data enable signal DE along with the data signal DATA supplied from the outside. The image processor 10 may output one or more of a vertical sync signal, a horizontal sync signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of description. The image processing unit 10 is formed in the form of an integrated circuit (IC) on a system circuit board.

The timing controller 20 receives a data signal DATA along with a data enable signal DE or driving signals including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal from the image processing unit 10 .

The timing controller 20 generates a gate timing control signal (GDC) for controlling the operation timing of the gate driver 40 and a data timing control signal (DDC) for controlling the operation timing of the data driver 30 based on the driving signal. outputs The timing controller 20 is formed in the form of an IC on a control circuit board.

The data driver 30 samples and latches the data signal DATA supplied from the timing controller 20 in response to the data timing control signal DDC supplied from the timing controller 20, converts it into a gamma reference voltage, and outputs the result. . The data driver 30 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 30 is attached in the form of an IC on a substrate.

The gate driver 40 outputs a gate signal while shifting the level of a gate voltage in response to the gate timing control signal GDC supplied from the timing controller 20 . The gate driver 40 outputs a gate signal through the gate lines GL1 to GLm. The gate driver 40 is formed in the form of an IC on the gate circuit board or formed on the display panel 50 in a Gate In Panel (GIP) method.

The display panel 50 displays an image in response to the data signal DATA and the gate signal supplied from the data driver 30 and the gate driver 40 . The display panel 50 includes sub-pixels SP that display an image.

Referring to FIG. 2 , one sub-pixel includes a switching transistor SW, a driving transistor DR, a compensation circuit CC, and an organic light emitting diode OLED. The organic light emitting diode (OLED) operates to emit light according to a driving current formed by the driving transistor DR.

The switching transistor SW performs a switching operation to store the data signal supplied through the first data line DL1 as a data voltage in the capacitor Cst in response to the gate signal supplied through the gate line GL1. The driving transistor DR operates to allow a driving current to flow between the high potential power line VDD and the low potential power line GND according to the data voltage stored in the capacitor Cst. The compensation circuit CC is a circuit for compensating for the threshold voltage of the driving transistor DR. Also, a capacitor connected to the switching transistor SW or the driving transistor DR may be located inside the compensation circuit CC. The compensation circuit (CC) is composed of one or more thin film transistors and capacitors. Since the configuration of the compensation circuit (CC) varies greatly depending on the compensation method, specific examples and descriptions thereof will be omitted.

In addition, as shown in FIG. 3 , when the compensation circuit CC is included, the sub-pixel further includes a signal line and a power supply line for supplying a specific signal or power as well as driving the compensation thin film transistor. The gate line GL1 includes a 1-1st gate line GL1a for supplying a gate signal to the switching transistor SW and a 1-2nd gate line GL1b for driving the compensation thin film transistor included in the sub-pixel. can include Also, the added power line may be defined as an initialization power line (INIT) for initializing a specific node of a subpixel to a specific voltage. However, this is only one example and is not limited thereto.

On the other hand, in FIGS. 2 and 3, it is taken as an example that a compensation circuit (CC) is included in one sub-pixel. However, when the subject of compensation is located outside the sub-pixel, such as the data driver 30, the compensation circuit CC may be omitted. That is, one sub-pixel is basically composed of a 2T (Transistor) 1C (Capacitor) structure including a switching transistor (SW), a driving transistor (DR), a capacitor, and an organic light emitting diode (OLED), but a compensation circuit (CC) When is added, it may be configured in various ways such as 3T1C, 4T2C, 5T2C, 6T2C, and 7T2C. 2 and 3 show that the compensation circuit CC is located between the switching transistor SW and the driving transistor DR, it may be further located between the driving transistor DR and the organic light emitting diode OLED. may be The position and structure of the compensation circuit (CC) is not limited to FIGS. 2 and 3 .

4 is a plan view showing an organic light emitting display device according to the present invention, FIG. 5 is a cross-sectional view showing a subpixel portion of the organic light emitting display device according to the present invention, FIG. 6 is a plan view showing a chip-on-film, and FIG. A cross-sectional view schematically showing a shape in which a chip-on film and a display panel are attached, and FIG. 8 is a schematic plan view of a part of a chip-on film having another structure.

Referring to FIG. 4 , the organic light emitting display device includes a substrate SUB1, a display unit A/A, and GIP driving units GIP disposed on both sides of the display unit A/A, and disposed below the substrate SUB1. A pad part PD is included. In the display unit A/A, a plurality of subpixels SP are arranged to emit R, G, B or R, G, B, W to implement full color. A GIP driving unit (GIP) is disposed on both sides of the display unit (A/A) to apply a gate driving signal to the display unit (A/A). The pad part PD is disposed on one side, for example, the lower side of the display part A/A, and the chip-on-films COF are attached to the pad part DP. Data signals and power applied through the chip-on-film COF are applied to a plurality of signal lines (not shown) connected from the display unit A/A.

Hereinafter, referring to FIG. 5 of the present invention, a cross-sectional structure of a sub-pixel (SP) region of an organic light emitting display device will be described.

Referring to FIG. 5 , in the organic light emitting display device according to the present invention, a light blocking layer LS is positioned on a substrate SUB1. The substrate SUB1 may be made of glass, plastic or metal. The light blocking layer LS serves to prevent photocurrent from being generated in the thin film transistor by blocking external light from being incident. A buffer layer BUF is positioned on the light blocking layer LS. The buffer layer BUF serves to protect the thin film transistor formed in a subsequent process from impurities such as alkali ions flowing out of the substrate SUB1. The buffer layer BUF may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

A semiconductor layer ACT is positioned on the buffer layer BUF. The semiconductor layer ACT may be formed of a silicon semiconductor or an oxide semiconductor. The silicon semiconductor may include amorphous silicon or crystallized polycrystalline silicon. Here, polycrystalline silicon has high mobility (more than 100 cm 2 /Vs), low energy consumption and excellent reliability, so it can be applied to gate drivers and/or multiplexers (MUX) for driving elements or to driving TFTs in pixels. there is. On the other hand, since the oxide semiconductor has a low off-current, it is suitable for a switching TFT that has a short on-time and long off-time. In addition, since the off current is small, the voltage holding period of the pixel is long, so it is suitable for a display device requiring low speed driving and/or low power consumption. In addition, the semiconductor layer ACT includes a drain region and a source region including p-type or n-type impurities and includes a channel therebetween.

A gate insulating layer GI is positioned on the semiconductor layer ACT. The gate insulating layer GI may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof. A gate electrode GA is positioned on the gate insulating film GI at a position corresponding to a predetermined region of the semiconductor layer ACT, that is, a channel when impurities are implanted therein. The gate electrode GA is selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It is formed from any one or an alloy thereof. In addition, the gate electrode GA is a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multi-layer made of any one selected from or an alloy thereof. For example, the gate electrode GA may be a double layer of molybdenum/aluminum-neodymium or molybdenum/aluminum.

An interlayer insulating layer ILD insulating the gate electrode GA is positioned on the gate electrode GA. The interlayer insulating layer ILD may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. Contact holes CH exposing a part of the semiconductor layer ACT are positioned in partial regions of the interlayer insulating layer ILD and the gate insulating layer GI.

A drain electrode DE and a source electrode SE are positioned on the interlayer insulating layer ILD. The drain electrode DE is connected to the semiconductor layer ACT through the contact hole CH exposing the drain region of the semiconductor layer ACT, and the source electrode SE exposes the source region of the semiconductor layer ACT. It is connected to the semiconductor layer ACT through the contact hole CH. The source electrode SE and the drain electrode DE may be formed of a single layer or multiple layers. When the source electrode SE and the drain electrode DE are a single layer, molybdenum (Mo), aluminum (Al), chromium It may be made of any one selected from the group consisting of (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, when the source electrode SE and the drain electrode DE are multi-layered, a double layer of molybdenum/aluminum-neodymium, a triple layer of titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, or molybdenum/aluminum-neodymium/molybdenum can be made with Thus, the thin film transistor TFT including the semiconductor layer ACT, the gate electrode GA, the drain electrode DE, and the source electrode SE is formed.

A first passivation layer PAS1 is positioned on the substrate SUB1 including the thin film transistor TFT. The first passivation layer PAS1 is an insulating layer that protects a lower element, and may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. An overcoat layer OC is positioned on the first passivation layer PAS1. The overcoat layer OC may be a planarization film for alleviating step differences in a lower structure, and is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. The overcoat layer OC may be formed by a method such as spin on glass (SOG) in which the organic material is coated in a liquid form and then cured.

A via hole VIA exposing the drain electrode DE is positioned in a portion of the overcoat layer OC. An organic light emitting diode (OLED) is positioned on the overcoat layer (OC). More specifically, the first electrode ANO is positioned on the overcoat layer OC. The first electrode ANO serves as a pixel electrode and is connected to the drain electrode DE of the thin film transistor TFT through the via hole VIA. The first electrode ANO is an anode and may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). When the first electrode ANO is a transparent electrode, it may be made of the transparent conductive material, and when the first electrode ANO is a reflective electrode, the first electrode ANO further includes a reflective layer. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or alloys thereof, preferably made of APC (silver/palladium/copper alloy).

A bank layer BNK partitioning pixels is positioned on the substrate SUB1 including the first electrode ANO. The bank layer BNK is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. In the bank layer BNK, the pixel defining part OP exposing the first electrode ANO is positioned.

An organic layer EML contacting the first electrode ANO is positioned on the entire surface of the substrate SUB1. The organic film layer (EML) is a layer that emits light by combining electrons and holes, and may include a hole injection layer or a hole transport layer between the organic film layer (EML) and the first electrode (ANO), and on the organic film layer (EML). An electron transport layer or an electron injection layer may be included. The second electrode CAT is positioned on the organic film layer EML. The second electrode CAT is located in front of the display unit A/A and is a cathode electrode and may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag) or an alloy thereof having a low work function. there is. When the second electrode CAT is a transmissive electrode, it is made thin enough to transmit light, and when it is a reflective electrode, it is made thick enough to reflect light. A second passivation film PAS2 is disposed on the second electrode CAT to protect the lower organic light emitting diode OLED.

Meanwhile, the structure of the chip-on-film according to the present invention will be described with reference to FIG. 6 .

Referring to FIG. 6 , the chip-on-film (COF) includes a semiconductor chip (SC) mounted on a base film (BF), and a mounting area (MA) in which the semiconductor chip (SC) is mounted is defined. On the base film BF, a plurality of leads 101 and 111 connected from the first terminal unit UDA located on one side of the base film BF to the semiconductor chip SC are included. A plurality of input bumps 102 and 112 are positioned at ends of the plurality of leads 101 and 111 located in the first terminal unit UDA. On the base film BF, a plurality of leads 105 and 115 connected to the semiconductor chip SC from the second terminal part LDA located on the other side of the base film BF are further included. A plurality of output bumps 106 and 116 are positioned at ends of the plurality of leads 105 and 115 located in the second terminal part LDA.

The plurality of leads 101, 105, 111, and 115 function to receive data signals, control signals, and power supply voltages for driving the display panel from the printed circuit board (PCB) and transmit them to the display panel. The plurality of leads include power input lead 101 , power output lead 105 , data input lead 111 , and data output lead 115 . The plurality of power input leads 101 are located between the plurality of data input leads 111, and the plurality of power output leads 106 are located between the plurality of data output leads 115.

The plurality of power input leads 101 include power input bumps 102 positioned at ends, and the plurality of power output leads 105 include power output bumps 105 positioned at ends. The plurality of data input leads 111 include data input bumps 112 positioned at ends, and the plurality of data output leads 115 include data output bumps 116 positioned at ends. The power input bump 102 and data input bump 112 are for connecting to terminals of the printed circuit board, and the power output bump 106 and data output bump 116 are for connecting to terminals of the display panel. .

The COF shown in FIG. 6 uses a method in which a power signal is output from the power input lead 101 to the power output lead 105 through the semiconductor chip SC. However, since the power input bumps 102 of the power input lead 101 and the data input bumps 112 of the data input lead 111 are arranged on the same line, these bumps 102, 112 The pitch between them is reduced.

Looking at the bonding structure of the chip on film (COF) and the printed circuit board (PCB) shown in FIG. 7, the power input bump 102 and the data input bump 112 of the chip on film (COF) are respectively It is bonded to the power bump 102P and the data bump 112P of the PCB through an anisotropic conductive film (ACF). Between the power input bumps 102 of the chip-on-film (COF) and the data bumps 112P of the printed circuit board (PCB), they are bonded to each other and have a constant pitch, that is, a second pitch (P2) to the extent that defects do not occur. . However, if the pitch between the power input bumps 102 and the data input bumps 112 of the chip on film COF, that is, the first pitch P1 is reduced, the second pitch P2 is reduced and the chip on film COF A bonding defect occurs between the power input bump 102 of ) and the data bump 112P of the printed circuit board (PCB).

In addition, in the staggered chip-on-film shown in FIG. 8, the power input bump 102 of the power input lead 101 and the data input bump 112 of the data input lead 111 are arranged in a zigzag pattern, resulting in poor bonding. is preventing However, as the high resolution goes, as the number of power input leads 101 and data input leads 111 and the number of power input bumps 102 and data input bumps 112 increase, their pitches are shortened, resulting in data signal interference. and the wiring becomes complicated.

The following discloses a chip-on-film capable of reducing the width of the chip-on-film and facilitating design of wiring.

<Example>

9 is a plan view illustrating a chip-on-film according to an exemplary embodiment, and FIG. 10 is a plan view schematically illustrating bumps. In the following, the same reference numerals will be given to the same components as the chip-on-film described above.

Referring to FIG. 9 , a chip on film (COF) according to an embodiment of the present invention includes a base film (BF) and a semiconductor chip (SC) mounted on the base film (BF). The base film BF may be formed of a flexible material that can be bent. For example, the base film BF may include polyimide. A mounting area MA in which the semiconductor chip SC is mounted is defined on the base film BF.

A plurality of leads 101 , 111 , and 115 connected from the first terminal unit UDA located on one side of the base film BF to the second terminal unit LDA are included on the base film BF. A plurality of input bumps 102 and 112 are positioned at ends of the plurality of leads 101 and 111 located in the first terminal unit UDA. A plurality of output bumps 106 and 116 are positioned at ends of the plurality of leads 101 and 115 located in the second terminal part LDA.

The leads 101, 111, and 115 may be formed of a conductive material such as copper. Although not shown, a solder resist may be further provided on the leads 101, 111, and 115. The solder resist may serve to prevent defects such as oxidation of the leads 101 , 111 , and 115 exposed to an external environment. In addition, a molding resin (not shown) may be filled in the mounting area MA where the semiconductor chip SC is mounted through an under fill process.

On the base film BF, input leads and output leads are electrically connected to form signal transmission paths. The signal transmission path functions to receive data signals, power supply voltages, etc. for driving the display panel from the printed circuit board and transfer them to the display panel. The signal transmission path may include a data signal transmission path and a power supply voltage transmission path. The data signal transmission path is a path through which data signals for driving the display panel are supplied. The power supply voltage transmission path is a path to which the power supply voltage is applied.

The data signal transmission path includes a data input lead 111 , a data input bump 112 , a data output lead 115 and a data output bump 116 . The data input bump 112 is connected to the printed circuit board and disposed on the first terminal unit UDA. The data output bump 116 is connected to the display panel and disposed on the second terminal part LDA. The data input leads 111 connect the data input bumps 112 to which data signals are supplied among the first terminal units UDA to the semiconductor chip SC. That is, one end of the data input leads 111 is connected to the data input bump 112 and the other end is connected to the semiconductor chip SC. The data output lead 115 connects the semiconductor chip SC from which the data signal is output among the second terminal units LDA to the data output bump 116 . That is, one end of the data output leads 115 is connected to the semiconductor chip SC and the other end is connected to the data output bump 116 . The data input lead 111 , the data input bump 112 , the semiconductor chip SC, the data output lead 115 , and the data output bump 116 are connected to each other to serve as a data signal transmission path for transmitting a data signal.

The power voltage transmission path includes a power lead 101 , power input bumps 102 and power output bumps 106 . Power input bump 102 and power output bump 106 are connected to power lead 101 . The power lead 101 connects the power input bump 102 of the first terminal unit UDA, to which the power voltage is supplied, to the power output bump 106 of the second terminal unit LDA, to which the power voltage is output. That is, one end of the power lead 101 is connected to the power input bump 102 and the other end is connected to the power output bump 106 .

The power lead 101 includes a main lead ML and a branch lead DL. The main lead ML is an integral area extending from the first terminal unit UDA to the second terminal unit LDA, and the branch lead DL is branched from the main lead ML into a plurality of power sources of the first terminal unit UDA. This is an area connected to the input bumps 102 .

The main lead ML of the power lead 101 is spaced apart from the mounting area MA of the semiconductor chip SC and is disposed to surround the mounting area MA. One end of the main lead ML starts from the second terminal part LDA, passes through the first terminal part UDA while surrounding the mounting area MA of the semiconductor chip SC, and the other end extends to the second terminal part LDA. placed in shape. Power output bumps 106 are respectively disposed at ends of the main leads ML located in the second terminal part LDA. The branch lead DL of the power supply lead 101 is branched from the main lead ML toward the mounting area MA of the semiconductor chip SC and extends. A plurality of branch leads DL are disposed, and power input bumps 102 are disposed at ends of the plurality of branch leads DL, respectively.

In the present invention, it is disclosed that the power lead 101 is disposed spaced apart from the mounting area MA of the semiconductor chip SC. When the power lead 101 is spaced apart from the mounting area MA, the power lead 101 existing between the data input/output leads 111 and 115 connected to the mounting area MA is removed, thereby facilitating the design of the leads. can do

Further, the direction in which the data input lead 111 extends from the mounting area MA of the semiconductor chip SC and the direction in which the branch lead DL of the power supply lead 101 extends face each other. In particular, an arbitrary first line L1 connecting the plurality of data input bumps 112 and an arbitrary second line L2 connecting the plurality of power input bumps 102 may be spaced apart from each other.

As shown in FIG. 10 , a width D occupied by the power input bump 102 exists between the data input bumps 112 . In the present invention, since the power input bumps 102 are not disposed between the data input bumps 112, the width of the chip on film (COF) can be reduced by the width D occupied by the power input bumps. In particular, since the number of power input bumps ranges from tens to hundreds, the width of the chip-on-film (COF) can be remarkably reduced.

As shown in FIG. 4 described above, since the width of the pad portion PD to which the chip on film COF is attached is limited, there is a limit to the left and right width of the chip on film COF, but the chip on film COF The upper and lower widths may be larger. Therefore, in the present invention, by arranging an arbitrary first line L1 connecting the plurality of data input bumps 112 and an arbitrary second line L2 connecting the plurality of power input bumps 102 to be spaced apart from each other. , there is an advantage in that the left and right widths of the COF can be remarkably reduced even if the vertical width of the COF is slightly increased.

In addition, by arranging the data input bumps 112 and the power input bumps 102 on lines spaced apart from each other, bumps on the printed circuit board to be bonded to the data input bumps 112 are mistaken for the power input bumps 102. Bonding can be prevented.

Meanwhile, the present invention discloses another example of a chip-on-film capable of reducing the width of the chip-on-film.

FIG. 11 is a plan view showing a chip-on-film according to another embodiment of the present invention, and FIG. 12 is a cross-sectional view taken along the line AA′ of FIG. 11 . In the following, the same reference numerals will be given to the same components as those of FIG. 9 described above.

Referring to FIG. 11 , a chip on film (COF) according to another embodiment of the present invention includes a base film (BF) and a semiconductor chip (SC) mounted on the base film (BF). A plurality of leads 101, 111, and 115 connected from the first terminal unit UDA located on one side of the base film BF to the second terminal unit LDA are included. A plurality of input bumps 102 and 112 are positioned at ends of the plurality of leads 101 and 111 located in the first terminal unit UDA. A plurality of output bumps 106 and 116 are positioned at ends of the plurality of leads 101 and 115 located in the second terminal part LDA.

The data signal transmission path includes a data input lead 111 , a data input bump 112 , a data output lead 115 and a data output bump 116 . Since the detailed description of the data signal transmission path is the same as that of FIG. 9 described above, the description thereof will be omitted.

The power voltage transmission path includes a power lead 101 , power input bumps 102 and power output bumps 106 . In this embodiment, the power lead 101 is disposed on the other side of the base film BF.

More specifically, the data input/output leads 111 and 115, the data input/output bumps 112 and 116, the semiconductor chip SC and the power input/output bumps 102 and 116 are formed on the upper surface of the base film BF. 106) is placed. A power lead 101 is disposed on the lower surface of the base film BF. The power lead 101 connects the power input bump 102 of the first terminal unit UDA, to which the power voltage is supplied, to the power output bump 106 of the second terminal unit LDA, to which the power voltage is output. That is, one end of the power lead 101 is connected to the power input bump 102 and the other end is connected to the power output bump 106 .

In particular, as shown in FIG. 12, the base film (BF) is provided with a plurality of contact holes (CH), the power lead 101 on the lower surface of the base film (BF) is connected to the power input bump 102 and Each is connected to the power output bump 106. Since the power lead 101 overlaps the mounting area MA of the semiconductor chip SC, the width of the chip-on-film COF may be reduced. In this embodiment, the power lead 101 overlaps the semiconductor chip SC with a plurality of lines, but the power lead 101 overlapping the semiconductor chip SC may be formed in a single line shape, and the line The number of is not particularly limited.

In this embodiment, an arbitrary first line L1 connecting the plurality of data input bumps 112 and an arbitrary second line L2 connecting the plurality of power input bumps 102 may be spaced apart from each other. there is. Accordingly, since the power input bumps 102 are not disposed between the data input bumps 112, the width of the COF can be reduced by the same width occupied by the power input bumps. In particular, since the number of power input bumps ranges from tens to hundreds, the width of the chip-on-film (COF) can be remarkably reduced.

In addition, by arranging the data input bumps 112 and the power input bumps 102 on lines spaced apart from each other, bumps on the printed circuit board to be bonded to the data input bumps 112 are mistaken for the power input bumps 102. Bonding can be prevented.

As described above, since power input bumps are not disposed between data input bumps in the chip-on-film according to an embodiment of the present invention, the width of the chip-on-film can be reduced by the width occupied by the power input bumps.

In addition, the chip-on film according to an embodiment of the present invention arranges the power lead at a distance from the mounting area of the semiconductor chip, so that data input/output leads connected to the mounting area can be easily designed.

In addition, in the chip-on-film according to an embodiment of the present invention, the width of the chip-on-film can be reduced by the width occupied by the power input bumps by arranging the power input bumps, which have been disposed between the data input bumps, elsewhere. It is possible to prevent a bump on the printed circuit board to be bonded with the bump from being erroneously bonded to the power input bump.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the above-described technical configuration of the present invention can be changed into other specific forms by those skilled in the art without changing the technical spirit or essential features of the present invention. It will be appreciated that this can be implemented. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

COF: Chip on Film BF: Base Film
UDA: 1st terminal LDA: 2nd terminal
101: power lead ML: main lead
DL: branch lead 102: power input bump
111: data input lead 112: data input bump
SC: semiconductor chip MA: mounting area

Claims (15)

a base film including a first terminal unit and a second terminal unit;
a semiconductor chip mounted on a mounting area of the base film; and
a power lead extending from the first terminal part to the second terminal part so as to surround a mounting area of the semiconductor chip;
The power lead includes a main lead and a plurality of branch leads, a power input bump is positioned at an end of each of the plurality of branch leads, and a power output bump is positioned at an end of the main lead. delete According to claim 1,
The plurality of branch leads extend in a direction from the main lead toward the semiconductor chip. According to claim 3,
a plurality of first output leads connected from the first terminal part to a mounting region of the semiconductor chip; and
The chip-on-film further comprises a plurality of first input leads connected from a mounting area of the semiconductor chip to the second terminal unit. According to claim 4,
First input bumps are positioned at ends of the plurality of first input leads, respectively, and first output bumps are positioned at ends of the plurality of first output leads, respectively. According to claim 5,
The first input bump is positioned on the second terminal part. According to claim 6,
A direction in which the first input lead extends from the mounting area of the semiconductor chip and a direction in which the branch lead of the power supply lead extends face each other. According to claim 6,
An arbitrary first line connecting the plurality of first input bumps and an arbitrary second line connecting the plurality of power input bumps are spaced apart from each other. a base film including a first terminal unit and a second terminal unit;
a semiconductor chip mounted on a mounting area of one surface of the base film;
a power lead located on the other surface of the base film and extending from the first terminal unit to the second terminal unit;
a plurality of first output leads connected from the first terminal part to a mounting region of the semiconductor chip; and
a plurality of first input leads connected from a mounting area of the semiconductor chip to the second terminal;
the power lead is disposed overlapping the mounting region of the semiconductor chip;
The power lead penetrates the base film and is connected to a plurality of power input bumps located on one surface of the base film on which the semiconductor chip is mounted.
First input bumps are positioned at ends of the plurality of first input leads, respectively, and first output bumps are positioned at ends of the plurality of first output leads, respectively;
The plurality of first output leads, the plurality of first input leads, the first input bumps, and the first output bumps are located on the one surface of the base film. delete delete delete According to claim 9,
The first input bump is positioned on the second terminal part. According to claim 13,
An arbitrary first line connecting the plurality of first input bumps and an arbitrary second line connecting the plurality of power input bumps are spaced apart from each other. a substrate including a display unit;
a pad part disposed below the substrate; and
It includes a plurality of chip-on-films attached to the pad part,
The chip-on-film,
a base film including a first terminal unit and a second terminal unit;
a semiconductor chip mounted on a mounting area of the base film; and
a power lead extending from the first terminal part to the second terminal part so as to surround a mounting area of the semiconductor chip;
The power lead includes a main lead and a plurality of branch leads, a power input bump is positioned at an end of each of the plurality of branch leads, and a power output bump is positioned at an end of the main lead.

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