KR102360353B1 - Display Device - Google Patents

Abstract

A display device according to an embodiment of the present invention includes a display unit and a non-display unit located on a substrate, a ground unit located in the non-display unit to which a ground voltage is applied, a power line unit applying power to the display unit, and a protection facing the substrate It includes a member, and the ground portion overlaps the protective member.

Description

Display Device

The present invention relates to a display device, and more particularly, to a display device capable of preventing damage by a foreign material or damage by a deposition mask in a non-display part.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. The display device field has rapidly changed to a thin, light, and large-area Flat Panel Display Device (FPD) that replaces a bulky cathode ray tube (CRT). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device. : ED), etc.

Among them, the organic light emitting display device is a self-luminous device that emits light by itself, and has advantages of fast response speed, luminous efficiency, luminance, and viewing angle. In particular, the organic light emitting display device can be formed on a flexible substrate, and can be driven at a lower voltage and consume less power than a plasma display panel or an inorganic electroluminescence (EL) display. And it has the advantage of excellent color.

However, there is a problem in that the organic light emitting display device is damaged by a foreign material or a deposition mask during a manufacturing process.

Accordingly, the present invention provides a display device capable of preventing damage due to a foreign material or damage due to a deposition mask in a non-display unit.

In order to achieve the above object, in a display device according to an embodiment of the present invention, a display unit and a non-display unit located on a substrate, and a ground unit located on the non-display unit, to which a ground voltage is applied, and power are applied to the display unit and a power line unit that is, and a protection member facing the substrate, wherein the ground unit overlaps with the protection member.

The ground part is adjacent to the outer edge of the substrate, and the power line part is adjacent to the display part.

The power line unit includes a power line bar to which power is applied from the outside, and a power line for applying power from the power line bar to the display unit, and includes a plurality of power branch lines connecting the power line bar and the power line. do.

and a shield layer pattern positioned between the plurality of power branch lines.

A reference voltage line unit for applying a reference voltage to the display unit is further included between the ground unit and the power line unit.

The ground unit includes a ground line and a ground auxiliary line connected to the ground line.

The ground auxiliary line has a plurality of patterns.

An auxiliary pattern overlapping the ground auxiliary line is further included on the ground auxiliary line.

The ground unit includes a ground line and a ground branch line branched from the ground line.

The non-display unit includes a chip-on film for applying a power or data driving signal, LOG lines for transferring a power or data driving signal from the chip-on-film to the display unit, and a LOG ground line to which a ground signal is applied.

The non-display unit further includes a GIP driver disposed between the display unit and the ground unit.

In addition, a display device according to an embodiment of the present invention includes a display unit and a non-display unit located on a substrate, a ground unit located in the non-display unit, to which a ground voltage is applied, and a power line for applying power to the display unit. a power line unit and a protection member facing the substrate; the ground unit overlapping the protection member; the power line unit including a contact pad connected to the power line bar; a power line bar to which power is applied and a power line for applying power from the power line bar to the display unit, and a plurality of power branch lines connecting the power line bar and the power line, the plurality of power sources and a shield layer pattern positioned between the branch lines.

The display unit includes a plurality of sub-pixels, and any one of the plurality of sub-pixels includes a shield layer disposed on the substrate, a buffer layer disposed on the shield layer, and a buffer layer disposed on the buffer layer, and includes a semiconductor layer, a gate A thin film transistor including an electrode, a source electrode and a drain electrode, an overcoat layer positioned on the thin film transistor, an organic light emitting diode positioned on the overcoat layer, the organic light emitting diode including a first electrode, an organic film layer, and a second electrode, and the and a bank layer positioned between the first electrode and the organic layer to define a pixel.

Ends of the bank layer and the overcoat layer are positioned between the contact pad and the power line.

The organic layer and the second electrode do not overlap the contact pad.

It further includes an auxiliary pattern positioned on the shield layer pattern and overlapping the shield layer pattern.

In addition, a display device according to an embodiment of the present invention includes a display unit and a non-display unit located on a substrate, a ground unit located in the non-display unit, to which a ground voltage is applied, a power line unit applying power to the display unit, and and a floating part positioned between the ground part and the power line part, and a protection member facing the substrate.

The floating part includes a floating floating line.

The floating line is integrally formed or formed in a plurality of patterns.

It is positioned on the floating line and further includes an auxiliary pattern overlapping the floating line.

The organic light emitting display device according to an embodiment of the present invention reduces the reference voltage line portion and forms the ground portion, thereby preventing the polarizing plate from being damaged because current does not flow between the protective member and the ground line even if a foreign object is generated on the outside of the substrate. can be prevented

In addition, in the organic light emitting display device according to an embodiment of the present invention, power can be reinforced by omitting the reference voltage line and adding a power branch line branched from the power line bar. Furthermore, it is possible to prevent the power branch lines from being reflected to the user by forming shield layer patterns between the power branch lines.

In addition, in the organic light emitting display device according to an embodiment of the present invention, a ground auxiliary line is formed between the ground line and the power line unit, and the ground auxiliary line is formed on the same layer as the shield layer, so that the second buffer layer and the gate are formed over the ground auxiliary line. An insulating film, an interlayer insulating film, and a first passivation film may be formed. Therefore, it is possible to protect the ground auxiliary line from being dented by the deposition mask during the process. In addition, by forming the auxiliary pattern on the ground auxiliary line, it is possible to protect the ground auxiliary line from dents that may occur during the process.

In addition, in the organic light emitting display device according to an embodiment of the present invention, since the overcoat layer and the bank layer are extended to the outside of the substrate, only the upper part of the bank layer is damaged even if it is photographed by the deposition mask. can reduce the likelihood that

In addition, in the organic light emitting display device according to an embodiment of the present invention, by forming the auxiliary pattern on the shield layer pattern, it is possible to further protect the shield layer pattern from dents that may occur during the process.

In addition, the organic light emitting display device according to an embodiment of the present invention has the advantage of preventing a short circuit due to foreign matter between the second electrode and the floating part by forming a floating part having a floating line between the ground line and the power line part. There is this.

In addition, by forming the floating line in a plurality of patterns, it is possible to minimize the amount of static electricity that each pattern may have, thereby preventing defects due to static electricity.

In addition, by forming the floating line on the same layer as the shield layer so as to be adjacent to the substrate, there is an advantage in that it can be protected from dents due to a plurality of insulating layers present on the floating line.

In addition, by forming the auxiliary pattern on the floating line, it is possible to further protect the floating line from dents that may occur during the process.

1 is a schematic block diagram of an organic light emitting diode display;
2 is a first exemplary diagram illustrating a circuit configuration of a sub-pixel;
3 is a second exemplary diagram illustrating a circuit configuration of a sub-pixel;
4 is a plan view illustrating an organic light emitting display device according to an embodiment of the present invention.
5 is a cross-sectional view illustrating a sub-pixel portion of an organic light emitting diode display according to an exemplary embodiment.
6 is a plan view illustrating a portion of a non-display portion of an organic light emitting diode display;
7 is a cross-sectional view taken along line AB of FIG. 6 .
8 is a plan view illustrating a part of a non-display part of an organic light emitting diode display according to a first exemplary embodiment of the present invention.
Fig. 9 is a cross-sectional view taken along the line CD of Fig. 8;
10 is a plan view illustrating a part of a non-display portion of an organic light emitting diode display according to a first exemplary embodiment of the present invention;
11 is a cross-sectional view taken along the cut line EF of FIG. 10 .
12 is a plan view illustrating a portion of a non-display portion of an organic light emitting diode display according to a first exemplary embodiment of the present invention.
13 is a cross-sectional view taken along line GH of FIG. 12 .
14 is a plan view illustrating another example of a non-display unit of the organic light emitting diode display according to the first exemplary embodiment of the present invention.
15 is a plan view illustrating another example of a non-display unit of the organic light emitting diode display according to the first exemplary embodiment of the present invention.
16 is a cross-sectional view taken along line IJ of FIG. 15 .
17 and 18 are plan views illustrating different examples of a non-display unit of the organic light emitting diode display according to the first embodiment of the present invention.
19 is a cross-sectional view taken along the cut line KL of FIG.
20 is a plan view illustrating a pad part of the organic light emitting diode display according to the first embodiment of the present invention;
21 is a cross-sectional view taken along line MN of FIG. 20;
22 is a plan view illustrating a GIP driver of the organic light emitting display device according to the first embodiment of the present invention;
23 is a cross-sectional view taken along line OP of FIG. 22 .
24 is a plan view illustrating a non-display unit of an organic light emitting diode display according to a second exemplary embodiment of the present invention.
25 is a cross-sectional view taken along the cut-out line QR of FIG.
26 is a plan view illustrating another example of a non-display unit of an organic light emitting diode display according to a second exemplary embodiment of the present invention;
Fig. 27 is a cross-sectional view taken along the cut line ST of Fig. 26;
28 is a plan view illustrating another example of a non-display unit of an organic light emitting diode display according to a second exemplary embodiment of the present invention;
29 is a cross-sectional view taken along the cut line UV of FIG.
30 is a plan view illustrating a non-display unit of an organic light emitting display device according to a third exemplary embodiment of the present invention;
Fig. 31 is a cross-sectional view taken along the line WX of Fig. 30;
32 is a plan view illustrating another example of a non-display unit of an organic light emitting diode display according to a third exemplary embodiment of the present invention.
33 is a plan view illustrating another example of a non-display unit of an organic light emitting diode display according to a third exemplary embodiment of the present invention;
Fig. 34 is a cross-sectional view taken along the line YZ of Fig. 33;
35 is a plan view illustrating another example of a non-display unit of an organic light emitting diode display according to a third exemplary embodiment of the present invention;
Fig. 36 is a cross-sectional view taken along line A'-B' of Fig. 35;
37 is an image showing a damaged bank layer of an organic light emitting diode display.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of writing the specification, and may be different from the component names of the actual product.

A display device according to the present invention is a display device in which a display element is formed on a glass substrate or a flexible substrate. As an example of the display device, an organic light emitting display device, a liquid crystal display device, an electrophoretic display device, etc. can be used, but in the present invention, an organic light emitting display device will be described as an example. The organic light emitting display device includes an organic layer made of an organic material between a first electrode that is an anode and a second electrode that is a cathode. Therefore, the holes supplied from the first electrode and the electrons supplied from the second electrode combine in the organic layer to form an exciton, a hole-electron pair, and emit light by the energy generated when the exciton returns to the ground state. It is a self-luminous display device.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram of an organic light emitting diode display, FIG. 2 is a first exemplary diagram illustrating a circuit configuration of a sub-pixel, and FIG. 3 is a second exemplary diagram illustrating a circuit configuration of a sub-pixel.

Referring to FIG. 1 , the organic light emitting diode display includes an image processor 10 , a timing controller 20 , a data driver 30 , a gate driver 40 , and a display panel 50 .

The image processing unit 10 outputs a data enable signal DE along with the data signal DATA supplied from the outside. The image processing unit 10 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of description. The image processing unit 10 is formed in the form of an IC (Integrated Circuit) on the system circuit board.

The timing controller 20 receives the data signal DATA from the image processing unit 10 as well as a driving signal including a data enable signal DE or a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

The timing controller 20 includes a gate timing control signal GDC for controlling an operation timing of the gate driver 40 and a data timing control signal DDC for controlling an operation timing of the data driver 30 based on the driving signal. to output The timing controller 20 is formed in the form of an IC on the control circuit board.

The data driver 30 samples and latches the data signal DATA supplied from the timing controller 20 in response to the data timing control signal DDC supplied from the timing controller 20 , converts it into a gamma reference voltage, and outputs it . The data driver 30 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 30 is attached to the substrate in the form of an IC.

The gate driver 40 outputs a gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 20 . The gate driver 40 outputs a gate signal through the gate lines GL1 to GLm. The gate driver 40 is formed in the form of an IC on the gate circuit board or in the form of a gate in panel (GIP) on the display panel 50 .

The display panel 50 displays an image in response to the data signal DATA and the gate signal supplied from the data driver 30 and the gate driver 40 . The display panel 50 includes sub-pixels SP displaying an image.

Referring to FIG. 2 , one sub-pixel includes a switching transistor SW, a driving transistor DR, a compensation circuit CC, and an organic light emitting diode (OLED). The organic light emitting diode OLED operates to emit light according to a driving current formed by the driving transistor DR.

The switching transistor SW performs a switching operation such that the data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst in response to the gate signal supplied through the gate line GL1 . The driving transistor DR operates so that a driving current flows between the power line VDD and the ground part GND according to the data voltage stored in the capacitor Cst. The compensation circuit CC is a circuit for compensating the threshold voltage of the driving transistor DR. Also, a capacitor connected to the switching transistor SW or the driving transistor DR may be located inside the compensation circuit CC. The compensation circuit CC is composed of one or more thin film transistors and a capacitor. The configuration of the compensation circuit CC varies greatly depending on the compensation method, and detailed examples and descriptions thereof will be omitted.

In addition, as shown in FIG. 3 , when the compensation circuit CC is included, the sub-pixel further includes a signal line and a power supply line for driving the compensation thin film transistor and supplying a specific signal or power. The gate line GL1 connects the first-first gate line GL1a for supplying a gate signal to the switching transistor SW and the first-second gate line GL1b for driving the compensation thin film transistor included in the sub-pixel. may include In addition, the added power line may be defined as an initialization power line INIT for initializing a specific node of the sub-pixel to a specific voltage. However, this is only an example and is not limited thereto.

Meanwhile, in FIGS. 2 and 3 , the compensation circuit CC is included in one sub-pixel as an example. However, when the subject of compensation is located outside the sub-pixel, such as the data driver 30 , the compensation circuit CC may be omitted. That is, one sub-pixel is basically composed of a 2T (Transistor) 1C (Capacitor) structure including a switching transistor (SW), a driving transistor (DR), a capacitor and an organic light emitting diode (OLED), but a compensation circuit (CC) When is added, it may be variously configured as 3T1C, 4T2C, 5T2C, 6T2C, 7T2C, and the like. In addition, although the compensation circuit CC is shown to be positioned between the switching transistor SW and the driving transistor DR in FIGS. 2 and 3 , it may be further positioned between the driving transistor DR and the organic light emitting diode (OLED). may be The position and structure of the compensation circuit CC are not limited to FIGS. 2 and 3 .

4 is a plan view illustrating an organic light emitting display device according to an embodiment of the present invention. 5 is a cross-sectional view illustrating a sub-pixel portion of an organic light emitting diode display according to an exemplary embodiment.

Referring to FIG. 4 , the organic light emitting display device includes a display unit A/A and a non-display unit N/A on a substrate SUB. The non-display unit N/A includes a GIP driver GIP disposed on left and right sides of the substrate SUB, respectively, and a pad unit PD disposed under the substrate SUB. In the display unit A/A, a plurality of sub-pixels SP are disposed to emit light of R, G, B or R, G, B, and W to realize full color. The GIP driver GIP applies a gate driving signal to the display unit A/A. The pad part PD is disposed on one side, for example, a lower side of the display part A/A, and chip-on-films COFs are attached to the pad part DP. A data signal and power applied through the chip-on-film COF are applied to a plurality of signal lines (not shown) connected from the display unit A/A.

Hereinafter, a cross-sectional structure of a sub-pixel (SP) region of an organic light emitting diode display will be described with reference to FIG. 5 of the present invention.

Referring to FIG. 5 , in the organic light emitting diode display according to an exemplary embodiment of the present invention, a first buffer layer BUF1 is positioned on a substrate SUB. The substrate SUB may be a flexible substrate or a glass substrate, and the flexible substrate may be a resin substrate such as flexible polyimide. The first buffer layer BUF1 serves to protect a thin film transistor formed in a subsequent process from impurities such as alkali ions leaking from the substrate SUB. The buffer layer BUF may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof.

A shield layer LS is positioned on the first buffer layer BUF1. The shield layer LS blocks external light from being incident and serves to prevent photocurrent from being generated in the thin film transistor. A second buffer layer BUF2 is positioned on the shield layer LS. The second buffer layer BUF2 serves to protect the thin film transistor formed in a subsequent process from impurities such as alkali ions leaking from the shield layer LS. The second buffer layer BUF2 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

The semiconductor layer ACT is positioned on the second buffer layer BUF2 . The semiconductor layer ACT may be formed of a silicon semiconductor or an oxide semiconductor. The silicon semiconductor may include amorphous silicon or crystallized polycrystalline silicon. Here, polycrystalline silicon has high mobility (100cm2/Vs or more), low energy consumption, and excellent reliability. have. On the other hand, since the oxide semiconductor has a low off-current, it is suitable for a switching TFT that has a short on-time and a long off-time. In addition, since the off current is small, the voltage holding period of the pixel is long, which is suitable for a display device requiring low-speed driving and/or low power consumption. In addition, the semiconductor layer ACT includes a drain region and a source region including p-type or n-type impurities, and includes a channel therebetween.

A gate insulating layer GI is positioned on the semiconductor layer ACT. The gate insulating layer GI may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof. The gate electrode GA is positioned on the gate insulating layer GI in a predetermined region of the semiconductor layer ACT, that is, in a position corresponding to the channel in which the impurity is implanted. The gate electrode GA is selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It is formed of any one or an alloy thereof. In addition, the gate electrode GA is a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multi-layer made of any one selected from or alloys thereof. For example, the gate electrode GA may be a double layer of molybdenum/aluminum-neodymium or molybdenum/aluminum.

An interlayer insulating layer ILD that insulates the gate electrode GA is disposed on the gate electrode GA. The interlayer insulating layer ILD may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. Contact holes CH exposing a portion of the semiconductor layer ACT are positioned in partial regions of the interlayer insulating layer ILD and the gate insulating layer GI.

A drain electrode DE and a source electrode SE are positioned on the interlayer insulating layer ILD. The drain electrode DE is connected to the semiconductor layer ACT through a contact hole CH exposing the drain region of the semiconductor layer ACT, and the source electrode SE exposes the source region of the semiconductor layer ACT. It is connected to the semiconductor layer ACT through the contact hole CH. The source electrode SE and the drain electrode DE may be formed of a single layer or a multilayer, and when the source electrode SE and the drain electrode DE are a single layer, molybdenum (Mo), aluminum (Al), chromium It may be made of any one selected from the group consisting of (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, when the source electrode SE and the drain electrode DE are multi-layered, a double layer of molybdenum/aluminum-neodymium, a triple layer of titanium/aluminum/titanium, molybdenum/aluminum/molybdenum or molybdenum/aluminum-neodymium/molybdenum can be made with Accordingly, the thin film transistor TFT including the semiconductor layer ACT, the gate electrode GA, the drain electrode DE, and the source electrode SE is configured.

A first passivation layer PAS1 is positioned on the substrate SUB including the thin film transistor TFT. The first passivation layer PAS1 is an insulating layer that protects an underlying device, and may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. The color filter CF is positioned on the first passivation layer PAS1 . The color filter CF serves to convert white light emitted from the organic light emitting diode OLED into red, green, or blue. An overcoat layer OC is positioned on the color filter CF. The overcoat layer OC may be a planarization layer for alleviating a step difference in a lower structure, and is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. The overcoat layer OC may be formed by a method such as spin on glass (SOG) in which the organic material is coated in a liquid form and then cured.

A via hole VIA exposing the drain electrode DE is positioned in a partial region of the overcoat layer OC. An organic light emitting diode (OLED) is positioned on the overcoat layer (OC). In more detail, the first electrode ANO is positioned on the overcoat layer OC. The first electrode ANO serves as a pixel electrode and is connected to the drain electrode DE of the thin film transistor TFT through the via hole VIA. The first electrode ANO is an anode and may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). When the first electrode ANO is a reflective electrode, the first electrode ANO further includes a reflective layer. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or an alloy thereof, preferably APC (silver/palladium/copper alloy).

A bank layer BNK partitioning pixels is positioned on the substrate SUB including the first electrode ANO. The bank layer BNK is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. In the bank layer BNK, the pixel defining part OP exposing the first electrode ANO is positioned. An organic layer EML contacting the first electrode ANO is positioned on the front surface of the flexible substrate PI. The organic layer EML is a layer that emits light by combining electrons and holes, and may include a hole injection layer or a hole transport layer between the organic layer EML and the first electrode ANO, and on the organic layer EML It may include an electron transport layer or an electron injection layer.

The second electrode CAT is positioned on the organic layer EML. The second electrode CAT is located on the front surface of the display unit A/A, and as a cathode electrode, it may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function. have. When the second electrode CAT is a transmissive electrode, it has a thickness that is thin enough to transmit light, and when it is a reflective electrode, it has a thickness that is thick enough to reflect light. A second passivation layer PAS2 is positioned on the second electrode CAT.

A protection member FSM is attached to the upper surface of the substrate SUB on which the thin film transistor TFT and the organic light emitting diode OLED are formed through the adhesive layer ADL. The protective member FSM may be a metal thin film.

In the organic light emitting diode display configured as described above, a protective member made of metal and a reference voltage line formed on a substrate are disposed to face each other in the non-display portion. In order to describe this in detail, reference will be made to the following drawings.

6 is a plan view illustrating a portion of a non-display portion of an organic light emitting diode display device, and FIG. 7 is a cross-sectional view taken along the line A-B of FIG. 6 .

Referring to FIG. 6 , in the non-display unit of the organic light emitting diode display, a display unit A/A, a power line unit EVDP, and a reference voltage line unit EVSP are positioned on a substrate SUB. In the power line unit EVDP, a power line EVDL extending from the display unit A/A is connected to the power line bar EVDD of the power line unit EVDP. The reference voltage line part EVSP is connected to the reference voltage line EVSS through the first and second contact pads CCP1 and CCP2 by extending the second electrode CAT.

Referring to FIG. 7 in more detail, the first buffer layer BUF1, the second buffer layer BUF2, and the gate insulating layer GI are positioned on the substrate SUB, and the reference voltage line EVSS is formed on the gate insulating layer GI, The power line bar EVDD is located. The reference voltage line EVSS is positioned in the reference voltage line part EVSP, and the power line bar EVDD is positioned in the power line part EVDP. The interlayer insulating layer ILD is positioned on the reference voltage line EVSS and the power line bar EVDD, and the first contact pad CCP1 and the power supply line EVDL are positioned on the interlayer insulating layer ILD. The first contact pad CCP1 is connected to the reference voltage line EVSS of the reference voltage line unit EVSP, and the power line EVDL is connected to the power line bar EVDD of the power line unit EVDP. The first passivation layer PAS1 is positioned on the first contact pad CCP1 and the power line EVDL, and the second contact pad CCP2 is positioned on the first passivation layer PAS1. The second contact pad CCP2 is connected to the first contact pad CCP1 of the reference voltage line unit EVSP.

An overcoat layer OC, a bank layer BNK, an organic layer OLE, a second electrode CAT, and a second passivation layer PAS2 are positioned in the power line unit EVDP and the display unit A/A. In the reference voltage line part EVSP, the second electrode CAT of the display part A/A extends and is connected to the second contact pad CCP2, so that the second electrode CAT is electrically connected to the reference voltage line EVSS. is connected to The second passivation layer PAS2 of the display unit A/A also extends to the reference voltage line unit EVSP to cover the second electrode CAT. The substrate SUB on which the second passivation layer PAS2 is formed is bonded to the protection member FSM through an adhesive FSA to constitute an organic light emitting display device.

In the above-described organic light emitting display device, a conductive foreign material may be generated between the protective member FSM and the substrate SUB during the process. In this case, the reference voltage line EVSS has 0V, so even if the reference voltage line EVSS is short-circuited with the metal protection member FSM by a foreign material, no current flow occurs due to the same potential. However, when a predetermined potential is applied to the reference voltage line EVSS during driving for pixel compensation, a potential difference with the protection member FSM is formed, thereby generating a current flow. Accordingly, there is a problem in that heat is generated while current flows between the reference voltage line EVSS and the protection member FSM, and the polarizing plate attached to the surface of the protection member is damaged.

Accordingly, the present invention discloses an organic light emitting display device according to the following embodiments in order to prevent damage to the polarizing plate due to the aforementioned foreign matter. Hereinafter, the same reference numerals are attached to the same components as those of FIGS. 6 and 7 to simplify the description.

<First embodiment>

8 is a plan view illustrating a portion of a non-display portion of the organic light emitting diode display according to the first exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line C-D of FIG. 8 .

Referring to FIG. 8 , in the non-display unit of the organic light emitting diode display, a display unit A/A, a power line unit EVDP, a reference voltage line unit EVSP, and a ground unit GND are positioned on a substrate SUB. do. The ground part GND is disposed between the reference voltage line part EVSP and the outermost part of the substrate SUB, and the ground line GNL is positioned.

In more detail, referring to FIG. 9 , a first buffer layer BUF1 , a second buffer layer BUF2 , and a gate insulating layer GI are positioned on a substrate SUB, and a reference voltage line EVSS is formed on the gate insulating layer GI, A power line bar EVDD and a ground line GNL are positioned. The reference voltage line EVSS is positioned in the reference voltage line part EVSP, and the power line bar EVDD is positioned in the power line part EVDP. The ground line GNL is positioned at the ground part GND and is disposed between the reference voltage line part EVSP and the outermost part of the substrate SUB.

The interlayer insulating layer ILD is positioned on the reference voltage line EVSS, the power line bar EVDD, and the ground line GNL, and the first contact pad CCP1 and the power line EVDL are positioned on the interlayer insulating layer ILD. do. The first contact pad CCP1 is connected to the reference voltage line EVSS of the reference voltage line unit EVSP, and the power line EVDL is connected to the power line bar EVDD of the power line unit EVDP. The first passivation layer PAS1 is positioned on the first contact pad CCP1 and the power line EVDL, and the second contact pad CCP2 is positioned on the first passivation layer PAS1. The second contact pad CCP2 is connected to the first contact pad CCP1 of the reference voltage line unit EVSP.

An overcoat layer OC, a bank layer BNK, an organic layer OLE, a second electrode CAT, and a second passivation layer PAS2 are positioned in the power line unit EVDP and the display unit A/A. In the reference voltage line part EVSP, the second electrode CAT of the display part A/A extends and is connected to the second contact pad CCP2, so that the second electrode CAT is electrically connected to the reference voltage line EVSS. is connected to The second passivation layer PAS2 of the display unit A/A also extends to the reference voltage line unit EVSP to cover the second electrode CAT. The substrate SUB on which the second passivation layer PAS2 is formed is bonded to the protection member FSM through an adhesive FSA to constitute an organic light emitting display device.

In the organic light emitting display device configured as described above, the reference voltage line portion is reduced and the ground portion is formed, so that even if a foreign material is generated outside the substrate, the foreign material contacts the ground line. Although not illustrated, the ground line GNL is applied with a ground voltage, that is, a 0V voltage from the pad part. Accordingly, since no current flows between the protective member and the ground line, it is possible to prevent the polarizing plate from being damaged.

On the other hand, the organic light emitting display device according to the first embodiment of the present invention can also be applied to other structures.

10 is a plan view illustrating a portion of a non-display part of an organic light emitting diode display according to a first exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along line E-F of FIG. 10 .

Referring to FIG. 10 , in the non-display part of the organic light emitting diode display, a display part A/A, a power line part EVDP, and a ground part GND are positioned on a substrate SUB. Since the embodiment in which the reference voltage line part EVSP does not exist is disclosed in FIG. 10, only the power line part EVDP and the ground part GND are disclosed. Here, the power line bar EVDD of the power line unit EVDP includes a plurality of power branch lines EVDBL connected to the power line EVDL. The plurality of power branch lines EVDBL acts as a structure for reinforcing power. At this time, shield layer patterns LSP are inserted in the space between the power branch lines EVDBL to prevent the power branch lines EVDBL from being reflected to the user.

11, the first buffer layer BUF1, the second buffer layer BUF2, and the gate insulating layer GI are positioned on the substrate SUB, and the power line bar EVDD is formed on the gate insulating layer GI; A power branch line EVDBL and a ground line GNL are positioned. The power line bar EVDD and the power branch line EVDBL are positioned in the power line unit EVDP. The ground line GNL is positioned at the ground part GND and is disposed between the power line part EVDP and the outermost part of the substrate SUB.

The interlayer insulating layer ILD is positioned on the power line bar EVDD, the power branch line EVDBL, and the ground line GNL, and the first contact pad CCP1 and the power line EVDL are positioned on the interlayer insulating layer ILD. do. The first contact pad CCP1 is connected to the power line bar EVDD and serves to lower the resistance. The power line EVDL is connected to the power line bar EVDD of the power line unit EVDP through the power branch line EVDBL. A first passivation layer PAS1 is positioned on the first contact pad CCP1 and the power line EVDL.

An overcoat layer OC, a bank layer BNK, an organic layer OLE, a second electrode CAT, and a second passivation layer PAS2 are positioned in the power line unit EVDP and the display unit A/A. The second electrode CAT of the display unit A/A is directly connected to the pad unit without the reference voltage line unit. The substrate SUB on which the second passivation layer PAS2 is formed is bonded to the protection member FSM through an adhesive FSA to constitute an organic light emitting display device.

In the organic light emitting display device configured as described above, power may be reinforced by omitting the reference voltage line portion and adding a power branch line branched from the power line bar. Furthermore, it is possible to prevent the power branch lines from being reflected to the user by forming shield layer patterns between the power branch lines. In addition, by forming the ground portion in the outer portion of the substrate, even if a foreign material is generated in the outer portion of the substrate, current does not flow between the protective member and the ground line, thereby preventing the polarizing plate from being damaged.

The above-described organic light emitting display devices have been disclosed to solve a problem caused by foreign matter between the protective member and the ground portion or between the protective member and the reference voltage line portion. On the other hand, since 0V or a constant voltage is also applied to the second electrode, damage by foreign substances may occur even between the second electrode and the ground portion. Accordingly, an organic light emitting display device for preventing damage that may occur between the second electrode and the ground portion will be described below.

12 is a plan view illustrating a portion of a non-display part of an organic light emitting diode display according to a first embodiment of the present invention, FIG. 13 is a cross-sectional view taken along the cut line GH of FIG. 12 , and FIG. 14 is a first embodiment of the present invention It is a plan view showing another example of the non-display part of the organic light emitting diode display according to FIG. Also, FIG. 15 is a plan view illustrating another example of a non-display part of the organic light emitting diode display according to the first embodiment of the present invention, and FIG. 16 is a cross-sectional view taken along the cut line I-J of FIG. 15 .

Referring to FIG. 12 , in the non-display unit of the organic light emitting diode display, a display unit A/A, a power line unit EVDP, and a ground unit GND are positioned on a substrate SUB. The ground part GND includes a ground line GNL and a ground auxiliary line GNLS connected to the ground line GNL. The ground auxiliary line GNLS is disposed between the power line unit EVDP and the ground line GNL, and is connected to the ground line GNL through the connection pattern CNP. The ground auxiliary line GNLS fills the space between the power line part EVDP and the ground line GNL, thereby preventing an appearance defect caused by a difference in light and shade to the user.

13 , the first buffer layer BUF1 is positioned on the substrate SUB, and the ground auxiliary line GNLS is positioned on the first buffer layer BUF1. The ground auxiliary line GNLS is made of the same material as the shield layer (not shown) and is disposed on the same layer. The ground auxiliary line GNLS is located in the ground part GND. The second buffer layer BUF2 and the gate insulating layer GI are positioned on the ground auxiliary line GNLS, and the power line bar EVDD and the ground line GNL are positioned on the gate insulating layer GI. The power line bar EVDD is located on the power line unit EVDP. The ground line GNL is positioned at the ground part GND and is disposed between the power line part EVDP and the outermost part of the substrate SUB.

The interlayer insulating layer ILD is positioned on the power line bar EVDD and the ground line GNL, and the connection pattern CNP and the power line EVDL are positioned on the interlayer insulating layer ILD. The connection pattern CNP serves to connect the ground line GNL and the ground auxiliary line GNLS. The power line EVDL is connected to the power line bar EVDD of the power line unit EVDP. A first passivation layer PAS1 is positioned on the connection pattern CNP and the power line EVDL. Since the configuration of the upper portion of the first passivation layer PAS1 is the same as that of the above-described embodiment, a description thereof will be omitted.

The organic light emitting display device configured as described above forms a ground auxiliary line between the ground line and the power line unit, thereby preventing an appearance defect that is displayed in contrast to the user. In addition, by forming the auxiliary ground line on the same layer as the shield layer, the second buffer layer, the gate insulating layer, the interlayer insulating layer, and the first passivation layer may be formed over the ground auxiliary line. Therefore, it is possible to protect the ground auxiliary line from being dented by the deposition mask during the process. Accordingly, there is an advantage in that it is possible to prevent a short circuit due to a foreign material between the ground auxiliary line and the second electrode.

It is disclosed that the above-described ground auxiliary line GNLS of FIG. 12 is integrally formed. However, referring to FIG. 14 , the ground auxiliary line GNLS may have a plurality of pattern shapes spaced apart from each other. When the ground auxiliary line GNLS is formed of a plurality of patterns, spaced spaces between the plurality of patterns exist even if they are printed by a deposition mask during a process, and thus the probability that the plurality of patterns will be imprinted may be reduced. However, the spacing between the plurality of patterns may be appropriately adjusted so that the patterns are not reflected to the user.

Also, referring to FIGS. 15 and 16 , an auxiliary pattern FSL may be further provided on the ground auxiliary line GNLS. The auxiliary pattern FSL is formed of a plurality of patterns so as to correspond to each of the plurality of patterns of the ground auxiliary line GNLS in a one-to-one correspondence. The auxiliary pattern FSL has a size smaller than that of the ground auxiliary line GNLS and is positioned to completely overlap the ground auxiliary line GNLS. The auxiliary pattern FSL is formed of a source/drain electrode material, and is formed of the same material as the adjacent connection pattern CNP and is positioned on the same layer. The auxiliary pattern FSL may act as a protective layer of the ground auxiliary line GNLS to protect the ground auxiliary line GNLS from dents that may occur during a process.

Meanwhile, in the organic light emitting display device according to the first embodiment of the present invention, the ground line may be formed in the same layer as the shield layer.

17 and 18 are plan views illustrating different examples of the non-display unit of the organic light emitting diode display according to the first embodiment of the present invention, and FIG. 19 is a cross-sectional view taken along line K-L of FIG. 17 .

Referring to FIG. 17 , in the non-display part of the organic light emitting diode display, a display part A/A, a power line part EVDP, and a ground part GND are positioned on a substrate SUB. The ground part GND includes only the ground line GNL. The ground line GNL is disposed on the entire ground portion GND, and fills a space between the outside of the substrate SUB and the power line portion EVDP to prevent an appearance defect caused by a difference in light and shade to a user.

Also, referring to FIG. 18 , the ground line GNL may include a ground branch line GNBL branched from the ground line GNL. The ground branch lines GNBL are disposed to be spaced apart from each other to reduce the probability that the ground branch lines GNBL are taken.

Since the cross-sectional views of FIGS. 17 and 18 are the same, referring to FIG. 19 , the first buffer layer BUF1 is positioned on the substrate SUB, and the ground line GNL is positioned on the first buffer layer BUF1. . The ground line GNL is formed of the same material as the shield layer (not shown) and is disposed on the same layer. The ground line GNL is located in the ground part GND. The second buffer layer BUF2 and the gate insulating layer GI are positioned on the ground line GNL, and the power line bar EVDD is positioned on the gate insulating layer GI. The power line bar EVDD is located on the power line unit EVDP. The configuration of the upper portion of the power line bar EVDD is omitted because there are no other features.

In the organic light emitting display device configured as described above, the second buffer layer, the gate insulating layer, the interlayer insulating layer, and the first passivation layer may be formed on the ground line by forming the ground line on the same layer as the shield layer. Accordingly, it is possible to protect the ground line from being dented by the deposition mask during the process. Accordingly, there is an advantage in that it is possible to prevent a short circuit due to a foreign material between the ground line and the second electrode.

On the other hand, the organic light emitting display device according to the first embodiment of the present invention discloses a structure capable of preventing a short circuit due to foreign matter in the pad part and the GIP driving part of the non-display part.

20 is a plan view illustrating a pad part of an organic light emitting diode display according to a first embodiment of the present invention, FIG. 21 is a cross-sectional view taken along the cut line MN of FIG. 20, and FIG. 22 is an organic light emitting diode display according to the first embodiment of the present invention. It is a plan view showing the GIP driver of the light emitting display device, and FIG. 23 is a cross-sectional view taken along the cut line OP of FIG. 22 .

Referring to FIG. 20 , the pad part of the organic light emitting display device includes a display part A/A, a LOG part LOG, and a chip-on film COF. In the LOG unit LOG, LOG lines LOGB for applying a power or data driving signal to the display unit A/A and a LOG ground line LOGG to which a ground signal is applied are located. The chip on film COF is attached to be connected to the LOG line LOGB and the LOG ground line LOGG.

In more detail, referring to FIG. 21 , the first buffer layer BUF1 , the second buffer layer BUF2 , and the gate insulating layer GI are positioned on the substrate SUB, and the LOG ground line LOGG and the gate insulating layer GI are disposed on the gate insulating layer GI. The LOG line (LOGB) is located. The LOG ground line LOGG and the LOG line LOGB are positioned on the same layer with the same material as the gate electrode. The LOG ground line LOGG and the LOG line LOGB are spaced apart from each other, and by providing the LOG ground line LOGG in the LOG part LOG, the protective member FSM and the LOG part LOG are separated by foreign substances. It can prevent a short circuit from occurring.

An interlayer insulating layer ILD is positioned on the LOG ground line LOGG and the LOG line LOGB. A source signal line SDL is positioned on the interlayer insulating layer ILD of the display unit A/A. A first passivation layer PAS1 is positioned on the source signal line SDL. Since the configuration of the upper portion of the first passivation layer PAS1 is the same as that of the above-described embodiment, a description thereof will be omitted.

The organic light emitting display device configured as described above has a LOG ground line in the pad portion to which the chip-on film is attached, so that even if a foreign material is generated in the pad portion, current does not flow between the protective member and the LOG ground line, thereby preventing the polarizer from being damaged. can be prevented

Meanwhile, referring to FIGS. 22 and 23 , a display unit A/A, a GIP driving unit GIP, and a ground unit GND are positioned on one side of the organic light emitting diode display. The ground part GND is positioned between the GIP driver GIP and the outer edge of the substrate SUB. The ground line GNL of the ground part GND is positioned on the second buffer layer BUF2 , and the GIP circuit GIPC of the GIP driver GIP is positioned. The above-described insulating layers are disposed on the ground line GNL and the GIP circuit GIPC.

In this embodiment, since the ground part GND is provided between the GIP driving part GIP and the outer periphery of the substrate SUB, even if a foreign material is generated on the periphery of the substrate SUB, a current is generated between the protective member and the ground part GND. Since it does not flow, it can prevent the polarizing plate from being damaged.

On the other hand, in the present invention, in a structure in which the reference voltage line part is omitted to reduce the bezel and the wiring of the power line part is reinforced, it is possible to prevent the problem of engraving by the deposition mask during the process. Hereinafter, the same reference numerals are given to the same components as those of the above-described first embodiment, and descriptions thereof will be omitted.

<Second embodiment>

24 is a plan view illustrating a non-display unit of an organic light emitting diode display according to a second exemplary embodiment of the present invention, and FIG. 25 is a cross-sectional view taken along line Q-R of FIG. 24 . 26 is a plan view illustrating another example of a non-display part of an organic light emitting diode display according to a second exemplary embodiment of the present invention, and FIG. 27 is a cross-sectional view taken along the line S-T of FIG. 26 . 28 is a plan view showing another example of a non-display part of an organic light emitting diode display according to a second exemplary embodiment of the present invention, and FIG. 29 is a cross-sectional view taken along line U-V of FIG. 28 .

Referring to FIG. 24 , in the non-display unit of the organic light emitting diode display, a display unit A/A, a power line unit EVDP, and a ground unit GND are positioned on a substrate SUB. Since the embodiment in which the reference voltage line part does not exist is disclosed in FIG. 24, only the power line part EVDP and the ground part GND are shown. Here, the power line bar EVDD of the power line unit EVDP includes a plurality of power branch lines EVDBL connected to the power line EVDL. The plurality of power branch lines EVDBL acts as a structure for reinforcing power. At this time, shield layer patterns LSP are inserted in the space between the power branch lines EVDBL to prevent the power branch lines EVDBL from being reflected to the user.

The first contact pad CCP1 is disposed on the power line unit EVDP to lower the resistance of the power line bar EVDD of the power line unit EVDP. In addition, the overcoat layer OC and the bank layer BNK extend from the display unit A/A to extend between the power line EVDL and the first contact pad CCP1. In addition, the second electrode CAT and the organic layer OLE are disposed to be spaced apart from the end of the bank layer BNK close to the display unit A/A. Therefore, when the overcoat layer OC and the bank layer BNK extend to the outside of the substrate SUB, only the upper portion of the bank layer BNK is damaged even if it is engraved by the deposition mask, so the second electrode CAT and the power line part ( EVDP) can reduce the possibility of a short circuit.

25, the first buffer layer BUF1, the second buffer layer BUF2, and the gate insulating layer GI are positioned on the substrate SUB, and the power line bar EVDD is formed on the gate insulating layer GI; A power branch line EVDBL and a ground line GNL are positioned. The power line bar EVDD and the power branch line EVDBL are positioned in the power line unit EVDP. The ground line GNL is positioned at the ground part GND and is disposed between the power line part EVDP and the outermost part of the substrate SUB.

The interlayer insulating layer ILD is positioned on the power line bar EVDD, the power branch line EVDBL, and the ground line GNL, and the first contact pad CCP1 and the power line EVDL are positioned on the interlayer insulating layer ILD. do. The first contact pad CCP1 is connected to the power line bar EVDD and serves to lower the resistance. The power line EVDL is connected to the power line bar EVDD of the power line unit EVDP through the power branch line EVDBL. A first passivation layer PAS1 is positioned on the first contact pad CCP1 and the power line EVDL.

An overcoat layer OC and a bank layer BNK are positioned on the first passivation layer PAS1 . The overcoat layer OC and the bank layer BNK extend from the display unit A/A to the outside of the substrate SUB and are disposed to extend between the power line EVDL and the first contact pad CCP1 . A second electrode CAT and an organic layer OLE are positioned on the bank layer BNK. The second electrode CAT and the organic layer OLE are disposed to be spaced apart from the end of the bank layer BNK close to the display unit A/A. Therefore, when the overcoat layer OC and the bank layer BNK extend to the outside of the substrate SUB, only the upper portion of the bank layer BNK is damaged even if it is engraved by the deposition mask, so the second electrode CAT and the power line part ( EVDP) can reduce the possibility of a short circuit.

The second passivation film PAS2 is positioned on the second electrode CAT, and the substrate SUB on which the second passivation film PAS2 is formed is bonded to the protective member FSM through an adhesive FSA to form an organic light emitting display device. make up

Also, referring to FIGS. 26 and 27 , an auxiliary pattern FSL may be further provided on the shield layer pattern LSP. The auxiliary pattern FSL includes a plurality of patterns so as to correspond to each of the plurality of patterns of the shield layer pattern LSP in a one-to-one correspondence. The auxiliary pattern FSL has a smaller size than the shield layer pattern LSP and is positioned to completely overlap the shield layer pattern LSP. The auxiliary pattern FSL is formed of a source/drain electrode material, and is formed of the same material as that of the first contact pad CCP1 and is positioned on the same layer. The auxiliary pattern FSL may act as a protective layer of the shield layer pattern LSP to further protect the shield layer pattern LSP from dents that may occur during a process.

26 and 27, the organic light emitting diode display device extends the overcoat layer OC and the bank layer BNK to the outside of the substrate SUB to protect the lower power line part EVDP from being stamped by the deposition mask. are doing However, the organic light emitting display device according to FIGS. 28 and 29 does not extend the overcoat layer OC and the bank layer BNK, but only includes the auxiliary pattern FSL disposed on the shield layer pattern LSP. It is also possible to protect the lower power line unit EVDP from being stamped by the mask.

Meanwhile, according to the present invention, in a structure in which the reference voltage line part is omitted to reduce the bezel, it is possible to prevent the problem of engraving by the deposition mask during the process. Hereinafter, the same reference numerals are given to the same components as those of the above-described first and second embodiments, and descriptions thereof will be omitted.

<Third embodiment>

30 is a plan view showing a non-display portion of an organic light emitting diode display according to a third embodiment of the present invention, FIG. 31 is a cross-sectional view taken along the line WX of FIG. 30, and FIG. 32 is a third embodiment of the present invention It is a plan view showing another example of the non-display part of the organic light emitting display device according to the present invention. 33 is a plan view illustrating another example of a non-display part of an organic light emitting diode display according to a third exemplary embodiment of the present invention, and FIG. 34 is a cross-sectional view taken along the line Y-Z of FIG. 33 . Also, FIG. 35 is a plan view illustrating another example of a non-display part of an organic light emitting diode display according to a third exemplary embodiment of the present invention, and FIG. 36 is a cross-sectional view taken along the cut line A′-B′ of FIG. 35 .

Referring to FIG. 30 , in the non-display part of the organic light emitting diode display, a display part A/A, a power line part EVDP, a floating part FP, and a ground part GND are positioned on a substrate SUB. The floating part FP includes a floating line FPL disposed between the power line part EVDP and the ground part GND. The floating part FP fills a space between the power line part EVDP and the ground line GNL to prevent an appearance defect caused by a difference in light and shade to a user. In addition, since the floating part FP floats even when a dent by the deposition mask occurs, it is possible to prevent a short circuit with the second electrode from occurring.

In more detail, referring to FIG. 31 , a first buffer layer BUF1 , a second buffer layer BUF2 , and a gate insulating layer GI are positioned on a substrate SUB. A power line bar EVDD, a floating line FPL, and a ground line GNL are positioned on the gate insulating layer GI. The power line bar EVDD is positioned on the power line part EVDP, and the ground line GNL is positioned on the ground part GND. The floating line FPL is positioned between the power line bar EVDD and the ground line GNL, but is made of the same material and on the same layer.

The interlayer insulating layer ILD is positioned on the power line bar EVDD, the floating line FPL, and the ground line GNL, and the power line EVDL is positioned on the interlayer insulating layer ILD, so that the power supply of the power line unit EVDP is It is connected to the line bar EVDD. A first passivation layer PAS1 is positioned on the power line EVDL. Since the configuration of the upper portion of the first passivation layer PAS1 is not different from the above-described embodiments, a description thereof will be omitted.

The organic light emitting display device configured as described above forms a floating portion in which a floating line is formed between the ground line and the power line portion, thereby preventing an appearance defect displayed by light and shade to a user. In addition, due to the floating part, there is an advantage in that it is possible to prevent a short circuit between the second electrodes due to foreign matter.

Although it has been described that the above-described floating line FPL of the floating part FP is formed of the same material as that of the ground line GNL and the power line bar EVDD and disposed on the same layer, the floating line FPL is formed of the same material as the shield layer. may be disposed on the same floor.

Referring to FIG. 32 , the floating line FPL of the above-described floating part FP may be formed of one integral line, and as illustrated in FIG. 33 , may be formed of a plurality of patterns spaced apart from each other. When the floating line FPL is formed of a plurality of patterns, spaced spaces between the plurality of patterns exist even if the floating line FPL is printed by a deposition mask during a process, so that the probability that the plurality of patterns are imprinted may be reduced. However, the spacing between the plurality of patterns may be appropriately adjusted so that the patterns are not reflected to the user. In addition, when the floating line FPL is formed of a plurality of patterns, the amount of static electricity that each pattern may have is minimized to prevent defects due to static electricity.

Referring to FIGS. 32 and 34 showing cross-sections of FIGS. 32 and 33 , the first buffer layer BUF1 is positioned on the substrate SUB, and the floating line FPL is positioned on the first buffer layer BUF1 . The floating line FPL is formed of the same material as the shield layer (not shown) of the display unit A/A and is positioned on the same layer. In particular, when the floating line FPL is made of a metal such as MoTi, it is possible to reduce the amount of static electricity in the floating line FPL to prevent damage due to static electricity.

A second buffer layer BUF2 and a gate insulating layer GI are positioned on the floating line FPL. A power line bar EVDD and a ground line GNL are positioned on the gate insulating layer GI. The power line bar EVDD is positioned in the power line part EVDP and the ground line GNL is positioned in the ground part GND. The above-described floating line FPL is positioned between the power line bar EVDD and the ground line GNL.

The interlayer insulating layer ILD is positioned on the power line bar EVDD and the ground line GNL, and the power line EVDL is positioned on the interlayer insulating layer ILD, so that it is connected to the power line bar EVDD of the power line unit EVDP. connected A first passivation layer PAS1 is positioned on the power line EVDL. Since the configuration of the upper portion of the first passivation layer PAS1 is not different from the above-described embodiments, a description thereof will be omitted.

The organic light emitting display device configured as described above forms a floating portion having a floating line formed between the ground line and the power line portion, thereby preventing an appearance defect displayed by light and shade to a user. In addition, due to the floating part, there is an advantage in that it is possible to prevent a short circuit between the second electrodes due to foreign matter. In addition, by forming the floating line on the same layer as the shield layer so as to be adjacent to the substrate, there is an advantage in that it can be protected from dents due to a plurality of insulating layers present on the floating line.

Meanwhile, referring to FIGS. 35 and 36 , an auxiliary pattern FSL may be further provided on the above-described floating line FPL of FIG. 33 . The auxiliary pattern FSL includes a plurality of patterns so as to correspond to each of the plurality of patterns of the floating line FPL in a one-to-one correspondence. The auxiliary pattern FSL has a size smaller than that of the floating line FPL and is positioned to completely overlap the floating line FPL. The auxiliary pattern FSL is formed of a source/drain electrode material and is formed of the same material as that of the power line EVDL and is positioned on the same layer. The auxiliary pattern FSL may act as a protective layer of the floating line FPL to further protect the floating line FPL from dents that may occur during a process.

37 is an image showing a damaged bank layer of an organic light emitting diode display. Referring to FIG. 37 , when the bank layer is dented by the deposition mask during the process of the organic light emitting diode display device, the bank layer is damaged. Accordingly, in the organic light emitting display device according to the first to third embodiments of the present invention described above, it is possible to prevent a short circuit or physical damage in the non-display unit.

In more detail, in the organic light emitting display device according to an embodiment of the present invention, since a current does not flow between the protective member and the ground line even when a foreign material is generated on the outside of the substrate by reducing the reference voltage line portion and forming the ground portion, the polarizing plate damage can be prevented.

In addition, in the organic light emitting display device according to an embodiment of the present invention, power can be reinforced by omitting the reference voltage line and adding a power branch line branched from the power line bar. Furthermore, it is possible to prevent the power branch lines from being reflected to the user by forming shield layer patterns between the power branch lines.

In addition, in the organic light emitting display device according to an embodiment of the present invention, a ground auxiliary line is formed between the ground line and the power line unit, and the ground auxiliary line is formed on the same layer as the shield layer, so that the second buffer layer and the gate are formed over the ground auxiliary line. An insulating film, an interlayer insulating film, and a first passivation film may be formed. Accordingly, it is possible to protect the ground auxiliary line from being dented by the deposition mask during the process. In addition, by forming the auxiliary pattern on the ground auxiliary line, it is possible to protect the ground auxiliary line from dents that may occur during the process.

In addition, in the organic light emitting display device according to an embodiment of the present invention, since the overcoat layer and the bank layer are extended to the outside of the substrate, only the upper part of the bank layer is damaged even if it is photographed by the deposition mask. can reduce the likelihood that

In addition, in the organic light emitting display device according to an embodiment of the present invention, by forming the auxiliary pattern on the shield layer pattern, it is possible to further protect the shield layer pattern from dents that may occur during the process.

In addition, the organic light emitting display device according to an embodiment of the present invention has the advantage of preventing a short circuit between the second electrode and the floating part due to foreign matter by forming a floating part having a floating line between the ground line and the power line part. There is this.

In addition, by forming the floating line in a plurality of patterns, it is possible to minimize the amount of static electricity that each pattern may have, thereby preventing defects due to static electricity.

In addition, by forming the floating line on the same layer as the shield layer so as to be adjacent to the substrate, there is an advantage in that it can be protected from dents due to a plurality of insulating layers present on the floating line.

In addition, by forming the auxiliary pattern on the floating line, it is possible to further protect the floating line from dents that may occur during the process.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

A/A : Display part N/A : Non-display part
SUB : Substrate GND : Ground part
EVSP : Reference voltage line part EVDP : Power line part

Claims (21)

a display unit and a non-display unit positioned on the substrate;
an organic light emitting diode positioned on the display unit and comprising a first electrode, an organic layer, and a second electrode;
a ground unit to which a ground voltage is applied, and a power line unit to apply power to the display unit, located in the non-display unit; and
Including; a protection member facing the substrate;
The ground portion overlaps with the protection member,
The ground portion includes a ground line, the ground line being electrically separated from the second electrode. According to claim 1,
The ground portion is adjacent to an outer periphery of the substrate, and the power line portion is adjacent to the display portion. According to claim 1,
The power line unit includes a power line bar to which power is applied from the outside, and a power line for applying power from the power line bar to the display unit, and includes a plurality of power branch lines connecting the power line bar and the power line. display device. 4. The method of claim 3,
and a shield layer pattern positioned between the plurality of power branch lines. According to claim 1,
and a reference voltage line part having a reference voltage line electrically connected to the second electrode and applying a reference voltage to the display part between the ground part and the power line part. According to claim 1,
and the ground portion includes a ground auxiliary line connected to the ground line. 7. The method of claim 6,
The ground auxiliary line is formed of a plurality of patterns. 8. The method of claim 7,
and an auxiliary pattern overlapping the ground auxiliary line on the ground auxiliary line. According to claim 1,
and the ground portion includes a ground branch line branched from the ground line. According to claim 1,
The non-display unit includes a chip-on film for applying a power or data driving signal, LOG lines for transferring a power or data driving signal from the chip-on-film to the display unit, and a LOG ground line to which a ground signal is applied. According to claim 1,
The non-display unit further includes a GIP driver disposed between the display unit and the ground unit. a display unit and a non-display unit positioned on the substrate;
an organic light emitting diode positioned on the display unit and comprising a first electrode, an organic layer, and a second electrode;
a power line unit positioned on the non-display unit and including a ground unit to which a ground voltage is applied and a power line for applying power to the display unit; and
Including; a protection member facing the substrate;
The ground portion overlaps with the protection member,
The power line unit includes a power line bar to which power is applied from the outside and a power line for applying power from the power line bar to the display unit,
The power line unit includes a contact pad connected to the power line bar,
and a plurality of power branch lines connecting the power line bar and the power line,
a shield layer pattern positioned between the plurality of power branch lines;
The ground portion includes a ground line, the ground line being electrically separated from the second electrode. 13. The method of claim 12,
The display unit includes a plurality of sub-pixels, any one of the plurality of sub-pixels,
a shield layer positioned on the substrate;
a buffer layer positioned on the shield layer;
a thin film transistor positioned on the buffer layer and including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode;
an overcoat layer positioned on the thin film transistor;
the organic light emitting diode positioned on the overcoat layer; and
and a bank layer positioned between the first electrode and the organic layer to define a pixel. 14. The method of claim 13,
ends of the bank layer and the overcoat layer are positioned between the contact pad and the power line. 15. The method of claim 14,
A display device in which the organic layer and the second electrode do not overlap the contact pad. 15. The method of claim 12 or 14,
and an auxiliary pattern positioned on the shield layer pattern and overlapping the shield layer pattern. a display unit and a non-display unit positioned on the substrate;
an organic light emitting diode positioned on the display unit and comprising a first electrode, an organic layer, and a second electrode;
a ground part to which a ground voltage is applied, a power line part for applying power to the display part, and a floating part positioned between the ground part and the power line part, located in the non-display part; and
Including; a protection member facing the substrate;
The ground portion includes a ground line, the ground line being electrically separated from the second electrode. 18. The method of claim 17,
and the floating part includes a power line bar of the power line part and a floating floating line formed on the same layer as a power line bar and the ground line. 19. The method of claim 18,
The floating line is integrally formed or is formed of a plurality of patterns. 20. The method of claim 19,
and an auxiliary pattern positioned on the floating line and overlapping the floating line. According to claim 1,
The protective member is made of metal and overlaps the ground line.

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