KR20180007456A - Display device - Google Patents

Abstract

The present invention relates to a display device capable of preventing a defect of the image quality. According to the present invention, a display panel of the display device is repeatedly and sequentially disposed with first, second, third, and fourth sub-pixels realizing different colors on a first horizontal line. The first to fourth sub-pixels disposed on the first horizontal line are disposed to be shifted by two rows in a left direction as apart from the first horizontal line to the last horizontal line. A data driving unit supplies data voltage having the inverted polarity in a column inversion method to a data line such that the data voltage having the same polarity is charged to the second and third sub-pixels. Also, the data voltage having a polarity different from that of the sub-pixels of a vertical line adjacent to each of the first and fourth sub-pixels is charged. As a result, a defect of the image quality such as a vertical line and a flicker in a screen can be relieved.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device capable of preventing image quality degradation.

The image display device that realizes various information on the screen is a core technology of the information communication age and it is becoming thinner, lighter, more portable and higher performance. Accordingly, a flat panel display device capable of reducing weight and volume, which is a disadvantage of a cathode ray tube (CRT), has attracted attention.

Among the flat panel display devices, a liquid crystal display device displays an image by adjusting the light transmittance of liquid crystal cells according to a video signal. To this end, the liquid crystal display device includes a plurality of liquid crystal cells and thin film transistors connected to each of the plurality of liquid crystal cells.

Such a liquid crystal display device has developed a high frequency driving technique to improve motion blur, afterimage and flicker which cause image quality deterioration. However, due to the unbalance of the polarity distribution of the sub pixels, .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a display device capable of preventing image quality degradation.

In order to achieve the above object, a display panel of a display device according to the present invention is repeatedly arranged in the order of first, second, third and fourth sub-pixels implementing different colors in a first horizontal line, The first to fourth sub-pixels arranged in the first horizontal line are shifted in the left direction by two columns from the horizontal line to the last horizontal line, and the data driver supplies the data voltage having the inverted polarity to the data line The data voltages of the same polarity are charged in the second and third sub-pixels and the data voltages of the polarities different from those of the sub-pixels of the vertical line adjacent to the first and fourth sub-pixels are charged, It is possible to improve the defective image quality.

Since the present invention is driven by a version method which is a column with a small heating power and a low power consumption, high frequency driving is possible, and image quality defects such as a vertical line and a corridor can be improved by arranging sub-pixels and thin film transistors.

FIGS. 1A and 1B are views for explaining a picture quality deterioration phenomenon of a display device according to the prior art of the present invention.
2 is a block diagram showing a display device according to the present invention.
3 is a view for explaining a configuration of a sub-pixel of the display panel shown in Fig.
4 is a diagram illustrating the polarity and charging sequence of sub-pixels according to the present invention.
FIG. 5 is a diagram illustrating polarities of image data applied to the sub-pixels shown in FIG.
6A to 6F are views showing examples in which a display device according to the present invention displays monochromatic or mixed colors.

Prior to the description of the embodiments of the present invention, the image quality degradation phenomenon of the display device according to the prior art of the present invention will be described with reference to FIGS. 1A and 1B.

As shown in FIGS. 1A and 1B, the sub-pixels arranged in the odd-numbered horizontal lines are connected to the odd-numbered data lines DL1, DL3, And is connected to the data lines DL2, DL4, .... In this case, the data voltages of the same polarity are supplied to the sub-pixels arranged in a zigzag manner in the vertical direction with respect to the same data line.

However, when the display device shown in FIG. 1A is implemented with a single color (for example, a green (G) sub-pixel is supplied with a 255-gradation data voltage and the remaining red (R), blue (B) The data voltages of the same polarity are supplied to the sub-pixels arranged in two adjacent vertical lines which implement the same color, so that the luminance difference between the vertical lines due to the uneven polarity distribution The image quality of the vertical line is deteriorated.

In addition, when the red (R), green (G), blue (B) and white (W) subpixels shown in FIG. 1B are activated for gray scale display, they are arranged on the fourth vertical line Since the data voltages of the same polarity are supplied to the red (R) and blue (B) subpixels, image quality defects such as defective pixels are generated due to uneven polarity distributions.

In order to solve the problems of the prior art, the display device according to the present invention proposes a method of improving the picture quality by setting the position of the thin film transistor to be suitable for a column-by-version driving method.

Hereinafter, preferred embodiments of the present invention will be described.

2 is a block diagram showing a liquid crystal display device according to the present invention.

The liquid crystal display device shown in FIG. 2 includes a liquid crystal display panel 100, a data driver 108, a scan driver 106, and a timing controller 120.

The timing controller 120 is connected to the data driver 108 (not shown) using a plurality of synchronizing signals input from a host computer (not shown), that is, a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, A data control signal DCS for controlling the driving timing of the scan driver 106 and a scan control signal SCS for controlling the driving timing of the scan driver 106 are generated. The timing controller 120 outputs the generated data control signal DCS and the scan control signal SCS to the data driver 108 and the scan driver 106, respectively. The data control signal DCS includes a source start pulse and a source sampling clock for controlling the latch of the data signal, a polarity control signal for controlling the polarity of the data signal, a source output enable signal for controlling the output period of the data signal, . The scan control signal SCS includes a scan start pulse and a scan shift clock for controlling scanning of a scan signal, and a scan output enable signal for controlling an output period of the scan signal.

The scan driver 106 sequentially drives the gate lines GL of the display panel 100 in response to a scan control signal SCS from the timing controller 120. [ The scan driver 106 supplies a scan pulse in a high state every corresponding scan period of each gate line GL and a scan pulse in a low state in the remaining period in which the gate line GL is driven.

The data driver 108 converts the digital data DATA from the timing controller 120 into an analog data voltage in response to the data control signal DCS from the timing controller 120 so that each gate line GL is driven And supplies it to the data line DL every time. This data driver 108 inverts the polarity of the data voltage in accordance with the data line DL and the frame in a column inversion manner. The column-inversion scheme inverts the polarity of the data voltage applied through the neighboring data lines DL without reversing the polarity of the data voltage applied through the same data line DL during one frame period. For example, the column-version method maintains the polarity of the data voltage supplied through the odd-numbered data line DL at the positive polarity (negative polarity) during the first frame period, Polarity) and maintains its negative polarity. Then, the polarity of the data voltage supplied through the even-numbered data line DL is maintained at the negative polarity (positive polarity) during the first frame period, then reversed to the positive polarity (negative polarity) during the second frame period, Maintain the polarity (negative polarity). When the polarity of the data voltage output from the data driver 108 is inverted in a column-version manner, since the swing width of the data voltage is small and the number of transitions is small, the amount of current of the plurality of drive ICs included in the data driver 108 It can reduce power consumption and heat generation. Accordingly, in the present invention, the power consumption and heat generation can be reduced, so that a high frequency driving technique such as 120Hz can be applied.

The liquid crystal display panel 100 displays an image through unit pixels arranged in a matrix form. The unit pixel UP is composed of 8x4 sub-pixels as shown in Fig. Sub-pixels that emit different colors are sequentially and repeatedly arranged in the first horizontal line HL1 of the unit pixel UP, and the sub-pixels sequentially arranged from the first horizontal line HL1 to the last horizontal line HL1 And the arranged sub-pixels are shifted by two columns in the left direction. In the present invention, a sub-pixel disposed at the intersection of the first horizontal line HL1 and the first vertical line VL1 includes a white W sub-pixel, a red R sub-pixel, a green G sub-pixel, (B) sub-pixel. In the present invention, the sub-pixel arranged at the intersection of the first horizontal line HL1 and the first vertical line VL1 is a white (W) sub-pixel. .

Accordingly, the odd-numbered horizontal lines HL1, HL3, HL5, ... are repeatedly arranged in the order of the white (W), red (R), green (G), and blue And the sub-pixels arranged in the odd-numbered horizontal lines HL1, HL3, HL5, ... are shifted leftward by two columns in the even-numbered horizontal lines HL2, HL4, HL6, ) Sub-pixels, blue (B) sub-pixels, white (W) sub-pixels and red (R) In addition, the first and fifth vertical lines VL1 and VL5 of the unit pixel UP are repeatedly arranged in the order of white (W) and green (G) subpixels, and the second and sixth vertical lines VL2, The red (R) and blue (B) subpixels are repeatedly arranged in the order of green (G) and white (W) subpixels in the third and seventh vertical lines VL3 and VL7, (B) and red (R) sub-pixels in the fourth and eighth vertical lines VL4 and VL8.

When white (W) and green (G) sub-pixels in the unit pixel UP are connected to the even-numbered data lines DL2, DL4, DL6, Is connected to the gate line GL and connected to the gate line GL in the next stage horizontal line when connected to the odd-numbered data lines DL1, DL3, DL5, .... The red (R) and blue (B) sub-pixels in the unit pixel are connected to the gate line GL of the current short horizontal line in which the corresponding sub-pixels are arranged. Sub-pixels implementing the same color in the same vertical line are connected in a zigzag fashion to a data line DL arranged on the left and right of the sub-pixel. The connection direction of each sub-pixel and the data line DL is inverted with respect to the data line DL arranged between the red (R) and green (G) sub-pixels arranged in each horizontal line.

Specifically, the green (G) sub-pixel arranged in the eighth j (where j is a natural number) -5th vertical line (VL) and the green (G) , The white (W) sub-pixel arranged in the (8j-3) -th vertical line VL is connected to the gate line GL in the next-stage horizontal line and the sub-pixels arranged in the remaining vertical line VL are connected to the And is connected to the gate line GL of the line. For example, in the first horizontal lines HL1, the green (VL3, VL11, VL19, ...) arranged in the third, eleventh, G subpixel and the white (W) sub-pixel arranged in the fifth, thirteenth, twenty first, ..., the 8j-3th vertical lines VL5, VL13, VL21, And red (R) and blue (B) sub-pixels which are connected to the line GL2 and are arranged in the remaining vertical line VL are connected to the first gate line GL1.

Further, in the (4i-3) th horizontal lines HL, the sub-pixels arranged in the 8j-7, 8j-6, 8j-1 and 8jj vertical lines (VL) Sub-pixels arranged in the 8j-5th, 8j-4, 8j-3 and 8j-2th vertical lines (VL) are connected to the data line DL located on the right side And is connected to the data line DL located on the left side. In this case, in the (4i-3) th horizontal lines HL, green (G) sub-pixels arranged in the (8j-5) th vertical line (VL) The red (R) sub-pixels arranged in the vertical line (VL) are connected to the same data line. For example, white (W), red (R), green (G), and green (G) colors arranged in the first, second, seventh, and eighth vertical lines VL1, VL2, VL7, and VL8 in the first horizontal line HL1 And blue (B) sub-pixels are connected to the data line DL located on the right side, and green (G), blue (B), and blue (B) sub-pixels arranged in the third to sixth vertical lines VL3, VL4, VL5, , White (W) and red (R) sub-pixels are connected to the data line DL located on the left side. The red (R) sub-pixel arranged in the second vertical line in the first horizontal line HL1 and the green (G) sub-pixel arranged in the third vertical line VL3 are connected to the same third data line DL3 And the sub-pixels arranged in the first horizontal line HL1 are not connected to the seventh data line DL7.

Thus, the third, eleventh, ninth, ..., and 8j-5th vertical lines (VL3, VL11, VL19, ...) of the subpixels arranged in the first horizontal line HL1 (W) sub-pixels arranged in the 5th, 13th, 21st, ..., 8j-3th vertical lines VL5, VL13, VL21, The thin film transistor TFT of the data line DL is supplied with the data voltage DL supplied through the data line DL located to the left of the green (G) and white (W) sub-pixels in response to the scan pulse supplied to the second gate line GL2. To the pixel electrode. The white pixels arranged in the first, ninth, 17th, ..., 8j-7th vertical lines (VL1, VL9, VL17, ...) among the subpixels arranged in the first horizontal line HL1 (R) sub-pixel arranged in the second, tenth, eighteenth, ..., 8j-6th vertical lines VL2, VL10, VL18, Green (G) sub-pixels arranged in the (8j-1) th vertical lines (VL7, VL15, VL23, The thin film transistors TFT of each of the blue (B) sub-pixels arranged in the (8j) -th vertical lines VL8, VL16, VL24, ... are connected to the scan pulse supplied to the first gate line GL1 A data voltage supplied through the data line DL located on the right side of each of the white (W), red (R), green (G) and blue (B) subpixels in response to the data signal is supplied to the pixel electrode. The subpixels are arranged in the fourth, twelfth, twentieth, ..., eighth j-4th vertical lines VL4, VL12, VL20, ... among the subpixels arranged in the first horizontal line HL1 (R) sub-pixels arranged in the 6th, 14th, 22nd, ..., 8j-2th vertical lines VL6, VL14, VL22, The thin film transistor TFT responds to the scan pulse supplied to the first gate line GL1 and supplies the data voltage DL through the data line DL located on the left side of each of the blue (B) and red (R) To the pixel electrode.

(G) subpixel arranged in the (8j-7) th vertical line (VL) and the white (W) subpixel arranged in the (8j-5) The sub-pixels are connected to the gate line GL of the next-stage horizontal line, and the sub-pixels arranged in the remaining vertical line VL are connected to the gate line GL of the present-stage horizontal line. For example, in the second horizontal lines HL2, a green ((VL1, VL9, VL17, ..., G) sub-pixel and the white (W) sub-pixel arranged in the third, eleventh, nineteen ..., the (8j-5) th vertical lines VL3, VL11, VL19, Sub-pixels connected to the line GL3 and the remaining vertical lines VL are connected to the second gate line GL2.

Further, in the (4i-2) th horizontal line HL, the sub-pixels arranged in the 8j-7th, 8j-6th, 8j-5th and 8j-4th vertical lines are connected to the left data line DL And the sub-pixels arranged in the 8j-3, 8j-2, 8j-1 and 8j-th vertical lines are connected to the right data line. In this case, in the (4i-2) th horizontal lines HL, the green (G) sub-pixel arranged in the (8j + 1) th vertical line VL and the green And red (R) sub-pixels arranged in the first vertical line (VL) are connected to the same data line (DL). For example, in the second horizontal line HL2, green (G), blue (B), white (W) and red (R ) Sub pixels are connected to the left data line DL and are connected to the left to the right in the order of green (G), blue (B), white (W), and red (VL5, VL6, VL7, VL8) R) sub-pixels are connected to the data line DL located on the right side. In the second horizontal line HL2, red (R) sub-pixels arranged in the eighth vertical line (VL8) and green (G) sub-pixels arranged in the ninth vertical line (VL9) And the sub-pixels arranged in the second horizontal line HL2 are not connected to the fifth data line DL5.

Accordingly, the sub-pixels arranged in the first, ninth, seventeenth, eighth, jth, and seventh vertical lines VL1, VL9, VL17, ... among the sub-pixels arranged in the second horizontal line HL2 (W) sub-pixels arranged in the third, the 11th, the 19th, ..., and the 8j-5th vertical lines VL3, VL11, VL19, The thin film transistor TFT responds to the scan pulse supplied to the third gate line GL3 and supplies the data voltage supplied through the data line DL located on the left side of the green (G) and white (W) And supplies it to the pixel electrode. In addition, the sub-pixels arranged in the 5th, 13th, 21st, ..., 8j-3th vertical lines (VL5, VL13, VL21, ...) among the sub pixels arranged in the second horizontal line HL2 Green (G) sub-pixels and blue (B) sub-pixels arranged in the 6th, 14th, 22nd, ..., 8j-2th vertical lines (VL6, VL14, VL22, (W) sub-pixels arranged in the seventh, the 15th, the 23rd, ..., the 8j-1th vertical lines VL7, VL15, VL23, TFTs of red (R) sub-pixels arranged in the (8j) th vertical lines VL8, VL16, VL24, The data voltage supplied to the pixel electrode through the data line DL located to the right of each of the white (W), red (R), green (G) and blue (B) subpixels in response to the data signal. The second horizontal line HL2 is arranged in the second, tenth, 18th, ..., 8j-6th vertical lines VL2, VL10, VL18, ... among the subpixels arranged in the second horizontal line HL2 (R) sub-pixels arranged in the 4th, 12th, 20th, ..., 8j-4th vertical lines (VL4, VL12, VL20, The thin film transistor TFT responds to the scan pulse supplied to the second gate line GL2 and supplies the data voltage DL through the data line DL located on the left side of each of the blue (B) and red (R) To the pixel electrode.

(G) th sub-pixel arranged in the (8j-1) -th vertical line VL and the white (W) sub-pixel arranged in the Sub pixels are connected to the gate line GL of the next short horizontal line and the sub pixels arranged in the remaining vertical line VL are connected to the gate line GL of the current short horizontal line HL. For example, in the third horizontal line HL3, the green (G (G), green (G), and blue ) Sub-pixels and the white (W) sub-pixels arranged in the first, ninth, seventeenth, twenty fifth, ..., 8j-7th vertical lines VL1, VL9, VL17, VL25, The sub-pixels connected to the fourth gate line GL4 and the remaining vertical lines VL are connected to the third gate line GL3.

Further, in the (4i-1) th horizontal line HL, the sub-pixels arranged in the 8j-7, 8j-6, 8j-1 and 8jj vertical lines VL are connected to the left data line DL And sub pixels arranged in the 8j-5, 8j-4, 8j-3 and 8j-2th vertical lines (VL) are connected to the right data line DL. In this case, in the (4i-1) th horizontal lines HL, green (G) sub-pixels arranged in the (8j-1) th vertical line VL and green The red (R) sub-pixels arranged in the vertical line (VL) are connected to the same data line (DL). For example, in the third horizontal line, white (W), red (R), green (G), and blue (B) colors arranged in the first, second, seventh and eighth vertical lines VL1, VL2, VL7, The blue (B) sub-pixels are connected to the data line DL located on the left, and the green (G), blue (B), and white (B) subpixels arranged in the third through sixth vertical lines VL3, VL4, VL5, (W) and red (R) sub-pixels are connected to the data line DL located on the right side. In the third horizontal line HL3, the red (R) sub-pixel arranged in the sixth vertical line (VL6) and the green (G) sub-pixel arranged in the seventh vertical line (VL7) And the sub-pixels arranged in the third horizontal line HL3 are not connected to the third data line DL3.

Accordingly, the sub-pixels arranged in the first, ninth, seventeenth, ..., 8j-7th vertical lines (VL1, VL9, VL17, ...) among the subpixels arranged in the third horizontal line HL3 (G) sub-pixels arranged in the seventh, the 15th, the 23rd, ..., the 8j-1th vertical lines VL7, VL15, VL23, The thin film transistor TFT responds to the scan pulse supplied to the fourth gate line GL4 and supplies the data voltage supplied through the data line DL located on the left side of the green (G) and white (W) And supplies it to the pixel electrode. The third, eleventh, ninth, ..., and 8j-5th vertical lines (VL3, VL11, VL19, ...) among the subpixels arranged in the third horizontal line HL3 Green (G) sub-pixels and blue (B) sub-pixels arranged in the 4th, 12th, 20th, ..., 8j-4th vertical lines VL4, VL12, VL20, (W) sub-pixels arranged in the 5th, 13th, 21st, ..., 8j-3th vertical lines (VL5, VL13, VL21, (R) sub-pixels arranged in the (8j-2) th vertical lines VL6, VL14, VL22, ... are supplied to the third gate line GL3 A data voltage supplied through a data line DL located to the right of each of the white (W), red (R), green (G) and blue (B) subpixels in response to the scan pulse is supplied to the pixel electrode . In addition, the subpixels are arranged in the second, tenth, eighteenth,..., 8j-6th vertical lines VL2, VL10, VL18, ... among the subpixels arranged in the third horizontal line HL3 (B) sub-pixels arranged in the red (R) sub-pixel and the 8th, 16th, 24th, ..., 8j th vertical lines (VL8, VL16, VL24, (TFT) supplies a data voltage supplied through a data line DL located on the left side of each of the blue (B) and red (R) sub-pixels in response to a scan pulse supplied to the third gate line GL3, To the electrode.

In the 4th horizontal lines HL, the green sub-pixel arranged in the (8j-3) th vertical line VL and the white (W) sub-pixel arranged in the (8j- And the sub-pixels arranged in the remaining vertical line (VL) are connected to the gate line (GL) in the current horizontal line. For example, in the fourth horizontal lines HL4, the green (Vl5, VL13, VL21, ...) arranged in the fifth, thirteenth, twenty first, G) sub-pixel and the white (W) sub-pixel arranged in the seventh, the 15th, the 23rd, ..., the 8j-1th vertical lines VL7, VL15, VL23, And the sub-pixels arranged in the remaining vertical line (VL) are connected to the fourth gate line (GL4).

Further, in the 4th horizontal lines HL, the sub-pixels arranged in the 8j-7, 8j-6, 8j-5 and 8j-4th vertical lines are connected to the right data line, The sub-pixels arranged in the 8j-3, 8j-2, 8j-1 and 8jj vertical lines are connected to the left data line. In this case, in the 4th horizontal lines HL, green (G) sub-pixels arranged in the 8j-3th vertical line (VL) and green (G) And red (R) sub-pixels arranged in the second vertical line (VL) are connected to the same data line. For example, in the fourth horizontal line HL4, green (G), blue (B), white (W) and red (R Subpixels are connected to the right data line DL and are connected to the green (G), blue (B), white (W) and red (B) pixels arranged in the fifth to eighth vertical lines VL5, VL6, VL7 and VL8 R) sub-pixels are connected to the left data line DL. In the fourth horizontal line HL4, the red (R) sub-pixel arranged in the fourth vertical line (VL4) and the green (G) sub-pixel arranged in the fifth vertical line (VL5) And the sub-pixels arranged in the fourth horizontal line HL4 are connected to the first and ninth data lines DL1 and DL9.

Accordingly, it is arranged in the fifth, thirteenth, twenty first, ..., the (8j-3) th vertical lines VL5, VL13, VL21, ... among the sub pixels arranged in the fourth horizontal line HL4 (W) sub-pixels arranged in the seventh, 15th, 23rd, ..., 8j-1th vertical lines VL7, VL15, VL23, The thin film transistor TFT of the data line DL is supplied with the data voltage DL supplied through the data line DL located to the left of the green (G) and white (W) sub-pixels in response to the scan pulse supplied to the fifth gate line GL5. To the pixel electrode. The green (G), green (G), green (G), and blue (G) disposed in the first, ninth, (B) sub-pixel arranged in the second, tenth, 18th, ..., 8j-6th vertical lines (VL2, VL10, VL18, (W) sub-pixels arranged in the first, third, 11th, 19th, .., and 8j-5th vertical lines VL3, VL11, VL19, TFTs of red (R) sub-pixels arranged in the (8j-4) -th vertical lines VL4, VL12, VL20, A data voltage supplied through a data line DL positioned to the right of each of the white (W), red (R), green (G) and blue (B) subpixels in response to a pulse is supplied to the pixel electrode. Then, the sub-pixels arranged in the 6th, 14th, 22nd, ..., 8j-2th vertical lines (VL6, VL14, VL22, ...) among the sub pixels arranged in the fourth horizontal line HL4 (R) sub-pixels arranged in the 8th, 16th, 24th, ..., 8j th vertical lines (VL8, VL16, VL24, (TFT) supplies a data voltage supplied through a data line DL located to the left of each of the blue (B) and red (R) sub-pixels in response to a scan pulse supplied to the fourth gate line GL4, To the electrode.

FIG. 4 is a diagram illustrating the polarity and filling order of sub-pixels according to the present invention, and FIG. 5 is a diagram illustrating image data applied to the sub-pixels shown in FIG.

As shown in FIGS. 4 and 5, data drivers (N1, N2, N1, N2, N1, N2, N1, And a positive data voltage is supplied to the even data lines DL2, DL4, DL6, .... Accordingly, the sub-pixels connected to the odd-numbered data lines DL1, DL3, DL5, ... are supplied with the same negative data voltage in synchronization with the high-level scan pulse supplied to the corresponding gate line GL Is charged. Sub-pixels connected to the even-numbered data lines DL2, DL4, DL6, ... are charged with the same positive polarity data voltage in synchronization with the high-level scan pulse supplied to the corresponding gate lines GL .

During the (N + 1) -th frame period, the positive data voltage is supplied to the odd-numbered data lines DL1, DL3, DL5, ... through the data driver 108 driven by the column- Th data lines DL2, DL4, DL6, ... are supplied with a negative data voltage. Accordingly, the sub-pixels connected to the odd-numbered data lines DL1, DL3, DL5, ... are charged with the same positive polarity data voltage in synchronization with the high-level scan pulse supplied to the corresponding gate lines. Sub-pixels connected to the even-numbered data lines DL2, DL4, DL6, ... are charged with the same negative data voltage in synchronization with the high-level scan pulse supplied to the corresponding gate lines.

Accordingly, the red (R) and green (G) sub-pixels of the present invention are charged with the same polarity data voltage, and each of the white (W) and blue The voltage is charged.

As described above, the data voltages outputted from the data driver 108 driven by the column inversion method maintain the same polarity for each data line and maintain the polarity opposite to that of the adjacent data lines. However, the sub- A data voltage having a different polarity is supplied.

Accordingly, as shown in FIGS. 6A to 6F, the polarity distribution and the charging characteristics are uniform, so that the difference in luminance between the horizontal and vertical lines and the defective discharge can be prevented.

6A, when red (R) sub-pixels are activated to display red, red data voltages of 255 gray scales are supplied to the red (R) sub-pixels and black gray scales of 0 Gray scale data voltage) is supplied. In this case, since the red data voltages of different polarities are supplied to the red (R) subpixels adjacent to the upper, lower, right, and left sides, the polarities of the red (R) subpixels are balanced without being shifted to any one polarity.

6B, when green (G) sub-pixels are activated to display green, green data voltages of 255 gray scales are supplied to the green (G) sub-pixels and black gray scales Voltage) is supplied. In this case, since green data voltages having different polarities are supplied to the green (G) sub-pixels adjacent to the upper, lower, left, and right sides, the polarities of the green (G) sub-pixels are balanced without being shifted to any one polarity.

6C, blue (B) sub-pixels are supplied with a blue data voltage of 255 gradations, and the remaining sub-pixels are supplied with black gradation (0 gradation data Voltage) is supplied. In this case, since the blue data voltages of different polarities are supplied to the blue (B) sub-pixels adjacent to the upper, lower, left, and right sides, the polarities of the blue (B) sub-pixels are balanced without any polarity.

6D, when the red (R) and green (G) sub-pixels are activated to display a yellow color, a data voltage of 255 gradations is applied to each of the red (R) And the remaining black (B) and white (W) sub-pixels are supplied with a black gradation (0 gradation data voltage). In this case, since the red (R) and green (G) subpixels are supplied with the data voltages of different polarities from the subpixels of the corresponding colors that are adjacent to the upper, Is balanced without being shifted to any one polarity.

6E, when the red (R) and blue (B) sub-pixels are activated to display a magenta color, a data voltage of 255 gradations is applied to each of the red (R) and blue And the black gradation (0 gradation data voltage) is supplied to the remaining green (G) and white (W) sub-pixels. In this case, since the red (R) and blue (B) subpixels are supplied with the data voltages having different polarities from the subpixels of the corresponding colors that are adjacent to the upper, Is balanced without being shifted to any one polarity.

(G) and blue (B) sub-pixels are activated to display a cyan color as shown in FIG. 6F, a data voltage of 255 gradations is applied to each of the green (G) and blue And the remaining black (R) and white (W) sub-pixels are supplied with black gradation (0-gradation data voltage). In this case, since the data voltages of different polarities are supplied to the sub-pixels of the corresponding color in the upper, lower, left, and right adjacent to the green (G) and blue (B) sub-pixels, Is balanced without being shifted to any one polarity.

As described above, the liquid crystal display device according to the present invention can prevent the difference in luminance between the horizontal and vertical lines and the defective pixels because the polarities of the colors are balanced.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

100: display panel 106: scan driver
108: Data driver 120: Timing controller

Claims (6)

Second, third, and fourth sub-pixels in a first horizontal line, wherein the first to fourth sub-pixels are arranged in the order of the first, second, third, and fourth sub- Pixels arranged in the first horizontal line so that the first through fourth sub-pixels are shifted leftward by two columns;
The data voltages of the same polarity are charged in the second and third sub-pixels and the data voltages of the polarities different from those of the sub-pixels of the vertical line adjacent to the first and fourth sub-pixels are charged, And a data driver for supplying a data voltage whose polarity is inverted to the data line. The method according to claim 1,
The odd-numbered horizontal lines of the display panel are repeatedly arranged in the order of the first, second, third and fourth sub-pixels,
And the third, fourth, first and second sub-pixels are repeatedly arranged in the order of the even-numbered horizontal lines of the display panel. The method according to claim 1,
The first and third sub-pixels connected to the odd-numbered data line of the display panel are connected to the gate line of the current short horizontal line in which the first to third sub-pixels are arranged,
The first and third sub-pixels connected to the odd-numbered data lines of the display panel are connected to the gate lines of the next horizontal line in which the first to third sub-pixels are arranged,
And the second and fourth sub-pixels are connected to the gate line of the current short horizontal line in which the second and fourth sub-pixels are arranged. The method of claim 3,
Sub-pixels arranged vertically so as to realize the same color in each of the vertical lines are connected to a data line disposed on left and right sides of the sub-pixel in a zigzag form,
And the connection direction of each of the sub-pixels and the data line is inverted with respect to the data line disposed between the second and third sub-pixels. 5. The method of claim 4,
Subpixels arranged on the 8j-7, 8j-6, 8j-1 and 8j-th vertical lines among the sub-pixels arranged on the 4i-3th horizontal line are connected to the right data line, The sub-pixels arranged in the 8j-5th, 8j-4, 8j-3 and 8j-2th vertical lines are connected to the left data line,
Subpixels arranged on the 8j-7, 8j-6, 8j-5, and 8j-4th vertical lines among the sub-pixels arranged on the 4i-2th horizontal line are connected to the left data line , The sub-pixels arranged in the 8j-3, 8j-2, 8j-1 and 8jj vertical lines are connected to the right data line,
Subpixels arranged on the 8j-7, 8j-6, 8j-1 and 8j-th vertical lines among the sub-pixels arranged on the (4i-1) th horizontal line are connected to the left data line, The sub-pixels arranged in the 8j-5th, 8j-4, 8j-3 and 8j-2th vertical lines are connected to the right data line,
Subpixels arranged on the 8j-7, 8j-6, 8j-5 and 8j-4th vertical lines of the sub-pixels arranged on the 4th horizontal line are connected to the right data line, Th sub-pixels arranged in the (8j-3) th, (8j-2) th, 8j-1, and 8j th vertical lines are connected to the left data line. 6. The method of claim 5,
Subpixels arranged on the (8j-6) th and (8j-5) th vertical lines of the sub-pixels arranged on the (4i-3) th horizontal line are connected to the same data line,
The subpixels arranged on the 8j-th and 8j + 1-th vertical lines of the sub-pixels arranged on the (4i-2) -th horizontal line are connected to the same data line,
Pixels arranged on the (8j-1) -th and (8j-2) -th vertical lines of the sub-pixels arranged on the (4i-1) -th horizontal line are connected to the same data line,
And the sub-pixels arranged on the (8j-3) th and (8j-4) th vertical lines of the sub-pixels arranged on the 4th horizontal line are connected to the same data line.

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