KR20170098623A - Method for manufacturimg the semiconductor device - Google Patents

Abstract

A method for producing a semiconductor device according to an embodiment of the present application comprises the steps of: forming a conductive material at the top of a semiconductor substrate of a cell region and a surrounding circuit region; forming a plate-shaped first mask pattern including a protrusion part and a concave part at the top of the conductive material of the cell region, and forming a second mask pattern for defining a gate electrode at the top of the conductive material of the surrounding circuit region; forming a gate pattern in the surrounding circuit region by etching the conductive material of the cell region by the first mask pattern as an etching mask and by etching the conductive material of the surrounding circuit region by the second mask pattern as an etching mask; forming a spacer for defining a bit line at the top of the first mask pattern of the cell region; and forming a line-shaped bit line pattern by etching the conductive material and the first mask pattern of the cell region by the spacer as an etching mask, wherein the pad region line width of one side end of the bit line pattern is greater than the line width of the central part of the bit line pattern.

Description

[0001] METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE [0002]

The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of forming a bit line in a cell region and a method of forming a gate in a peripheral circuit region.

As the degree of integration of semiconductor memory devices increases, the number of design rules decreases and the pattern of semiconductor devices becomes finer. As miniaturization and high integration of a semiconductor device progresses, the overall chip area increases in proportion to an increase in memory capacity, but the area of a cell area where a semiconductor device pattern is formed is actually decreasing.

Therefore, in order to secure a desired memory capacity, a larger number of patterns must be formed in a limited cell region, so that a fine pattern with a reduced critical dimension of the pattern must be formed. In order to form such a fine pattern, it is easy to apply the double patterning technique (DPT) or the spacer patterning technique (SPT). However, in the case of a gate or a bit line formed in a cell region, a line / space pattern having a desired fine pitch is formed using a SPT in a simple line pattern, and a contact as an electrical characteristic connection is formed at the end of the line It is difficult to precisely form a contact on a small pattern with a desired size because the pattern becomes finer and the process becomes insufficient in margin. As a result, there is a problem that overlap and punch margin of a contact formed at the bit line end of the cell region are reduced.

Various embodiments of the present invention provide a method for self-aligning a contact pad formed at a bit line end of a cell region by patterning a bit line of a cell region and a gate electrode of a peripheral circuit region, respectively .

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, including: forming a conductive material on a semiconductor substrate in a cell region and a peripheral circuit region; Forming a first mask pattern in the form of a plate including a recessed portion and forming a second mask pattern defining a gate electrode on the conductive material in the peripheral circuit region; Etching the material, etching the conductive material of the peripheral circuit region with a second mask pattern using an etch mask to form a gate pattern in the peripheral circuit region, and forming a spacer defining a bit line above the first mask pattern of the cell region Etching the first mask pattern and the conductive material in the cell region using the spacers as an etching mask to form a bit line pattern And a line width of the pad region at one end of the bit line pattern is formed to be larger than a line width of the bit line pattern center portion.

The forming of the buried gate in the cell region may further include forming an insulating film on the semiconductor substrate including the buried gate and etching the insulating film to form the bit line contact hole.

Forming a bit line contact plug by embedding a conductive material in the bit line contact hole of the cell region; depositing a gate insulating film on the semiconductor substrate of the peripheral circuit region; And forming a conductive layer.

Furthermore, the first mask pattern includes a plurality of protrusions and depressions on both sides in the first direction, and the protrusions and depressions of the first mask pattern are arranged to correspond to each other in the first direction.

Furthermore, the protrusions and recesses of the first mask pattern are alternately arranged along a second direction intersecting the first direction.

Further, forming the spacers defining the bit lines may include forming a plurality of sacrificial layer patterns on the first mask pattern of the cell region, forming a spacer layer on the sides of the sacrificial layer pattern, Forming a photoresist pattern on the second mask pattern of the peripheral circuit region in the step of etching the first mask pattern and the conductive material in the cell region using the spacer as an etch mask, So as not to be etched.

Further, the method may further include forming a hard mask layer on the first mask pattern, wherein an end of the sacrificial pattern is disposed at a convex portion and a concave portion between the concave portions of the first mask pattern.

Furthermore, the pitch of the sacrificial pattern formed in the cell region is formed to be twice the bit line pitch to be finally formed, and spacers are formed to be connected to each other at the end of the sacrificial pattern.

Further, the one side pattern of the spacer connected to the end portion passes through the convex portion of the first mask pattern, and the other side pattern passes over the concave portion of the first mask pattern. The line width of the pad region of the bit line pattern corresponds to the line width Which is twice as large as that of the first embodiment.

Furthermore, the pad regions at the end of the bit line pattern are alternately arranged.

Further, the bit line pattern end formed with the pad region is formed to be longer in the first direction than the adjacent bit line pattern. The method further includes forming a metal contact plug connected to the pad region at the end of the bit line pattern .

According to another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a conductive material on a semiconductor substrate; forming a plate-shaped mask pattern on the conductive material including protrusions and recesses; Etching the conductive material with an etch mask, forming spacers defining the bit lines above the mask pattern, etching the mask pattern and the conductive material with the etch mask to form bit line patterns in a line form, Wherein the width of the pad region at one end of the bit line pattern is larger than the width of the bit line pattern center portion.

Furthermore, the line width of the pad region of the bit line pattern is two times larger than the line width of the center portion of the bit line pattern, and pad regions at the end of the bit line pattern are alternately arranged.

According to various embodiments of the present invention, the bit line of the cell region and the gate electrode of the peripheral circuit region are patterned respectively so that the contact pad is self-aligned to the bit line end of the cell region and connected to the bit line end of the cell region An effect of improving the overlap and punch margin of the contact plug can be obtained.

1 to 8 are a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference symbols as possible even if they are shown in different drawings. In the following description of the embodiments of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make sense to the person skilled in the art to which the invention pertains.

FIGS. 1 to 8 illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 1A, 2A, 3A, 4A, 5A, 6A, and 7A are plan views, 1C, 2B, 3B, 4B, 5B, 6B, 7B, 8B and 8C are cross-sectional views taken along the line A-A ', B-B' or C-C ' Sectional views.

1A, 1B and 1C, FIG. 1B is a cross-sectional view taken along the line A-A 'in FIG. 1A. FIG. 1B is a sectional view taken along the direction perpendicular to the gate, that is, FIG. 1C is a cross-sectional view taken along the line B-B 'in FIG. 1A, and shows a cross-sectional view taken along the direction in which the gate extends. Hereinafter, only the sectional view cut along the direction in which the bit lines extend is described.

An element isolation film 110 defining an active region 105 is formed on a semiconductor substrate 100 including a cell region I and a peripheral circuit region II.

A first hard mask pattern 115 for forming a buried gate is formed on the semiconductor substrate 100 on which the device isolation film 110 is formed. The first hard mask pattern 115 may be formed of an oxide film or a nitride film. Subsequently, the active region 105 and the device isolation film 110 exposed by the first hard mask pattern 115 are etched by a certain depth to form a recess for forming a buried gate.

An oxidation process is performed to form a gate insulating film (not shown) on the inner wall of the recess.

Then, the gate conductive layer 120 is buried in the recess bottom where the gate insulating film (not shown) is formed. The gate conductive layer 120 may be formed of a layered structure of titanium nitride (TiN) or titanium nitride (TiN) and tungsten (W).

A capping layer 122 is deposited over the gate conductive layer 120 to fill the remaining portion of the recess where the gate conductive layer 120 is formed to form a plurality of buried gates 125 in the cell region I. [ Here, the capping layer 122 may be formed of a nitride layer.

Next, the capping film 122 and the first hard mask pattern 115 of the predetermined bit line contact region of the cell region I are etched to form a bit line contact hole exposing the active region 105. After the conductive material is formed on the entire upper surface including the bit line contact holes, the planarization etching is performed until the capping layer 122 is exposed to form the bit line contact plug 140 in which the conductive material is buried in the bit line contact hole .

Then, the first hard mask pattern 115 and the capping film 122 formed in the peripheral circuit region II are removed.

Next, the gate insulating film 130 is formed on the entire surface of the semiconductor substrate 100 in the cell region I and the peripheral circuit region II including the bit line contact plug 140, The gate insulating film 130 is removed so that the gate insulating film 130 is left only on the semiconductor substrate 100 in the peripheral circuit region.

Thereafter, a gate conductive layer 135 is formed on the gate insulating film 130 in the peripheral circuit region.

Next, a second conductive material 145 and a second hard mask layer 150 are formed on the entire upper surface of the semiconductor substrate 100 including the capping layer 122, the bit line contact plug 140, and the gate conductive layer 135, . The second conductive material 145 may include a structure in which a metal or a metal and a barrier metal are stacked. For example, the metal may comprise a tungsten material, and the barrier metal may comprise titanium, a titanium nitride film.

Referring to FIGS. 2A and 2B, the second hard mask layer 150 is etched to form second hard mask patterns 152 and 153 in the cell region and the peripheral circuit region. Here, the second hard mask pattern 152 of the cell region is formed to include a plurality of protrusions 152a and recesses 152b as shown in FIG. 2A. In the second hard mask pattern 152 of the cell region, the protrusions 152a and the recesses 152b are alternately arranged along the second direction.

More specifically, the first hard mask pattern 152 of the cell region includes a plurality of protrusions 152a and recesses 152b on both sides in the first direction. Assuming that the protrusion 152a is formed on one side of the second hard mask pattern 152 in the cell region, a concave portion 152b is formed on the other side of the second hard mask pattern 152 facing in the first direction.

The hard mask pattern 153 in the peripheral circuit region is formed in a rectangular band shape defining the gate electrode.

The second hard mask pattern 152 of the cell region is etched using the etch mask to etch the second conductive material 145, the capping layer 122 and the first hard mask pattern 115 in the cell region, The second conductive material 145, the gate conductive layer 135 and the gate insulating layer 130 are etched using the hard mask pattern 153 as an etch mask to form the gate pattern 154 in the peripheral circuit region. Conventionally, a bit line of a cell region and a gate pattern of a peripheral circuit region are simultaneously formed through a single etching process. However, in the present application, only the etching process using the second hard mask pattern including protrusions and recesses is performed without performing the patterning process for forming the bit lines in the cell region during the formation of the gate pattern by etching the peripheral circuit region.

Therefore, the bit line of the cell region and the gate electrode of the peripheral circuit region are formed through different etching processes.

Thereafter, gate spacers 157 are formed on the sidewalls of the gate patterns 154 in the peripheral circuit region. Then, an ion implantation process is performed on the entire upper surface of the semiconductor substrate 100 including the gate pattern 154 in the peripheral circuit region. As the ion implantation process proceeds, the gate characteristics of the peripheral circuit region can be improved.

Referring to FIGS. 3A and 3B, an interlayer insulating layer 160 is formed on the entire upper surface of the semiconductor substrate 100 in the cell region and the peripheral circuit region. At this time, the interlayer insulating layer 160 may be formed of an oxide layer material having an etching selectivity difference from the second hard mask pattern 153 on the upper portion of the gate pattern 154. The planarization etching is continued until the second hard mask pattern 152 of the cell region and the second hard mask pattern 153 formed at the upper end of the gate pattern 154 of the peripheral circuit region are exposed.

Referring to FIGS. 4A and 4B, a third hard mask layer 165 is formed over the cell region and the peripheral circuit region. The third hard mask layer 165 is formed for compensation of the second hard mask pattern 152 formed in the cell region. The third hard mask layer 165 may be formed of the same material as the second hard mask patterns 152 and 153. However, the present invention is not limited to this, and any material may be used as long as it can protect the second hard mask patterns 152 and 153.

A fourth hard mask layer 167 is then formed over the third hard mask layer 165.

Referring to FIGS. 5A and 5B, a plurality of sacrificial layer patterns 170 are formed on the fourth hard mask layer 167 of the cell region. The sacrificial layer pattern 170 is formed to form a bit line using the SPT process and is formed as a line pattern extending in a first direction intersecting the buried gate 125. [ The sacrificial film pattern 170 may be formed of a material that is easily removed. For example, it may be formed of an oxide-based material.

It is preferable that the pitch of the sacrificial layer pattern 170 formed in the cell region is twice the pitch of the bit line to be finally formed. The sacrificial pattern 170 may be disposed between the protrusion 152a and the recess 152b of the second hard mask pattern 152 formed in the cell region so that the sacrificial pattern 170 is curved So that the end of the second hard mask pattern 152 is positioned.

Next, a spacer layer is formed on the entire surface of the fourth hard mask layer 167 including the sacrificial film pattern 170.

Since the thickness of the spacer layer affects the line width of the bit line formed in a subsequent process, a material having excellent step coverage characteristics can be used and can be formed by an atomic layer deposition method. Since the spacer layer must be left upon removal of the sacrificial layer pattern 170, it may be formed of a material having an etch selectivity difference from that of the sacrificial layer pattern 170. For example, if the sacrificial film pattern 170 is an oxide-based material, the spacer layer can be formed of a nitride-based material.

An etch back etching is performed so that the surface of the sacrificial layer pattern 170 is exposed to form a spacer pattern 175 on the side surface of the sacrificial layer pattern 170. [ Since the spacer layer is formed so as to surround the sacrificial layer pattern 170, the spacer patterns 175 are formed to be connected to each other at the ends of the sacrificial layer pattern 170.

Referring to FIGS. 6A and 6B, the sacrificial film pattern 170 is removed by a wet dip-out process so that only the spacer pattern 175 is left. One of the spacer patterns 175 formed by connecting the end portions of the second hard mask pattern 152 passes through the convex portion 152a of the second hard mask pattern 152 and the other pattern passes through the concave portion 152b of the second hard mask pattern 152 It goes.

Referring to FIGS. 7A and 7B, the fourth hard mask layer 167 is etched using the spacer pattern 175 as an etch mask to form a fourth hard mask pattern 167a.

Then, the photosensitive film pattern 180 is formed in the peripheral circuit region. The photoresist pattern 180 is formed to prevent the peripheral circuit area from being etched during the subsequent bit line patterning process.

Thereafter, the spacer pattern 175 is removed.

The bit line pattern forming step will be described with reference to FIGS. 8A to 8C. Here, FIG. 8B is a cross-sectional view taken along the line A-A 'in FIG. 7A, and FIG. 8C is a cross-sectional view taken along the line C-C' in FIG. 8A.

A third hard mask pattern 165a is formed by etching the third hard mask layer 165 in the cell region using the fourth hard mask pattern 167a as an etch mask and the photoresist pattern 180 formed in the peripheral circuit region is removed do.

Thereafter, the second hard mask pattern 152, the second conductive material 145, the capping film 122, and the bit line contact plug 140 are sequentially etched using the third hard mask pattern 165a as an etch mask, Thereby forming a line pattern 185.

The bent portion of the second hard mask pattern 152 is positioned at a portion where the bit line pattern 185 is formed at the time of etching the bit line pattern 185 using the fourth hard mask pattern 167a as an etch mask. An etch loading effect is generated at the end of the bit line pattern 185 corresponding to the bent portion of the second hard mask pattern 152 so that the long axis of the bit line pattern 185 is long, The line width W2 of the bit line pattern end 185b is formed to be larger than the line width W1 of the bit line pattern 185a. And the bit line pattern ends 185b having a relatively large line width are arranged in a zigzag form. For example, if one end of the bit line pattern 185 has a relatively large line width, the adjacent bit line pattern 185 is arranged such that the other end has a relatively large line width.

A portion formed by increasing the line width at the bit line pattern end 185b becomes a position to be connected to a contact plug formed in a subsequent process. That is, at the end 185b of the bit line pattern, a bit line pad having an increased line width is automatically formed.

As described above, in the present application, the bit line pattern of the cell region and the gate pattern of the peripheral circuit region are formed by separate etching processes so that the line width of the bit line pattern end is larger than the line width of the center portion of the bit line pattern Thereby providing an effect of improving Over Lap and Punch margin of the metal contact plug formed on the bit line of the cell region.

It will be understood by those skilled in the art that various modifications and variations can be made in the present invention without departing from the essential characteristics thereof.

Therefore, the embodiments disclosed in the present application are intended to illustrate rather than limit the technical idea of the present application, and the scope of the technical idea of the present application is not limited by these embodiments.

The scope of protection of the present application should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

Claims (20)

Forming a conductive material on the semiconductor substrate of the cell region and the peripheral circuit region;
Forming a first mask pattern in the form of a plate including projections and depressions on the conductive material in the cell region and forming a second mask pattern defining a gate electrode on the conductive material in the peripheral circuit region;
Etching the conductive material in the cell region using the first mask pattern as an etch mask and etching the conductive material in the peripheral circuit region using the second mask pattern as an etch mask to form a gate pattern in the peripheral circuit region ;
Forming a spacer defining a bit line above the first mask pattern of the cell region;
And forming a bit line pattern of a line shape by etching the first mask pattern and the conductive material of the cell region using the spacer as an etching mask, wherein a line width of the pad region at one end of the bit line pattern is larger than a line width of the center line of the bit line pattern Wherein the first semiconductor layer and the second semiconductor layer are formed to have a large size. The method according to claim 1,
Forming a buried gate in the cell region; And
Forming an insulating film on the semiconductor substrate including the buried gate, and etching the insulating film to form a bit line contact hole. The method of claim 2,
Filling a bit line contact hole of the cell region with a conductive material to form a bit line contact plug;
Depositing a gate insulating film on the semiconductor substrate in the peripheral circuit region; And
Forming a gate conductive layer on the gate insulating film in the peripheral circuit region
Further comprising the step of: The method according to claim 1,
Wherein the first mask pattern includes a plurality of protrusions and recesses on both sides of the first direction. Claim 4
Wherein protrusions and recesses of the first mask pattern are arranged to correspond to each other in the first direction. The method of claim 4,
Wherein protrusions and recesses of the first mask pattern are alternately arranged along a second direction intersecting with the first direction. Claim 1
Wherein forming the spacers defining the bit lines comprises:
Forming a plurality of sacrificial layer patterns on the first mask pattern of the cell region;
Forming a spacer layer on a side surface of the sacrificial film pattern; And
And removing the sacrificial film pattern. Claim 7
Forming a photoresist pattern on the second mask pattern of the peripheral circuit region by etching the first mask pattern and the conductive material in the cell region using the spacer as an etching mask so that the peripheral circuit region is not etched Wherein the semiconductor device is a semiconductor device. Claim 7
Further comprising forming a hard mask layer on the first mask pattern. The method of claim 7,
Wherein an end of the sacrificial film pattern is disposed at a curved portion between the convex portion and the concave portion of the first mask pattern. Claim 7
Wherein a pitch of the sacrificial pattern formed in the cell region is twice the bit line pitch to be finally formed. Claim 7
Wherein spacers are formed to be connected to each other at the end of the sacrificial film pattern. Claim 12
Wherein one of the patterns of the spacer connected to the end portion passes through the convex portion of the first mask pattern and the other pattern passes over the concave portion of the first mask pattern. Claim 1
And the line width of the pad region of the bit line pattern is twice as large as the line width of the bit line pattern center portion. Claim 1
And pad regions at the ends of the bit line pattern are alternately arranged. Claim 1
Wherein the bit line pattern end formed with the pad region is formed longer in the first direction than the adjacent bit line pattern. Claim 1
And forming a metal contact plug to be connected to a pad region at the end of the bit line pattern. Forming a conductive material on the semiconductor substrate;
Forming a mask pattern in the form of a plate including protrusions and depressions on the conductive material;
Etching the conductive material with the mask pattern using an etching mask;
Forming a spacer over the mask pattern to define a bit line; And
Forming a bit line pattern in a line shape by etching the mask pattern and the conductive material using the spacer as an etching mask, wherein a line width of the pad area at one end of the bit line pattern is larger than a line width of the center line of the bit line pattern Wherein the first semiconductor layer is formed on the first semiconductor layer. 19. The method of claim 18,
And the line width of the pad region of the bit line pattern is twice as large as the line width of the bit line pattern center portion. 19. The method of claim 18,
And pad regions at the ends of the bit line pattern are alternately arranged.

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