KR20170043440A - Fan-out semiconductor package and manufacturing method for the same - Google Patents

Abstract

The present invention relates to a fan-out semiconductor package and a manufacturing method thereof. The fan-out semiconductor package comprises: a first connection member having a through hole; a semiconductor chip which is arranged on the through hole of the first connection member and has an active surface with an access pad and a non-active surface arranged on an opposite side of the active surface; an enclosing material to enclose at least a portion of the non-active surface of the semiconductor chip and the first connection member; and a second connection member arranged on the active surface of the semiconductor chip and the first connection member and provided with a rewiring layer electrically connected to the access pad. The first connection member includes a first insulation layer, a first rewiring layer which comes in contact with the second connection member and is buried in the first insulation layer, and a second rewiring layer arranged on a side of the first insulation layer opposite to a side where the first rewiring layer is buried. The first and the second rewiring layer are electrically connected to the access pad.

Description

[0001] FAN-OUT SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD FOR THE SAME [0002]

The present disclosure relates to a semiconductor package, for example, a fan-out semiconductor package and a method of manufacturing the same, which can expand the connection terminal to the area where the semiconductor chip is disposed.

One of the main trends of technology development related to semiconductor chips in recent years is to reduce the size of components. Accordingly, in the field of packages, it is required to implement a large number of pins with a small size in response to a surge in demand of small semiconductor chips and the like .

One of the proposed package technologies to meet this is the fan-out semiconductor package. The fan-out semiconductor package rewires the connection terminal out of the region where the semiconductor chip is disposed, thereby realizing a plurality of pins with a small size.

One of the objects of the present disclosure is to provide a semiconductor device and a method of manufacturing the same that can introduce a first connecting member in which a re-wiring layer is formed in a region where a semiconductor chip is sealed, Out semiconductor package and a method for efficiently manufacturing the same.

One of the solutions proposed through the present disclosure is to embed a rewiring layer in contact with the second connection member of the first connection member inside the first connection member.

For example, a fan-out semiconductor package according to the present disclosure may include a first connecting member having a through-hole; A semiconductor chip disposed in the through-hole of the first connection member, the semiconductor chip having an active surface on which the connection pad is disposed and an inactive surface disposed on the opposite side of the active surface; A sealing member for sealing at least a part of the inactive surface of the first connecting member and the semiconductor chip; And a second connection member disposed on the active surface of the first connection member and the semiconductor chip, the second connection member including a re-wiring layer electrically connected to the connection pad; Wherein the first connecting member is disposed on the opposite side of the first rewiring layer in contact with the first insulating layer, the second connecting member, and the first rewiring layer embedded in the first insulating layer and the first rewiring layer And the first and second rewiring layers may be electrically connected to the connection pads.

In addition, a method of manufacturing a fan-out semiconductor package according to the present disclosure includes: preparing a carrier film; Forming a first connecting member on the carrier film; Removing the carrier film; Forming a through hole passing through the first connecting member; Disposing a semiconductor chip having an active surface in which a connection pad is disposed in the through hole and an inactive surface disposed on the opposite side of the active surface; Sealing the first connecting member and at least a part of the inactive surface of the semiconductor chip with a sealing material; And forming a second connection member including a first connection member and a re-wiring layer electrically connected to the connection pad on the active surface of the semiconductor chip; Wherein forming the first connecting member includes forming a first rewiring layer on the carrier film, forming a first rewiring layer on the carrier film to embed the first rewiring layer, Forming a second rewiring layer on the opposite side of the side where the first rewiring layer is embedded, wherein the first and second rewiring layers are electrically connected to the connection pad.

On the other hand, the fan-out semiconductor package according to the present disclosure includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface disposed on the opposite side of the active surface; At least one connection unit disposed around the semiconductor chip; And a connection member and a connection member disposed on the semiconductor chip; Wherein the connecting unit includes a first insulating layer, a first rewiring layer buried in the first insulating layer and in contact with the connecting member, and a second rewiring layer disposed on the opposite side of the first rewiring layer, The rewiring layer of the connection unit and the rewiring layer of the connection member are electrically connected to the connection pads of the semiconductor chip, It is possible.

As one of the effects of the present disclosure, it is possible to improve the bending problem of the fan-out semiconductor package as well as to have a wider routing area, and also to design a high-density wiring of the second connection member, Method can be provided.

1 is a block diagram schematically showing an example of an electronic equipment system.
2 is a perspective view schematically showing an example of an electronic apparatus.
3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.
4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.
5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.
6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.
7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.
8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.
9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.
10 is a schematic sectional elevational-cut view of the fan-out semiconductor package of FIG.
FIG. 11 is a cross-sectional view schematically illustrating various views of vias formed in the first connecting member of the fan-out semiconductor package of FIG. 9; FIG.
Figs. 12A to 12D are schematic manufacturing examples of the fan-out semiconductor package of Fig.
13 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.
Figure 14 is a schematic diagram of the fan-out semiconductor package of Figure 13; Fig.
15 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.
Figure 16 is a schematic cross-sectional view of the fan-out semiconductor package of Figure 15; Fig.
17 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.
Figure 18 is a schematic diagram of the fan-out semiconductor package of Figure 17; Fig.
Fig. 19 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig. 9;
Fig. 20 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig. 9;
Fig. 21 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig. 9;
22 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.
23 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
24 is a schematic V-V 'cutting plan view of the fan-out semiconductor package of FIG.
Figure 25 is a cross-sectional view schematically illustrating various views of vias formed in the first connection member of the fan-out semiconductor package of Figure 23;
Figs. 26A to 26D are schematic manufacturing examples of the fan-out semiconductor package of Fig.
Fig. 27 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig. 23;
28 is a schematic VI-VI 'cutting plan view of the fan-out semiconductor package of FIG. 27;
29 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of FIG.
30 is a schematic sectional view VII-VII 'of the fan-out semiconductor package of FIG. 29;
Fig. 31 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig. 23;
32 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.
33 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.
34 is a cross-sectional view schematically showing an example of a fan-out semiconductor package in which the insulation distance of the second connection member is non-uniform.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape and size of elements in the drawings may be exaggerated or reduced for clarity.

Electronics

1 is a block diagram schematically showing an example of an electronic equipment system.

Referring to the drawings, an electronic device 1000 accommodates a main board 1010. The main board 1010 is physically and / or electrically connected to the chip-related components 1020, the network-related components 1030, and other components 1040. They are also combined with other components to be described later to form various signal lines 1090.

Chip related components 1020 include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.; An application processor chip such as a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, a cryptographic processor, a microprocessor, Analog-to-digital converters, and logic chips such as application-specific integrated circuits (ICs), and the like, but it is needless to say that other types of chip-related components may be included. It goes without saying that these components 1020 can be combined with each other.

IEEE 802.11 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM , And any other wireless and wired protocols designated as GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and later, as well as any other wireless or wired Any of the standards or protocols may be included. It goes without saying that the network-related component 1030 may be combined with the chip-related component 1020, as well.

Other components 1040 include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-firing ceramics (LTCC), EMI (Electro Magnetic Interference) filters, and MLCC (Multi-Layer Ceramic Condenser) But is not limited to, passive components used for various other purposes, and the like. It is also understood that other components 1040 may be combined with each other with the chip-related component 1020 and / or the network-related component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the mainboard 1010. Other components include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (Not shown), a CD (compact disk) (not shown), and a DVD (not shown), an accelerometer (not shown), a gyroscope a digital versatile disk (not shown), and the like. However, the present invention is not limited thereto, and other components used for various purposes may be included depending on the type of the electronic device 1000.

The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, it is needless to say that the present invention is not limited thereto and may be any other electronic device that processes data.

2 is a perspective view schematically showing an example of an electronic apparatus.

Referring to the drawings, a semiconductor package is applied to various electronic apparatuses as described above for various purposes. For example, a main board 1110 is accommodated in the body 1101 of the smartphone 1100, and various components 1120 are physically and / or electrically connected to the main board 1110. In addition, other components, such as the camera 1130, that are physically and / or electrically connected to the main board 1010 or not may be contained within the body 1101. Some of the components 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor, but is not limited thereto. It is needless to say that the electronic device is not necessarily limited to the smartphone 1100, but may be another electronic device as described above.

Semiconductor package

In general, a semiconductor chip has many microelectronic circuits integrated therein, but itself can not serve as a finished product of a semiconductor, and there is a possibility of being damaged by external physical or chemical impact. Therefore, the semiconductor chip itself is not used as it is, and the semiconductor chip is packaged and used as electronic devices in a package state.

The reason for the necessity of semiconductor packaging is that there is a difference in circuit width between the semiconductor chip and the main board of the electronic device from the viewpoint of electrical connection. Specifically, in the case of a semiconductor chip, the size of the connection pad and the spacing between the connection pads are very small. On the other hand, in the case of the main board used in electronic equipment, the size of the component mounting pad and the interval between the component mounting pads are much larger than the scale of the semiconductor chip . Therefore, there is a need for a packaging technique which makes it difficult to directly mount a semiconductor chip on such a main board and can buffer the difference in circuit width between the semiconductor chips.

The semiconductor package manufactured by such a packaging technique can be classified into a fan-in semiconductor package and a fan-out semiconductor package depending on the structure and use.

Hereinafter, the fan-in semiconductor package and the fan-out semiconductor package will be described in more detail with reference to the drawings.

(Fan-in semiconductor package)

3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.

4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.

The semiconductor chip 2220 includes a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like; A connection pad 2222 including a conductive material and a passivation film 2223 such as an oxide film or a nitride film formed on one surface of the body 2221 and covering at least a part of the connection pad 2222. [ May be an integrated circuit (IC) in a bare state. At this time, since the connection pad 2222 is very small, the integrated circuit (IC) is difficult to be mounted on a medium-level printed circuit board (PCB) as well as a main board of an electronic apparatus.

A connection member 2240 is formed on the semiconductor chip 2220 in accordance with the size of the semiconductor chip 2220 in order to rewire the connection pad 2222. [ The connecting member 2240 is formed by forming an insulating layer 2241 with an insulating material such as a photosensitive insulating resin (PID) on the semiconductor chip 2220 and forming a via hole 2243h for opening the connecting pad 2222, The wiring pattern 2242 and the via 2243 can be formed. Thereafter, a passivation layer 2250 for protecting the connecting member 2240 is formed, and an under-bump metal layer 2260 or the like is formed after the opening 2251 is formed. That is, through a series of processes, a fan-in semiconductor package 2200 including, for example, a semiconductor chip 2220, a connecting member 2240, a passivation layer 2250, and an under bump metal layer 2260, do.

As described above, the fan-in semiconductor package is a package in which all the connection pads of the semiconductor chip, for example, I / O (Input / Output) terminals are disposed inside the element, and the fan-in semiconductor package has good electrical characteristics and can be produced at low cost have. Accordingly, many devices incorporated in a smart phone are manufactured in the form of a fan-in semiconductor package. Specifically, development is being made in order to implement a small-sized and fast signal transmission.

However, in the fan-in semiconductor package, all of the I / O terminals must be disposed inside the semiconductor chip, so that there are many space limitations. Therefore, such a structure is difficult to apply to a semiconductor chip having a large number of I / O terminals or a semiconductor chip having a small size. In addition, due to this vulnerability, the fan-in semiconductor package can not be directly mounted on the main board of the electronic device. This is because even if the size and spacing of the I / O terminals of the semiconductor chip are enlarged by the rewiring process, they do not have a size and a gap enough to be directly mounted on the electronic device main board.

5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.

6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.

Referring to the drawing, the fan-in semiconductor package 2200 is again rewired with the connection pads 2222 of the semiconductor chip 2220, that is, the I / O terminals through the interposer substrate 2301, May be mounted on the main board 2500 of the electronic device with the fan-in semiconductor package 2200 mounted on the interposer substrate 2301. At this time, the solder ball 2270 and the like can be fixed with the underfill resin 2280 and the outside can be covered with the molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the interposer substrate 2302 may be embedded in the connection pads 2220 of the semiconductor chip 2220, The I / O terminals 2222, i.e., the I / O terminals, may be re-routed again and finally mounted on the main board 2500 of the electronic device.

Since the fan-in semiconductor package is difficult to be directly mounted on the main board of the electronic apparatus, it is mounted on a separate interposer substrate and then re-packaged to be mounted on the electronic device main board, And is mounted on an electronic device main board while being embedded in a substrate.

(Fan-out semiconductor package)

7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.

In the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 is protected by the sealing material 2130, and the connection pad 2122 of the semiconductor chip 2120 is connected to the connection member 2120. [ The semiconductor chip 2120 is rewound to the outside of the semiconductor chip 2120. At this time, a passivation layer 2150 may be further formed on the connecting member 2140, and an under bump metal layer 2160 may be further formed on the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation film (not shown), and the like. The connecting member 2140 includes an insulating layer 2141, a re-wiring layer 2142 formed on the insulating layer 2241, and a via 2143 for electrically connecting the connecting pad 2122 and the re-wiring layer 2142 .

As described above, the fan-out semiconductor package is formed by rewiring the I / O terminals to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all of the I / O terminals of the semiconductor chip must be disposed inside the semiconductor chip. If the element size is reduced, the ball size and pitch must be reduced. On the other hand, in the fan-out semiconductor package, the I / O terminals are rewired to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip so that the size of the semiconductor chip is reduced. And can be mounted on a main board of an electronic device without a separate interposer substrate as will be described later.

8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.

Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on a main board 2500 of an electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes a connection member 2120 that can rewire the connection pad 2122 to the fan-out area beyond the size of the semiconductor chip 2120 on the semiconductor chip 2120, The standardized ball layout can be used as it is, and as a result, it can be mounted on the main board 2500 of the electronic apparatus without a separate interposer substrate or the like.

Since the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, the thickness of the fan-out semiconductor package can be reduced compared to a fan-in semiconductor package using the interposer substrate. Do. In addition, it has excellent thermal characteristics and electrical characteristics and is particularly suitable for mobile products. In addition, it can be implemented more compactly than a general POP (Package on Package) type using a printed circuit board (PCB), and it is possible to solve a problem caused by a bending phenomenon.

On the other hand, the fan-out semiconductor package means a package technology for mounting the semiconductor chip on a main board or the like of an electronic device and protecting the semiconductor chip from an external impact, and the scale, (PCB) such as an interposer substrate having a built-in fan-in semiconductor package.

Hereinafter, with respect to a fan-out semiconductor package in which a first connecting member having a re-wiring layer formed in a region where a semiconductor chip is sealed is introduced, and the unevenness of the insulation distance of the second connecting member caused by the thickness of the re- Will be described with reference to the drawings.

9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.

10 is a schematic sectional elevational-cut view of the fan-out semiconductor package of FIG.

Referring to FIG. 1, a fan-out semiconductor package 100A according to an exemplary embodiment includes a first connection member 110 having a through hole 110H, a through hole 110H of the first connection member 110, The first connecting member 110 and the semiconductor chip 120 having the active surface on which the semiconductor chip 120 is disposed and the inactive surface disposed on the opposite side of the active surface, And a second connection member 140 (140) including a first connection member (110) and a redistribution layer (142a, 142b) disposed on the active surface of the semiconductor chip (120) and electrically connected to the connection pad ). The first connection member 110 includes a first insulation layer 111a contacting the second connection member 140 and a first rewiring layer 112a which contacts the second connection member 140 and is embedded in the first insulation layer 111a. A second redistribution layer 112b disposed on the opposite side of the first insulation layer 111a on the side where the first redistribution layer 112a is embedded; a second redistribution layer 112b disposed on the first insulation layer 111a, A second insulating layer 111b covering the first insulating layer 112b and a third redistribution layer 112c disposed on the second insulating layer 111b. The first to third rewiring layers 112a, 112b, and 112c are electrically connected to the connection pad 122. In addition, the exemplary fan-out semiconductor package 100A includes a passivation layer 150 disposed on the second connection member 140, an under bump metal layer 150 disposed on the opening 151 of the passivation layer 150, (160) and a connection terminal (170) disposed on the under bump metal layer (160).

In general, the fan-out semiconductor package has a structure in which the periphery of the semiconductor chip is simply sealed with a sealing material such as EMC (Epoxy Molding Compound) or the like, and a second connection member is formed at a lower portion thereof, . However, when the periphery of the semiconductor chip is simply sealed with the sealing material, it is difficult to control the warpage caused by various causes, and there is a limitation in fixing the semiconductor chip. In addition, It is difficult to utilize them, and the degree of freedom of wiring design is reduced.

As a method of improving this, for example, as shown in FIG. 34, a first connecting member 210 'made of an insulating layer 211' having an excellent rigidity is introduced into a region where a semiconductor chip is sealed, It may be considered that a rewiring layer 212a ', 212b', a via 213 ', or the like is formed in the connecting member 210' to improve a bending problem and provide a wider routing area. In this case, the level difference H is generated by the thickness of the re-wiring layer 212a 'formed on one side of the first connection member 210'. The stepped portion H has a problem that the insulation distance of the second connection member 240 'is uneven. The step height H caused by the thickness of the normal re-distribution layer 212a 'is at least about 10 占 퐉, and thus the unevenness of the insulation distance is greatly influenced by the design of the first via 243a' of the second connection member 212a ' . That is, the unevenness of the insulation distance becomes an element that makes it difficult to fine pitch the via 243a 'connected to the connection pad 222' of the semiconductor chip 220 '. As a result, 240 ") is difficult to design.

On the other hand, the first rewiring layer 112a of the first connection member 110, which is in contact with the second connection member 140 as in the exemplary fan-out semiconductor package 100A, is embedded in the first insulation layer 111a The step generated by the thickness of the first rewiring layer 112a is minimized so that the insulation distance of the second connection member 140 becomes constant. The distance from the rewiring layer 142a of the second connection member 140 to the lower surface of the first insulation layer 111a and the distance from the rewiring layer 142a of the second connection member 140 to the connection pad 122 Is smaller than the thickness of the first redistribution layer 112a. Therefore, there is an advantage that the high-density wiring design of the second connection member 140 is easy.

Hereinafter, each configuration included in the fan-out semiconductor package 100A according to the example will be described in more detail.

The first connection member 110 can reduce the number of bars of the second connection member 140 including the redistribution layers 112a and 112b for rewiring the connection pads 122 of the semiconductor chip 120. [ The rigidity of the package 100A can be maintained according to a specific material and the function of securing the thickness uniformity of the sealing material 130 can be performed. In some cases, the fan-out semiconductor package 100A according to the example of the first connecting member 110 may be used as a part of a Package on Package. The first connecting member 110 has a through hole 110H. In the through hole 110H, the semiconductor chip 120 is disposed to be spaced apart from the first connection member 110 by a predetermined distance. The periphery of the side surface of the semiconductor chip 120 may be surrounded by the first connection member 110. However, it is to be understood that the present invention is not limited thereto and various modifications may be made in other forms, and other functions may be performed according to the forms.

The first connection member 110 includes a first insulation layer 111a contacting the second connection member 140 and a first rewiring layer 112a which contacts the second connection member 140 and is embedded in the first insulation layer 111a. A second redistribution layer 112b disposed on the opposite side of the first insulation layer 111a on the side where the first redistribution layer 112a is embedded; a second redistribution layer 112b disposed on the first insulation layer 111a, A second insulating layer 111b covering the first insulating layer 112b and a third redistribution layer 112c disposed on the second insulating layer 111b. The first to third rewiring layers 112a, 112b, and 112c are electrically connected to the connection pad 122. The first connection member 110 passes through the first and second insulation layers 111a and 111b and is electrically connected to the first and second rewiring layers 112a and 112b and the second and third rewiring layers 112b and 112c And first and second vias 113a and 113b, which are electrically connected to each other. Since the first rewiring layer 112a is buried, the insulation distance of the insulating layer 141a of the second connection member 140 can be substantially constant as described above. Since the first connection member 110 includes a large number of rewiring layers 112a, 112b and 112c, the second connection member 140 can be further simplified. Therefore, it is possible to improve the yield reduction due to defects generated in the process of forming the second linking member 140.

The material of the insulating layers 111a and 111b is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a core material such as a glass cloth (glass cloth) For example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (bismaleimide triazine), or the like can be used. If desired, a photosensitive insulator (PID) resin may be used. The first insulating layer 111a and the second insulating layer 111b may include the same insulating material, and the boundaries thereof may be unclear, but are not limited thereto.

The redistribution layers 112a, 112b and 112c serve to rewire the connection pads 122 of the semiconductor chip 120. The redistribution layers 112a, 112b and 112c are formed of copper (Cu), aluminum (Al), silver (Ag) (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers 112a, 112b, 112c can perform various functions according to the design design of the layer. For example, it may include a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern, Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. It also includes via pads, connection terminal pads, and the like. As a non-limiting example, the rewiring layers 112a, 112b, and 112c may include a ground pattern. In this case, the rewiring layers 142a and 142b of the second connection member 140 may be formed by minimizing the ground pattern As a result, the degree of freedom in wiring design can be improved.

A surface treatment layer (not shown) may be further formed on the partially rewiring layer 112c exposed through the opening 131 formed in the sealing material 130 among the rewiring layers 112a, 112b, and 112c. The surface treatment layer (not shown) is not particularly limited as long as it is a known one, and examples thereof include electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / HASL or the like.

The vias 113a and 113b electrically connect the redistribution layers 112a, 112b, and 112c formed in the different layers, thereby forming an electrical path in the first connection member 110. [ As the forming material of the vias 113a and 113b, a conductive material may also be used. The via 113 may be completely filled with a conductive material as shown in Fig. 11, or a conductive material may be formed along the wall surface of the via hole. In addition, not only tapered but also all known shapes such as a cylindrical shape can be applied. Meanwhile, as will be described later, some pads of the first rewiring layer 112a may serve as stoppers when forming the holes for the first vias 113a, and the second vias 113b Some of the pads of the second rewiring layer 112b may serve as stoppers when the holes for the first and second vias 113a and 113b are formed. It may be advantageous in terms of the process to be larger in taper shape. In this case, the first via 113a may be integrated with a part of the second rewiring layer 112b, and the second via 113b may be integrated with a part of the third rewiring layer 112c.

The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. The integrated circuit may, for example, be but is not limited to an application processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, . The semiconductor chip 120 may be formed on the basis of an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as a base material of the body 121. The body 121 may have various circuits. The connection pad 122 electrically connects the semiconductor chip 120 to other components. As the forming material, a conductive material such as aluminum (Al) may be used without any particular limitation. A passivation film 123 exposing the connection pad 122 may be formed on the body 121. The passivation film 123 may be an oxide film or a nitride film or may be a double layer of an oxide film and a nitride film. The lower surface of the connection pad 122 may have a step with the lower surface of the sealing material 130 through the passivation film 123 so that the sealing material 130 can be prevented from bleeding to the lower surface of the connection pad 122 to some extent have. An insulating film (not shown) or the like may be further disposed at a necessary position.

The inactive surface of the semiconductor chip 120 may be positioned below the upper surface of the third rewiring layer 112c of the first connection member 110. [ For example, the inactive surface of the semiconductor chip 120 may be positioned below the upper surface of the second insulating layer 111b of the first connecting member 110. [ The height difference between the inactive surface of the semiconductor chip 120 and the top surface of the third redistribution layer 112c of the first connection member 110 may be 2 占 퐉 or more, for example, 5 占 퐉 or more. At this time, cracks occurring at the corners of the inactive surface of the semiconductor chip 120 can be effectively prevented. In addition, the deviation of the insulation distance on the inactive surface of the semiconductor chip 120 when the sealing material 130 is applied can be minimized.

The second rewiring layer 112b of the first connection member 110 may be positioned between the active surface and the inactive surface of the semiconductor chip 120. [ The first connection member 110 may be formed to have a thickness corresponding to the thickness of the semiconductor chip 120 so that the second rewiring layer 112b formed in the first connection member 110 is electrically connected to the semiconductor chip 120 May be disposed at a level between the active surface and the inactive surface.

The sealing member 130 may protect the first connection member 110 and / or the semiconductor chip 120. [ The sealing shape is not particularly limited and may be a shape that covers at least a part of the first connection member 110 and / or the semiconductor chip 120. For example, the sealing member 130 may cover the inactive surfaces of the first connecting member 110 and the semiconductor chip 120, and may be formed to have a space between the wall surface of the through hole 110H and the side surface of the semiconductor chip 120 Can be filled. The sealing member 130 may fill at least a part of the space between the passivation film 123 of the semiconductor chip 120 and the second connecting member 140. [ On the other hand, by filling the through hole 110H with the sealing material 130, it can act as an adhesive according to a specific material and reduce buckling.

The specific material of the sealing material 130 is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin containing a reinforcing material such as an inorganic filler, for example, ABF, FR-4, BT, PID resin, etc. may be used. It is needless to say that a known molding material such as EMC may be used. If necessary, a thermosetting resin or a resin impregnated with a core material such as glass cloth (glass cloth) together with an inorganic filler with a thermoplastic resin may be used.

The sealing material 130 may be composed of a plurality of layers made of a plurality of materials. For example, the space in the through hole 110H may be filled with the first sealing material, and then the first connecting member 110 and the semiconductor chip 120 may be covered with the second sealing material. Alternatively, it is also possible to fill the space in the through hole 110H with the first sealing material, cover the first connecting member 110 and the semiconductor chip 120 with a predetermined thickness, The sealing material may be used in a form of covering the sealing material again with a predetermined thickness. In addition, it can be applied in various forms.

The sealing material 130 may include conductive particles as needed for shielding electromagnetic waves. The conductive particles may be any of those capable of interrupting the electromagnetic wave, and examples of the conductive particles include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au) (Pd), titanium (Ti), solder, or the like, but this is merely an example, and the present invention is not limited thereto.

The second connection member 140 is a structure for rewiring the connection pad 122 of the semiconductor chip 120. Hundreds of hundreds of connection pads 122 having various functions can be rewired through the second connection member 140 and physically and / or electrically connected to the outside through the connection terminal 170 to be described later . The second connection member 140 penetrates through the insulating layers 141a and 141b, the re-wiring layers 142a and 142b disposed on the insulating layers 141a and 141b and the insulating layers 141a and 141b, And 142b, respectively. In the fan-out semiconductor package 100A according to the exemplary embodiment, the plurality of re-wiring layers 142a and 142b are formed by the second connection member 140, but the present invention is not limited thereto. Needless to say, it is also possible to have a different number of layers.

As the material of the insulating layers 141a and 141b, an insulating material may be used. In addition to the above-described insulating material, a photosensitive insulating material such as a PID resin may be used as the insulating material. In this case, the insulating layers 141a and 141b can be formed to be thinner and the pitches of the vias 143a and 143b can be more easily achieved. The materials of the insulating layers 141a and 141b may be the same as each other, and may be different from each other if necessary. The insulating layers 141a and 141b may be integrated according to the process, and the boundaries may be unclear.

The re-distribution layers 142a and 142b substantially rewire the connection pad 122 and may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn) (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The re-distribution layers 142a and 142b can perform various functions according to the design design of the layer. For example, a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern and the like. Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. It also includes via pads, connection terminal pads, and the like.

A surface treatment layer (not shown) may be further formed on the partially rewiring layer 142b of the rewiring layers 142a and 142b as necessary. The surface treatment layer (not shown) is not particularly limited as long as it is known in the art, and examples thereof include electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / , DIG plating, HASL, or the like.

The vias 143a and 143b electrically connect the rewiring layers 142a and 142b and the connection pad 122 formed in different layers and thereby form an electrical path in the package 100A. As the material for forming the vias 143a and 143b, copper, aluminum, silver, tin, gold, nickel, lead, titanium, , Or an alloy thereof can be used. The vias 143a and 143b may be completely filled with a conductive material, or a conductive material may be formed along the wall of the via. In addition, any shape known in the art, such as a tapered shape, a cylindrical shape, etc., can be applied.

The thickness of the redistribution layers 112a, 112b and 112c of the first connection member 110 may be thicker than the thickness of the redistribution layers 142a and 142b of the second connection member 140. [ The first connection member 110 may have a thickness greater than that of the semiconductor chip 120 and the rewiring layers 112a, 112b, and 112c formed thereon may be formed in a larger size to match the scale. On the other hand, the redistribution layers 142a and 142b of the second connection member 140 are relatively smaller than the redistribution layers 112a, 112b, and 112c of the first connection member 110 for reducing the thickness of the second connection member 140 .

The passivation layer 150 is an additional structure for protecting the second connection member 140 from external physical chemical damage or the like. The passivation layer 150 may have an opening 151 for exposing at least a part of the rewiring layer 142b among the rewiring layers 142a and 142b of the second connection member 140. [ The opening 151 can completely or partially expose only one side of the re-wiring layer 142b. The material of the passivation layer 150 is not particularly limited, and for example, a photosensitive insulating material such as a photosensitive insulating resin can be used. Alternatively, a solder resist may be used. Alternatively, an ABF (Ajinomoto Build-up Film) including an insulating resin including a filler, for example, an inorganic filler and an epoxy resin, which does not include a core, may be used.

The under bump metal layer 160 is an additional structure for improving the connection reliability of the connection terminal 170 to improve the board level reliability. The under bump metal layer 160 may be disposed on the wall surface in the opening 151 of the passivation layer 150 and on the rewiring layer 142b of the exposed second connecting member 140. [ The under bump metal layer 160 can be formed by a known metalization method using a known conductive material, that is, a metal.

The connection terminal 170 is an additional configuration for physically and / or electrically connecting the fan-out semiconductor package 100A to the outside. For example, the fan-out semiconductor package 100A may be mounted on the main board of the electronic device via the connection terminal 170. [ The connection terminal 170 may be formed of a conductive material, for example, a solder or the like, but this is merely an example and the material is not particularly limited thereto. The connection terminal 170 may be a land, a ball, a pin, or the like. The connection terminal 170 may be formed as a multilayer or a single layer. In the case of a multi-layered structure, it may include a copper pillar and a solder. In the case of a single layer, tin-silver may include solder or copper. However, the present invention is not limited thereto. . The number, spacing, arrangement type, etc. of the connection terminals 170 are not particularly limited and can be sufficiently modified according to the design specifications of the ordinary artisan. For example, the number of the connection terminals 170 may be several tens to several thousands depending on the number of the connection pads 122 of the semiconductor chip 120, and may have more or less numbers.

At least one of the connection terminals 170 is disposed in a fan-out region. The fan-out area means an area outside the area where the semiconductor chip 120 is disposed. That is, the semiconductor package 100A according to the example is a fan-out package. The fan-out package is more reliable than the fan-in package, allows multiple I / O terminals, and facilitates 3D interconnection. In addition, compared with BGA (Ball Grid Array) package and LGA (Land Grid Array) package, it is possible to manufacture a thin bar that can be mounted on electronic devices without a separate substrate, and is excellent in price competitiveness.

Although not shown in the drawing, a plurality of semiconductor chips (not shown) may be disposed in the through holes 110H of the first connection member 110, if necessary, and the through holes 110H of the first connection member 110 (Not shown), and a semiconductor chip (not shown) may be disposed in each of the through holes. Further, other passive components (not shown) such as a capacitor, an inductor, and the like may be sealed together in the through hole 110H together with the semiconductor chip. Surface mount components (not shown) may also be mounted on the passivation layer 150.

Figs. 12A to 12D are schematic manufacturing examples of the fan-out semiconductor package of Fig.

12A, first, a carrier film 301 is prepared. Metal films 302 and 303 may be formed on one side or both sides of the carrier film 301. The bonding surfaces between the metal films 302 and 303 may be surface-treated so as to facilitate separation in the subsequent separation process. Alternatively, a release layer may be provided between the metal films 302 and 303 to facilitate separation in a subsequent process. The carrier film 301 may be a known insulating substrate, and any material may be used. The metal films 302 and 303 may be generally copper foils, but are not limited thereto, and may be thin films made of other conductive materials. Next, the dry film 304 is used to perform patterning for forming the first rewiring layer 112a. This can be formed by using a known photolithography method. The dry film 304 may be a known dry film made of a photosensitive material. Next, the patterned space of the dry film 304 is filled with a conductive material to form a first rewiring layer 112a. A plating process may be used. At this time, the metal film 303 may serve as a seed layer. Examples of the plating process include electroplating or electroless plating, specifically, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, subtractive, additive, SAP (Semi- Additive Process, Modified Semi-Additive Process (MSAP), and the like, but the present invention is not limited thereto. Next, the dry film 304 is removed. A known method such as an etching process can be used.

Referring to Fig. 12B, next, a first insulating layer 111a is formed on the metal film 303 to fill at least a part of the rewiring layer 112a. Thereafter, a first via 113a penetrating the first insulating layer 111a is formed. Further, a second rewiring layer 112b is formed on the first insulating layer 111a. The first insulating layer 111a may be formed by a method of laminating a precursor by a known lamination method and curing, or a method of applying a precursor material by a known coating method and curing. The first via 113a and the second redistribution layer 112b may be formed by forming a via hole in the first insulating layer 111a using a photolithography method, a mechanical drill, and / or a laser drill, And filling the via hole and the patterned space with a plating process or the like. Next, a second insulating layer 111b covering the second rewiring layer 112b is formed on the first insulating layer 111a. Thereafter, a second via 113b penetrating the second insulating layer 111b is formed. Further, a third re-wiring layer 113b is formed on the second insulating layer 112a. The forming method of these is the same as described above. Next, the carrier film 301 is peeled off. At this time, the peeling may be that the metal films 302 and 303 are separated. Blades may be used for the separation, but not limited thereto, and all known methods can be used. However, the present invention is not limited to this. The carrier film 301 may be peeled off before the peeling off of the carrier film 301, 1 connection member 110 may be formed. That is, the order is not necessarily limited to the order described.

Referring to FIG. 12C, the remaining metal film 303 is removed by a known etching method or the like, and a through hole 110H is formed in the first connection member 110. Next, as shown in FIG. The through hole 110H can be formed by a mechanical drill and / or a laser drill. However, the present invention is not limited to this, and may be performed by a sandblast method using abrasive particles, a dry etching method using plasma, or the like. In the case of forming using a mechanical drill and / or a laser drill, a desmear treatment such as a permanganate method is performed to remove the resin smear in the hole 110H. Next, an adhesive film 305 is attached to one side of the first linking member 110. The adhesive film 305 can be used as long as it can fix the first connecting member 110, and a known tape or the like can be used as a non-limiting example. Examples of known tapes include a heat-curable adhesive tape which is weakened in adhesion by heat treatment, and an ultraviolet-curable adhesive tape whose adhesion is weakened by ultraviolet irradiation. Next, the semiconductor chip 120 is disposed in the through hole 110H of the first connection member 110. Next, For example, the semiconductor chip 120 is disposed on the adhesive film 305 in the through hole 110H by a method of attaching the semiconductor chip 120 thereto. The semiconductor chip 120 is disposed in a face-down manner so that the connection pad 122 is attached to the adhesive film 305.

Referring to FIG. 12D, next, the semiconductor chip 120 is sealed using the sealing material 130. FIG. The sealing member 130 at least seals the inactive surface of the first connecting member 110 and the semiconductor chip 120 and fills the space in the through hole 110H. The sealing material 130 may be formed by a known method. For example, the sealing material 130 may be formed by laminating and then curing the precursor of the sealing material 130. Alternatively, the sealing material 130 may be applied and cured so that the semiconductor chip 120 can be sealed on the adhesive film 305. The semiconductor chip 120 is fixed by curing. As the lamination method, for example, a hot pressing method in which the resin is pressed at a high temperature for a certain period of time and then reduced in pressure to room temperature, and then cooled in a cold press to separate the working tool can be used. As the application method, for example, a screen printing method in which ink is applied by squeezing, a spray printing method in which ink is fogged and applied, and the like can be used. Next, the adhesive film 305 is peeled off. The peeling method is not particularly limited, and can be carried out by a known method. For example, when a heat-curable adhesive tape whose adhesion is weakened by heat treatment with the adhesive film 305, an ultraviolet-curable adhesive tape whose adhesion is weakened by ultraviolet irradiation is used, the adhesive film 305 is heat- Or may be performed after weakening the adhesive force by irradiating the adhesive film 305 with ultraviolet light. Next, the second connection member 140 is formed on the active surface of the semiconductor chip 120 and the first connection member 110 from which the adhesive film 305 is removed. The second connection member 140 is formed by successively forming the insulating layers 141a and 141b and after forming the insulating layers 141a and 141b, the re-wiring layers 142a and 142b and the vias 143a and 143b, And 143b. If necessary, a passivation layer 150 is formed on the second connecting member 140. The passivation layer 150 may be formed by a method of laminating the passivation layer 150 precursor and then curing the passivation layer 150, a method of applying the material for forming the passivation layer 150, and then curing the passivation layer 150. An opening (not shown) may be formed in the passivation layer 150 such that at least a portion of the redistribution layer 142b of the second connection member 140 is exposed, and an under bump metal layer 160 ) May be formed. If necessary, the connection terminal 170 is formed on the under bump metal layer 160. The method of forming the connection terminal 170 is not particularly limited and may be formed by a known method well known in the art depending on its structure and form. The connection terminal 170 may be fixed by reflow and a part of the connection terminal 170 may be buried in the passivation layer 150 and the remaining part may be exposed to the outside in order to enhance the fixing force, .

A plurality of fan-out semiconductor packages 100A are manufactured after a carrier film 301 of a large capacity size is prepared so as to facilitate mass production, and then a separate fan-out semiconductor package 100A is manufactured through a sawing process. And may be singulated with the package 100A. In this case, there is an advantage that productivity is excellent.

13 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.

Figure 14 is a schematic diagram of the fan-out semiconductor package of Figure 13; Fig.

Referring to the drawings, in a fan-out semiconductor package 100B according to a modification, a metal layer 114 is disposed on a wall surface of a through hole 110H of a first connection member 110. FIG. The metal layer 114 effectively disperses heat generated in the semiconductor chip 120. In addition, the metal layer 114 may also prevent electromagnetic interference. The metal layer 114 may be connected to the ground patterns of the other rewiring layers 112a, 112b and 112c of the first connection member 110 to be used as a ground. The metal layer 114 may be disposed on the entire wall surface or may be patterned and arranged in a specific shape. The metal layer 114 may comprise a conductive material, such as a metal material, as described above.

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 100A according to the example.

15 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.

Figure 16 is a schematic cross-sectional view of the fan-out semiconductor package of Figure 15; Fig.

Referring to the drawings, in the fan-out semiconductor package 100C according to the modification, a separate first passive component 124 is disposed in the through hole 110H. Also, a separate second passive component 126 is disposed on the surface of the passivation layer 150. The first passive component 124 may be, but is not limited to, a high capacity capacitor, for example, an MLCC. The second passive component 126 may be a low-capacitance capacitor, for example, a Si-based capacitor, but is not limited thereto. They may be connected to the same power line, and may be electrically connected to the semiconductor chip 120 to improve power supply efficiency.

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 100A according to the example.

17 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.

Figure 18 is a schematic diagram of the fan-out semiconductor package of Figure 17; Fig.

Referring to the drawings, in the fan-out semiconductor package 100D according to the modification, the first connection member 110 is formed of one or more connection units 110A to 110E. Each connecting unit 100A to 100E is disposed around the semiconductor chip 120. [ Each of the connection units 100A to 100E is in contact with the first insulation layer 111a-1, 111a-2, etc. and the second connection member 140 and is embedded in the first insulation layers 111a-1 and 111a-2, The first rewiring layers 112a-1 and 112a-2 and the like of the first rewiring layers 112a-1 and 112a-2 and the like of the first insulation layers 111a-1 and 111a-2, The second rewiring layers 112b-1, 112b-2, and the like disposed on the first insulating layers 111a-1, 111a-2, The third rewiring layer 112c-1, 112c-2, etc.) disposed on the second insulating layer 111b-1, 111b-2, . The first to third rewiring layers 112a-1, 112a-2, 112b-1, 112b-2, 112c-1 and 112c-2 of the connection units 100A to 100E are electrically connected to the connection pads 122 Lt; / RTI > The sealing member 130 seals at least a part of the inactive surface of the semiconductor chip 120 and each connecting unit 100A to 100E. The sealing member 130 seals all of the side surfaces of each connecting unit 100A to 100E. As a result, the side surfaces of the respective connection units 100A to 100E are not exposed to the outside.

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 100A according to the example.

Fig. 19 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig. 9;

Referring to the drawings, in a fan-out semiconductor package 100E according to a modification, a third material (not shown) of a first connecting member 110 is connected to a sealing material 130 via a via 183 passing through a sealing material 130 A re-wiring layer 182 electrically connected to the wiring layer 112c is disposed. A passivation layer 180 having an opening (not shown) for exposing a part of the re-wiring layer 182 is disposed on the sealing material 130. On the opening (not shown), separate surface-mounted components 181 and 186 are disposed and electrically connected to the re-wiring layer 182. The surface mount components 181 and 186 may be directly connected to the redistribution layer 182 or may be connected through soldering (not shown) or the like to the underbump metal layer 184 and the connection terminal 185 . The surface mount components 181 and 186 may be various kinds of passive components or may be various kinds of integrated circuits.

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 100A according to the example.

Fig. 20 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig. 9;

Referring to the drawings, a memory chip package 187 is stacked on a sealing material 130 in a fan-out semiconductor package 100F according to a modification. The memory chip package 187 includes an under bump metal layer 184 and an under bump metal layer 184 formed in the opening 131 exposing a part of the third redistribution layer 112c of the first connection member 110 of the sealant 130 And is electrically connected to the third rewiring layer 112c of the first connection member 110 through the connection terminal 185 formed on the first connection member 184. Memory chip package 187 may be one that includes memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory,

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 100A according to the example.

Fig. 21 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig. 9;

Referring to the drawings, in the fan-out semiconductor package 100G according to the modification, the first rewiring layer 112a is recessed into the first insulating layer, so that the lower surface of the first insulating layer 111a, The lower surface of the wiring layer 112a has a step. As a result, it is possible to prevent the material for forming the sealant 130 from being contaminated by contamination of the first rewiring layer 112a when the sealant 130 is formed. The lower surface of the first rewiring layer 112a of the first connection member 110 is formed on the lower surface of the semiconductor chip 120. The first rewiring layer 112a is recessed into the first insulation layer 111a, And may be located on the upper side of the lower surface of the connection pad 122. The distance between the rewiring layer 142a of the second connecting member 140 and the first rewiring layer 112a of the first connecting member 110 is larger than the distance between the rewiring layer 142a of the second connecting member 140, May be greater than the distance between the connection pads (122) of the substrate (120).

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 100A according to the example.

22 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.

In the fan-out semiconductor package 100H according to the modification, the first connecting member 110 is disposed on the second insulating layer 112b, and the third insulating layer 112b covers the third rewiring layer 112c. And a fourth rewiring layer 112d disposed on the third insulating layer 112c and the third insulating layer 112c. That is, the first connection member 110 can have a greater number of redistribution layers 112a, 112b, 112c and 112d. As a result, the second connecting member 140 can be further minimized, and thus the process yield and the like can be further improved as described above.

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 100A according to the example.

23 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

24 is a schematic V-V 'cutting plan view of the fan-out semiconductor package of FIG.

Referring to the drawings, a fan-out semiconductor package 200B according to another embodiment includes a first connection member 210 having a through hole 210H, a through hole 210H of the first connection member 210, The first connection member 210 and the semiconductor chip 220 having the active surface on which the pad 222 is disposed and the inactive surface disposed on the opposite side of the active surface, And a second connection member (230) including a rewiring layer (242a, 242b) electrically connected to the connection pad (222) and disposed on the active surface of the first connection member (210) 240). The first connection member 210 includes an insulation layer 211 in contact with the second connection member 240, a first rewiring layer 212a in contact with the second connection member 240 and embedded in the insulation layer 211, And a second rewiring layer 212b disposed on the opposite side of the layer 211 on the side where the first rewiring layer 212a is embedded. The first connection member 210 includes a via 213 which penetrates the insulating layer 211 and electrically connects the first and second rewiring layers 212a and 112b. The first and second rewiring layers 212a and 212b are electrically connected to the connection pad 222. In addition, another exemplary fan-out semiconductor package 200A includes a passivation layer 250 disposed on the second connection member 240, an under bump 250 disposed on the opening 251 of the passivation layer 250, And a connection terminal 270 disposed on the metal layer 260 and the under bump metal layer 260.

When the first rewiring layer 212a of the first connection member 210 in contact with the second connection member 240 is buried in the insulating layer 211 like the fan-out semiconductor package 200A according to another example, Since the step generated by the thickness of the first rewiring layer 212a is minimized, the insulation distance of the second connection member 240 becomes constant. The distance from the rewiring layer 242a of the second connection member 240 to the lower surface of the insulating layer 211 and the distance from the rewiring layer 242a of the second connection member 240 to the connection pad 222 Is smaller than the thickness of the first redistribution layer 212a. Therefore, there is an advantage that the design of the high-density wiring of the second connection member 240 is easy.

Hereinafter, each configuration included in the fan-out semiconductor package 200B according to another example will be described in more detail.

The first connection member 210 can reduce the number of bars of the second connection member 240 including the redistribution layers 212a and 212b for rewiring the connection pads 222 of the semiconductor chip 220. [ According to need, rigidity of the package 200A can be maintained according to a specific material, and the function of securing the thickness uniformity of the sealing material 230 can be performed. The first connecting member 210 has a through hole 210H. In the through hole 210H, the semiconductor chip 220 is disposed to be spaced apart from the first connection member 210 by a predetermined distance. The side surface of the semiconductor chip 220 may be surrounded by the first connection member 210. However, it is to be understood that the present invention is not limited thereto and various modifications may be made in other forms, and other functions may be performed according to the forms.

The material of the insulating layer 211 is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a core material such as a glass cloth (glass cloth) For example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (bismaleimide triazine), or the like can be used. If desired, a photosensitive insulator (PID) resin may be used.

The rewiring layers 212a and 212b serve to rewire the connection pads 222 of the semiconductor chip 220. Copper (Cu), aluminum (Al), silver (Ag), tin ), Gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers 212a, 212b, and 212c may perform various functions according to the design design of the layer. For example, it may include a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern, Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. It also includes via pads, connection terminal pads, and the like. As a non-limiting example, the rewiring layers 212a and 212b may include a ground pattern. In this case, the rewiring layers 242a and 242b of the second connection member 240 may be formed by minimizing the ground pattern. , The degree of freedom in wiring design can be improved.

A surface treatment layer (not shown) may be further formed on the partially rewiring layer 212b exposed through the opening 231 formed in the sealing material 230 among the rewiring layers 212a and 212b. The surface treatment layer (not shown) is not particularly limited as long as it is a known one, and examples thereof include electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / HASL or the like.

The vias 213 electrically connect the rewiring layers 212a and 212b formed in the different layers, thereby forming an electrical path in the first connection member 210. [ The via 213 may also be formed of a conductive material. The via 213 may be completely filled with a conductive material, as shown in Fig. 25, or a conductive material may be formed along the wall surface of the via hole. In addition, not only tapered but also all known shapes such as a cylindrical shape can be applied. Meanwhile, as will be described later, some pads of the first rewiring layer 212a may serve as stoppers when forming the holes for the vias 213, It is advantageous in terms of the process that the width of the lower surface is larger than the width of the lower surface. In this case, the via 213 can be integrated with a part of the second redistribution layer 212b.

The semiconductor chip 220 may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. The integrated circuit may, for example, be but is not limited to an application processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, . The semiconductor chip 220 may be formed on the basis of an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as a base material of the body 221. Various circuits may be formed in the body 221. The connection pad 222 electrically connects the semiconductor chip 220 to other components. As the forming material, a conductive material such as aluminum (Al) may be used without any particular limitation. A passivation film 223 exposing the connection pad 222 may be formed on the body 221. The passivation film 223 may be an oxide film or a nitride film or may be a double layer of an oxide film and a nitride film. The lower surface of the connection pad 222 may have a step with the lower surface of the sealing material 230 through the passivation film 223 so that the sealing material 230 can be prevented from bleeding to the lower surface of the connection pad 222 to some extent have. An insulating film (not shown) or the like may be further disposed at a necessary position.

The inactive surface of the semiconductor chip 220 may be located below the upper surface of the second rewiring layer 212b of the first connection member 210. [ For example, the non-active surface of the semiconductor chip 220 may be located below the upper surface of the insulating layer 211 of the first connection member 210. The height difference between the inactive surface of the semiconductor chip 220 and the upper surface of the second rewiring layer 212b of the first connecting member 210 may be 2 占 퐉 or more, for example, 5 占 퐉 or more. At this time, cracks occurring at the corners of the inactive surface of the semiconductor chip 220 can be effectively prevented. In addition, the deviation of the insulation distance on the inactive surface of the semiconductor chip 220 when the sealing material 230 is applied can be minimized.

The sealing member 230 may protect the first connection member 210 and / or the semiconductor chip 220. [ The sealing shape is not particularly limited and may be any shape that covers at least a part of the first connection member 210 and / or the semiconductor chip 220. For example, the sealing material 230 may cover the inactive surfaces of the first connection member 210 and the semiconductor chip 220, and the space between the wall surface of the through hole 210H and the side surface of the semiconductor chip 220 Can be filled. The sealing member 230 may fill at least a part of the space between the passivation film 223 of the semiconductor chip 220 and the second connecting member 240. On the other hand, by filling the through hole 210H with the sealing material 230, it is possible to reduce buckling while performing an adhesive function according to a specific material.

The specific material of the sealing material 230 is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin containing a reinforcing material such as an inorganic filler, for example, ABF, FR-4, BT, PID resin, etc. may be used. It is needless to say that a known molding material such as EMC may be used. If necessary, a thermosetting resin or a resin impregnated with a core material such as glass cloth (glass cloth) together with an inorganic filler with a thermoplastic resin may be used.

The sealing material 230 may be composed of a plurality of layers made of a plurality of materials. For example, the space in the through hole 210H may be filled with the first sealing material, and then the first connecting member 210 and the semiconductor chip 220 may be covered with the second sealing material. Alternatively, the first sealing member may be used to fill the space in the through hole 210H to cover the first connecting member 210 and the semiconductor chip 220 with a predetermined thickness, and then the second sealing member 210 The sealing material may be used in a form of covering the sealing material again with a predetermined thickness. In addition, it can be applied in various forms.

The sealing material 230 may include conductive particles as needed for shielding electromagnetic waves. The conductive particles may be any of those capable of interrupting the electromagnetic wave, and examples of the conductive particles include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au) (Pd), titanium (Ti), solder, or the like, but this is merely an example, and the present invention is not limited thereto.

The second connection member 240 is a structure for rewiring the connection pad 222 of the semiconductor chip 220. Several hundreds of connection pads 222 having various functions may be rewired through the second connection member 240 and may be physically and / or electrically connected to the outside through the connection terminal 270 described later . The second connecting member 240 is connected to the re-wiring layers 242a and 242b through the insulating layers 241a and 241b, the re-wiring layers 242a and 242b disposed on the insulating layers 241a and 241b, And vias 243a and 243b connecting the first and second electrodes 242a and 242b. In the fan-out semiconductor package 200A according to another example, the plurality of redistribution layers 242a and 242b are formed by the second connection member 240, but they may be formed of a single layer. Needless to say, it is also possible to have a different number of layers.

As the material of the insulating layers 241a and 241b, an insulating material may be used. In addition to the insulating material as described above, a photosensitive insulating material such as a PID resin may be used as the insulating material. In this case, the insulating layers 241a and 241b can be made thinner and the pitches of the vias 243a and 243b can be more easily achieved. The materials of the insulating layers 241a and 241b may be the same as each other, and may be different from each other as needed. The insulating layers 241a and 241b may be integrated according to the process, and the boundaries may be unclear.

The re-distribution layers 242a and 242b substantially rewire the connection pads 222 and may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn) (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The redistribution layers 242a and 242b can perform various functions according to the design design of the layer. For example, a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern and the like. Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. It also includes via pads, connection terminal pads, and the like.

A surface treatment layer (not shown) may be further formed on the partially rewiring layer 242b of the rewiring layers 242a and 242b as necessary. The surface treatment layer (not shown) is not particularly limited as long as it is known in the art, and examples thereof include electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / , DIG plating, HASL, or the like.

The vias 243a and 243b electrically connect the rewiring layers 242a and 242b formed in different layers and the connection pads 222 and so on to form an electrical path in the package 200B. As the material for forming the vias 243a and 243b, copper, aluminum, silver, tin, gold, nickel, lead, titanium, , Or an alloy thereof can be used. The vias 243a and 243b may be completely filled with a conductive material, or a conductive material may be formed along the wall of the via. In addition, any shape known in the art, such as a tapered shape, a cylindrical shape, etc., can be applied.

The thickness of the redistribution layers 212a and 212b of the first connection member 210 may be thicker than the thickness of the redistribution layers 242a and 242b of the second connection member 240. [ The first connection member 210 may have a thickness greater than that of the semiconductor chip 220, and the re-wiring layers 212a and 212b formed thereon may be formed in a larger size to match the scale. On the other hand, the redistribution layers 242a and 242b of the second connection member 240 are formed to be relatively smaller than the redistribution layers 212a and 212b of the first connection member 210 in order to reduce the thickness of the second connection member 240 .

The passivation layer 250 is an additional structure for protecting the second connection member 240 from external physical chemical damage or the like. The passivation layer 250 may have an opening 251 that exposes at least a part of the re-wiring layer 242b among the re-wiring layers 242a and 242b of the second connection member 240. [ The openings 251 can expose only one portion of the re-distribution layer 242b completely or only partially. The material of the passivation layer 250 is not particularly limited, and for example, a photosensitive insulating material such as a photosensitive insulating resin can be used. Alternatively, a solder resist may be used. Alternatively, an ABF (Ajinomoto Build-up Film) including an insulating resin including a filler, for example, an inorganic filler and an epoxy resin, which does not include a core, may be used.

The under bump metal layer 260 is an additional structure for improving the connection reliability of the connection terminal 270 to improve the board level reliability. The under bump metal layer 260 may be disposed on the wall surface in the opening 251 of the passivation layer 250 and on the redistribution layer 242b of the exposed second connection member 240. [ The under bump metal layer 260 can be formed by a known metalization method using a known conductive material, that is, a metal.

The connection terminal 270 is an additional configuration for physically and / or electrically connecting the fan-out semiconductor package 200A to the outside. For example, the fan-out semiconductor package 200A may be mounted on the main board of the electronic device through the connection terminal 270. [ The connection terminal 270 may be formed of a conductive material, for example, a solder or the like, but this is merely an example and the material is not particularly limited thereto. The connection terminal 270 may be a land, a ball, a pin, or the like. The connection terminal 270 may be formed as a multilayer or a single layer. In the case of a multi-layered structure, it may include a copper pillar and a solder. In the case of a single layer, tin-silver may include solder or copper. However, the present invention is not limited thereto. . The number, spacing, arrangement and the like of the connection terminals 270 are not particularly limited and can be sufficiently modified according to the design specifications of the ordinary artisan. For example, the number of the connection terminals 270 may be several tens to several thousands depending on the number of the connection pads 222 of the semiconductor chip 220, and may be more or less.

At least one of the connection terminals 270 is disposed in a fan-out region. The fan-out area means an area outside the area where the semiconductor chip 220 is disposed. That is, the semiconductor package 200A according to the example is a fan-out package. The fan-out package is more reliable than the fan-in package, allows multiple I / O terminals, and facilitates 3D interconnection. In addition, compared with BGA (Ball Grid Array) package and LGA (Land Grid Array) package, it is possible to manufacture a thin bar that can be mounted on electronic devices without a separate substrate, and is excellent in price competitiveness.

Although not shown in the drawings, a plurality of semiconductor chips (not shown) may be disposed in the through holes 210H of the first connection member 210, and the through holes 210H of the first connection member 210 (Not shown), and a semiconductor chip (not shown) may be disposed in each of the through holes. In addition to the semiconductor chip, another passive component (not shown), for example, a capacitor, an inductor, and the like may be sealed together in the through hole 210H. Also, surface mount components (not shown) may be mounted on the passivation layer 250.

Figs. 26A to 26D are schematic manufacturing examples of the fan-out semiconductor package of Fig.

Referring to Fig. 26A, first, a carrier film 301 is prepared. Metal films 302 and 303 may be formed on one side or both sides of the carrier film 301. The bonding surfaces between the metal films 302 and 303 may be surface-treated so as to facilitate separation in the subsequent separation process. Alternatively, a release layer may be provided between the metal films 302 and 303 to facilitate separation in a subsequent process. The carrier film 301 may be a known insulating substrate, and any material may be used. The metal films 302 and 303 may be generally copper foils, but are not limited thereto, and may be thin films made of other conductive materials. Next, the dry film 304 is used to perform patterning for forming the first rewiring layer 212a. This can be formed by using a known photolithography method. The dry film 304 may be a known dry film made of a photosensitive material. Next, the patterned space of the dry film 304 is filled with a conductive material to form a first rewiring layer 212a. A plating process may be used. At this time, the metal film 303 may serve as a seed layer. Examples of the plating process include electroplating or electroless plating, specifically, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, subtractive, additive, SAP (Semi- Additive Process, Modified Semi-Additive Process (MSAP), and the like, but the present invention is not limited thereto. Next, the dry film 304 is removed. A known method such as an etching process can be used.

Referring to FIG. 26B, next, an insulating layer 211 for embedding at least a part of the rewiring layer 212a is formed on the metal film 303. Next, as shown in FIG. Thereafter, a via 213 penetrating the insulating layer 211 is formed. Further, a second rewiring layer 212b is formed on the insulating layer 211. [ The insulating layer 211 can be formed by a method of laminating a precursor by a known lamination method and then curing, or a method of applying a precursor material by a known coating method and curing. The via 213 and the second rewiring layer 212b are patterned with a dry film or the like after forming a via hole in the insulating layer 211 by photolithography, mechanical drilling, and / or laser drilling, And filling the via hole with the patterned space. Next, the carrier film 301 is peeled off. At this time, the peeling may be that the metal films 302 and 303 are separated. Blades may be used for the separation, but not limited thereto, and all known methods can be used. However, the present invention is not limited to this. The carrier film 301 may be peeled off before the carrier film 301 is separated from the carrier film 301, 1 connecting member 210 may be formed. That is, the order is not necessarily limited to the order described.

Referring to FIG. 26C, the remaining metal film 303 is removed by a known etching method or the like, and a through hole 210H is formed in the first connecting member 210. Next, as shown in FIG. The through hole 210H can be formed by a mechanical drill and / or a laser drill. However, the present invention is not limited to this, and may be performed by a sandblast method using abrasive particles, a dry etching method using plasma, or the like. In the case of using a mechanical drill and / or a laser drill, a desmear treatment such as a permanganate method is performed to remove the resin smear in the hole 210H. Next, an adhesive film 305 is attached to one side of the first linking member 210. The adhesive film 305 can be used as long as it can fix the first connecting member 210, and a known tape or the like can be used as a non-limiting example. Examples of known tapes include a heat-curable adhesive tape which is weakened in adhesion by heat treatment, and an ultraviolet-curable adhesive tape whose adhesion is weakened by ultraviolet irradiation. Next, the semiconductor chip 220 is disposed in the through hole 210H of the first connection member 210. [ For example, the semiconductor chip 220 is disposed on the adhesive film 305 in the through hole 210H by a method of attaching the semiconductor chip 220 thereto. The semiconductor chip 220 is disposed in face-down fashion so that the connection pad 222 is attached to the adhesive film 305.

Referring to FIG. 26D, the semiconductor chip 220 is sealed using the sealing material 230. Next, as shown in FIG. The sealing member 230 at least seals the inactive surface of the first connecting member 210 and the semiconductor chip 220 and fills the space in the through hole 210H. The sealing material 230 may be formed by a known method. For example, the sealing material 230 can be formed by laminating and then curing the precursor. Alternatively, the sealing material 230 may be coated on the adhesive film 305 so that the semiconductor chip 220 can be sealed, followed by curing. The semiconductor chip 220 is fixed by the curing. As the lamination method, for example, a hot pressing method in which the resin is pressed at a high temperature for a certain period of time and then reduced in pressure to room temperature, and then cooled in a cold press to separate the working tool can be used. As the application method, for example, a screen printing method in which ink is applied by squeezing, a spray printing method in which ink is fogged and applied, and the like can be used. Next, the adhesive film 305 is peeled off. The peeling method is not particularly limited, and can be carried out by a known method. For example, when a heat-curable adhesive tape whose adhesion is weakened by heat treatment with the adhesive film 305, an ultraviolet-curable adhesive tape whose adhesion is weakened by ultraviolet irradiation is used, the adhesive film 305 is heat- Or may be performed after weakening the adhesive force by irradiating the adhesive film 305 with ultraviolet light. Next, the second connection member 240 is formed on the active surface of the semiconductor chip 220 and the first connection member 210 from which the adhesive film 305 is removed. The second connection member 240 is formed by successively forming the insulating layers 241a and 141b and after forming the insulating layers 241a and 141b, the re-wiring layers 242a and 142b and the vias 243a and 243b, And 143b. If necessary, a passivation layer 250 is formed on the second connection member 240. The passivation layer 250 may be formed by a method of laminating and curing the precursor of the passivation layer 250, a method of applying the material for forming the passivation layer 250, and then curing. An opening (not shown) may be formed in the passivation layer 250 to expose at least a portion of the redistribution layer 242b of the second connection member 240. An under bump metal layer 260 ) May be formed. If necessary, a connection terminal 270 is formed on the under bump metal layer 260. The method of forming the connection terminal 270 is not particularly limited and may be formed by a known method well known in the art depending on its structure and form. The connection terminal 270 may be fixed by reflow and a part of the connection terminal 270 may be buried in the passivation layer 250 and the remaining part may be exposed to the outside in order to enhance the fixing force, .

A plurality of fan-out semiconductor packages 200A are manufactured after a carrier film 301 of a large capacity size is prepared so as to facilitate mass production. Then, a plurality of fan-out semiconductor packages 200A are manufactured through a sawing process, Or may be singulated with the package 200A. In this case, there is an advantage that productivity is excellent.

Fig. 27 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig. 23;

28 is a schematic VI-VI 'cutting plan view of the fan-out semiconductor package of FIG. 27;

In the fan-out semiconductor package 200B according to the modification, the metal layer 214 is disposed on the wall surface of the through hole 210H of the first connection member 210. As shown in FIG. The metal layer 214 effectively dissipates heat generated from the semiconductor chip 220. In addition, the metal layer 214 may also function as an electromagnetic wave shielding preventer. The metal layer 214 may be connected to the ground patterns of the other rewiring layers 212a and 112b of the first connection member 210 to be used as a ground. The metal layer 214 may be disposed over the entire wall surface or may be patterned and arranged in a specific shape. The metal layer 214 may comprise a conductive material, i. E., A metal material, as described above.

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 200A according to another example.

29 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of FIG.

30 is a schematic sectional view VII-VII 'of the fan-out semiconductor package of FIG. 29;

Referring to the drawings, in the fan-out semiconductor package 200C according to the modification, a separate first passive component 224 is disposed in the through hole 210H. In addition, a separate second passive component 226 is disposed on the surface of the passivation layer 250. The first passive component 224 may be, but is not limited to, a high capacitance capacitor, for example, an MLCC. The second passive component 226 may be a low-capacitance capacitor, for example, a Si-based capacitor, but is not limited thereto. They may be connected to the same power line and electrically connected to the semiconductor chip 220 to improve power supply efficiency.

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 200A according to another example.

Fig. 31 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig. 23;

Referring to the drawings, in the fan-out semiconductor package 200D according to the modification, the third material of the first connection member 210 is connected to the sealing material 230 via the via 283 passing through the sealing material 230, A re-wiring layer 282 electrically connected to the wiring layer 212c is disposed. A passivation layer 280 having an opening (not shown) for exposing a part of the rewiring layer 282 is disposed on the sealing material 230. On the opening (not shown), separate surface-mounted components 281 and 286 are disposed and electrically connected to the re-wiring layer 282. The surface mount components 281 and 286 may be directly connected to the rewiring layer 282 or may be connected through soldering (not shown) or the like to the underbump metal layer 284 and the connection terminal 285 . The surface mount components 281 and 286 may be various kinds of passive components or may be various kinds of integrated circuits.

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 200A according to another example.

32 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.

Referring to the drawings, a memory chip package 287 is stacked on a sealing material 230 in a fan-out semiconductor package 200E according to a modification. The memory chip package 287 includes an under bump metal layer 284 and an under bump metal layer 284 formed in the opening 231 exposing a portion of the third rewiring layer 212c of the first connecting member 210 of the sealing material 230 And is electrically connected to the third rewiring layer 212c of the first connection member 210 through the connection terminal 285 formed on the first connection member 284. Memory chip package 287 may be one that includes memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory,

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 200A according to another example.

33 is a cross-sectional view schematically showing a modification of the fan-out semiconductor package of Fig.

In the fan-out semiconductor package 200F according to the modification, the first rewiring layer 212a is recessed into the first insulation layer, so that the lower surface of the first insulation layer 211a, The lower surface of the wiring layer 212a has a step. As a result, it is possible to prevent the material for forming the sealing material 230 from being contaminated by contaminating the first rewiring layer 212a when the sealing material 230 is formed. The lower surface of the first rewiring layer 212a of the first connection member 210 is connected to the lower surface of the semiconductor chip 220. The first rewiring layer 212a is recessed into the first insulation layer 211a, And may be located on the upper side of the lower surface of the connection pad 222. The distance between the rewiring layer 242a of the second connecting member 240 and the first rewiring layer 212a of the first connecting member 210 is larger than the distance between the rewiring layer 242a of the second connecting member 240, May be greater than the distance between the connection pads (222) of the first electrode (220).

Other configurations and manufacturing methods are substantially the same as those described in the fan-out semiconductor package 200A according to another example.

34 is a cross-sectional view schematically showing an example of a fan-out semiconductor package in which the insulation distance of the second connection member is non-uniform.

Referring to the drawings, a fan-out semiconductor package having an uneven insulation distance of the second connection member is formed in the same manner as the first connection member 210 ', the semiconductor chip 220', the sealing member 230 ' 240 ', a passivation layer 250', and a connection terminal 270 '. The first connection member 210 'has a through hole 210H' and includes an insulating layer 211 ', re-wiring layers 212a' and 212b 'formed on both surfaces of the insulating layer 211' RTI ID = 0.0 > 211 '. ≪ / RTI > The semiconductor chip 220 'includes a body 221', a connection pad 222 ', a passivation film 223', and the like. The second connection member 240 'includes insulating layers 241a' and 241b ', re-wiring layers 242a' and 242b ', and vias 243a' and 243b '. The rewiring layer 212a 'formed on the lower surface of the first connecting member 210' is embedded in the insulating material of the second connecting member 240 ', so that the rewiring layer 212a' This may lead to uneven insulation distances. In addition, since there is no separate under bump metal layer, board level reliability can be degraded.

The terms "an example" and "modifications" used in the present disclosure are not intended to be construed to limit the same embodiments, but are provided to emphasize and describe different features. However, it should be understood that the above-described examples and modifications do not exclude that they are implemented in combination with the features of other examples or modifications. For example, although the description in the specific example is not described in another example, it can be understood as an explanation related to another example, unless otherwise described or contradicted by the other example.

In the present disclosure, the meaning of being connected is not a direct connection but a concept including an indirect connection. In addition, the term "electrically connected" means a concept including both a physical connection and a non-connection. Also, the first, second, etc. expressions are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the right, the first component may be referred to as a second component, and similarly, the second component may be referred to as a first component.

In the present disclosure, upper, lower, upper, lower, upper, lower, and the like are determined based on the attached drawings. For example, the first connecting member is located above the re-wiring layer. However, the claims are not limited thereto. In addition, the vertical direction means the above-mentioned upper and lower direction, and the horizontal direction means the direction perpendicular thereto. In this case, the vertical cross-section means a case of cutting into a plane in the vertical direction, and the cross-sectional view shown in the figure is an example. In addition, the horizontal cross-section means a case where the horizontal cross-section is cut into a plane in the horizontal direction, for example, the plan view shown in the drawing.

The terms used in this disclosure are used only to illustrate an example and are not intended to limit the present disclosure. Wherein the singular expressions include plural expressions unless the context clearly dictates otherwise.

1000: electronic device 1010: main board
1020: Chip related parts 1030: Network related parts
1040: Other parts 1050: Camera
1060: antenna 1070: display
1080: Battery 1090: Signal line
1100: Smartphone 1101: Smartphone body
1110: Smartphone mainboard 1111: mainboard insulation layer
1112: main board wiring 1120: parts
1130: Smartphone camera 2200: Fan-in semiconductor package
2220: semiconductor chip 2221: body
2222: connection pad 2223: passivation film
2240: connecting member 2241: insulating layer
2242: re-wiring layer 2243: via
2250: passivation layer 2260: under bump metal layer
2270: solder ball 2280: underfill resin
2290: molding material 2500: main board
2301: Interposer substrate 2302: Interposer substrate
2100: Fan-out semiconductor package 2120: Semiconductor chip
2121: Body 2122: Connection pad
2140: connecting member 2141: insulating layer
2142: re-wiring layer 2143: via
2150: passivation layer 2160: under bump metal layer
2170: solder ball 100: semiconductor package
100A to 100H, 200A to 200G: Fan-out semiconductor package
110, 210: a first connecting member
111a, 111b, 211: insulating layer
112a, 112b, 112c, 212a, and 212b:
113a, 113b, 213: vias
114, 214: metal layer
130 and 230:
140, 240: a second connecting member
141a, 141b, 241a, and 241b:
142a, 142b, 242a, 242b, 182, 282:
143a, 143b, 243a, 243b, 183, 283: vias
150, 180, 250, 280: passivation layer
160, 260, 184, 284: under bump metal layer
170, 270, 185, 285: connection terminal
181, 281, 186, 286: Surface mount parts
187, 287: Memory chip package
124, 126, 224, 226: passive components

Claims (24)

A first connecting member having a through hole;
A semiconductor chip disposed in the through hole of the first connection member and having an active surface on which the connection pad is disposed and an inactive surface disposed on the opposite side of the active surface;
A sealing member for sealing at least a part of the inactive surfaces of the first connecting member and the semiconductor chip; And
A second connection member disposed on the active surface of the first connection member and the semiconductor chip and including a re-wiring layer electrically connected to the connection pad; / RTI >
Wherein the first connecting member comprises a first insulating layer, a first rewiring layer in contact with the second connecting member and embedded in the first insulating layer, and a second rewiring layer on the opposite side of the first rewiring layer, And a second rewiring layer disposed on the first rewiring layer,
Wherein the first and second rewiring layers are electrically connected to the connection pad,
A fan-out semiconductor package.
The method according to claim 1,
Wherein the first and second rewiring layers are electrically connected through vias through the first insulation layer,
A fan-out semiconductor package.
The method according to claim 1,
The first connecting member further includes a second insulating layer disposed on the first insulating layer and covering the second rewiring layer and a third rewiring layer disposed on the second insulating layer,
Wherein the third re-wiring layer is electrically connected to the connection pad,
A fan-out semiconductor package.
The method of claim 3,
And the second re-distribution layer is electrically connected to the first and third re-distribution layers through first and second via holes respectively passing through the first and second insulation layers,
A fan-out semiconductor package.
The method of claim 3,
The first connecting member further comprises a third insulating layer disposed on the second insulating layer and covering the third rewiring layer and a fourth rewiring layer disposed on the third insulating layer,
Wherein the fourth redistribution layer is electrically connected to the connection pad,
A fan-out semiconductor package.
The method according to claim 1,
The distance between the re-wiring layer of the second connection member and the first re-distribution layer is larger than the distance between the re-distribution layer of the second connection member and the connection pad,
A fan-out semiconductor package.
The method according to claim 1,
A passivation layer disposed on the second connection member and having an opening exposing a part of the rewiring layer of the second connection member;
An under bump metal layer disposed on the opening and connected to the exposed re-wiring layer of the second connection member; And
A connection terminal disposed on the under bump metal layer and electrically connected to the connection pad; ≪ / RTI >
A fan-out semiconductor package.
The method of claim 3,
Wherein the sealing material has an opening for exposing a part of the third rewiring layer,
A fan-out semiconductor package.
The method of claim 3,
A re-wiring layer disposed on the sealing material and electrically connected to the third re-wiring layer; And
A passivation layer disposed on the seal material and having an opening exposing a part of the re-wiring layer disposed on the seal material; ≪ / RTI >
A fan-out semiconductor package.
The method of claim 3,
Wherein each of the first to third rewiring layers includes a ground pattern,
A fan-out semiconductor package.
The method according to claim 1,
Wherein the first re-wiring layer is thicker than the re-wiring layer of the second connection member,
A fan-out semiconductor package.
The method according to claim 1,
And the lower surface of the first re-distribution layer is located above the lower surface of the connection pad,
A fan-out semiconductor package.
The method according to claim 1,
And the second re-wiring layer is located between the active surface and the inactive surface of the semiconductor chip,
A fan-out semiconductor package.
The method according to claim 1,
Wherein the sealing material comprises a core material, an inorganic filler, and an insulating resin,
A fan-out semiconductor package.
Preparing a carrier film;
Forming a first connecting member on the carrier film;
Removing the carrier film;
Forming a through hole through the first connection member;
Disposing a semiconductor chip having an active surface in which the connection pad is disposed in the through hole and an inactive surface disposed on the opposite side of the active surface;
Sealing at least a part of the inactive surface of the first connecting member and the semiconductor chip with a sealing material; And
Forming a second connection member including a rewiring layer electrically connected to the connection pad on the active surface of the first connection member and the semiconductor chip; / RTI >
The step of forming the first connecting member may include the steps of forming a first rewiring layer on the carrier film, forming a first insulating layer on the carrier film to embed the first rewiring layer, And forming a second rewiring layer on the opposite side of one insulating layer on the side where the first rewiring layer is buried,
Wherein the first and second rewiring layers are electrically connected to the connection pad,
A method of manufacturing a fan-out semiconductor package.
16. The method of claim 15,
The step of forming the first connecting member may include the steps of forming a second insulating layer covering the second rewiring layer on the first insulating layer and forming a third rewiring layer on the second insulating layer , ≪ / RTI >
Wherein the third re-wiring layer is electrically connected to the connection pad,
A method of manufacturing a fan-out semiconductor package.
17. The method of claim 16,
Exposing a part of the third rewiring layer by opening a part of the sealing material; ≪ / RTI >
A method of manufacturing a fan-out semiconductor package.
17. The method of claim 16,
Forming a re-wiring layer electrically connected to the third re-wiring layer on the sealing material;
Forming a passivation layer covering the rewiring layer formed on the sealing material on the sealing material; And
Opening a part of the passivation layer to expose a part of the re-wiring layer formed on the sealing material; ≪ / RTI >
A method of manufacturing a fan-out semiconductor package.
A semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface disposed on the opposite side of the active surface;
At least one connection unit disposed around the semiconductor chip; And
A connecting member disposed on the connection unit and the semiconductor chip; / RTI >
The connecting unit includes a first insulating layer, a first rewiring layer in contact with the connecting member and embedded in the first insulating layer, and a second rewiring layer disposed on the opposite side of the first insulating layer, 2 redistribution layer,
Wherein the connecting member includes an insulating layer and a redistribution layer disposed on the insulating layer,
Wherein the first and second rewiring layers of the connection unit and the rewiring layer of the connection member are electrically connected to the connection pads of the semiconductor chip,
A fan-out semiconductor package.
20. The method of claim 19,
Wherein the connecting unit further comprises a second insulating layer disposed on the first insulating layer and covering the second rewiring layer and a third rewiring layer disposed on the second insulating layer,
And the third re-wiring layer is electrically connected to the connection pad of the semiconductor chip,
A fan-out semiconductor package.
20. The method of claim 19,
The connection unit includes a plurality of users,
Fan-out van conductor package.
21. The method of claim 20,
A sealing member for sealing at least a part of the inactive surface of the connection unit and the semiconductor chip; ≪ / RTI >
A fan-out semiconductor package.
23. The method of claim 22,
Wherein the sealing material has an opening for exposing a part of the third rewiring layer,
A fan-out semiconductor package.
23. The method of claim 22,
Wherein the sealing member seals all the side surfaces of the connecting unit,
A fan-out semiconductor package.

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