KR20190038013A - Fan-out semiconductor package - Google Patents

Abstract

The present disclosure relates to a fan-out semiconductor package comprising: a semiconductor chip having an active surface on which a connection pad is arranged and an inactive surface on an opposite side of the active surface; a sealing material sealing at least a part of the semiconductor chip; and a connecting member arranged on the active surface of the semiconductor chip and including a re-wiring layer electrically connected to the connection pad. The re-wiring layer includes pad patterns, and at least one of the pad patterns does not have a constant distance from the center to the edge. One of the various objectives of the present disclosure is to resolve a failure in delamination such as interlayer delamination risk generated by the pad patterns.

Description

[0001] FAN-OUT SEMICONDUCTOR PACKAGE [0002]

The present disclosure relates to a semiconductor package, for example, a fan-out semiconductor package capable of extending a connection terminal to an area outside the area where the semiconductor chip is disposed.

Observing the wiring design of the semiconductor package, it is possible to confirm the ground pattern arranged for the purpose of heat radiation, signal return, etc. in addition to the signal pattern which is a micro circuit for signal transmission purpose. In the case of the grounded region, since the copper foil remaining ratio is very high, the risk of delamination is high. In order to solve this problem, it is necessary to increase the adhesion between the insulating layer and the copper foil by reflecting the circular or straight shape of the Degas design in the design, and to facilitate the discharge of the digestion component discharged from the lower insulating layer.

On the other hand, in addition to the ground pattern, since the copper foil remaining ratio is also high in the case of the pad pattern, the risk of delamination by the pad pattern can not be ignored.

One of the objects of the present disclosure is to solve delamination defects such as interlaminar spreading risks caused by pad patterns.

One of the various solutions proposed through this disclosure is to introduce a digg design into at least one pad pattern of the rewiring layer of the connecting member.

For example, a fan-out semiconductor package according to one example proposed in the present disclosure may include a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface disposed on the opposite side of the active surface, And a re-wiring layer disposed on the active surface of the semiconductor chip and electrically connected to the connection pad, wherein the re-wiring layer includes a pad pattern, at least one of the pad patterns being a center The distance from the edge to the edge may not be constant.

As one of the effects of the present disclosure, it is possible to solve delamination defects such as the interlayer spreading risk caused by the pad pattern.

1 is a block diagram schematically showing an example of an electronic equipment system.
2 is a perspective view schematically showing an example of an electronic apparatus.
3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.
4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.
5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.
6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.
7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.
8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.
9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.
10 is a schematic sectional elevational-cut view of the fan-out semiconductor package of FIG.
FIG. 11 is a perspective view schematically showing an example of various pad patterns included in the connecting member of the fan-out semiconductor package of FIG. 9; FIG.
12 is a plan view schematically illustrating various examples of the digg design that can be applied to at least one of the various pad patterns of FIG.
13 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.
14 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape and size of elements in the drawings may be exaggerated or reduced for clarity.

Electronics

1 is a block diagram schematically showing an example of an electronic equipment system.

Referring to the drawings, an electronic device 1000 accommodates a main board 1010. The main board 1010 is physically and / or electrically connected to the chip-related components 1020, the network-related components 1030, and other components 1040. They are also combined with other components to be described later to form various signal lines 1090.

Chip related components 1020 include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.; An application processor chip such as a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, a cryptographic processor, a microprocessor, Analog-to-digital converters, and logic chips such as application-specific integrated circuits (ICs), and the like, but it is needless to say that other types of chip-related components may be included. It goes without saying that these components 1020 can be combined with each other.

IEEE 802.11 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM , And any other wireless and wired protocols designated as GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and later, as well as any other wireless or wired Any of the standards or protocols may be included. It goes without saying that the network-related component 1030 may be combined with the chip-related component 1020, as well.

Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-firing ceramics (LTCC), EMI (Electro Magnetic Interference) filters, and MLCC (Multi-Layer Ceramic Condenser) But is not limited to, passive components used for various other purposes, and the like. It is also understood that other components 1040 may be combined with each other with the chip-related component 1020 and / or the network-related component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the mainboard 1010. Other components include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (Not shown), a CD (compact disk) (not shown), and a DVD (not shown), an accelerometer (not shown), a gyroscope a digital versatile disk (not shown), and the like. However, the present invention is not limited thereto, and other components used for various purposes may be included depending on the type of the electronic device 1000.

The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, it is needless to say that the present invention is not limited thereto and may be any other electronic device that processes data.

2 is a perspective view schematically showing an example of an electronic apparatus.

Referring to the drawings, a semiconductor package is applied to various electronic apparatuses as described above for various purposes. For example, a motherboard 1110 is accommodated in the body 1101 of the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components, such as the camera 1130, that are physically and / or electrically connected to the main board 1010 or not may be contained within the body 1101. Some of the components 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor, but is not limited thereto. It is needless to say that the electronic device is not necessarily limited to the smartphone 1100, but may be another electronic device as described above.

Semiconductor package

In general, a semiconductor chip has many microelectronic circuits integrated therein, but itself can not serve as a finished product of a semiconductor, and there is a possibility of being damaged by external physical or chemical impact. Therefore, the semiconductor chip itself is not used as it is, and the semiconductor chip is packaged and used as electronic devices in a package state.

The reason for the necessity of semiconductor packaging is that there is a difference in circuit width between the semiconductor chip and the main board of the electronic device from the viewpoint of electrical connection. Specifically, in the case of a semiconductor chip, the size of the connection pad and the spacing between the connection pads are very small. On the other hand, in the case of the main board used in electronic equipment, the size of the component mounting pad and the interval between the component mounting pads are much larger than the scale of the semiconductor chip . Therefore, there is a need for a packaging technique which makes it difficult to directly mount a semiconductor chip on such a main board and can buffer the difference in circuit width between the semiconductor chips.

The semiconductor package manufactured by such a packaging technique can be classified into a fan-in semiconductor package and a fan-out semiconductor package depending on the structure and use.

Hereinafter, the fan-in semiconductor package and the fan-out semiconductor package will be described in more detail with reference to the drawings.

(Fan-in semiconductor package)

3 is a cross-sectional view schematically showing the front and rear of the package of the fan-in semiconductor package.

4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.

The semiconductor chip 2220 includes a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like; A connection pad 2222 including a conductive material and a passivation film 2223 such as an oxide film or a nitride film formed on one surface of the body 2221 and covering at least a part of the connection pad 2222. [ May be an integrated circuit (IC) in a bare state. At this time, since the connection pad 2222 is very small, the integrated circuit (IC) is difficult to be mounted on a medium-level printed circuit board (PCB) as well as a main board of an electronic apparatus.

A connection member 2240 is formed on the semiconductor chip 2220 in accordance with the size of the semiconductor chip 2220 in order to rewire the connection pad 2222. [ The connecting member 2240 is formed by forming an insulating layer 2241 with an insulating material such as a photosensitive insulating resin (PID) on the semiconductor chip 2220 and forming a via hole 2243h for opening the connecting pad 2222, The wiring pattern 2242 and the via 2243 can be formed. Thereafter, a passivation layer 2250 for protecting the connecting member 2240 is formed, and an under-bump metal layer 2260 or the like is formed after the opening 2251 is formed. That is, through a series of processes, a fan-in semiconductor package 2200 including, for example, a semiconductor chip 2220, a connecting member 2240, a passivation layer 2250, and an under bump metal layer 2260, do.

As described above, the fan-in semiconductor package is a package in which all the connection pads of the semiconductor chip, for example, I / O (Input / Output) terminals are disposed inside the element, and the fan-in semiconductor package has good electrical characteristics and can be produced at low cost have. Accordingly, many devices incorporated in a smart phone are manufactured in the form of a fan-in semiconductor package. Specifically, development is being made in order to implement a small-sized and fast signal transmission.

However, in the fan-in semiconductor package, all of the I / O terminals must be disposed inside the semiconductor chip, so that there are many space limitations. Therefore, such a structure is difficult to apply to a semiconductor chip having a large number of I / O terminals or a semiconductor chip having a small size. In addition, due to this vulnerability, the fan-in semiconductor package can not be directly mounted on the main board of the electronic device. This is because even if the size and spacing of the I / O terminals of the semiconductor chip are enlarged by the rewiring process, they do not have a size and a gap enough to be directly mounted on the electronic device main board.

5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic apparatus.

6 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic apparatus.

Referring to the drawing, the fan-in semiconductor package 2200 is again rewired with the connection pads 2222 of the semiconductor chip 2220, that is, the I / O terminals through the interposer substrate 2301, May be mounted on the main board 2500 of the electronic device with the fan-in semiconductor package 2200 mounted on the interposer substrate 2301. At this time, the solder ball 2270 and the like can be fixed with the underfill resin 2280 and the outside can be covered with the molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the interposer substrate 2302 may be embedded in the connection pads 2220 of the semiconductor chip 2220, The I / O terminals 2222, i.e., the I / O terminals, may be re-routed again and finally mounted on the main board 2500 of the electronic device.

Since the fan-in semiconductor package is difficult to be directly mounted on the main board of the electronic apparatus, it is mounted on a separate interposer substrate and then re-packaged to be mounted on the electronic device main board, And is mounted on an electronic device main board while being embedded in a substrate.

(Fan-out semiconductor package)

7 is a cross-sectional view showing a schematic view of a fan-out semiconductor package.

In the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 is protected by the sealing material 2130, and the connection pad 2122 of the semiconductor chip 2120 is connected to the connection member 2120. [ The semiconductor chip 2120 is rewound to the outside of the semiconductor chip 2120. At this time, a passivation layer 2202 may be further formed on the connection member 2140, and an under bump metal layer 2160 may be further formed on the opening of the passivation layer 2202. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation film (not shown), and the like. The connecting member 2140 includes an insulating layer 2141, a re-wiring layer 2142 formed on the insulating layer 2241, and a via 2143 for electrically connecting the connecting pad 2122 and the re-wiring layer 2142 .

As described above, the fan-out semiconductor package is formed by rewiring the I / O terminals to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all of the I / O terminals of the semiconductor chip must be disposed inside the semiconductor chip. If the element size is reduced, the ball size and pitch must be reduced. On the other hand, in the fan-out semiconductor package, the I / O terminals are rewired to the outside of the semiconductor chip through the connecting member formed on the semiconductor chip so that the size of the semiconductor chip is reduced. And can be mounted on a main board of an electronic device without a separate interposer substrate as will be described later.

8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on a main board of an electronic apparatus.

Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on a main board 2500 of an electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes a connection member 2120 that can rewire the connection pad 2122 to the fan-out area beyond the size of the semiconductor chip 2120 on the semiconductor chip 2120, The standardized ball layout can be used as it is, and as a result, it can be mounted on the main board 2500 of the electronic apparatus without a separate interposer substrate or the like.

Since the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, the thickness of the fan-out semiconductor package can be reduced compared to a fan-in semiconductor package using the interposer substrate. Do. In addition, it has excellent thermal characteristics and electrical characteristics and is particularly suitable for mobile products. In addition, it can be implemented more compactly than a general POP (Package on Package) type using a printed circuit board (PCB), and it is possible to solve a problem caused by a bending phenomenon.

On the other hand, the fan-out semiconductor package means a package technology for mounting the semiconductor chip on a main board or the like of an electronic device and protecting the semiconductor chip from an external impact, and the scale, (PCB) such as an interposer substrate having a built-in fan-in semiconductor package.

Hereinafter, a fan-out semiconductor package capable of preventing a problem of pattern breakage of a signal pattern passing over a dig-hole of a ground pattern will be described with reference to the drawings.

9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.

10 is a schematic sectional elevational-cut view of the fan-out semiconductor package of FIG.

FIG. 11 is a perspective view schematically showing an example of various pad patterns included in the connecting member of the fan-out semiconductor package of FIG. 9; FIG.

12 is a plan view schematically illustrating various examples of the digg design that can be applied to at least one of the various pad patterns of FIG.

Referring to FIG. 1, a fan-out semiconductor package 100A according to an exemplary embodiment includes a core member 110 having a through hole 110H, a through hole 110H of the core member 110, A sealing member 130 for sealing at least a part of the semiconductor chip 120, the core member 110, and the semiconductor chip 120, the core member 110 having an active surface and an inactive surface disposed on the opposite side of the active surface, And a passivation layer 150 disposed on the connecting member 140. The passivation layer 150 includes an opening 151 formed on the passivation layer 150. The passivation layer 150 is formed on the active surface of the semiconductor chip 120, A metal layer 160 and an electrical connection structure 170 disposed on the passivation layer 150 and connected to the underbump metal layer 160.

The connecting member 140 includes a first insulating layer 141a disposed on the active surface of the core member 110 and the semiconductor chip 120, a first rewiring layer 142a disposed on the first insulating layer 141a, A first via 143a connecting the first insulating layer 141a and the connection pad 122 of the semiconductor chip 120, a second insulating layer 141b disposed on the first insulating layer 141a, A second via 143b connected to the first and second rewiring layers 142a and 142b through the second insulating layer 141b, a second via 143b disposed on the second insulating layer 141b, A third insulating layer 141c disposed on the second insulating layer 141b, a third redistribution layer 142c disposed on the third insulating layer 141c, and a third insulating layer 141c penetrating the third insulating layer 141c And a third via 143c connecting the second and third rewiring layers 142b and 142c.

The first rewiring layer 142a includes a wiring pattern 142aw such as a signal line and a via pad 142ap for the second via 143b and the like. The second redistribution layer 142b includes a wiring pattern 142bw such as a signal line and a via pad 142bp for the third via 143c and the like. The third redistribution layer 142c includes a wiring pattern 142cw such as a signal line and an electrical connection structure pad 142ap for the electrical connection structure 170 and the like. At this time, at least one of the via pads 142ap, 142bp, and 142cp and the electrical connection structure pad 142ap may not be a simple circular arc as shown in Figs. 12 (a) and 12 (b). That is, at least one of the via pads 142ap, 142bp, 142cp and the electrical connection structure pads 142ap may not have a uniform distance from the center to the rim. Specifically, at least one of the via pads 142ap, 142bp, and 142cp and the electrical connection structure pad 142ap may be formed with a plurality of grooves g facing the center thereof. This groove portion g can be used as a digging path. In this case, the degassing can proceed easily, and as a result, the reliability can be secured by reducing the stress. For example, the risk of delamination can be improved.

Hereinafter, each configuration included in the fan-out semiconductor package 100A according to the example will be described in more detail.

The core member 110 can further improve the rigidity of the package 100A according to a specific material and can play a role of ensuring uniformity of the thickness of the sealing material 130. [ In the case of forming the through wiring or the like in the core member 110, the fan-out semiconductor package 100A may be used as a package of a POP (package on package) type. The core member 110 has a through hole 110H. In the through hole 110H, the semiconductor chip 120 is disposed to be spaced apart from the core member 110 by a predetermined distance. The side surface of the semiconductor chip 120 may be surrounded by the core member 110. However, it is to be understood that the present invention is not limited thereto and various modifications may be made in other forms, and other functions may be performed according to the forms. The core member 110 may be omitted if necessary, but the core member 110 may be more advantageous in securing the board level reliability as intended in the present disclosure.

The core member 110 includes an insulating layer 111. As the material of the insulating layer 111, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler, Such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), etc., which are impregnated into core materials such as glass fiber (glass fiber, glass cloth, Can be used. The core member 110 may serve as a supporting member.

The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. The integrated circuit may then be a processor such as, for example, a central processor (e.g., CPU), a graphics processor (e.g., a GPU), a field programmable gate array (FPGA), a digital signal processor, (DRAM) such as an analog-to-digital converter, an application-specific IC (IC), or the like, a non-volatile memory - volatile memory (e.g., ROM), flash memory, and the like. It goes without saying that they may be arranged in combination with each other.

The semiconductor chip 120 may be formed on the basis of an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as a base material of the body 121. The body 121 may have various circuits. The connection pad 122 electrically connects the semiconductor chip 120 to other components. As the forming material, a conductive material such as aluminum (Al) may be used without any particular limitation. A passivation film 123 exposing the connection pad 122 may be formed on the body 121. The passivation film 123 may be an oxide film or a nitride film or may be a double layer of an oxide film and a nitride film. The lower surface of the connection pad 122 may have a step with the lower surface of the sealing material 130 through the passivation film 123 to some extent prevent the sealing material 130 from bleeding to the lower surface of the connection pad 122. An insulating film (not shown) or the like may be further disposed at a necessary position. The semiconductor chip 120 may be a bare die but may be further formed with a re-wiring layer (not shown) on the active surface of the semiconductor chip 120, May be connected to the connection pad 122.

The sealing member 130 can protect the core member 110, the semiconductor chip 120, and the like. The sealing shape is not particularly limited and may be any shape that covers at least a part of the core member 110, the semiconductor chip 120, and the like. For example, the sealing material 130 may cover the inactive surface of the core member 110 and the semiconductor chip 120, and may fill the space between the wall surface of the through hole 110H and the side surface of the semiconductor chip 120 have. The sealing material 130 may fill at least a part of the space between the passivation film 123 of the semiconductor chip 120 and the connecting member 140. [ By filling the through hole 110H with the sealing material 130, it is possible to reduce buckling while performing an adhesive function according to a specific material.

The material of the sealing material 130 is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a mixture of these resins with an inorganic filler, or a glass fiber Such as a prepreg, an Ajinomoto Build-up Film (ABF), a bismaleimide triazine (BT), or the like, may be used. If desired, a photosensitive insulator (PID) resin may be used.

The connection member 140 can rewire the connection pad 122 of the semiconductor chip 120. [ The connection pads 122 of dozens of hundreds of semiconductor chips 120 having various functions can be rewired through the connection member 140 and the electrical connection structure 170 can be physically and / And can be electrically connected. The connecting member 140 includes a first insulating layer 141a disposed on the active surface of the core member 110 and the semiconductor chip 120, a first rewiring layer 142a disposed on the first insulating layer 141a, A first via 143a connecting the first insulating layer 141a and the connection pad 122 of the semiconductor chip 120, a second insulating layer 141b disposed on the first insulating layer 141a, A second rewiring layer 142b disposed on the second insulating layer 141b and a second via 143b passing through the second insulating layer 141b and connecting the first and second rewiring layers 142a, 142b, A third insulating layer 141c disposed on the second insulating layer 141b, a third rewiring layer 142c disposed on the third insulating layer 141c, and a third insulating layer 141c And a third via 143c connecting the second and third rewiring layers 142b and 142c. The first to third rewiring layers 142a, 142b and 142c are electrically connected to the connection pads 122 of the semiconductor chip 120. [

As the material of the insulating layers 141a, 141b, and 141c, an insulating material may be used. In addition to the above-described insulating material, a photosensitive insulating material such as a PID resin may be used as the insulating material. That is, the insulating layers 141a, 141b, and 141c may be photosensitive insulating layers, respectively. When the insulating layers 141a, 141b and 141c are photosensitive, the insulating layers 141a, 141b and 141c can be made thinner and the pitches of the vias 143a, 143b and 143c can be more easily achieved can do. Each of the insulating layers 141a, 141b, and 141c may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layers 141a, 141b, and 141c are multilayered, these materials may be identical to each other, and may be different from each other as needed. When the insulating layers 141a, 141b, and 141c are multi-layered, they may be integrated according to the process, and the boundaries themselves may be unclear. It is needless to say that a larger number of insulating layers than those shown in the drawings can be formed.

The re-distribution layers 142a, 142b and 142c can substantially rewire the connection pads 122. The re-distribution layers 142a, 142b and 142c may be formed of copper (Cu), aluminum (Al), silver (Ag) ), Gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The re-distribution layer 142 may perform various functions according to the design of the layer. For example, it may include a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern, Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. The redistribution layers 142a, 142b and 142c may include wiring patterns such as signal lines 142aw, 142bw and 143cw and may also include pad patterns such as via pads 142ap and 142bp and electrical connection structure pads 142cp .

The vias 143a, 143b and 143c electrically connect the rewiring layers 142a, 142b and 142c and the connection pads 122 formed in different layers, and as a result, form an electrical path in the package 100A. As the materials for forming the vias 143a, 143b and 143c, copper, aluminum, silver, tin, gold, nickel, lead, titanium, (Ti), or an alloy thereof may be used. The vias 143a, 143b, and 143c may each be completely filled with a conductive material, or a conductive material may be formed along the wall of the via. In addition, any shape known in the art, such as a tapered shape, a cylindrical shape, etc., can be applied.

The passivation layer 150 may protect the connecting member 140 from external physical chemical damage or the like. The passivation layer 150 may have an opening 151 that exposes at least a portion of the electrical connection structure pad 142cp in the redistribution layer 142c of the connection member 140. [ The openings 151 may be formed in the passivation layer 150 in several tens to several thousands. The material of the passivation layer 150 is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a mixture of these resins with an inorganic filler, or a glass fiber Such as a prepreg, an Ajinomoto Build-up Film (ABF), a bismaleimide triazine (BT), or the like, may be used. Alternatively, a solder resist may be used.

The under bump metal layer 160 improves the connection reliability of the electrical connection structure 170, thereby improving the board level reliability of the package 100A. The under bump metal layer 160 is connected to the electrical connection structure pad 142cp of the re-wiring layer 142c of the connection member 140 exposed through the opening 151 of the passivation layer 150. [ The under bump metal layer 160 may be formed on the opening 151 of the passivation layer 150 using a known conductive material, that is, a metal, by a known metallization method, but the present invention is not limited thereto.

The electrical connection structure 170 physically and / or electrically connects the fan-out semiconductor package 100A to the outside. For example, the fan-out semiconductor package 100A may be mounted on the main board of the electronic device through the electrical connection structure 170. [ The electrical connection structure 170 may be formed of a conductive material, for example, a solder or the like, but this is merely an example and the material is not particularly limited thereto. The electrical connection structure 170 may be a land, a ball, a pin, or the like. The electrical connection structure 170 may be formed of multiple layers or a single layer. In the case of a multi-layered structure, it may include a copper pillar and a solder. In the case of a single layer, tin-silver may include solder or copper. However, the present invention is not limited thereto. .

The electrical connection structure 170 is disposed on the under bump metal layer 160 and electrically connected to the electrical connection structure pad 142cp through the under bump metal layer 160. [ The number, spacing, arrangement type, etc. of the electrical connection structures 170 are not particularly limited and can be sufficiently modified according to design specifications for a typical engineer. For example, the number of electrical connection structures 170 may be in the range of tens to thousands, depending on the number of connection pads 122, and may be more or less. When the electrical connection structure 170 is a solder ball, the electrical connection structure 170 may cover the side surface formed on one side of the passivation layer 150 of the under bump metal layer 160 and may have a better connection reliability have.

At least one of the electrical connection structures 170 is disposed in the fan-out area. The fan-out area means an area outside the area where the semiconductor chip 120 is disposed. The fan-out package is more reliable than the fan-in package, allows multiple I / O terminals, and facilitates 3D interconnection. Compared with BGA (Ball Grid Array) package and LGA (Land Grid Array) package, it is possible to make package thickness thinner and excellent price competitiveness.

Though not shown in the drawing, a metal thin film may be formed on the wall surface of the through hole 110H for heat radiation and / or electromagnetic wave shielding, if necessary. In addition, if necessary, a plurality of semiconductor chips 120 that perform the same or different functions in the through holes 110H may be disposed. If necessary, another passive component such as an inductor or a capacitor may be disposed in the through hole 110H. Optionally, surface mount (SMT) components may also be disposed on the surface of the passivation layer 150, including passive components such as inductors, capacitors, and the like.

13 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to the drawings, a fan-out semiconductor package 100B according to another embodiment includes a first insulating layer 111a, a connecting member 140, and a first insulating layer 111a, A first wiring layer 112a buried in the first insulating layer 111a, a second wiring layer 112b disposed on the opposite side of the first insulating layer 111a on the side where the first wiring layer 112a is buried, A second insulating layer 111b disposed on the second insulating layer 111b and covering the second wiring layer 112b and a third wiring layer 112c disposed on the second insulating layer 111b. The first to third wiring layers 112a, 112b, and 112c are electrically connected to the connection pad 122. [ The first and second wiring layers 112a and 112b and the second and third wiring layers 112b and 112c have first and second vias 113a and 113b penetrating the first and second insulating layers 111a and 111b, As shown in Fig.

When the first wiring layer 112a is embedded in the first insulation layer 111a, the step generated by the thickness of the first wiring layer 112a is minimized, so that the insulation distance of the connection member 140 becomes constant. The distance from the first rewiring layer 142a of the connecting member 140 to the lower surface of the first insulating layer 111a and the distance from the first rewiring layer 142a of the connecting member 140 to the bottom surface of the semiconductor chip 120 The difference in distance to the connection pad 122 may be smaller than the thickness of the first wiring layer 112a. Therefore, high-density wiring design of the connecting member 140 can be facilitated.

The lower surface of the first wiring layer 112a of the core member 110 may be located above the lower surface of the connection pad 122 of the semiconductor chip 120. [ The distance between the first rewiring layer 142a of the connecting member 140 and the first wiring layer 112a of the core member 110 is larger than the distance between the first rewiring layer 142a of the connecting member 140 and the semiconductor chip 120, The connection pad 122 may be formed of a metal. This is because the first wiring layer 112a can be recessed into the insulating layer 111. When the first wiring layer 112a is recessed into the first insulating layer and the lower surface of the first insulating layer 111a and the lower surface of the first wiring layer 112a have stepped portions, It is possible to prevent the first wiring layer 112a from being contaminated. The second wiring layer 112b of the core member 110 may be positioned between the active surface and the inactive surface of the semiconductor chip 120. [ The second wiring layer 112b formed in the core member 110 is electrically connected to the active surface of the semiconductor chip 120 and the inactive surface 112b of the semiconductor chip 120. [ As shown in FIG.

The thickness of the wiring layers 112a, 112b and 112c of the core member 110 may be thicker than the thickness of the re-wiring layers 142a, 142b and 142c of the connecting member 140. [ The core member 110 may have a thickness larger than that of the semiconductor chip 120 and the wiring layers 112a, 112b, and 112c may be formed in a larger size to match the scale. On the other hand, the redistribution layers 142a, 142b, and 142c of the connection member 140 may be formed to have a relatively smaller size than the wiring layers 112a, 112b, and 112c for thinning.

The material of the insulating layers 111a and 111b is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a mixture of these resins with an inorganic filler, or a glass fiber Such as a prepreg, an Ajinomoto Build-up Film (ABF), a bismaleimide triazine (BT), or the like, may be used. If desired, a photosensitive insulator (PID) resin may be used.

The wiring layers 112a, 112b, and 112c can perform the role of rewiring the connection pads 122 of the semiconductor chip 120. [ The wiring layers 112a, 112b and 112c may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) Ti), an alloy thereof, or the like can be used. The wiring layers 112a, 112b, 112c can perform various functions according to the design design of the layer. For example, it may include a ground (GND) pattern, a power (PoWeR: PWR) pattern, a signal (S: S) pattern, Here, the signal S pattern includes various signals except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. It may also include via pads, wire pads, connection terminal pads, and the like.

The vias 113a and 113b electrically connect the wiring layers 112a, 112b, and 112c formed in different layers, thereby forming an electrical path in the core member 110. [ As the forming material of the vias 113a and 113b, a conductive material may also be used. The vias 113a and 113b may be completely filled with a conductive material, or a conductive material may be formed along the wall surface of the via hole. In addition, not only tapered but also all known shapes such as a cylindrical shape can be applied. A part of the pad of the first wiring layer 112a may serve as a stopper when the hole for the first via 113a is formed. The width of the upper surface of the first via 113a is larger than the width of the lower surface It may be advantageous in terms of the process to be a large tapered shape. In this case, the first vias 113a can be integrated with the pad pattern of the second wiring layer 112b. In addition, when forming the holes for the second vias 113b, some of the pads of the second wiring layer 112b may serve as stoppers, and the second vias 113b may have a width of the upper surface of the lower surface A taper shape larger than the width may be advantageous in terms of the process. In this case, the second via 113b may be integrated with the pad pattern of the third wiring layer 112c.

Other configurations, for example, the contents of the digg design of the pad pattern described with reference to Figs. 11 and 12 and the like can also be applied to the fan-out semiconductor package 100B according to another example, Substantially the same as described in the fan-out semiconductor package 100A and the like, and detailed description is omitted.

14 is a cross-sectional view schematically showing another example of the fan-out semiconductor package.

Referring to the drawings, in a fan-out semiconductor package 100C according to another example, a core member 110 includes a first insulating layer 111a, a first wiring layer 112a disposed on both surfaces of the first insulating layer 111a, A second insulating layer 111b disposed on the first insulating layer 112a and covering the first wiring layer 112a; a second insulating layer 111b disposed on the second insulating layer 111b; A third insulating layer 111c disposed on the first insulating layer 111a and covering the second wiring layer 112b and a fourth wiring layer 112d disposed on the third insulating layer 111c, . The first to fourth wiring layers 112a, 112b, 112c, and 112d are electrically connected to the connection pad 122. Since the core member 110 includes a larger number of wiring layers 112a, 112b, 112c and 112d, the connecting member 140 can be further simplified. Therefore, it is possible to improve the yield reduction due to defects generated in the process of forming the connecting member 140. The first to fourth wiring layers 112a, 112b, 112c and 112d have first to third vias 113a, 113b and 113c passing through the first to third insulating layers 111a, 111b and 111c, respectively. As shown in FIG.

The first insulating layer 111a may be thicker than the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity and the second insulating layer 111b and the third insulating layer 111c may be formed to have a larger number of wiring layers 112c and 112d It may be introduced. The first insulating layer 111a may include an insulating material different from the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, a filler, and an insulating resin, and the second insulating layer 111c and the third insulating layer 111c may be filler and insulating But is not limited to, an ABF film or a PID film containing a resin. The first vias 113a passing through the first insulating layer 111a have diameters larger than the second and third vias 113b and 113c passing through the second and third insulating layers 111b and 111c It can be big.

The lower surface of the third wiring layer 112c of the core member 110 may be located below the lower surface of the connection pad 122 of the semiconductor chip 120. [ The distance between the first rewiring layer 142a of the connecting member 140 and the third wiring layer 112c of the core member 110 is larger than the distance between the first rewiring layer 142a of the connecting member 140 and the semiconductor chip 120, The connection pad 122 may be formed of a metal. The third wiring layer 112c may be disposed on the second insulation layer 111b so as to be in contact with the connection member 140. [ The first wiring layer 112a and the second wiring layer 112b of the core member 110 may be positioned between the active surface and the inactive surface of the semiconductor chip 120. [ The first wiring layer 112a and the second wiring layer 112b formed in the core member 110 may be formed to correspond to the thickness of the semiconductor chip 120, May be disposed at a level between the active surface and the inactive surface.

The thickness of the wiring layers 112a, 112b, 112c and 112d of the core member 110 may be thicker than the thickness of the re-wiring layers 142a, 142b and 142c of the connecting member 140. [ The core member 110 may have a thickness larger than that of the semiconductor chip 120 and the wiring layers 112a, 112b, 112c and 112d may also be formed in a larger size. On the other hand, the redistribution layers 142a, 142b, and 142c of the connection member 140 can be formed in a relatively smaller size for thinning.

Other configurations, for example, the contents of the digg design of the pad pattern described with reference to Figs. 11 and 12, etc., can also be applied to the fan-out semiconductor package 100C according to another example, Substantially the same as described in the fan-out semiconductor package 100A and the like, and detailed description is omitted.

In the present disclosure, the lower side, the lower side, the lower side and the like refer to the direction toward the mounting surface of the fan-out semiconductor package with reference to the cross section of the drawing for convenience, and the upper side, the upper side and the upper side are used in the opposite direction. It should be noted, however, that this is a definition of a direction for the sake of convenience of explanation, and it is needless to say that the scope of rights of the claims is not particularly limited by description of such direction.

The meaning of being connected in this disclosure includes not only a direct connection but also an indirect connection through an adhesive layer or the like. In addition, the term "electrically connected" means a concept including both a physical connection and a non-connection. Also, the first, second, etc. expressions are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the right, the first component may be referred to as a second component, and similarly, the second component may be referred to as a first component.

The expression " exemplary " used in this disclosure does not mean the same embodiment but is provided for emphasizing and explaining different unique features. However, the above-mentioned examples do not exclude that they are implemented in combination with the features of other examples. For example, although the description in the specific example is not described in another example, it can be understood as an explanation related to another example, unless otherwise described or contradicted by the other example.

The terms used in this disclosure are used only to illustrate an example and are not intended to limit the present disclosure. Wherein the singular expressions include plural expressions unless the context clearly dictates otherwise.

1000: electronic device 1010: main board
1020: Chip related parts 1030: Network related parts
1040: Other parts 1050: Camera
1060: antenna 1070: display
1080: Battery 1090: Signal line
1100: Smartphone 1101: Smartphone body
1110: Smartphone mainboard 1111: mainboard insulation layer
1112: main board wiring 1120: parts
1130: Smartphone camera 2200: Fan-in semiconductor package
2220: semiconductor chip 2221: body
2222: connection pad 2223: passivation film
2240: connecting member 2241: insulating layer
2242: re-wiring layer 2243: via
2250: passivation layer 2260: under bump metal layer
2270: solder ball 2280: underfill resin
2290: molding material 2500: main board
2301: Interposer substrate 2302: Interposer substrate
2100: Fan-out semiconductor package 2120: Semiconductor chip
2121: Body 2122: Connection pad
2140: connecting member 2141: insulating layer
2142: re-wiring layer 2143: via
2150: passivation layer 2160: under bump metal layer
2170: solder ball 100: semiconductor package
100A to 100C: Fan-out semiconductor package
110: connecting member 111, 112a, 112b, 112c: insulating layer
112a, 112b, 112c, 112d: wiring layers 113a, 113b, 113c: vias
120: semiconductor chip 121: body
122: connection pad 123: passivation film
130: sealing member 140: connecting member
141a, 141b, 141c: insulating layers 142a, 142b, 142c:
142aw, 142bw, 142cw: wiring pattern 142ap, 142bp, 142cp: pad pattern
143a, 143b, 143c: via 150: passivation layer
151: opening 160: under bump metal layer
170: electrical connection structure

Claims (8)

A semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface disposed on the opposite side of the active surface;
A sealing material for sealing at least a part of the semiconductor chip; And
A connecting member disposed on an active surface of the semiconductor chip and including a re-wiring layer electrically connected to the connection pad; / RTI >
Wherein the redistribution layer comprises a pad pattern,
Wherein at least one of the pad patterns has a constant distance from the center to the rim,
A fan-out semiconductor package.
The method according to claim 1,
Wherein at least one of the pad patterns has a plurality of grooves formed at a rim thereof toward the center,
A fan-out semiconductor package.
The method according to claim 1,
Wherein the pad pattern comprises a via pad and an electrical connection structure pad.
A fan-out semiconductor package.
The method according to claim 1,
A core member having a through hole; Further comprising:
Wherein the semiconductor chip is disposed in the through hole,
A fan-out semiconductor package.
5. The method of claim 4,
The core member may include a first insulating layer, a first wiring layer in contact with the connecting member and embedded in the first insulating layer, and a second wiring layer on the opposite side of the first insulating layer, And a wiring layer,
Wherein the first and second wiring layers are electrically connected to the connection pad,
A fan-out semiconductor package.
6. The method of claim 5,
The core member further includes a second insulating layer disposed on the first insulating layer and covering the second wiring layer, and a third wiring layer disposed on the second insulating layer,
Wherein the third wiring layer is electrically connected to the connection pad,
A fan-out semiconductor package.
5. The method of claim 4,
Wherein the core member includes a first insulating layer and a first wiring layer and a second wiring layer disposed on both surfaces of the first insulating layer,
Wherein the first and second wiring layers are electrically connected to the connection pad,
A fan-out semiconductor package.
8. The method of claim 7,
A second insulating layer disposed on the first insulating layer and covering the first wiring layer, a third wiring layer disposed on the second insulating layer, and a second insulating layer disposed on the first insulating layer and covering the second wiring layer 3 insulating layer, and a fourth wiring layer disposed on the third insulating layer,
And the third and fourth wiring layers are electrically connected to the connection pad,
A fan-out semiconductor package.

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