KR20160141492A - Light emitting diode and manufacturing method of the same - Google Patents

Light emitting diode and manufacturing method of the same Download PDF

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KR20160141492A
KR20160141492A KR1020150077229A KR20150077229A KR20160141492A KR 20160141492 A KR20160141492 A KR 20160141492A KR 1020150077229 A KR1020150077229 A KR 1020150077229A KR 20150077229 A KR20150077229 A KR 20150077229A KR 20160141492 A KR20160141492 A KR 20160141492A
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layer
type
nitride semiconductor
shock
forming
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KR1020150077229A
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Korean (ko)
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김경해
정정환
곽우철
장삼석
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서울바이오시스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The present invention relates to a method of manufacturing a light emitting diode, and a method of manufacturing a light emitting diode according to an embodiment of the present invention includes the steps of: disposing a substrate in a growth chamber; Forming an n-type nitride semiconductor layer on the substrate; Forming an active layer on the n-type nitride semiconductor layer; And forming a p-type nitride semiconductor layer on the active layer, wherein forming the n-type nitride semiconductor layer includes: forming a lower n-type nitride layer on the substrate; Forming a second intermediate layer on the lower n-type nitride layer; Forming an n-type shock doping layer including a layer doped with an n-type dopant on the first intermediate layer; Forming an interlevel layer on the n-type shock doping layer; And forming a second intermediate layer on the interlayer, wherein the second intermediate layer comprises a super lattice layer in which a second sub interlayer having a band gap energy smaller than that of the first sub interlayer and the first sub interlayer is repeated, And the n-type shock doping layer and the second intermediate layer may be spaced apart by the insertion layer so that the n-type shock doping layer is located in the electric field generated in the second intermediate layer. According to the present invention, as the nitride semiconductor layer grows on the sapphire semiconductor, the electron density in the electron cloud generated by the band-banding at the lower end of the interlayer is increased by the intermediate layer for blocking the defect caused by the mismatch, The operation voltage can be lowered.

Description

TECHNICAL FIELD [0001] The present invention relates to a light emitting diode (LED)

The present invention relates to a method of manufacturing a light emitting diode, and more particularly, to a method of manufacturing a light emitting diode by increasing the electron dispersion efficiency of a light emitting diode epitaxially grown on a C surface of a sapphire substrate and increasing the probability of recombination of holes and electrons with respect to a horizontal plane of the light emitting diode And a manufacturing method thereof.

Generally, a light emitting diode includes a p-type semiconductor layer, an active layer, and an n-type semiconductor layer. When electric power is applied thereto, electrons in the n-type semiconductor layer and holes in the p- The electric energy is converted into light energy using the principle of emitting. Such a light emitting diode has advantages of energy conversion efficiency, long life, good light steering, and low voltage driving.

In addition, there is no need for a preheating time, no driving circuit is necessary, and it is strong against impact and vibration, and it is attracting attention as a next generation light source that can replace conventional light sources such as incandescent lamps, fluorescent lamps and mercury lamps.

In the light emitting diode, a nitride semiconductor is widely used as a base material. The nitride semiconductor is formed using a homogeneous substrate such as a gallium nitride substrate or a heterogeneous substrate such as sapphire. However, the melting point of gallium nitride is more than 2000 占 폚, and the nitrogen vapor pressure is very high, so that it is difficult to produce the ingot type. Therefore, the nitride semiconductor is generally grown using a heterogeneous substrate such as a sapphire substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, or the like.

However, nitride semiconductors manufactured using heterogeneous substrates have high defect densities due to differences in lattice constant and thermal expansion coefficient between the growth substrate and the nitride semiconductor.

In order to solve the problems occurring in such nitride semiconductors, Korean Patent Laid-Open No. 10-2013-0013968 discloses a technique of interposing an intermediate layer having a relatively large energy band gap in an n-type semiconductor layer to block defects . However, the intermediate layer has a larger band gap energy than the other semiconductor layers of the n-type semiconductor layer, thereby hindering electrons from being injected into the active layer, thereby increasing the forward voltage of the light emitting device.

FIG. 1 is a view showing the concentration profiles of Al and Si for electron injection of a conventional light emitting diode.

Referring to FIG. 1 (a), even if Al is doped with Si, the injected current can be dispersed in the horizontal direction. However, since the doping is not performed at a high concentration of Si at this time, the dispersion efficiency is not high and the effect of horizontal dispersion of the current is not so large, so that the light emitting efficiency of the light emitting diode may not be high. At this time, doping of Si can be doped by a conventional method.

In order to increase the luminous efficiency of the light emitting diode accordingly, as shown in FIG. 1 (b), when doping is performed so that a predetermined peak (or shock) occurs in the Si doping concentration when Si is doped, The horizontal dispersion effect of the injected current can be increased. However, as shown in FIG. 1 (b), when Si doping is performed, the relationship with Al must be specified. Conventionally, the distance between Al and Si is separated by about 500 nm or more, There is a problem that is not big. Accordingly, the effect of the horizontal dispersion of the injected current is not large, so that the light emitting efficiency of the light emitting diode is not high.

In addition, in a light emitting diode, it is difficult for the current supplied generally to be uniformly dispersed in the semiconductor layer in the horizontal direction over the entire light emitting region, and recombination of electrons and holes is mainly performed around the electrode pad. Accordingly, the light emission intensity is lowered in a part of the light emitting region of the conventional light emitting diode, and the overall light emitting efficiency of the light emitting diode is lowered.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a light emitting diode capable of increasing the efficiency of horizontal dispersion of an injected current to improve recombination efficiency of electrons and holes.

A light emitting diode according to an embodiment of the present invention includes a growth substrate; An n-type nitride semiconductor layer formed on the growth substrate; An active layer formed on the n-type nitride semiconductor layer; A p-type nitride semiconductor layer formed on the active layer; The n-type nitride semiconductor layer may include: a lower n-type nitride semiconductor layer formed on the growth substrate; An intermediate layer having a larger bandgap than the lower n-type nitride semiconductor layer; And an n-type shock layer interposed between the intermediate layer and the lower n-type nitride semiconductor layer and including at least one layer doped at a higher concentration than the lower n-type nitride semiconductor layer.

At this time, the n-type nitride semiconductor layer may include a modulation doped layer of an n-type dopant, and the n-type shock layer may be included in the modulation doped layer of the n-type dopant.

The n-type shock layer may be n-type doped with a doping concentration of 1 x 10 18 atoms / cm 3 or more, and the n-type shock layer may be formed adjacent to the middle layer.

The n-type shock layer may have a reduced n-type doping concentration toward the intermediate layer. The distance between the n-type shock layer and the intermediate layer may be 0 to 20 nm, and the thickness of the n-type shock layer may be 1 to 10 nm.

According to another aspect of the present invention, there is provided a method of fabricating a light emitting diode, comprising: disposing a growth substrate in a growth chamber; Forming an n-type nitride semiconductor layer on the growth substrate; Forming an active layer on the n-type nitride semiconductor layer; And forming a p-type nitride semiconductor layer on the active layer, wherein forming the n-type nitride semiconductor layer includes forming a lower n-type nitride semiconductor layer on the growth substrate to inject electrons into the active layer, ; Forming an n-type shock layer including a layer doped at a higher concentration than the lower n-type nitride semiconductor layer on the lower n-type nitride semiconductor layer; And forming an intermediate layer having a larger bandgap than the lower n-type nitride semiconductor layer on the n-type shock layer.

At this time, the step of forming the n-type nitride semiconductor layer may include a modulation doped layer of n-type dopant.

And forming the n-type shock layer comprises: a T 1 step of supplying an n-type dopant source into the growth chamber at a first flow rate for T 1 hour; And a T 2 step of supplying an n-type dopant source into the growth chamber at a second flow rate less than the first flow rate for T 2 hours.

In this case, the T the flow rate of the n-type dopyeon bit source between step 1 and T Step 2 above at a first flow rate may further comprise a T Step 3 for continuously changed while T 3 time as the second flow rate, the The first flow rate may increase as the T 1 and T 2 steps are repeated.

Here, the n-type shock layer may be n-type doped with a doping concentration of 1 x 10 18 atoms / cm 3 or more.

And forming the intermediate layer includes introducing an Al source, a Ga and / or In source, an N source, and an n-type dopant source into the growth chamber to grow the first sub-intermediate layer; And stopping the introduction of the Al source gas and the n-type dopant source, and continuously introducing the Ga and / or In source and N source gas into the growth chamber to grow the second sub-intermediate layer, And forming a repetitive laminated structure of the first sub-intermediate layer and the second sub-intermediate layer.

At this time, the n-type dopant concentration of the first sub-intermediate layer may increase as the respective steps are periodically repeated.

According to another aspect of the present invention, there is provided a method of fabricating a light emitting diode including: disposing a growth substrate in a growth chamber; Forming an n-type nitride semiconductor layer on the growth substrate; Forming an active layer on the n-type nitride semiconductor layer; And forming a p-type nitride semiconductor layer on the active layer, wherein the step of forming the n-type nitride semiconductor layer includes forming a p-type nitride semiconductor layer on the growth substrate to inject electrons into the active layer, Forming an n-type shock modulation layer including a shock layer; And forming an intermediate layer for dispersing electrons injected from the n-type shock modulation layer into the active layer, wherein the shock layer can be formed to partially overlap the heavily doped peak of the intermediate layer.

At this time, the shock layer may be formed so as to change the doping concentration, and the doping concentration of the shock layer may be doped within a range of 1 to 50% with respect to the doping concentration of the intermediate layer.

According to the present invention, since the n-type nitride layer doped at a high concentration is formed adjacent to the intermediate layer containing AlGaN, injected electrons can distribute the electrons evenly in the horizontal direction in the intermediate layer.

1 is a view showing a concentration profile of a conventional light emitting diode.
2 is a cross-sectional view illustrating a light emitting diode according to an exemplary embodiment of the present invention.
3 is a view for explaining a concentration profile and band gap of a light emitting diode according to an embodiment of the present invention.
4 to 9 are views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention.
10A to 10C are charts for explaining a growth method of an n-type shock doping layer according to an embodiment of the present invention.
FIG. 10D is a graph for explaining the n-type dopant concentration of the n-type shock doping layer according to an embodiment of the present invention.
11 is a view for explaining a growth method and structure of a second intermediate layer according to an embodiment of the present invention.
12 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention.
13 is a view for explaining a concentration profile and band gap of a light emitting diode according to another embodiment of the present invention.
FIG. 14 is a view for explaining a concentration profile and a band gap of another light emitting diode according to another embodiment of the present invention.
Fig. 15 is a diagram showing SIMS data for the concentration profile shown in Fig. 14 (a). Fig.
16 is a diagram for comparing Vf and power of a conventional light emitting diode and a light emitting diode according to another embodiment of the present invention.
17 to 19 are diagrams showing simulation results of a light emitting diode according to another embodiment of the present invention.

Preferred embodiments of the present invention will be described more specifically with reference to the accompanying drawings.

FIG. 2 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention. FIG. 3 (a) is a view showing a concentration profile of a light emitting diode according to an embodiment of the present invention, Is a view for explaining a bandgap of a light emitting diode according to an embodiment of the present invention.

The light emitting diode includes a substrate 110, a buffer layer 121, an n-type nitride semiconductor layer 130, an active layer 140, and a p-type nitride semiconductor layer 150.

The substrate 110 is not limited as long as it can grow the nitride semiconductor layer, and may be an insulating or conductive substrate. The substrate 110 may be, for example, a sapphire substrate, a silicon substrate, a silicon carbide substrate, an aluminum nitride substrate, or a gallium nitride substrate. In this embodiment, the substrate 110 may be a patterned sapphire substrate (PSS) having a concavo-convex pattern (not shown) on its upper surface, and the PSS may include a C face as a growth surface . However, the present invention is not limited thereto.

The buffer layer 121 may comprise AlGaN and / or GaN and may be grown on the substrate 110 at a temperature of about 500-600 < 0 > C. The buffer layer 121 can serve as a nucleus layer in which the nitride semiconductor can grow when the substrate 110 is a substrate different from the nitride semiconductor. It may also play a role in relieving stress and strain due to lattice constant mismatch. However, the buffer layer 121 may be omitted.

The n-type nitride semiconductor layer 130 is formed on the buffer layer 121 and the lower n-type nitride layer 131, the first intermediate layer 133, the n-type shock doping layer 135 and the second intermediate layer 137 .

The lower n-type nitride layer 131 may include an n-type GaN layer and may be formed to a thickness of about 0.5 to 1.5 탆, but is not particularly limited. The n-type dopant doping concentration of the lower n-type nitride layer 131 may be lower than the maximum doping concentration of the n-type shock doping layer 135, which will be described later.

As described above, the impurity doping concentration of the lower n-type nitride layer 131 is relatively lowered, and the crystallinity of the lower n-type nitride layer 131 located relatively closer to the substrate 110 can be improved. Accordingly, the crystallinity of the semiconductor layers grown in the subsequent process can be increased.

The first intermediate layer 133 may include a nitride semiconductor having a composition different from that of the lower n-type nitride layer 131, and may include AlGaN in particular. Or n-type doped, and may be an undoped state.

As described above, since the first intermediate layer 133 includes a nitride semiconductor having a composition different from that of the lower n-type nitride layer 131, the lower n-type nitride layer 131 is grown and dislocated in the subsequent process It can be prevented from being propagated to other semiconductor layers to be grown. Accordingly, the first intermediate layer 133 can improve the crystallinity of the n-type nitride semiconductor layer 130 and the light emitting diode according to an embodiment of the present invention.

The n-type shock doping layer 135 may include a modulation-doped structure in which the n-type dopant is doped. Details of the growth of the n-type shock doping layer 135 and the n-type dopant concentration of the n-type shock doping layer 135 will be described in detail in the growth method.

As described above, the n-type shock doping layer 135 is formed and the n-type shock doping layer 135 is formed adjacent to the second intermediate layer 137, so that the light emitting diode including the n-type nitride semiconductor layer 130 When the power source is applied, electrons injected from the n-type shock doping layer 135 can be uniformly dispersed in the horizontal direction. This can repeatedly deposit a high concentration doping region and a low concentration doping region in the n-type shock doping layer 135, thereby forming a barrier in an electron transfer path in the vertical direction. Thereby promoting the movement of electrons in the horizontal direction.

More specifically, since the mobility of electrons is inversely proportional to the doping concentration, if the doping concentration is too high, the mobility of electrons is lowered and the dispersion of electrons is limited. On the other hand, if the doping concentration is too low, the self-resistance of the semiconductor becomes high, so that the dispersion of electrons is limited. Accordingly, in one embodiment of the present invention, electrons are injected through the n-type shock doping layer 135 at a concentration of a low region adjacent to the high region, so that the mobility of electrons can be further improved.

In addition, the n-type shock doping layer 135 according to an embodiment of the present invention includes a shock layer that is a heavily doped region, and prevents the electron injection efficiency from decreasing in the active layer 140 in the horizontal direction of electrons . The shock layer means a region doped with Si at a high concentration in the concentration profile shown in Fig. 3 (a). As shown in Fig. 3 (a), the shock layer may be formed adjacent to the second intermediate layer 137 (Al position in Fig. 3 (a)). So that electron injection in the n-type shock doping layer 135 can be improved.

The second intermediate layer 137 may be formed on the n-type shock doping layer 135 and may include a first sub-intermediate layer 137a and a second sub-intermediate layer 137b. The second intermediate layer 137 may be formed of a super lattice layer in which the first sub-intermediate layer 137a and the second sub-intermediate layer 137b are alternately repeatedly laminated, but the present invention is not limited thereto.

The first sub-intermediate layer 137a may be doped at a certain concentration, and the second sub-doping layer may be doped or undoped at a lower concentration than the first sub-intermediate layer 137a. The first sub-intermediate layer 137a may have a thickness of about 3 to 5 mu m and the second sub-intermediate layer 137b may have a thickness of about 2 to 4 mu m, and the thickness of the first sub- May be thicker than the thickness of the second sub-intermediate layer 137b.

The number of repeating cycles of the first sub-intermediate layer 137a and the second sub-middle layer 137b is not limited. However, if the number of repeating cycles is increased to a certain level or more, the difference in lattice constant between the active layer 140 and the active layer 140 increases, There is a possibility of deterioration. Therefore, in one embodiment of the present invention, the number of repeating cycles of the first sub-intermediate layer 137a and the second sub-middle layer 137b may be 1 to 6, for example.

The band gap energy of the first sub interlayer 137a may be greater than the band gap energy of the second sub interlayer 137b and the doping densities of the first sub interlayers 137a may be the same or different. And can be changed regularly according to the stacking order. The doping concentration of the first sub-intermediate layer 137a may be higher than the doping concentration of the n-type shock doping layer 135. It is possible to effectively prevent the injection of electrons from the n-type shock doping layer 135 into the active layer 140. This prevents the injection of electrons from the n-type shock doping layer 135 into the active layer 140 more smoothly Lt; / RTI >

The active layer 140 may include a nitride based semiconductor such as (Al, Ga, In) N and may be grown on the n-type nitride semiconductor layer 130 using a technique such as MOCVD, MBE, or HVPE . In addition, the active layer 140 may have a multiple quantum well structure (MQW) including a plurality of barrier layers and a well layer. At this time, the elements constituting the semiconductor layers and the composition thereof can be adjusted so that the semiconductor layers constituting the multiple quantum well structure emit light of a desired peak wavelength.

The p-type nitride semiconductor layer 150 may include a nitride semiconductor such as (Al, Ga, In) N and may be grown on the active layer 140 using a technique such as MOCVD, MBE, or HVPE . The p-type nitride semiconductor layer 150 may include a p-type dopant, for example, Mg as a dopant.

The active layer 140 and the p-type nitride semiconductor layer 150 may be formed of any known technique, and a detailed description thereof will be omitted herein.

As described above, as the n-type nitride semiconductor layer 130 is formed, the n-type shock doping layer 135 is formed adjacent to the second intermediate layer 137, so that a difference in energy band gap Lt; / RTI > So that injection of electrons from the n-type shock doping layer 135 into the second intermediate layer 137 can be performed more smoothly.

4 to 9 are views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention. 10A to 10C are charts for explaining a growth method of the n-type shock doping layer 135 according to an embodiment of the present invention, and Fig. 10D is a graph illustrating a growth method of the n-type shock doping layer 135). ≪ / RTI > 11 is a view for explaining a growth method and structure of the second intermediate layer 137 according to an embodiment of the present invention.

First, referring to FIG. 4, a substrate 110 is placed in a growth chamber. The substrate 110 is not limited to the substrate 110 on which the nitride semiconductor layer can be grown as described above, and the same description is omitted. Next, referring to FIG. 5, a buffer layer 121 may be formed on the substrate 110.

Next, referring to FIGS. 6 to 9, an n-type nitride semiconductor layer 130 is formed on the buffer layer 121. Hereinafter, a method of growing the n-type nitride semiconductor layer 130 will be described in detail.

First, referring to FIG. 6, a lower n-type nitride layer 131 may be formed on the buffer layer 121.

The lower n-type nitride layer 131 can be grown by introducing a Group III atom source such as Al, Ga, In, etc., a Group V atom source such as N, and an n-type dopant source such as Si into the growth chamber. For example, the lower n-type nitride layer 131 may include an n-type GaN layer.

Referring to FIG. 7, a first intermediate layer 133 is formed on the lower n-type nitride layer 131. At this time, the first intermediate layer 133 can be grown by introducing a Group III atom source such as Al, Ga, In, etc. and a Group V atom source such as N into the growth chamber.

Next, referring to FIG. 8, an n-type shock doping layer 135 is formed on the first intermediate layer 133. Referring to FIGS. 10A to 10C, details of the method for forming the n-type shock doping layer 135 will be described in detail .

The n-type shock doping layer 135 is grown by introducing a Group III atom source such as Al, Ga, In, etc., a Group V atom source such as N, and an n-type dopant source such as Si into the growth chamber, Can be grown with a constant flow rate. That is, growing the n-type shock doping layer 135 includes increasing and decreasing the introduction flow rate of the n-type dopant source at least once during the growth process. When the n-type shock doping layer 135 is grown, the introduced flow rate of the n-type dopant source may be periodically changed or irregularly changed with time.

Specifically, referring to FIG. 10A, in growth of the n-type shock doping layer 135, a Group III atom source, a Group V atom source, and an n-type dopant source are introduced into the growth chamber. At this time, the supply flow rate of the Group III atom source and the Group V atom source can be kept constant. The n-type dopant source can be grown by repeating the period P1 supplied at the first flow rate f1 for the time T1 and the second flow rate f2 for the time T2 after the time T1.

On the other hand, according to the embodiment of FIG. 10A, the variation of the flow rate of the n-type dopant source is described as being intermittent, but the present invention is not limited thereto and the flow rate change of the n-type dopant source may be continuous. Thus, growing the n-type shock doping layer 135 can further include varying the introduction flow rate of the n-type dopant source over time.

For example, referring to FIG. 10B, the n-type dopant source is supplied at the first flow rate f1 for a time T1, and the introduction flow rate for the time T3 after the time T1 is the second flow rate f2 at the first flow rate f1, And is supplied to the second flow rate f2 for the time T2 after the time T3 and again for the time period T4 after the time T2 to the first flow rate f1 from the second flow rate f2 to the first flow rate f1 Can be grown by repeating the increasing period P2.

10A and 10B, it is explained that the introduction flow rate of the n-type dopant source repeatedly changes in the first flow rate f1 and the second flow rate f2, but the present invention is not limited thereto , the introduction flow rate of the n-type dopant source may vary continuously.

For example, as shown in FIG. 10C, when the n-type dopant source is introduced into the growth chamber along the period of P3 to P5, the maximum flow rate in each cycle is increased from P3 to P5, The introduced flow rate may be adjusted. That is, when the maximum flow rate in each cycle is defined as a first flow rate at the time of growing the n-type shock doping layer 135, the first flow rate in the following cycle may be larger than the first flow rate in the preceding cycle.

It should be noted, however, that the present invention is not limited to the above-mentioned examples, and it is the scope of the present invention to change the introduction flow rate of the n-type dopant source with increasing and decreasing in the growth of the n-type shock doping layer 135 .

Referring again to FIG. 8, according to the introduction method of the n-type dopant source, the n-type dopant concentration of the grown n-type shock doping layer 135 can be modulated along its growth direction. Therefore, the n-type dopant concentration of the n-type shock doping layer 135 can be changed as shown in Fig. 10D. At this time, the n-type dopant concentration of the n-type shock doping layer 135 may be 1 x 10 17 atoms / cm 3 or more, the maximum doping concentration of the heavily doped region is about 5 x 10 18 atoms / cm 3 to 1 x 10 20 atoms / The minimum doping concentration of the lightly doped region may be about 5 x 10 17 atoms / cm 3 to 3 x 10 18 atoms / cm 3. For example, the maximum doping concentration of the high concentration doping region may be about 1 x 10 19 atoms / cm 3, and the minimum doping concentration of the low concentration doping region may be about 1 x 10 18 atoms / cm 3. The thickness of the n-type shock doping layer 135 may be about 2 to 3 占 퐉, and the repetition period of the heavily doped region and the heavily doped region may be about 100 to 200 cycles. At this time, the thicknesses of the high concentration doped region and the low concentration doped region may be substantially the same. However, the present invention is not limited thereto.

At this time, the shock layer included in the n-type shock doping layer 135 can be grown at about 900 占 폚 or lower, preferably at 850 占 폚, and grown at a lower temperature than other layers. Also, the growth pressure of the shock layer may be relatively lower than the underlying n-type nitride layer 131, and may be grown, for example, at a pressure of about 150 torr or less.

Next, referring to FIG. 9, a second intermediate layer 137 may be formed on the n-type shock doping layer 135, thereby forming an n-type nitride semiconductor layer 130.

The second intermediate layer 137 is formed by introducing an Al source, a Ga and / or In source, an N source, and an n-type dopant source into the growth chamber to grow the first subintermediate layer 137a, Type dopant source is stopped and the Ga and / or In source and the N source are continuously introduced into the growth chamber to grow the second sub-intermediate layer 137b, and the first sub-intermediate layer 137a and the second sub- To form a repeated laminated structure of the sub-intermediate layer 137b. Accordingly, the first sub-intermediate layer 137a may be doped to a certain concentration, and the second sub-intermediate layer 137b may be doped or undoped to a lower concentration than the first sub-intermediate layer 137a.

As shown in FIG. 10A, the second intermediate layer 137 may include a superlattice structure in which the first subintermediate layer 137a and the second subintermediate layer 137b are repeatedly stacked. 10 (b), an Al source, a Ga source, an N source, and an n-type dopant source are first introduced into the growth chamber for T1 hours to grow a first subintermediate layer 137a, The supply of the Al source and the n-type dopant source is stopped, and only the Ga source and the N source are introduced into the growth chamber to repeat the cycle P for growing the second sub-intermediate layer 137b, whereby the second intermediate layer 137 is grown .

Further, during the growth of the second intermediate layer 137, an In source may be further introduced into the growth chamber, and the In source may be continuously introduced into the growth chamber while the second intermediate layer 137 is being grown, . Alternatively, the In source may be introduced into the growth chamber only during the growth period of the second sub-intermediate layer 137b.

On the other hand, when the second sub-intermediate layer 137b is grown to include InGaN, the Ga source can use TEGa. When TEGa is used, the second subintermediate layer 137b can be formed at a lower growth temperature, and therefore the In content of InGaN can be increased. The mobility of electrons can be improved when the In content in the second sub-intermediate layer 137b is increased, so that the light emitting efficiency of the light emitting diode including the n-type nitride semiconductor layer 130 of the present embodiment can be improved have.

In the second intermediate layer 137 thus formed, the doping concentration of the first sub-intermediate layer 137a may be higher than the doping concentration of the n-type shock doping layer 135 and may be, for example, 1 x 10 18 atoms / cm 3 3 or more, and may be 5 x 10 19 atoms / cm 3 or more, and may be 2.9 x 10 20 atoms / cm 3 or more. The composition ratio of Al in the first sub-intermediate layer 137a may be 0.02 or more and 0.2 or less.

As described above, since the superlattice layer is formed as the second intermediate layer 137, defects such as dislocations can be prevented from propagating to the active layer 140. The efficiency of injecting electrons into the active layer 140 can be increased by including the first intermediate sublayer 137a doped with a relatively high concentration of the second intermediate layer 137. This n-type nitride semiconductor layer 130 can be formed, It is possible to prevent or even reduce the forward voltage of the light emitting diode. More specifically, the first sub interlayer 137a having a large band gap energy and the second sub interlayer 137b having a relatively small band gap energy are formed in a superlattice structure, so that a quantum well structure can be formed have. At this time, the first sub-intermediate layer 137a may be doped with a high concentration to provide a large number of electrons to the second intermediate layer 137, and a large amount of electrons located in the conduction band may not be isolated from the quantum well, . ≪ / RTI > Thus, the second intermediate layer 137, which can perform the same function as the defect prevention, can be provided while preventing the electron injection efficiency from being lowered by the conventional intermediate layer.

2DEG (2-Dimensional Electron Gas) may be formed at each interface by the repetitive lamination structure of the first sub interlayer 137a and the second sub interlayer 137b. In this case, The movement of electrons in both directions can be facilitated. Accordingly, the resistance to both the vertical direction and the horizontal direction is lowered, so that the forward voltage of the light emitting device including the nitride semiconductor layer structure of the present embodiment can be lowered, and the dispersion efficiency of electrons in the light emitting diode can also be improved.

Referring again to FIG. 2, the active layer 140 and the p-type nitride semiconductor layer 150 are formed on the n-type nitride semiconductor layer 130 to provide a semiconductor stacked structure as shown in FIG.

FIG. 12 is a cross-sectional view illustrating a light emitting diode according to another embodiment of the present invention. FIG. 13 (a) is a view showing a concentration profile of a light emitting diode according to another embodiment of the present invention, Is a view for explaining a bandgap of a light emitting diode according to another embodiment of the present invention.

The light emitting diode according to another embodiment of the present invention includes a substrate 110, a buffer layer 121, an n-type nitride semiconductor layer 130, an active layer 140, and a p-type nitride semiconductor layer 150. The n-type nitride semiconductor layer 130 is formed on the buffer layer 121 and the lower n-type nitride layer 131, the first intermediate layer 133, the n-type shock doping layer 135, the intercalation layer 135a, And a second intermediate layer 137. In explaining another embodiment of the present invention, the same description as in the embodiment is omitted.

The interlevel layer 135a may be interposed between the n-type shock doping layer 135 and the second intermediate layer 137. At this time, the uppermost portion of the n-type shock doping layer 135 may be formed as a lightly doped region, the interlayer 135a may be grown on the lightly doped region, the second intermediate layer 137 may be formed on the interlayer 135a, Lt; / RTI > Accordingly, the lightly doped region of the n-type shock doping layer 135 and the intercalation layer 135a can be formed to be in contact with each other. doped region in the uppermost region of the n-type shock doping layer 135, thereby acting as a 2DEG channel of the second intermediate layer 137. [ As a result, the dispersion of electrons in the horizontal direction can be further facilitated. At this time, the n-type shock doping layer 135 may include a shock layer (a position where Si is heavily doped in Fig. 13 (a)). In another embodiment of the present invention, the shock layer may be spaced a predetermined distance by the second intermediate layer 137 and the interposition layer 135a, and the shock layer may be grown by the same method as in one embodiment of the present invention .

The insertion layer 135a is formed between the n-type shock doping layer 135 and the second intermediate layer 137 so that the n-type shock doping layer 135 and the second intermediate layer 137 are formed due to the insertion layer 135a. . In this case, the thickness of the interlayer 135a, that is, the distance d between the n-type shock doping layer 135 and the second intermediate layer 137 is set so that the n-type shock doping layer 135 is in contact with the second intermediate layer 137, The insertion layer 135a is grown so as to be located in an electric field generated in the 2DEG of the substrate. In an embodiment of the present invention, the distance d between the shock layer and the second intermediate layer 137 may be about 100 nm to 200 nm, and may be within 100 nm.

FIG. 14 is a view for explaining a concentration profile and band gap of a light emitting diode according to another embodiment of the present invention, and FIG. 15 is a graph showing SIMS data of a concentration profile of a light emitting diode according to another embodiment of the present invention FIG.

A light emitting diode according to another embodiment of the present invention includes a substrate 110, a buffer layer 121, an n-type nitride semiconductor layer 130, an active layer 140, and a p- And a semiconductor layer 150. The n-type nitride semiconductor layer 130 is formed on the buffer layer 121 and the lower n-type nitride layer 131, the first intermediate layer 133, the n-type shock doping layer 135 and the second intermediate layer 137, . ≪ / RTI >

Here, the n-type shock doping layer 135 may include a structure in which an n-type dopant is modulation-doped. In another embodiment of the present invention, the n-type shock doping layer 135 can be grown at a relatively lower temperature than the underlying n-type nitride layer 131. Whereby the n-type dopant source can be introduced into the growth crystal without being dissociated and doped to a sufficient concentration in the shock layer. At this time, the n-type shock doping layer 135 may include a shock layer. In another embodiment of the present invention, the n-type dopant source is Si, for example.

That is, the lower n-type nitride layer 131 can be grown at 1000 ° C. or higher by using MOCVD technique. The shock layer included in the n-type shock doping layer 135 can be grown at about 900 ° C. or lower, Lt; RTI ID = 0.0 > 850 C. < / RTI >

And the growth pressure in forming the shock layer may be relatively lower than the growth pressure of the underlying n-type nitride layer 131. If the underlying n-type nitride layer 131 is grown at a pressure greater than about 150 torr, Can grow at pressures below 150 torr. Thereby reducing the amount of NH 3 introduced into the shock layer so that the pores of the nitrogen atoms can be more easily filled with Si.

Further, when forming the shock layer, the amount of NH 3 injected may be relatively smaller than that of the lower n-type nitride layer 131. As the amount of NH 3 injected decreases, Si is filled in the vacancies, Can be increased. For example, if the amount of NH 3 introduced into the lower n-type nitride layer 131 is 50 slm, the injection amount of NH 3 in the shock layer may be 40 slm.

As described above, when the n-type shock doping layer 135 is manufactured including the shock layer, the conditions such as growth temperature and pressure are modified so that Si is injected as shown in Fig. 14 (a) . When the 2DEG formed in the second intermediate layer 137 is formed so as to be included, the shock layer of Si can be doped so as to partially overlap the concentration of Al. That is, as shown in FIG. 14A, when the 2DEG made of Al forms a peak, the inclination of the shock layer is gentle so that the point where the density of the 2DEG becomes small and the point where the shock layer is formed are partially overlapped . So that the point at which the shock layer begins can start in the middle region of the 2DEG peak. Here, the region where the 2DEG peak and the shock layer overlap may be within 1 to 50% of the height of the 2DEG layer.

As shown in FIG. 14B, the bandgap along the shock layer is as shown in FIG. 14, and as shown in FIG. 15, the SIMS data show that the shock layer due to Si doping is a 2DEG peak composed of Al And the slope of the shock layer is gently formed. At this time, in another embodiment of the present invention, the shock layer can be formed within 100 nm from the 2DEG peak.

FIG. 16 (a) is a view showing Vf and power of a conventional light emitting diode, and FIG. 16 (b) is a view showing Vf and power of a light emitting diode according to another embodiment of the present invention.

Accordingly, the data according to FIG. 16 (a) and FIG. 16 (b) can be compared as shown in Table 1. As a result, it can be seen that the Vf of the LED according to another embodiment of the present invention is reduced by about 0.084 V, and the power is reduced by about 0.26%.

At this time, the second intermediate layer 137 is formed by repeatedly repeating five cycles of 3 nm each of AlGaN and GaN by 30 nm, and electrons can more easily pass through the second intermediate layer 137, thereby efficiently generating the 2DEG. At this time, when the Si gradation layer having the doping concentration changed between the AlGaN second intermediate layers 137 is introduced, the thickness of the Si gradation layer is 10 nm, the thickness of the Si shock layer is 10 nm, and the doping concentration is 2E19.

Here, the Si gradation layer may be formed by gradually reducing the flow of SiH 4 , and may be formed by heating in a state in which the source is shut off, and then slowly depositing Si in the chamber.

Fig. 16 (a) of the prior art shows no Si gradation layer as described above, and Fig. 16 (b) shows a Si shock layer and a Si gradation layer.

Mo MO28 MO28 POWER deviation Vf deviation (V) RECIPE Conventional In this embodiment -0.26% -0.084V DEVICE M0905-GA-4I M0905-GA-LU-4I Parameter (EA) 92 17 Run time 7:42 6:40 run / day 3.05 3.60 IR_AVG 0.016 0.014 Vf1_AVG 2.280 2.274 Vf2_AVG 3.090 3.006 WD_AVG 455.850 455.799 Watt_AVG 117.590 177.290

As a result, when the injection efficiency of electrons into the 2DEG was examined, it was confirmed that the operation voltage was reduced by about 3% although the difference in luminous intensity was similar as a result of injecting the Si shock layer.

17 to 19 are diagrams showing simulation results of a light emitting diode according to another embodiment of the present invention.

The conditions for performing the simulation as shown in FIGS. 17 to 19 are as follows. Using a simulation tool called SiLENSe, the dislocation density is 1E8 cm -2 and the conduction band DOS tail of the quantum well layer is 0.035 eV. The basic structure is shown in Table 2.

layer Composition ratio Thickness (nm) Doping concentration (cm -3 ) p layer GaN 200 2E19 AlGAN EBL Al 0.2 GaN 20 5E19 5 cycle MQW
Well In 0.15 GaN 3 - GaN 10 - N layer GaN 100 5E18 AlGaN middle layer Al 0.1 GaN 20 5E18 Si shock layer N layer GaN 500 5E18

17 shows the operating current and IQE at a constant voltage of 3.8 V. When the Si shock layer is located adjacent to the lower end of the AlGaN second intermediate layer 137 and the thickness of the Si shock layer is fixed at 20 nm, And the change of the characteristics according to the doping concentration. As a result, as shown in FIG. 17, a high-concentration doping layer is implanted into the lower end of the second intermediate layer 137, but the IQE is not significantly different, and the thickness of the 2DEG may be about 20 to 30 nm.

Here, when the operating current is observed, the highest value appears at 2E19, and the 2DEG can be extended toward the n-layer in the Si doping. This indicates that the electron density in the vertical direction is injected and the dispersion is improved in the horizontal direction. However, if the concentration becomes higher than a certain level, the Si dopant atoms act as a resistor and can inhibit the horizontal dispersion.

Referring to FIG. 18, the operating current and IQE at a constant voltage of 3.8 V are shown. The Si shock layer thickness is 20 nm and the doping concentration is 2E19. When the undoped layer is introduced between the AlGaN second intermediate layers, And the change of the characteristics according to the thickness.

As a result, it can be seen that the operating current decreases as the Si shock layer included in the n-type shock doping layer 135, which is the electron injection layer, moves away from the AlGaN second intermediate layer 137. When the insertion layer 135a, which is an undoped layer, is inserted into the second intermediate layer 137, the electron injection efficiency is lowered, but the disturbance of dispersion due to Si atoms can be reduced. Here, the thickness of the undoped layer may be from 0 to 20 nm, and preferably from 0 to 10 nm.

Referring to FIG. 19, the operating current and IQE at a constant voltage of 3.8 V are shown. The thickness of the Si shock layer is 20 nm, the doping concentration is 2E19, and the Si doping concentration varies between the AlGaN second intermediate layer 137 And the gradation layer was changed to the thickness of the undoped layer.

Accordingly, it can be seen that the use of the gradation layer improves the injection efficiency of electrons and reduces the interference effect of Si atoms, compared with the case where the insertion layer 135a, which is an undoped layer, is introduced. Then, by injecting the gradation layer, the optimum point for the distance between the n-type shock doping layer 135 and the second intermediate layer 137, which is the electron injection layer, can be set to 10 nm. As a result, there is an effect that the constant-voltage operation current can be made higher. At this time, the thickness of the gradation layer may be 1 to 10 nm.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It should be understood that the scope of the present invention is to be understood as the scope of the following claims and their equivalents.

110: substrate
121: buffer layer 130: n-type nitride semiconductor layer
131: lower n-type nitride layer 133: first intermediate layer
135: n-type shock doping layer 135a:
137: second intermediate layer 137a: first sub-
137b: second sub-intermediate layer 140: active layer
150: a p-type nitride semiconductor layer

Claims (19)

Growth substrate;
An n-type nitride semiconductor layer formed on the growth substrate;
An active layer formed on the n-type nitride semiconductor layer;
A p-type nitride semiconductor layer formed on the active layer;
Type nitride semiconductor layer,
A lower n-type nitride semiconductor layer formed on the growth substrate;
An intermediate layer having a larger bandgap than the lower n-type nitride semiconductor layer; And
And an n-type shock layer interposed between the intermediate layer and the lower n-type nitride semiconductor layer and including at least one layer doped at a higher concentration than the lower n-type nitride semiconductor layer. The nitride semiconductor light emitting device according to claim 1, wherein the n-type nitride semiconductor layer
wherein the n-type dopant comprises a modulation doped layer. The method of claim 2,
Wherein the n-type shock layer is included in the modulation doped layer of the n-type dopant. The method according to claim 1,
Wherein the n-type shock layer has a doping concentration of 1 x 10 18 atoms / cm 3 or more. The method according to claim 1,
And the n-type shock layer is formed adjacent to the intermediate layer. The method according to claim 1,
Wherein the n-type shock layer has a n-type doping concentration that decreases toward the intermediate layer. The method of claim 6,
And the distance between the n-type shock layer and the intermediate layer is 0 to 20 nm. The method of claim 6,
Wherein the n-type shock layer has a thickness of 1 to 10 nm. Disposing a growth substrate in a growth chamber;
Forming an n-type nitride semiconductor layer on the growth substrate;
Forming an active layer on the n-type nitride semiconductor layer; And
And forming a p-type nitride semiconductor layer on the active layer,
The forming of the n-type nitride semiconductor layer includes:
Forming a lower n-type nitride semiconductor layer on the growth substrate to inject electrons into the active layer;
Forming an n-type shock layer including a layer doped at a higher concentration than the lower n-type nitride semiconductor layer on the lower n-type nitride semiconductor layer; And
And forming an intermediate layer having a larger bandgap than the lower n-type nitride semiconductor layer on the n-type shock layer. The method of claim 9,
Wherein the step of forming the n-type nitride semiconductor layer includes a modulation doped layer of an n-type dopant. The method of claim 10,
The step of forming the n-type shock layer comprises:
A T 1 step of supplying an n-type dopant source into the growth chamber at a first flow rate for T 1 hour; And
And repeating periodically a T 2 step of supplying an n-type dopant source into the growth chamber at a second flow rate lower than the first flow rate for T 2 hours. The method of claim 11,
Further comprising a T 3 step of continuously varying the flow rate of the n-type plumb source from the first flow rate to the second flow rate for T 3 hours between the T 1 and T 2 stages. The method of claim 12,
Wherein the first flow rate increases as the T 1 and T 2 steps are repeated. The method of claim 9,
Wherein the n-type shock layer is n-type doped with a doping concentration of 1 x 10 18 atoms / cm 3 or more. [12] The method of claim 9,
Introducing an Al source, a Ga and / or In source, an N source and an n-type dopant source into the growth chamber to grow a first subintermediate layer; And
The step of interrupting the introduction of the Al source gas and the n-type dopant source, and continuously introducing the Ga and / or In source and the N source gas into the growth chamber to grow the second sub- 1 sub-intermediate layer and the second sub-intermediate layer. 16. The method of claim 15,
Wherein the n-type dopant concentration of the first sub-intermediate layer increases as the respective steps are periodically repeated. Disposing a growth substrate in a growth chamber;
Forming an n-type nitride semiconductor layer on the growth substrate;
Forming an active layer on the n-type nitride semiconductor layer; And
And forming a p-type nitride semiconductor layer on the active layer,
The forming of the n-type nitride semiconductor layer includes:
Forming an n-type shock modulation layer on the growth substrate for injecting electrons into the active layer, the n-type shock modulation layer including a highly doped shock layer; And
And forming an intermediate layer for dispersing electrons injected from the n-type shock modulation layer into the active layer,
And the shock layer is partially overlapped with a heavily doped peak of the intermediate layer. 18. The method of claim 17,
Wherein the shock layer is formed so as to change the doping concentration. 19. The method of claim 18,
Wherein a doping concentration of the shock layer is doped in a range of 1 to 50% relative to a doping concentration of the intermediate layer.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190126631A (en) * 2018-05-02 2019-11-12 연세대학교 산학협력단 Apparatus for vapor deposition and method of vapor deposition of thin film
CN116705942A (en) * 2023-08-08 2023-09-05 江西兆驰半导体有限公司 Light emitting diode and preparation method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190126631A (en) * 2018-05-02 2019-11-12 연세대학교 산학협력단 Apparatus for vapor deposition and method of vapor deposition of thin film
CN116705942A (en) * 2023-08-08 2023-09-05 江西兆驰半导体有限公司 Light emitting diode and preparation method thereof
CN116705942B (en) * 2023-08-08 2023-10-17 江西兆驰半导体有限公司 Light emitting diode and preparation method thereof

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