KR20160119411A - Semiconductor package module - Google Patents
Semiconductor package module Download PDFInfo
- Publication number
- KR20160119411A KR20160119411A KR1020150047755A KR20150047755A KR20160119411A KR 20160119411 A KR20160119411 A KR 20160119411A KR 1020150047755 A KR1020150047755 A KR 1020150047755A KR 20150047755 A KR20150047755 A KR 20150047755A KR 20160119411 A KR20160119411 A KR 20160119411A
- Authority
- KR
- South Korea
- Prior art keywords
- circuit board
- package substrate
- magnetic material
- material layer
- substrate
- Prior art date
Links
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A semiconductor package includes: a circuit board having a first surface and a second surface opposite to the first surface, the first substrate including a first layer of magnetic material; A package substrate disposed on the circuit board and having a second magnetic material layer having a polarity opposite to that of the first magnetic material layer with a face curved at a predetermined curvature, A semiconductor chip disposed on a package substrate; And a molding member covering an exposed region of the semiconductor chip and the package substrate.
Description
The present application relates to package technology, and more particularly, to a semiconductor package module incorporating a magnetic material layer.
As electronic products become smaller and higher performance, portable electronic products increase, space for mounting semiconductor devices is further reduced, while functions required for electronic products are becoming more diverse. As a result, there is an increasing demand for a semiconductor memory having a small size and a large capacity. In addition, as interest in wearable electronics requiring mobility has increased, there has been a demand for a flexible characteristic capable of being bent in an electronic product, such as a function of warping or folding.
Semiconductor chips can be realized to have a thin thickness at a level that can be bent, but it is difficult to obtain flexible characteristics of package substrates on which semiconductor chips are arranged. Such a package substrate is mounted on a circuit board for connection to the outside. When the circuit board is warped or warped, tensile stress or compressive stress may be applied to the package substrate. Such stress causes the connection between the package substrate and the circuit board It will be cut off. If the electrical connection between the package substrate and the circuit board is lost, a problem may occur in the operation of the package, and further, reliability may be lost. Accordingly, there is a demand for a package structure capable of maintaining electrical connection with the package substrate even when the circuit board is bent or warped.
SUMMARY OF THE INVENTION The present invention provides a semiconductor package module structure capable of stably maintaining electrical connection between a package substrate and a circuit substrate.
According to an aspect of the present invention, there is provided a circuit board comprising: a circuit board including a first surface and a second surface opposite to the first surface, the first magnetic material layer embedded therein; A package substrate disposed on the circuit board and including a second magnetic material layer having a polarity opposite to that of the first magnetic material layer, the surface facing the circuit board being bent at a predetermined curvature; A semiconductor chip disposed on the package substrate; And a molding member covering an exposed region of the semiconductor chip and the package substrate.
In the present application, the first surface or the second surface of the circuit board is formed as a flat surface, and the circuit board may be formed of a flexible printed circuit board (PCB), an organic substrate, or an insulating substrate have.
The package substrate may have a flat surface on which the semiconductor chip is disposed, and the package substrate may include a rigid type printed circuit board.
The circuit board further includes a first substrate pad part on a first surface, and the package substrate further includes a contact metal film that contacts the first substrate pad part on a surface facing the circuit board.
The first substrate pad portion may include a plurality of dot patterns that are line-shaped or spaced apart from each other.
The first substrate pad portion or the contact metal film may include aluminum (Al) or copper.
The first magnetic material layer or the second magnetic material layer includes a permanent magnet or an electromagnet.
The permanent magnet may include a ceramic magnet which does not decrease the magnetic force even at a temperature of 300 to 460 degrees.
The ceramic magnet may be formed by mixing a single material of nickel (Ni), manganese (Mn), and cobalt (Co) or an oxide of nickel (Ni), manganese (Mn), and cobalt (Co) with iron.
The first magnetic material layer may be disposed in the form of a plate in a plane structure in the circuit board body portion.
The second magnetic material layer may be disposed in the form of a plate having a surface structure in the body portion of the package substrate.
The second magnetic material layer may be arranged in a line-shaped rim surrounding the outer frame portion of the body portion of the package substrate.
An EMI shielding film formed on an upper surface of the semiconductor chip; And a metal wire connecting the EMI shielding film and the circuit board.
The EMI shielding film may be formed of a metal film containing at least one of copper (Cu), silver (Ah), chrome (Cr), nickel (Ni), and gold (Au).
According to the embodiments of the present application, there is an advantage that a shape curved at a predetermined curvature is introduced into one surface of the package substrate to maintain electrical connection with another circuit substrate. As a result, the semiconductor chip can be prevented from being damaged by the force applied while the package substrate is bent.
In addition, the influence of the electromagnetic field can be controlled by introducing an EMI shielding film.
1 is a cross-sectional view illustrating a semiconductor package structure according to an embodiment of the present invention.
FIG. 2 is a perspective view showing the package substrate of FIG. 1; FIG.
3 is a view for explaining a stress relieving operation of the semiconductor package module according to an embodiment.
4 is a cross-sectional view illustrating a semiconductor package structure according to another embodiment.
The embodiments of the present application are illustrated and described in the drawings, which are intended to illustrate what is being suggested by the present application and are not intended to limit what is presented in the present application in a detailed form.
Like reference numerals refer to like elements throughout the specification. Accordingly, although the same reference numerals or similar reference numerals are not mentioned or described in the drawings, they may be described with reference to other drawings. Further, even if the reference numerals are not shown, they can be described with reference to other drawings.
1 is a cross-sectional view illustrating a semiconductor package structure according to an embodiment of the present invention. FIG. 2 is a perspective view showing the package substrate of FIG. 1; FIG. FIGS. 3 and 4 are diagrams for explaining the stress relieving action of the semiconductor package module according to one embodiment.
1, a
The
The first
The first
A
A second
A
The second
The second
The
The exposed region of the
Referring to FIG. 3, which is a sectional view for explaining the stress relieving action of the semiconductor package according to an embodiment of the present invention, a magnetic field is generated on the first
4 is a cross-sectional view illustrating a semiconductor package structure according to another embodiment.
4, a
The
The first
The first
A
The
A
The second
The second
The
The exposed area of the
An
The
1000, 2000: semiconductor package module
100, 300:
115, 315: first
215, 415: second
Claims (16)
A package substrate disposed on the circuit board and including a second magnetic material layer having a polarity opposite to that of the first magnetic material layer, the surface of the package substrate facing the circuit board having a predetermined curvature;
A semiconductor chip disposed on the package substrate; And
And a molding member covering an exposed region of the semiconductor chip and the package substrate.
Wherein a first surface or a second surface of the circuit board is formed as a flat surface.
The circuit board is formed of a flexible printed circuit board (PCB), an organic substrate, or an insulating substrate.
Wherein the package substrate has a flat surface on which the semiconductor chip is disposed.
Wherein the package substrate comprises a rigid type printed circuit board.
Wherein the circuit board further comprises a first substrate pad portion on a first side,
Wherein the package substrate further comprises a contact metal film that contacts the first substrate pad portion on a surface facing the circuit board.
Wherein the first substrate pad portion includes a plurality of dots in a line shape or spaced apart from each other.
Wherein the first substrate pad portion or the contact metal film includes aluminum (Al) or copper.
Wherein the first magnetic material layer or the second magnetic material layer comprises a permanent magnet or an electromagnet.
Wherein the permanent magnet includes a ceramic magnet which does not decrease its magnetic force even at a temperature of 300 to 460 degrees.
The ceramic magnet is formed by mixing a single material of nickel (Ni), manganese (Mn), and cobalt (Co) or an oxide of nickel (Ni), manganese (Mn), and cobalt (Co) with iron.
Wherein the first magnetic material layer is disposed in a plate shape in a plane structure in the circuit board body portion.
And the second magnetic material layer is disposed in a plate shape in a plane structure in a body portion of the package substrate.
And the second magnetic material layer is arranged in a line-shaped rim surrounding the outer portion of the body portion of the package substrate.
An EMI shielding film formed on an upper surface of the semiconductor chip; And
And a metal wire connecting the EMI shielding film and the circuit board.
Wherein the EMI shielding film is formed of a metal film containing at least one of copper (Cu), silver (Ah), chromium (Cr), nickel (Ni), and gold (Au).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020150047755A KR20160119411A (en) | 2015-04-03 | 2015-04-03 | Semiconductor package module |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020150047755A KR20160119411A (en) | 2015-04-03 | 2015-04-03 | Semiconductor package module |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20160119411A true KR20160119411A (en) | 2016-10-13 |
Family
ID=57173996
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020150047755A KR20160119411A (en) | 2015-04-03 | 2015-04-03 | Semiconductor package module |
Country Status (1)
Country | Link |
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KR (1) | KR20160119411A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113380723A (en) * | 2021-04-29 | 2021-09-10 | 苏州通富超威半导体有限公司 | Packaging structure |
-
2015
- 2015-04-03 KR KR1020150047755A patent/KR20160119411A/en unknown
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113380723A (en) * | 2021-04-29 | 2021-09-10 | 苏州通富超威半导体有限公司 | Packaging structure |
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